Nenad Djalovic / BSP_DISCO_F469NIfdsf

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Fork of BSP_DISCO_F469NI by ST

stm32469i_discovery/stm32469i_discovery_qspi.c@0:0002c86c2220, 2015-12-18 (annotated)

Committer:
bcostm
Date:
Fri Dec 18 07:32:01 2015 +0000
Revision:
0:0002c86c2220
Initial version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 0:0002c86c2220 1 /**
bcostm 0:0002c86c2220 2 ******************************************************************************
bcostm 0:0002c86c2220 3 * @file stm32469i_discovery_qspi.c
bcostm 0:0002c86c2220 4 * @author MCD Application Team
bcostm 0:0002c86c2220 5 * @version V1.0.1
bcostm 0:0002c86c2220 6 * @date 29-September-2015
bcostm 0:0002c86c2220 7 * @brief This file includes a standard driver for the N25Q128A QSPI
bcostm 0:0002c86c2220 8 * memory mounted on STM32469I-Discovery board.
bcostm 0:0002c86c2220 9 @verbatim
bcostm 0:0002c86c2220 10 ==============================================================================
bcostm 0:0002c86c2220 11 ##### How to use this driver #####
bcostm 0:0002c86c2220 12 ==============================================================================
bcostm 0:0002c86c2220 13 [..]
bcostm 0:0002c86c2220 14 (#) This driver is used to drive the N25Q128A QSPI external
bcostm 0:0002c86c2220 15 memory mounted on STM32469I-Discovery board.
bcostm 0:0002c86c2220 16
bcostm 0:0002c86c2220 17 (#) This driver need a specific component driver N25Q128A to be included with.
bcostm 0:0002c86c2220 18
bcostm 0:0002c86c2220 19 (#) Initialization steps:
bcostm 0:0002c86c2220 20 (++) Initialize the QPSI external memory using the BSP_QSPI_Init() function. This
bcostm 0:0002c86c2220 21 function includes the MSP layer hardware resources initialization and the
bcostm 0:0002c86c2220 22 QSPI interface with the external memory.
bcostm 0:0002c86c2220 23
bcostm 0:0002c86c2220 24 (#) QSPI memory operations
bcostm 0:0002c86c2220 25 (++) QSPI memory can be accessed with read/write operations once it is
bcostm 0:0002c86c2220 26 initialized.
bcostm 0:0002c86c2220 27 Read/write operation can be performed with AHB access using the functions
bcostm 0:0002c86c2220 28 BSP_QSPI_Read()/BSP_QSPI_Write().
bcostm 0:0002c86c2220 29 (++) The function BSP_QSPI_GetInfo() returns the configuration of the QSPI memory.
bcostm 0:0002c86c2220 30 (see the QSPI memory data sheet)
bcostm 0:0002c86c2220 31 (++) Perform erase block operation using the function BSP_QSPI_Erase_Block() and by
bcostm 0:0002c86c2220 32 specifying the block address. You can perform an erase operation of the whole
bcostm 0:0002c86c2220 33 chip by calling the function BSP_QSPI_Erase_Chip().
bcostm 0:0002c86c2220 34 (++) The function BSP_QSPI_GetStatus() returns the current status of the QSPI memory.
bcostm 0:0002c86c2220 35 (see the QSPI memory data sheet)
bcostm 0:0002c86c2220 36 @endverbatim
bcostm 0:0002c86c2220 37 ******************************************************************************
bcostm 0:0002c86c2220 38 * @attention
bcostm 0:0002c86c2220 39 *
bcostm 0:0002c86c2220 40 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bcostm 0:0002c86c2220 41 *
bcostm 0:0002c86c2220 42 * Redistribution and use in source and binary forms, with or without modification,
bcostm 0:0002c86c2220 43 * are permitted provided that the following conditions are met:
bcostm 0:0002c86c2220 44 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 0:0002c86c2220 45 * this list of conditions and the following disclaimer.
bcostm 0:0002c86c2220 46 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 0:0002c86c2220 47 * this list of conditions and the following disclaimer in the documentation
bcostm 0:0002c86c2220 48 * and/or other materials provided with the distribution.
bcostm 0:0002c86c2220 49 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 0:0002c86c2220 50 * may be used to endorse or promote products derived from this software
bcostm 0:0002c86c2220 51 * without specific prior written permission.
bcostm 0:0002c86c2220 52 *
bcostm 0:0002c86c2220 53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 0:0002c86c2220 54 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 0:0002c86c2220 55 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 0:0002c86c2220 56 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 0:0002c86c2220 57 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 0:0002c86c2220 58 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 0:0002c86c2220 59 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 0:0002c86c2220 60 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 0:0002c86c2220 61 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 0:0002c86c2220 62 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 0:0002c86c2220 63 *
bcostm 0:0002c86c2220 64 ******************************************************************************
bcostm 0:0002c86c2220 65 */
bcostm 0:0002c86c2220 66
bcostm 0:0002c86c2220 67 /* Includes ------------------------------------------------------------------*/
bcostm 0:0002c86c2220 68 #include "stm32469i_discovery_qspi.h"
bcostm 0:0002c86c2220 69
bcostm 0:0002c86c2220 70 /** @addtogroup BSP
bcostm 0:0002c86c2220 71 * @{
bcostm 0:0002c86c2220 72 */
bcostm 0:0002c86c2220 73
bcostm 0:0002c86c2220 74 /** @addtogroup STM32469I_Discovery
bcostm 0:0002c86c2220 75 * @{
bcostm 0:0002c86c2220 76 */
bcostm 0:0002c86c2220 77
bcostm 0:0002c86c2220 78 /** @defgroup STM32469I_Discovery_QSPI STM32469I_Discovery QSPI
bcostm 0:0002c86c2220 79 * @{
bcostm 0:0002c86c2220 80 */
bcostm 0:0002c86c2220 81
bcostm 0:0002c86c2220 82
bcostm 0:0002c86c2220 83 /* Private variables ---------------------------------------------------------*/
bcostm 0:0002c86c2220 84
bcostm 0:0002c86c2220 85
bcostm 0:0002c86c2220 86 /** @defgroup STM32469I_Discovery_QSPI_Private_Variables Private Variables
bcostm 0:0002c86c2220 87 * @{
bcostm 0:0002c86c2220 88 */
bcostm 0:0002c86c2220 89 QSPI_HandleTypeDef QSPIHandle;
bcostm 0:0002c86c2220 90
bcostm 0:0002c86c2220 91 /**
bcostm 0:0002c86c2220 92 * @}
bcostm 0:0002c86c2220 93 */
bcostm 0:0002c86c2220 94
bcostm 0:0002c86c2220 95
bcostm 0:0002c86c2220 96
bcostm 0:0002c86c2220 97 /* Private functions ---------------------------------------------------------*/
bcostm 0:0002c86c2220 98
bcostm 0:0002c86c2220 99 /** @defgroup STM32469I_Discovery_QSPI_Private_Functions QSPI Private Functions
bcostm 0:0002c86c2220 100 * @{
bcostm 0:0002c86c2220 101 */
bcostm 0:0002c86c2220 102 static uint8_t QSPI_ResetMemory (QSPI_HandleTypeDef *hqspi);
bcostm 0:0002c86c2220 103 static uint8_t QSPI_DummyCyclesCfg (QSPI_HandleTypeDef *hqspi);
bcostm 0:0002c86c2220 104 static uint8_t QSPI_WriteEnable (QSPI_HandleTypeDef *hqspi);
bcostm 0:0002c86c2220 105 static uint8_t QSPI_AutoPollingMemReady (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
bcostm 0:0002c86c2220 106
bcostm 0:0002c86c2220 107
bcostm 0:0002c86c2220 108 /**
bcostm 0:0002c86c2220 109 * @}
bcostm 0:0002c86c2220 110 */
bcostm 0:0002c86c2220 111
bcostm 0:0002c86c2220 112 /** @defgroup STM32469I_Discovery_QSPI_Exported_Functions QSPI Exported Functions
bcostm 0:0002c86c2220 113 * @{
bcostm 0:0002c86c2220 114 */
bcostm 0:0002c86c2220 115
bcostm 0:0002c86c2220 116 /**
bcostm 0:0002c86c2220 117 * @brief Initializes the QSPI interface.
bcostm 0:0002c86c2220 118 * @retval QSPI memory status
bcostm 0:0002c86c2220 119 */
bcostm 0:0002c86c2220 120 uint8_t BSP_QSPI_Init(void)
bcostm 0:0002c86c2220 121 {
bcostm 0:0002c86c2220 122 QSPIHandle.Instance = QUADSPI;
bcostm 0:0002c86c2220 123
bcostm 0:0002c86c2220 124 /* Call the DeInit function to reset the driver */
bcostm 0:0002c86c2220 125 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
bcostm 0:0002c86c2220 126 {
bcostm 0:0002c86c2220 127 return QSPI_ERROR;
bcostm 0:0002c86c2220 128 }
bcostm 0:0002c86c2220 129
bcostm 0:0002c86c2220 130 /* System level initialization */
bcostm 0:0002c86c2220 131 BSP_QSPI_MspInit(&QSPIHandle, NULL);
bcostm 0:0002c86c2220 132
bcostm 0:0002c86c2220 133 /* QSPI initialization */
bcostm 0:0002c86c2220 134 QSPIHandle.Init.ClockPrescaler = 1; /* QSPI Freq= 180 MHz / (1+1) = 90 MHz */
bcostm 0:0002c86c2220 135 QSPIHandle.Init.FifoThreshold = 1;
bcostm 0:0002c86c2220 136 QSPIHandle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE;
bcostm 0:0002c86c2220 137 QSPIHandle.Init.FlashSize = POSITION_VAL(N25Q128A_FLASH_SIZE) - 1;
bcostm 0:0002c86c2220 138 QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_2_CYCLE;
bcostm 0:0002c86c2220 139 QSPIHandle.Init.ClockMode = QSPI_CLOCK_MODE_0;
bcostm 0:0002c86c2220 140 QSPIHandle.Init.FlashID = QSPI_FLASH_ID_1;
bcostm 0:0002c86c2220 141 QSPIHandle.Init.DualFlash = QSPI_DUALFLASH_DISABLE;
bcostm 0:0002c86c2220 142
bcostm 0:0002c86c2220 143 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)
bcostm 0:0002c86c2220 144 {
bcostm 0:0002c86c2220 145 return QSPI_ERROR;
bcostm 0:0002c86c2220 146 }
bcostm 0:0002c86c2220 147
bcostm 0:0002c86c2220 148 /* QSPI memory reset */
bcostm 0:0002c86c2220 149 if (QSPI_ResetMemory(&QSPIHandle) != QSPI_OK)
bcostm 0:0002c86c2220 150 {
bcostm 0:0002c86c2220 151 return QSPI_NOT_SUPPORTED;
bcostm 0:0002c86c2220 152 }
bcostm 0:0002c86c2220 153
bcostm 0:0002c86c2220 154
bcostm 0:0002c86c2220 155 /* Configuration of the dummy cucles on QSPI memory side */
bcostm 0:0002c86c2220 156 if (QSPI_DummyCyclesCfg(&QSPIHandle) != QSPI_OK)
bcostm 0:0002c86c2220 157 {
bcostm 0:0002c86c2220 158 return QSPI_NOT_SUPPORTED;
bcostm 0:0002c86c2220 159 }
bcostm 0:0002c86c2220 160
bcostm 0:0002c86c2220 161 return QSPI_OK;
bcostm 0:0002c86c2220 162 }
bcostm 0:0002c86c2220 163
bcostm 0:0002c86c2220 164 /**
bcostm 0:0002c86c2220 165 * @brief De-Initializes the QSPI interface.
bcostm 0:0002c86c2220 166 * @retval QSPI memory status
bcostm 0:0002c86c2220 167 */
bcostm 0:0002c86c2220 168 uint8_t BSP_QSPI_DeInit(void)
bcostm 0:0002c86c2220 169 {
bcostm 0:0002c86c2220 170 QSPIHandle.Instance = QUADSPI;
bcostm 0:0002c86c2220 171
bcostm 0:0002c86c2220 172 /* Call the DeInit function to reset the driver */
bcostm 0:0002c86c2220 173 if (HAL_QSPI_DeInit(&QSPIHandle) != HAL_OK)
bcostm 0:0002c86c2220 174 {
bcostm 0:0002c86c2220 175 return QSPI_ERROR;
bcostm 0:0002c86c2220 176 }
bcostm 0:0002c86c2220 177
bcostm 0:0002c86c2220 178 /* System level De-initialization */
bcostm 0:0002c86c2220 179 BSP_QSPI_MspDeInit(&QSPIHandle, NULL);
bcostm 0:0002c86c2220 180
bcostm 0:0002c86c2220 181 return QSPI_OK;
bcostm 0:0002c86c2220 182 }
bcostm 0:0002c86c2220 183
bcostm 0:0002c86c2220 184 /**
bcostm 0:0002c86c2220 185 * @brief Reads an amount of data from the QSPI memory.
bcostm 0:0002c86c2220 186 * @param pData: Pointer to data to be read
bcostm 0:0002c86c2220 187 * @param ReadAddr: Read start address
bcostm 0:0002c86c2220 188 * @param Size: Size of data to read
bcostm 0:0002c86c2220 189 * @retval QSPI memory status
bcostm 0:0002c86c2220 190 */
bcostm 0:0002c86c2220 191 uint8_t BSP_QSPI_Read(uint8_t* pData, uint32_t ReadAddr, uint32_t Size)
bcostm 0:0002c86c2220 192 {
bcostm 0:0002c86c2220 193 QSPI_CommandTypeDef s_command;
bcostm 0:0002c86c2220 194
bcostm 0:0002c86c2220 195 /* Initialize the read command */
bcostm 0:0002c86c2220 196 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 0:0002c86c2220 197 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD;
bcostm 0:0002c86c2220 198 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 0:0002c86c2220 199 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 0:0002c86c2220 200 s_command.Address = ReadAddr;
bcostm 0:0002c86c2220 201 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 0:0002c86c2220 202 s_command.DataMode = QSPI_DATA_4_LINES;
bcostm 0:0002c86c2220 203 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD;
bcostm 0:0002c86c2220 204 s_command.NbData = Size;
bcostm 0:0002c86c2220 205 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 0:0002c86c2220 206 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 0:0002c86c2220 207 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 0:0002c86c2220 208
bcostm 0:0002c86c2220 209 /* Configure the command */
bcostm 0:0002c86c2220 210 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 211 {
bcostm 0:0002c86c2220 212 return QSPI_ERROR;
bcostm 0:0002c86c2220 213 }
bcostm 0:0002c86c2220 214
bcostm 0:0002c86c2220 215 /* Reception of the data */
bcostm 0:0002c86c2220 216 if (HAL_QSPI_Receive(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 217 {
bcostm 0:0002c86c2220 218 return QSPI_ERROR;
bcostm 0:0002c86c2220 219 }
bcostm 0:0002c86c2220 220
bcostm 0:0002c86c2220 221 return QSPI_OK;
bcostm 0:0002c86c2220 222 }
bcostm 0:0002c86c2220 223
bcostm 0:0002c86c2220 224 /**
bcostm 0:0002c86c2220 225 * @brief Writes an amount of data to the QSPI memory.
bcostm 0:0002c86c2220 226 * @param pData: Pointer to data to be written
bcostm 0:0002c86c2220 227 * @param WriteAddr: Write start address
bcostm 0:0002c86c2220 228 * @param Size: Size of data to write
bcostm 0:0002c86c2220 229 * @retval QSPI memory status
bcostm 0:0002c86c2220 230 */
bcostm 0:0002c86c2220 231 uint8_t BSP_QSPI_Write(uint8_t* pData, uint32_t WriteAddr, uint32_t Size)
bcostm 0:0002c86c2220 232 {
bcostm 0:0002c86c2220 233 QSPI_CommandTypeDef s_command;
bcostm 0:0002c86c2220 234 uint32_t end_addr, current_size, current_addr;
bcostm 0:0002c86c2220 235
bcostm 0:0002c86c2220 236 /* Calculation of the size between the write address and the end of the page */
bcostm 0:0002c86c2220 237 current_addr = 0;
bcostm 0:0002c86c2220 238
bcostm 0:0002c86c2220 239 while (current_addr <= WriteAddr)
bcostm 0:0002c86c2220 240 {
bcostm 0:0002c86c2220 241 current_addr += N25Q128A_PAGE_SIZE;
bcostm 0:0002c86c2220 242 }
bcostm 0:0002c86c2220 243 current_size = current_addr - WriteAddr;
bcostm 0:0002c86c2220 244
bcostm 0:0002c86c2220 245 /* Check if the size of the data is less than the remaining place in the page */
bcostm 0:0002c86c2220 246 if (current_size > Size)
bcostm 0:0002c86c2220 247 {
bcostm 0:0002c86c2220 248 current_size = Size;
bcostm 0:0002c86c2220 249 }
bcostm 0:0002c86c2220 250
bcostm 0:0002c86c2220 251 /* Initialize the address variables */
bcostm 0:0002c86c2220 252 current_addr = WriteAddr;
bcostm 0:0002c86c2220 253 end_addr = WriteAddr + Size;
bcostm 0:0002c86c2220 254
bcostm 0:0002c86c2220 255 /* Initialize the program command */
bcostm 0:0002c86c2220 256 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 0:0002c86c2220 257 s_command.Instruction = EXT_QUAD_IN_FAST_PROG_CMD;
bcostm 0:0002c86c2220 258 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 0:0002c86c2220 259 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 0:0002c86c2220 260 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 0:0002c86c2220 261 s_command.DataMode = QSPI_DATA_4_LINES;
bcostm 0:0002c86c2220 262 s_command.DummyCycles = 0;
bcostm 0:0002c86c2220 263 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 0:0002c86c2220 264 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 0:0002c86c2220 265 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 0:0002c86c2220 266
bcostm 0:0002c86c2220 267 /* Perform the write page by page */
bcostm 0:0002c86c2220 268 do
bcostm 0:0002c86c2220 269 {
bcostm 0:0002c86c2220 270 s_command.Address = current_addr;
bcostm 0:0002c86c2220 271 s_command.NbData = current_size;
bcostm 0:0002c86c2220 272
bcostm 0:0002c86c2220 273 /* Enable write operations */
bcostm 0:0002c86c2220 274 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 0:0002c86c2220 275 {
bcostm 0:0002c86c2220 276 return QSPI_ERROR;
bcostm 0:0002c86c2220 277 }
bcostm 0:0002c86c2220 278
bcostm 0:0002c86c2220 279 /* Configure the command */
bcostm 0:0002c86c2220 280 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 281 {
bcostm 0:0002c86c2220 282 return QSPI_ERROR;
bcostm 0:0002c86c2220 283 }
bcostm 0:0002c86c2220 284
bcostm 0:0002c86c2220 285 /* Transmission of the data */
bcostm 0:0002c86c2220 286 if (HAL_QSPI_Transmit(&QSPIHandle, pData, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 287 {
bcostm 0:0002c86c2220 288 return QSPI_ERROR;
bcostm 0:0002c86c2220 289 }
bcostm 0:0002c86c2220 290
bcostm 0:0002c86c2220 291 /* Configure automatic polling mode to wait for end of program */
bcostm 0:0002c86c2220 292 if (QSPI_AutoPollingMemReady(&QSPIHandle, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
bcostm 0:0002c86c2220 293 {
bcostm 0:0002c86c2220 294 return QSPI_ERROR;
bcostm 0:0002c86c2220 295 }
bcostm 0:0002c86c2220 296
bcostm 0:0002c86c2220 297 /* Update the address and size variables for next page programming */
bcostm 0:0002c86c2220 298 current_addr += current_size;
bcostm 0:0002c86c2220 299 pData += current_size;
bcostm 0:0002c86c2220 300 current_size = ((current_addr + N25Q128A_PAGE_SIZE) > end_addr) ? (end_addr - current_addr) : N25Q128A_PAGE_SIZE;
bcostm 0:0002c86c2220 301 } while (current_addr < end_addr);
bcostm 0:0002c86c2220 302
bcostm 0:0002c86c2220 303 return QSPI_OK;
bcostm 0:0002c86c2220 304 }
bcostm 0:0002c86c2220 305
bcostm 0:0002c86c2220 306 /**
bcostm 0:0002c86c2220 307 * @brief Erases the specified block of the QSPI memory.
bcostm 0:0002c86c2220 308 * @param BlockAddress: Block address to erase
bcostm 0:0002c86c2220 309 * @retval QSPI memory status
bcostm 0:0002c86c2220 310 */
bcostm 0:0002c86c2220 311 uint8_t BSP_QSPI_Erase_Block(uint32_t BlockAddress)
bcostm 0:0002c86c2220 312 {
bcostm 0:0002c86c2220 313 QSPI_CommandTypeDef s_command;
bcostm 0:0002c86c2220 314
bcostm 0:0002c86c2220 315 /* Initialize the erase command */
bcostm 0:0002c86c2220 316 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 0:0002c86c2220 317 s_command.Instruction = SUBSECTOR_ERASE_CMD;
bcostm 0:0002c86c2220 318 s_command.AddressMode = QSPI_ADDRESS_1_LINE;
bcostm 0:0002c86c2220 319 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 0:0002c86c2220 320 s_command.Address = BlockAddress;
bcostm 0:0002c86c2220 321 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 0:0002c86c2220 322 s_command.DataMode = QSPI_DATA_NONE;
bcostm 0:0002c86c2220 323 s_command.DummyCycles = 0;
bcostm 0:0002c86c2220 324 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 0:0002c86c2220 325 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 0:0002c86c2220 326 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 0:0002c86c2220 327
bcostm 0:0002c86c2220 328 /* Enable write operations */
bcostm 0:0002c86c2220 329 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 0:0002c86c2220 330 {
bcostm 0:0002c86c2220 331 return QSPI_ERROR;
bcostm 0:0002c86c2220 332 }
bcostm 0:0002c86c2220 333
bcostm 0:0002c86c2220 334 /* Send the command */
bcostm 0:0002c86c2220 335 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 336 {
bcostm 0:0002c86c2220 337 return QSPI_ERROR;
bcostm 0:0002c86c2220 338 }
bcostm 0:0002c86c2220 339
bcostm 0:0002c86c2220 340 /* Configure automatic polling mode to wait for end of erase */
bcostm 0:0002c86c2220 341 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_SUBSECTOR_ERASE_MAX_TIME) != QSPI_OK)
bcostm 0:0002c86c2220 342 {
bcostm 0:0002c86c2220 343 return QSPI_ERROR;
bcostm 0:0002c86c2220 344 }
bcostm 0:0002c86c2220 345
bcostm 0:0002c86c2220 346 return QSPI_OK;
bcostm 0:0002c86c2220 347 }
bcostm 0:0002c86c2220 348
bcostm 0:0002c86c2220 349 /**
bcostm 0:0002c86c2220 350 * @brief Erases the entire QSPI memory.
bcostm 0:0002c86c2220 351 * @retval QSPI memory status
bcostm 0:0002c86c2220 352 */
bcostm 0:0002c86c2220 353 uint8_t BSP_QSPI_Erase_Chip(void)
bcostm 0:0002c86c2220 354 {
bcostm 0:0002c86c2220 355 QSPI_CommandTypeDef s_command;
bcostm 0:0002c86c2220 356
bcostm 0:0002c86c2220 357 /* Initialize the erase command */
bcostm 0:0002c86c2220 358 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 0:0002c86c2220 359 s_command.Instruction = BULK_ERASE_CMD;
bcostm 0:0002c86c2220 360 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 0:0002c86c2220 361 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 0:0002c86c2220 362 s_command.DataMode = QSPI_DATA_NONE;
bcostm 0:0002c86c2220 363 s_command.DummyCycles = 0;
bcostm 0:0002c86c2220 364 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 0:0002c86c2220 365 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 0:0002c86c2220 366 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 0:0002c86c2220 367
bcostm 0:0002c86c2220 368 /* Enable write operations */
bcostm 0:0002c86c2220 369 if (QSPI_WriteEnable(&QSPIHandle) != QSPI_OK)
bcostm 0:0002c86c2220 370 {
bcostm 0:0002c86c2220 371 return QSPI_ERROR;
bcostm 0:0002c86c2220 372 }
bcostm 0:0002c86c2220 373
bcostm 0:0002c86c2220 374 /* Send the command */
bcostm 0:0002c86c2220 375 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 376 {
bcostm 0:0002c86c2220 377 return QSPI_ERROR;
bcostm 0:0002c86c2220 378 }
bcostm 0:0002c86c2220 379
bcostm 0:0002c86c2220 380 /* Configure automatic polling mode to wait for end of erase */
bcostm 0:0002c86c2220 381 if (QSPI_AutoPollingMemReady(&QSPIHandle, N25Q128A_BULK_ERASE_MAX_TIME) != QSPI_OK)
bcostm 0:0002c86c2220 382 {
bcostm 0:0002c86c2220 383 return QSPI_ERROR;
bcostm 0:0002c86c2220 384 }
bcostm 0:0002c86c2220 385
bcostm 0:0002c86c2220 386 return QSPI_OK;
bcostm 0:0002c86c2220 387 }
bcostm 0:0002c86c2220 388
bcostm 0:0002c86c2220 389 /**
bcostm 0:0002c86c2220 390 * @brief Reads current status of the QSPI memory.
bcostm 0:0002c86c2220 391 * @retval QSPI memory status
bcostm 0:0002c86c2220 392 */
bcostm 0:0002c86c2220 393 uint8_t BSP_QSPI_GetStatus(void)
bcostm 0:0002c86c2220 394 {
bcostm 0:0002c86c2220 395 QSPI_CommandTypeDef s_command;
bcostm 0:0002c86c2220 396 uint8_t reg;
bcostm 0:0002c86c2220 397
bcostm 0:0002c86c2220 398 /* Initialize the read flag status register command */
bcostm 0:0002c86c2220 399 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 0:0002c86c2220 400 s_command.Instruction = READ_FLAG_STATUS_REG_CMD;
bcostm 0:0002c86c2220 401 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 0:0002c86c2220 402 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 0:0002c86c2220 403 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 0:0002c86c2220 404 s_command.DummyCycles = 0;
bcostm 0:0002c86c2220 405 s_command.NbData = 1;
bcostm 0:0002c86c2220 406 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 0:0002c86c2220 407 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 0:0002c86c2220 408 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 0:0002c86c2220 409
bcostm 0:0002c86c2220 410 /* Configure the command */
bcostm 0:0002c86c2220 411 if (HAL_QSPI_Command(&QSPIHandle, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 412 {
bcostm 0:0002c86c2220 413 return QSPI_ERROR;
bcostm 0:0002c86c2220 414 }
bcostm 0:0002c86c2220 415
bcostm 0:0002c86c2220 416 /* Reception of the data */
bcostm 0:0002c86c2220 417 if (HAL_QSPI_Receive(&QSPIHandle, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 418 {
bcostm 0:0002c86c2220 419 return QSPI_ERROR;
bcostm 0:0002c86c2220 420 }
bcostm 0:0002c86c2220 421
bcostm 0:0002c86c2220 422 /* Check the value of the register */
bcostm 0:0002c86c2220 423 if ((reg & (N25Q128A_FSR_PRERR | N25Q128A_FSR_VPPERR | N25Q128A_FSR_PGERR | N25Q128A_FSR_ERERR)) != 0)
bcostm 0:0002c86c2220 424 {
bcostm 0:0002c86c2220 425 return QSPI_ERROR;
bcostm 0:0002c86c2220 426 }
bcostm 0:0002c86c2220 427 else if ((reg & (N25Q128A_FSR_PGSUS | N25Q128A_FSR_ERSUS)) != 0)
bcostm 0:0002c86c2220 428 {
bcostm 0:0002c86c2220 429 return QSPI_SUSPENDED;
bcostm 0:0002c86c2220 430 }
bcostm 0:0002c86c2220 431 else if ((reg & N25Q128A_FSR_READY) != 0)
bcostm 0:0002c86c2220 432 {
bcostm 0:0002c86c2220 433 return QSPI_OK;
bcostm 0:0002c86c2220 434 }
bcostm 0:0002c86c2220 435 else
bcostm 0:0002c86c2220 436 {
bcostm 0:0002c86c2220 437 return QSPI_BUSY;
bcostm 0:0002c86c2220 438 }
bcostm 0:0002c86c2220 439 }
bcostm 0:0002c86c2220 440
bcostm 0:0002c86c2220 441 /**
bcostm 0:0002c86c2220 442 * @brief Reads the configuration of the memory and fills QspiInfo struct
bcostm 0:0002c86c2220 443 * @param pInfo pointer to Info structure
bcostm 0:0002c86c2220 444 * @retval QSPI memory status
bcostm 0:0002c86c2220 445 */
bcostm 0:0002c86c2220 446 uint8_t BSP_QSPI_GetInfo(QSPI_InfoTypeDef* pInfo)
bcostm 0:0002c86c2220 447 {
bcostm 0:0002c86c2220 448 /* Configure the structure with the memory configuration */
bcostm 0:0002c86c2220 449 pInfo->FlashSize = N25Q128A_FLASH_SIZE;
bcostm 0:0002c86c2220 450 pInfo->EraseSectorSize = N25Q128A_SUBSECTOR_SIZE;
bcostm 0:0002c86c2220 451 pInfo->EraseSectorsNumber = (N25Q128A_FLASH_SIZE/N25Q128A_SUBSECTOR_SIZE);
bcostm 0:0002c86c2220 452 pInfo->ProgPageSize = N25Q128A_PAGE_SIZE;
bcostm 0:0002c86c2220 453 pInfo->ProgPagesNumber = (N25Q128A_FLASH_SIZE/N25Q128A_PAGE_SIZE);
bcostm 0:0002c86c2220 454
bcostm 0:0002c86c2220 455 return QSPI_OK;
bcostm 0:0002c86c2220 456 }
bcostm 0:0002c86c2220 457
bcostm 0:0002c86c2220 458 /**
bcostm 0:0002c86c2220 459 * @brief Configure the QSPI in memory-mapped mode
bcostm 0:0002c86c2220 460 * @param None
bcostm 0:0002c86c2220 461 * @retval QSPI memory status
bcostm 0:0002c86c2220 462 */
bcostm 0:0002c86c2220 463 uint8_t BSP_QSPI_MemoryMappedMode(void)
bcostm 0:0002c86c2220 464 {
bcostm 0:0002c86c2220 465 QSPI_CommandTypeDef s_command;
bcostm 0:0002c86c2220 466 QSPI_MemoryMappedTypeDef s_mem_mapped_cfg;
bcostm 0:0002c86c2220 467
bcostm 0:0002c86c2220 468 /* Configure the command for the read instruction */
bcostm 0:0002c86c2220 469 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 0:0002c86c2220 470 s_command.Instruction = QUAD_INOUT_FAST_READ_CMD;
bcostm 0:0002c86c2220 471 s_command.AddressMode = QSPI_ADDRESS_4_LINES;
bcostm 0:0002c86c2220 472 s_command.AddressSize = QSPI_ADDRESS_24_BITS;
bcostm 0:0002c86c2220 473 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 0:0002c86c2220 474 s_command.DataMode = QSPI_DATA_4_LINES;
bcostm 0:0002c86c2220 475 s_command.DummyCycles = N25Q128A_DUMMY_CYCLES_READ_QUAD;
bcostm 0:0002c86c2220 476 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 0:0002c86c2220 477 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 0:0002c86c2220 478 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 0:0002c86c2220 479
bcostm 0:0002c86c2220 480 /* Configure the memory mapped mode */
bcostm 0:0002c86c2220 481 s_mem_mapped_cfg.TimeOutActivation = QSPI_TIMEOUT_COUNTER_ENABLE;
bcostm 0:0002c86c2220 482 s_mem_mapped_cfg.TimeOutPeriod = 100;
bcostm 0:0002c86c2220 483
bcostm 0:0002c86c2220 484 if (HAL_QSPI_MemoryMapped(&QSPIHandle, &s_command, &s_mem_mapped_cfg) != HAL_OK)
bcostm 0:0002c86c2220 485 {
bcostm 0:0002c86c2220 486 return QSPI_ERROR;
bcostm 0:0002c86c2220 487 }
bcostm 0:0002c86c2220 488
bcostm 0:0002c86c2220 489 return QSPI_OK;
bcostm 0:0002c86c2220 490 }
bcostm 0:0002c86c2220 491
bcostm 0:0002c86c2220 492 /**
bcostm 0:0002c86c2220 493 * @}
bcostm 0:0002c86c2220 494 */
bcostm 0:0002c86c2220 495
bcostm 0:0002c86c2220 496 /** @addtogroup STM32446E_Discovery_QSPI_Private_Functions
bcostm 0:0002c86c2220 497 * @{
bcostm 0:0002c86c2220 498 */
bcostm 0:0002c86c2220 499
bcostm 0:0002c86c2220 500 /**
bcostm 0:0002c86c2220 501 * @brief QSPI MSP Initialization
bcostm 0:0002c86c2220 502 * This function configures the hardware resources used in this example:
bcostm 0:0002c86c2220 503 * - Peripheral's clock enable
bcostm 0:0002c86c2220 504 * - Peripheral's GPIO Configuration
bcostm 0:0002c86c2220 505 * - NVIC configuration for QSPI interrupt
bcostm 0:0002c86c2220 506 * @retval None
bcostm 0:0002c86c2220 507 */
bcostm 0:0002c86c2220 508 __weak void BSP_QSPI_MspInit(QSPI_HandleTypeDef *hqspi, void *Params)
bcostm 0:0002c86c2220 509 {
bcostm 0:0002c86c2220 510 GPIO_InitTypeDef gpio_init_structure;
bcostm 0:0002c86c2220 511
bcostm 0:0002c86c2220 512 /*##-1- Enable peripherals and GPIO Clocks #################################*/
bcostm 0:0002c86c2220 513 /* Enable the QuadSPI memory interface clock */
bcostm 0:0002c86c2220 514 QSPI_CLK_ENABLE();
bcostm 0:0002c86c2220 515 /* Reset the QuadSPI memory interface */
bcostm 0:0002c86c2220 516 QSPI_FORCE_RESET();
bcostm 0:0002c86c2220 517 QSPI_RELEASE_RESET();
bcostm 0:0002c86c2220 518 /* Enable GPIO clocks */
bcostm 0:0002c86c2220 519 QSPI_CS_GPIO_CLK_ENABLE();
bcostm 0:0002c86c2220 520 QSPI_DX_CLK_GPIO_CLK_ENABLE();
bcostm 0:0002c86c2220 521
bcostm 0:0002c86c2220 522 /*##-2- Configure peripheral GPIO ##########################################*/
bcostm 0:0002c86c2220 523 /* QSPI CS GPIO pin configuration */
bcostm 0:0002c86c2220 524 gpio_init_structure.Pin = QSPI_CS_PIN;
bcostm 0:0002c86c2220 525 gpio_init_structure.Mode = GPIO_MODE_AF_PP;
bcostm 0:0002c86c2220 526 gpio_init_structure.Pull = GPIO_PULLUP;
bcostm 0:0002c86c2220 527 gpio_init_structure.Speed = GPIO_SPEED_HIGH;
bcostm 0:0002c86c2220 528 gpio_init_structure.Alternate = GPIO_AF10_QSPI;
bcostm 0:0002c86c2220 529 HAL_GPIO_Init(QSPI_CS_GPIO_PORT, &gpio_init_structure);
bcostm 0:0002c86c2220 530
bcostm 0:0002c86c2220 531 /* QSPI CLK GPIO pin configuration */
bcostm 0:0002c86c2220 532 gpio_init_structure.Pin = QSPI_CLK_PIN;
bcostm 0:0002c86c2220 533 gpio_init_structure.Pull = GPIO_NOPULL;
bcostm 0:0002c86c2220 534 gpio_init_structure.Alternate = GPIO_AF9_QSPI;
bcostm 0:0002c86c2220 535 HAL_GPIO_Init(QSPI_CLK_GPIO_PORT, &gpio_init_structure);
bcostm 0:0002c86c2220 536
bcostm 0:0002c86c2220 537 /* QSPI D0 and D1 GPIO pin configuration */
bcostm 0:0002c86c2220 538 gpio_init_structure.Pin = (QSPI_D0_PIN | QSPI_D1_PIN);
bcostm 0:0002c86c2220 539 gpio_init_structure.Alternate = GPIO_AF10_QSPI;
bcostm 0:0002c86c2220 540 HAL_GPIO_Init(QSPI_DX_GPIO_PORT, &gpio_init_structure);
bcostm 0:0002c86c2220 541
bcostm 0:0002c86c2220 542 /* QSPI D2 and D3 GPIO pin configuration */
bcostm 0:0002c86c2220 543 gpio_init_structure.Pin = (QSPI_D2_PIN | QSPI_D3_PIN) ;
bcostm 0:0002c86c2220 544 gpio_init_structure.Alternate = GPIO_AF9_QSPI;
bcostm 0:0002c86c2220 545 HAL_GPIO_Init(QSPI_DX_GPIO_PORT, &gpio_init_structure);
bcostm 0:0002c86c2220 546
bcostm 0:0002c86c2220 547 /*##-3- Configure the NVIC for QSPI #########################################*/
bcostm 0:0002c86c2220 548 /* NVIC configuration for QSPI interrupt */
bcostm 0:0002c86c2220 549 HAL_NVIC_SetPriority(QUADSPI_IRQn, 0x0F, 0);
bcostm 0:0002c86c2220 550 HAL_NVIC_EnableIRQ(QUADSPI_IRQn);
bcostm 0:0002c86c2220 551
bcostm 0:0002c86c2220 552 }
bcostm 0:0002c86c2220 553
bcostm 0:0002c86c2220 554 /**
bcostm 0:0002c86c2220 555 * @brief QSPI MSP De-Initialization
bcostm 0:0002c86c2220 556 * This function frees the hardware resources used in this example:
bcostm 0:0002c86c2220 557 * - Disable the Peripheral's clock
bcostm 0:0002c86c2220 558 * - Revert GPIO and NVIC configuration to their default state
bcostm 0:0002c86c2220 559 * @retval None
bcostm 0:0002c86c2220 560 */
bcostm 0:0002c86c2220 561 __weak void BSP_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi, void *Params)
bcostm 0:0002c86c2220 562 {
bcostm 0:0002c86c2220 563 /*##-1- Disable the NVIC for QSPI ###########################################*/
bcostm 0:0002c86c2220 564 HAL_NVIC_DisableIRQ(QUADSPI_IRQn);
bcostm 0:0002c86c2220 565
bcostm 0:0002c86c2220 566 /*##-2- Disable peripherals and GPIO Clocks ################################*/
bcostm 0:0002c86c2220 567 /* De-Configure QSPI pins */
bcostm 0:0002c86c2220 568 HAL_GPIO_DeInit(QSPI_CS_GPIO_PORT, QSPI_CS_PIN);
bcostm 0:0002c86c2220 569 HAL_GPIO_DeInit(QSPI_CLK_GPIO_PORT, QSPI_CLK_PIN);
bcostm 0:0002c86c2220 570 HAL_GPIO_DeInit(QSPI_DX_GPIO_PORT, QSPI_D0_PIN);
bcostm 0:0002c86c2220 571 HAL_GPIO_DeInit(QSPI_DX_GPIO_PORT, QSPI_D1_PIN);
bcostm 0:0002c86c2220 572 HAL_GPIO_DeInit(QSPI_DX_GPIO_PORT, QSPI_D2_PIN);
bcostm 0:0002c86c2220 573 HAL_GPIO_DeInit(QSPI_DX_GPIO_PORT, QSPI_D3_PIN);
bcostm 0:0002c86c2220 574
bcostm 0:0002c86c2220 575 /*##-3- Reset peripherals ##################################################*/
bcostm 0:0002c86c2220 576 /* Reset the QuadSPI memory interface */
bcostm 0:0002c86c2220 577 QSPI_FORCE_RESET();
bcostm 0:0002c86c2220 578 QSPI_RELEASE_RESET();
bcostm 0:0002c86c2220 579
bcostm 0:0002c86c2220 580 /* Disable the QuadSPI memory interface clock */
bcostm 0:0002c86c2220 581 QSPI_CLK_DISABLE();
bcostm 0:0002c86c2220 582 }
bcostm 0:0002c86c2220 583
bcostm 0:0002c86c2220 584 /**
bcostm 0:0002c86c2220 585 * @brief This function reset the QSPI memory.
bcostm 0:0002c86c2220 586 * @param hqspi: QSPI handle
bcostm 0:0002c86c2220 587 * @retval None
bcostm 0:0002c86c2220 588 */
bcostm 0:0002c86c2220 589 static uint8_t QSPI_ResetMemory(QSPI_HandleTypeDef *hqspi)
bcostm 0:0002c86c2220 590 {
bcostm 0:0002c86c2220 591 QSPI_CommandTypeDef s_command;
bcostm 0:0002c86c2220 592
bcostm 0:0002c86c2220 593 /* Initialize the reset enable command */
bcostm 0:0002c86c2220 594 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 0:0002c86c2220 595 s_command.Instruction = RESET_ENABLE_CMD;
bcostm 0:0002c86c2220 596 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 0:0002c86c2220 597 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 0:0002c86c2220 598 s_command.DataMode = QSPI_DATA_NONE;
bcostm 0:0002c86c2220 599 s_command.DummyCycles = 0;
bcostm 0:0002c86c2220 600 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 0:0002c86c2220 601 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 0:0002c86c2220 602 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 0:0002c86c2220 603
bcostm 0:0002c86c2220 604 /* Send the command */
bcostm 0:0002c86c2220 605 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 606 {
bcostm 0:0002c86c2220 607 return QSPI_ERROR;
bcostm 0:0002c86c2220 608 }
bcostm 0:0002c86c2220 609
bcostm 0:0002c86c2220 610 /* Send the reset memory command */
bcostm 0:0002c86c2220 611 s_command.Instruction = RESET_MEMORY_CMD;
bcostm 0:0002c86c2220 612 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 613 {
bcostm 0:0002c86c2220 614 return QSPI_ERROR;
bcostm 0:0002c86c2220 615 }
bcostm 0:0002c86c2220 616
bcostm 0:0002c86c2220 617 /* Configure automatic polling mode to wait the memory is ready */
bcostm 0:0002c86c2220 618 if (QSPI_AutoPollingMemReady(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != QSPI_OK)
bcostm 0:0002c86c2220 619 {
bcostm 0:0002c86c2220 620 return QSPI_ERROR;
bcostm 0:0002c86c2220 621 }
bcostm 0:0002c86c2220 622
bcostm 0:0002c86c2220 623 return QSPI_OK;
bcostm 0:0002c86c2220 624 }
bcostm 0:0002c86c2220 625
bcostm 0:0002c86c2220 626 /**
bcostm 0:0002c86c2220 627 * @brief This function configure the dummy cycles on memory side.
bcostm 0:0002c86c2220 628 * @param hqspi: QSPI handle
bcostm 0:0002c86c2220 629 * @retval None
bcostm 0:0002c86c2220 630 */
bcostm 0:0002c86c2220 631 static uint8_t QSPI_DummyCyclesCfg(QSPI_HandleTypeDef *hqspi)
bcostm 0:0002c86c2220 632 {
bcostm 0:0002c86c2220 633 QSPI_CommandTypeDef s_command;
bcostm 0:0002c86c2220 634 uint8_t reg;
bcostm 0:0002c86c2220 635
bcostm 0:0002c86c2220 636 /* Initialize the read volatile configuration register command */
bcostm 0:0002c86c2220 637 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 0:0002c86c2220 638 s_command.Instruction = READ_VOL_CFG_REG_CMD;
bcostm 0:0002c86c2220 639 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 0:0002c86c2220 640 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 0:0002c86c2220 641 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 0:0002c86c2220 642 s_command.DummyCycles = 0;
bcostm 0:0002c86c2220 643 s_command.NbData = 1;
bcostm 0:0002c86c2220 644 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 0:0002c86c2220 645 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 0:0002c86c2220 646 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 0:0002c86c2220 647
bcostm 0:0002c86c2220 648 /* Configure the command */
bcostm 0:0002c86c2220 649 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 650 {
bcostm 0:0002c86c2220 651 return QSPI_ERROR;
bcostm 0:0002c86c2220 652 }
bcostm 0:0002c86c2220 653
bcostm 0:0002c86c2220 654 /* Reception of the data */
bcostm 0:0002c86c2220 655 if (HAL_QSPI_Receive(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 656 {
bcostm 0:0002c86c2220 657 return QSPI_ERROR;
bcostm 0:0002c86c2220 658 }
bcostm 0:0002c86c2220 659
bcostm 0:0002c86c2220 660 /* Enable write operations */
bcostm 0:0002c86c2220 661 if (QSPI_WriteEnable(hqspi) != QSPI_OK)
bcostm 0:0002c86c2220 662 {
bcostm 0:0002c86c2220 663 return QSPI_ERROR;
bcostm 0:0002c86c2220 664 }
bcostm 0:0002c86c2220 665
bcostm 0:0002c86c2220 666 /* Update volatile configuration register (with new dummy cycles) */
bcostm 0:0002c86c2220 667 s_command.Instruction = WRITE_VOL_CFG_REG_CMD;
bcostm 0:0002c86c2220 668 MODIFY_REG(reg, N25Q128A_VCR_NB_DUMMY, (N25Q128A_DUMMY_CYCLES_READ_QUAD << POSITION_VAL(N25Q128A_VCR_NB_DUMMY)));
bcostm 0:0002c86c2220 669
bcostm 0:0002c86c2220 670 /* Configure the write volatile configuration register command */
bcostm 0:0002c86c2220 671 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 672 {
bcostm 0:0002c86c2220 673 return QSPI_ERROR;
bcostm 0:0002c86c2220 674 }
bcostm 0:0002c86c2220 675
bcostm 0:0002c86c2220 676 /* Transmission of the data */
bcostm 0:0002c86c2220 677 if (HAL_QSPI_Transmit(hqspi, &reg, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 678 {
bcostm 0:0002c86c2220 679 return QSPI_ERROR;
bcostm 0:0002c86c2220 680 }
bcostm 0:0002c86c2220 681
bcostm 0:0002c86c2220 682 return QSPI_OK;
bcostm 0:0002c86c2220 683 }
bcostm 0:0002c86c2220 684
bcostm 0:0002c86c2220 685 /**
bcostm 0:0002c86c2220 686 * @brief This function send a Write Enable and wait it is effective.
bcostm 0:0002c86c2220 687 * @param hqspi: QSPI handle
bcostm 0:0002c86c2220 688 * @retval None
bcostm 0:0002c86c2220 689 */
bcostm 0:0002c86c2220 690 static uint8_t QSPI_WriteEnable(QSPI_HandleTypeDef *hqspi)
bcostm 0:0002c86c2220 691 {
bcostm 0:0002c86c2220 692 QSPI_CommandTypeDef s_command;
bcostm 0:0002c86c2220 693 QSPI_AutoPollingTypeDef s_config;
bcostm 0:0002c86c2220 694
bcostm 0:0002c86c2220 695 /* Enable write operations */
bcostm 0:0002c86c2220 696 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 0:0002c86c2220 697 s_command.Instruction = WRITE_ENABLE_CMD;
bcostm 0:0002c86c2220 698 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 0:0002c86c2220 699 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 0:0002c86c2220 700 s_command.DataMode = QSPI_DATA_NONE;
bcostm 0:0002c86c2220 701 s_command.DummyCycles = 0;
bcostm 0:0002c86c2220 702 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 0:0002c86c2220 703 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 0:0002c86c2220 704 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 0:0002c86c2220 705
bcostm 0:0002c86c2220 706 if (HAL_QSPI_Command(hqspi, &s_command, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 707 {
bcostm 0:0002c86c2220 708 return QSPI_ERROR;
bcostm 0:0002c86c2220 709 }
bcostm 0:0002c86c2220 710
bcostm 0:0002c86c2220 711 /* Configure automatic polling mode to wait for write enabling */
bcostm 0:0002c86c2220 712 s_config.Match = N25Q128A_SR_WREN;
bcostm 0:0002c86c2220 713 s_config.Mask = N25Q128A_SR_WREN;
bcostm 0:0002c86c2220 714 s_config.MatchMode = QSPI_MATCH_MODE_AND;
bcostm 0:0002c86c2220 715 s_config.StatusBytesSize = 1;
bcostm 0:0002c86c2220 716 s_config.Interval = 0x10;
bcostm 0:0002c86c2220 717 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
bcostm 0:0002c86c2220 718
bcostm 0:0002c86c2220 719 s_command.Instruction = READ_STATUS_REG_CMD;
bcostm 0:0002c86c2220 720 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 0:0002c86c2220 721
bcostm 0:0002c86c2220 722 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
bcostm 0:0002c86c2220 723 {
bcostm 0:0002c86c2220 724 return QSPI_ERROR;
bcostm 0:0002c86c2220 725 }
bcostm 0:0002c86c2220 726
bcostm 0:0002c86c2220 727 return QSPI_OK;
bcostm 0:0002c86c2220 728 }
bcostm 0:0002c86c2220 729
bcostm 0:0002c86c2220 730 /**
bcostm 0:0002c86c2220 731 * @brief This function read the SR of the memory and wait the EOP.
bcostm 0:0002c86c2220 732 * @param hqspi: QSPI handle
bcostm 0:0002c86c2220 733 * @param Timeout: timeout value before returning an error
bcostm 0:0002c86c2220 734 * @retval None
bcostm 0:0002c86c2220 735 */
bcostm 0:0002c86c2220 736 static uint8_t QSPI_AutoPollingMemReady(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
bcostm 0:0002c86c2220 737 {
bcostm 0:0002c86c2220 738 QSPI_CommandTypeDef s_command;
bcostm 0:0002c86c2220 739 QSPI_AutoPollingTypeDef s_config;
bcostm 0:0002c86c2220 740
bcostm 0:0002c86c2220 741 /* Configure automatic polling mode to wait for memory ready */
bcostm 0:0002c86c2220 742 s_command.InstructionMode = QSPI_INSTRUCTION_1_LINE;
bcostm 0:0002c86c2220 743 s_command.Instruction = READ_STATUS_REG_CMD;
bcostm 0:0002c86c2220 744 s_command.AddressMode = QSPI_ADDRESS_NONE;
bcostm 0:0002c86c2220 745 s_command.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE;
bcostm 0:0002c86c2220 746 s_command.DataMode = QSPI_DATA_1_LINE;
bcostm 0:0002c86c2220 747 s_command.DummyCycles = 0;
bcostm 0:0002c86c2220 748 s_command.DdrMode = QSPI_DDR_MODE_DISABLE;
bcostm 0:0002c86c2220 749 s_command.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY;
bcostm 0:0002c86c2220 750 s_command.SIOOMode = QSPI_SIOO_INST_EVERY_CMD;
bcostm 0:0002c86c2220 751
bcostm 0:0002c86c2220 752 s_config.Match = 0;
bcostm 0:0002c86c2220 753 s_config.Mask = N25Q128A_SR_WIP;
bcostm 0:0002c86c2220 754 s_config.MatchMode = QSPI_MATCH_MODE_AND;
bcostm 0:0002c86c2220 755 s_config.StatusBytesSize = 1;
bcostm 0:0002c86c2220 756 s_config.Interval = 0x10;
bcostm 0:0002c86c2220 757 s_config.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE;
bcostm 0:0002c86c2220 758
bcostm 0:0002c86c2220 759 if (HAL_QSPI_AutoPolling(hqspi, &s_command, &s_config, Timeout) != HAL_OK)
bcostm 0:0002c86c2220 760 {
bcostm 0:0002c86c2220 761 return QSPI_ERROR;
bcostm 0:0002c86c2220 762 }
bcostm 0:0002c86c2220 763
bcostm 0:0002c86c2220 764 return QSPI_OK;
bcostm 0:0002c86c2220 765 }
bcostm 0:0002c86c2220 766 /**
bcostm 0:0002c86c2220 767 * @}
bcostm 0:0002c86c2220 768 */
bcostm 0:0002c86c2220 769
bcostm 0:0002c86c2220 770 /**
bcostm 0:0002c86c2220 771 * @}
bcostm 0:0002c86c2220 772 */
bcostm 0:0002c86c2220 773
bcostm 0:0002c86c2220 774 /**
bcostm 0:0002c86c2220 775 * @}
bcostm 0:0002c86c2220 776 */
bcostm 0:0002c86c2220 777
bcostm 0:0002c86c2220 778 /**
bcostm 0:0002c86c2220 779 * @}
bcostm 0:0002c86c2220 780 */
bcostm 0:0002c86c2220 781
bcostm 0:0002c86c2220 782 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bcostm 0:0002c86c2220 783