stm32469i_discovery_sdram.c

00001 /**
00002   ******************************************************************************
00003   * @file    stm32469i_discovery_sdram.c
00004   * @author  MCD Application Team
00005   * @version V2.0.0
00006   * @date    27-January-2017
00007   * @brief   This file includes the SDRAM driver for the MT48LC4M32B2B5-7 memory
00008   *          device mounted on STM32469I-Discovery board.
00009   ******************************************************************************
00010   * @attention
00011   *
00012   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00013   *
00014   * Redistribution and use in source and binary forms, with or without modification,
00015   * are permitted provided that the following conditions are met:
00016   *   1. Redistributions of source code must retain the above copyright notice,
00017   *      this list of conditions and the following disclaimer.
00018   *   2. Redistributions in binary form must reproduce the above copyright notice,
00019   *      this list of conditions and the following disclaimer in the documentation
00020   *      and/or other materials provided with the distribution.
00021   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00022   *      may be used to endorse or promote products derived from this software
00023   *      without specific prior written permission.
00024   *
00025   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00026   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00027   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00028   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00029   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00030   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00031   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00032   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00033   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00034   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00035   *
00036   ******************************************************************************
00037   */
00038 
00039 /* File Info : -----------------------------------------------------------------
00040                                    User NOTES
00041 1. How To use this driver:
00042 --------------------------
00043    - This driver is used to drive the MT48LC4M32B2B5-7 SDRAM external memory mounted
00044      on STM32469I-Discovery board.
00045    - This driver does not need a specific component driver for the SDRAM device
00046      to be included with.
00047 
00048 2. Driver description:
00049 ---------------------
00050   + Initialization steps:
00051      o Initialize the SDRAM external memory using the BSP_SDRAM_Init() function. This
00052        function includes the MSP layer hardware resources initialization and the
00053        FMC controller configuration to interface with the external SDRAM memory.
00054      o It contains the SDRAM initialization sequence to program the SDRAM external
00055        device using the function BSP_SDRAM_Initialization_sequence(). Note that this
00056        sequence is standard for all SDRAM devices, but can include some differences
00057        from a device to another. If it is the case, the right sequence should be
00058        implemented separately.
00059 
00060   + SDRAM read/write operations
00061      o SDRAM external memory can be accessed with read/write operations once it is
00062        initialized.
00063        Read/write operation can be performed with AHB access using the functions
00064        BSP_SDRAM_ReadData()/BSP_SDRAM_WriteData(), or by DMA transfer using the functions
00065        BSP_SDRAM_ReadData_DMA()/BSP_SDRAM_WriteData_DMA().
00066      o The AHB access is performed with 32-bit width transaction, the DMA transfer
00067        configuration is fixed at single (no burst) word transfer (see the
00068        BSP_SDRAM_MspInit() weak function).
00069      o User can implement his own functions for read/write access with his desired
00070        configurations.
00071      o If interrupt mode is used for DMA transfer, the function BSP_SDRAM_DMA_IRQHandler()
00072        is called in IRQ handler file, to serve the generated interrupt once the DMA
00073        transfer is complete.
00074      o You can send a command to the SDRAM device in runtime using the function
00075        BSP_SDRAM_Sendcmd(), and giving the desired command as parameter chosen between
00076        the predefined commands of the "FMC_SDRAM_CommandTypeDef" structure.
00077 
00078 ------------------------------------------------------------------------------*/
00079 
00080 /* Includes ------------------------------------------------------------------*/
00081 #include "stm32469i_discovery_sdram.h"
00082 
00083 // mbed
00084 void wait_ms(int ms);
00085 
00086 /** @addtogroup BSP
00087   * @{
00088   */
00089 
00090 /** @addtogroup STM32469I_Discovery
00091   * @{
00092   */
00093 
00094 /** @defgroup STM32469I-Discovery_SDRAM STM32469I Discovery SDRAM
00095   * @{
00096   */
00097 
00098 /** @defgroup STM32469I-Discovery_SDRAM_Private_Types_Definitions STM32469I Discovery SDRAM Private TypesDef
00099   * @{
00100   */
00101 /**
00102   * @}
00103   */
00104 
00105 /** @defgroup STM32469I-Discovery_SDRAM_Private_Defines STM32469I Discovery SDRAM Private Defines
00106   * @{
00107   */
00108 /**
00109   * @}
00110   */
00111 
00112 /** @defgroup STM32469I-Discovery_SDRAM_Private_Macros STM32469I Discovery SDRAM Private Macros
00113   * @{
00114   */
00115 /**
00116   * @}
00117   */
00118 
00119 /** @defgroup STM32469I-Discovery_SDRAM_Private_Variables STM32469I Discovery SDRAM Private Variables
00120   * @{
00121   */
00122 static SDRAM_HandleTypeDef sdramHandle;
00123 static FMC_SDRAM_TimingTypeDef Timing;
00124 static FMC_SDRAM_CommandTypeDef Command;
00125 /**
00126   * @}
00127   */
00128 
00129 /** @defgroup STM32469I-Discovery_SDRAM_Private_Function_Prototypes STM32469I Discovery SDRAM Private Prototypes
00130   * @{
00131   */
00132 
00133 /**
00134   * @}
00135   */
00136 
00137 /** @defgroup STM32469I-Discovery_SDRAM_Private_Functions STM32469I Discovery SDRAM Private Functions
00138   * @{
00139   */
00140 
00141 /**
00142   * @}
00143   */
00144 
00145 /** @defgroup STM32469I_Discovery_SDRAM_Exported_Functions STM32469I Discovery SDRAM Exported Functions
00146   * @{
00147   */
00148 
00149 /**
00150   * @brief  Initializes the SDRAM device.
00151   * @retval SDRAM status
00152   */
00153 uint8_t BSP_SDRAM_Init(void)
00154 {
00155   static uint8_t sdramstatus = SDRAM_ERROR;
00156 
00157   /* SDRAM device configuration */
00158   sdramHandle.Instance = FMC_SDRAM_DEVICE;
00159 
00160   /* Timing configuration for 90 MHz as SD clock frequency (System clock is up to 180 MHz) */
00161   Timing.LoadToActiveDelay    = 2;
00162   Timing.ExitSelfRefreshDelay = 7;
00163   Timing.SelfRefreshTime      = 4;
00164   Timing.RowCycleDelay        = 7;
00165   Timing.WriteRecoveryTime    = 2;
00166   Timing.RPDelay              = 2;
00167   Timing.RCDDelay             = 2;
00168 
00169   sdramHandle.Init.SDBank             = FMC_SDRAM_BANK1;
00170   sdramHandle.Init.ColumnBitsNumber   = FMC_SDRAM_COLUMN_BITS_NUM_8;
00171   sdramHandle.Init.RowBitsNumber      = FMC_SDRAM_ROW_BITS_NUM_12;
00172   sdramHandle.Init.MemoryDataWidth    = SDRAM_MEMORY_WIDTH;
00173   sdramHandle.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
00174   sdramHandle.Init.CASLatency         = FMC_SDRAM_CAS_LATENCY_3;
00175   sdramHandle.Init.WriteProtection    = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
00176   sdramHandle.Init.SDClockPeriod      = SDCLOCK_PERIOD;
00177   sdramHandle.Init.ReadBurst          = FMC_SDRAM_RBURST_ENABLE;
00178   sdramHandle.Init.ReadPipeDelay      = FMC_SDRAM_RPIPE_DELAY_0;
00179 
00180   /* SDRAM controller initialization */
00181   /* __weak function can be surcharged by the application code */
00182   BSP_SDRAM_MspInit(&sdramHandle, (void *)NULL);
00183   if(HAL_SDRAM_Init(&sdramHandle, &Timing) != HAL_OK)
00184   {
00185     sdramstatus = SDRAM_ERROR;
00186   }
00187   else
00188   {
00189     sdramstatus = SDRAM_OK;
00190   }
00191 
00192   /* SDRAM initialization sequence */
00193   BSP_SDRAM_Initialization_sequence(REFRESH_COUNT);
00194 
00195   return sdramstatus;
00196 }
00197 
00198 /**
00199   * @brief  DeInitializes the SDRAM device.
00200   * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
00201   */
00202 uint8_t BSP_SDRAM_DeInit(void)
00203 {
00204   static uint8_t sdramstatus = SDRAM_ERROR;
00205 
00206   /* SDRAM device configuration */
00207   sdramHandle.Instance = FMC_SDRAM_DEVICE;
00208 
00209   if(HAL_SDRAM_DeInit(&sdramHandle) == HAL_OK)
00210   {
00211     sdramstatus = SDRAM_OK;
00212 
00213   /* SDRAM controller De-initialization */
00214    BSP_SDRAM_MspDeInit(&sdramHandle, (void *)NULL);
00215   }
00216 
00217   return sdramstatus;
00218 }
00219 
00220 
00221 /**
00222   * @brief  Programs the SDRAM device.
00223   * @param  RefreshCount: SDRAM refresh counter value
00224   */
00225 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount)
00226 {
00227   __IO uint32_t tmpmrd = 0;
00228 
00229   /* Step 1: Configure a clock configuration enable command */
00230   Command.CommandMode            = FMC_SDRAM_CMD_CLK_ENABLE;
00231   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00232   Command.AutoRefreshNumber      = 1;
00233   Command.ModeRegisterDefinition = 0;
00234 
00235   /* Send the command */
00236   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00237 
00238   /* Step 2: Insert 100 us minimum delay */
00239   /* Inserted delay is equal to 1 ms due to systick time base unit (ms) */
00240   //HAL_Delay(1);
00241   wait_ms(1);
00242 
00243   /* Step 3: Configure a PALL (precharge all) command */
00244   Command.CommandMode            = FMC_SDRAM_CMD_PALL;
00245   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00246   Command.AutoRefreshNumber      = 1;
00247   Command.ModeRegisterDefinition = 0;
00248 
00249   /* Send the command */
00250   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00251 
00252   /* Step 4: Configure an Auto Refresh command */
00253   Command.CommandMode            = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
00254   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00255   Command.AutoRefreshNumber      = 8;
00256   Command.ModeRegisterDefinition = 0;
00257 
00258   /* Send the command */
00259   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00260 
00261   /* Step 5: Program the external memory mode register */
00262   tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_1          |\
00263                      SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL   |\
00264                      SDRAM_MODEREG_CAS_LATENCY_3           |\
00265                      SDRAM_MODEREG_OPERATING_MODE_STANDARD |\
00266                      SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
00267 
00268   Command.CommandMode            = FMC_SDRAM_CMD_LOAD_MODE;
00269   Command.CommandTarget          = FMC_SDRAM_CMD_TARGET_BANK1;
00270   Command.AutoRefreshNumber      = 1;
00271   Command.ModeRegisterDefinition = tmpmrd;
00272 
00273   /* Send the command */
00274   HAL_SDRAM_SendCommand(&sdramHandle, &Command, SDRAM_TIMEOUT);
00275 
00276   /* Step 6: Set the refresh rate counter */
00277   /* Set the device refresh rate */
00278   HAL_SDRAM_ProgramRefreshRate(&sdramHandle, RefreshCount);
00279 }
00280 
00281 /**
00282   * @brief  Reads an mount of data from the SDRAM memory in polling mode.
00283   * @param  uwStartAddress: Read start address
00284   * @param  pData: Pointer to data to be read
00285   * @param  uwDataSize: Size of read data from the memory
00286   * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
00287   */
00288 uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00289 {
00290   if(HAL_SDRAM_Read_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00291   {
00292     return SDRAM_ERROR;
00293   }
00294   else
00295   {
00296     return SDRAM_OK;
00297   }
00298 }
00299 
00300 /**
00301   * @brief  Reads an mount of data from the SDRAM memory in DMA mode.
00302   * @param  uwStartAddress: Read start address
00303   * @param  pData: Pointer to data to be read
00304   * @param  uwDataSize: Size of read data from the memory
00305   * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
00306   */
00307 uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00308 {
00309   if(HAL_SDRAM_Read_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00310   {
00311     return SDRAM_ERROR;
00312   }
00313   else
00314   {
00315     return SDRAM_OK;
00316   }
00317 }
00318 
00319 /**
00320   * @brief  Writes an mount of data to the SDRAM memory in polling mode.
00321   * @param  uwStartAddress: Write start address
00322   * @param  pData: Pointer to data to be written
00323   * @param  uwDataSize: Size of written data from the memory
00324   * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
00325   */
00326 uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00327 {
00328   if(HAL_SDRAM_Write_32b(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00329   {
00330     return SDRAM_ERROR;
00331   }
00332   else
00333   {
00334     return SDRAM_OK;
00335   }
00336 }
00337 
00338 /**
00339   * @brief  Writes an mount of data to the SDRAM memory in DMA mode.
00340   * @param  uwStartAddress: Write start address
00341   * @param  pData: Pointer to data to be written
00342   * @param  uwDataSize: Size of written data from the memory
00343   * @retval SDRAM status : SDRAM_OK or SDRAM_ERROR.
00344   */
00345 uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t *pData, uint32_t uwDataSize)
00346 {
00347   if(HAL_SDRAM_Write_DMA(&sdramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
00348   {
00349     return SDRAM_ERROR;
00350   }
00351   else
00352   {
00353     return SDRAM_OK;
00354   }
00355 }
00356 
00357 /**
00358   * @brief  Sends command to the SDRAM bank.
00359   * @param  SdramCmd: Pointer to SDRAM command structure
00360   * @retval HAL status : SDRAM_OK or SDRAM_ERROR.
00361   */
00362 uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd)
00363 {
00364   if(HAL_SDRAM_SendCommand(&sdramHandle, SdramCmd, SDRAM_TIMEOUT) != HAL_OK)
00365   {
00366     return SDRAM_ERROR;
00367   }
00368   else
00369   {
00370     return SDRAM_OK;
00371   }
00372 }
00373 
00374 /**
00375   * @brief  Handles SDRAM DMA transfer interrupt request.
00376   */
00377 void BSP_SDRAM_DMA_IRQHandler(void)
00378 {
00379   HAL_DMA_IRQHandler(sdramHandle.hdma);
00380 }
00381 
00382 /**
00383   * @brief  Initializes SDRAM MSP.
00384   * @note   This function can be surcharged by application code.
00385   * @param  hsdram: pointer on SDRAM handle
00386   * @param  Params: pointer on additional configuration parameters, can be NULL.
00387   */
00388 __weak void BSP_SDRAM_MspInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
00389 {
00390   static DMA_HandleTypeDef dma_handle;
00391   GPIO_InitTypeDef gpio_init_structure;
00392 
00393   if(hsdram != (SDRAM_HandleTypeDef  *)NULL)
00394   {
00395     /* Enable FMC clock */
00396     __HAL_RCC_FMC_CLK_ENABLE();
00397 
00398     /* Enable chosen DMAx clock */
00399     __DMAx_CLK_ENABLE();
00400 
00401     /* Enable GPIOs clock */
00402     __HAL_RCC_GPIOC_CLK_ENABLE();
00403     __HAL_RCC_GPIOD_CLK_ENABLE();
00404     __HAL_RCC_GPIOE_CLK_ENABLE();
00405     __HAL_RCC_GPIOF_CLK_ENABLE();
00406     __HAL_RCC_GPIOG_CLK_ENABLE();
00407     __HAL_RCC_GPIOH_CLK_ENABLE();
00408     __HAL_RCC_GPIOI_CLK_ENABLE();
00409 
00410     /* Common GPIO configuration */
00411     gpio_init_structure.Mode      = GPIO_MODE_AF_PP;
00412     gpio_init_structure.Pull      = GPIO_PULLUP;
00413     gpio_init_structure.Speed     = GPIO_SPEED_FAST;
00414     gpio_init_structure.Alternate = GPIO_AF12_FMC;
00415 
00416     /* GPIOC configuration : PC0 is SDNWE */
00417     gpio_init_structure.Pin   = GPIO_PIN_0;
00418     HAL_GPIO_Init(GPIOC, &gpio_init_structure);
00419 
00420     /* GPIOD configuration */
00421     gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_8| GPIO_PIN_9 | GPIO_PIN_10 |\
00422                                 GPIO_PIN_14 | GPIO_PIN_15;
00423 
00424 
00425     HAL_GPIO_Init(GPIOD, &gpio_init_structure);
00426 
00427     /* GPIOE configuration */
00428     gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_7| GPIO_PIN_8 | GPIO_PIN_9 |\
00429                                 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00430                                 GPIO_PIN_15;
00431 
00432     HAL_GPIO_Init(GPIOE, &gpio_init_structure);
00433 
00434     /* GPIOF configuration */
00435     gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
00436                                 GPIO_PIN_5 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00437                                 GPIO_PIN_15;
00438 
00439     HAL_GPIO_Init(GPIOF, &gpio_init_structure);
00440 
00441     /* GPIOG configuration */
00442     gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4| GPIO_PIN_5 | GPIO_PIN_8 |\
00443                                 GPIO_PIN_15;
00444     HAL_GPIO_Init(GPIOG, &gpio_init_structure);
00445 
00446     /* GPIOH configuration */
00447     gpio_init_structure.Pin   = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_8 | GPIO_PIN_9 |\
00448                                 GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 |\
00449                                 GPIO_PIN_15;
00450     HAL_GPIO_Init(GPIOH, &gpio_init_structure);
00451 
00452     /* GPIOI configuration */
00453     gpio_init_structure.Pin   = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 |\
00454                                 GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_9 | GPIO_PIN_10;
00455     HAL_GPIO_Init(GPIOI, &gpio_init_structure);
00456 
00457     /* Configure common DMA parameters */
00458     dma_handle.Init.Channel             = SDRAM_DMAx_CHANNEL;
00459     dma_handle.Init.Direction           = DMA_MEMORY_TO_MEMORY;
00460     dma_handle.Init.PeriphInc           = DMA_PINC_ENABLE;
00461     dma_handle.Init.MemInc              = DMA_MINC_ENABLE;
00462     dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD;
00463     dma_handle.Init.MemDataAlignment    = DMA_MDATAALIGN_WORD;
00464     dma_handle.Init.Mode                = DMA_NORMAL;
00465     dma_handle.Init.Priority            = DMA_PRIORITY_HIGH;
00466     dma_handle.Init.FIFOMode            = DMA_FIFOMODE_DISABLE;
00467     dma_handle.Init.FIFOThreshold       = DMA_FIFO_THRESHOLD_FULL;
00468     dma_handle.Init.MemBurst            = DMA_MBURST_SINGLE;
00469     dma_handle.Init.PeriphBurst         = DMA_PBURST_SINGLE;
00470 
00471     dma_handle.Instance = SDRAM_DMAx_STREAM;
00472 
00473     /* Associate the DMA handle */
00474     __HAL_LINKDMA(hsdram, hdma, dma_handle);
00475 
00476     /* Deinitialize the stream for new transfer */
00477     HAL_DMA_DeInit(&dma_handle);
00478 
00479     /* Configure the DMA stream */
00480     HAL_DMA_Init(&dma_handle);
00481 
00482     /* NVIC configuration for DMA transfer complete interrupt */
00483     HAL_NVIC_SetPriority(SDRAM_DMAx_IRQn, 5, 0);
00484     HAL_NVIC_EnableIRQ(SDRAM_DMAx_IRQn);
00485 
00486   } /* of if(hsdram != (SDRAM_HandleTypeDef  *)NULL) */
00487 }
00488 
00489 /**
00490   * @brief  DeInitializes SDRAM MSP.
00491   * @note   This function can be surcharged by application code.
00492   * @param  hsdram: pointer on SDRAM handle
00493   * @param  Params: pointer on additional configuration parameters, can be NULL.
00494   */
00495 __weak void BSP_SDRAM_MspDeInit(SDRAM_HandleTypeDef  *hsdram, void *Params)
00496 {
00497     static DMA_HandleTypeDef dma_handle;
00498 
00499     if(hsdram != (SDRAM_HandleTypeDef  *)NULL)
00500     {
00501       /* Disable NVIC configuration for DMA interrupt */
00502       HAL_NVIC_DisableIRQ(SDRAM_DMAx_IRQn);
00503 
00504       /* Deinitialize the stream for new transfer */
00505       dma_handle.Instance = SDRAM_DMAx_STREAM;
00506       HAL_DMA_DeInit(&dma_handle);
00507 
00508       /* DeInit GPIO pins can be done in the application
00509        (by surcharging this __weak function) */
00510 
00511       /* GPIO pins clock, FMC clock and DMA clock can be shut down in the application
00512        by surcharging this __weak function */
00513 
00514     } /* of if(hsdram != (SDRAM_HandleTypeDef  *)NULL) */
00515 }
00516 
00517 /**
00518   * @}
00519   */
00520 
00521 /**
00522   * @}
00523   */
00524 
00525 /**
00526   * @}
00527   */
00528 
00529 /**
00530   * @}
00531   */
00532 
00533 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/