Francisco Martin / Mbed 2 deprecated n64

The Nintendo 64 Controller Interface is an mbed library that allows one or more Nintendo 64 controllers to be used as input devices for the mbed. With this library, one will be able to control games created for an mbed using a Nintendo 64 controller. In addition, the library can easily be used to forward N64 inputs to a computer. Using the N64 Controller executable, one can communicate with multiple controllers.

Dependencies:   mbed

N64Controller/my_wait_us_asm.s@0:95064759a964, 2016-04-28 (annotated)

Committer:
fomartin
Date:
Thu Apr 28 00:10:38 2016 +0000
Revision:
0:95064759a964
N64 Controller Interface;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
fomartin 0:95064759a964 1 AREA asm_func, CODE, READONLY
fomartin 0:95064759a964 2 EXPORT my_wait_us_asm
fomartin 0:95064759a964 3
fomartin 0:95064759a964 4 my_wait_us_asm
fomartin 0:95064759a964 5
fomartin 0:95064759a964 6 WAIT_1_US
fomartin 0:95064759a964 7 ; According to ARM spec, NOPs may be removed by the assembler, so they
fomartin 0:95064759a964 8 ; are not a reliable way to eat up time. Instead we simply do empty adds
fomartin 0:95064759a964 9 ; to eat up clock cycles.
fomartin 0:95064759a964 10
fomartin 0:95064759a964 11 ; The LPC1768 operates at 96 MHz. Assuming each instruction is 1 clock cycle,
fomartin 0:95064759a964 12 ; 96 instructions should take 1 microsecond
fomartin 0:95064759a964 13
fomartin 0:95064759a964 14 ADD R1, R2, #0 ; clock cycle 1
fomartin 0:95064759a964 15 ADD R1, R2, #0
fomartin 0:95064759a964 16 ADD R1, R2, #0
fomartin 0:95064759a964 17 ADD R1, R2, #0
fomartin 0:95064759a964 18 ADD R1, R2, #0
fomartin 0:95064759a964 19 ADD R1, R2, #0
fomartin 0:95064759a964 20 ADD R1, R2, #0
fomartin 0:95064759a964 21 ADD R1, R2, #0
fomartin 0:95064759a964 22 ADD R1, R2, #0
fomartin 0:95064759a964 23 ADD R1, R2, #0 ; clock cycle 10
fomartin 0:95064759a964 24 ADD R1, R2, #0
fomartin 0:95064759a964 25 ADD R1, R2, #0
fomartin 0:95064759a964 26 ADD R1, R2, #0
fomartin 0:95064759a964 27 ADD R1, R2, #0
fomartin 0:95064759a964 28 ADD R1, R2, #0
fomartin 0:95064759a964 29 ADD R1, R2, #0
fomartin 0:95064759a964 30 ADD R1, R2, #0
fomartin 0:95064759a964 31 ADD R1, R2, #0
fomartin 0:95064759a964 32 ADD R1, R2, #0
fomartin 0:95064759a964 33 ADD R1, R2, #0 ; clock cycle 20
fomartin 0:95064759a964 34 ADD R1, R2, #0
fomartin 0:95064759a964 35 ADD R1, R2, #0
fomartin 0:95064759a964 36 ADD R1, R2, #0
fomartin 0:95064759a964 37 ADD R1, R2, #0
fomartin 0:95064759a964 38 ADD R1, R2, #0
fomartin 0:95064759a964 39 ADD R1, R2, #0
fomartin 0:95064759a964 40 ADD R1, R2, #0
fomartin 0:95064759a964 41 ADD R1, R2, #0
fomartin 0:95064759a964 42 ADD R1, R2, #0
fomartin 0:95064759a964 43 ADD R1, R2, #0 ; clock cycle 20
fomartin 0:95064759a964 44 ADD R1, R2, #0
fomartin 0:95064759a964 45 ADD R1, R2, #0
fomartin 0:95064759a964 46 ADD R1, R2, #0
fomartin 0:95064759a964 47 ADD R1, R2, #0
fomartin 0:95064759a964 48 ADD R1, R2, #0
fomartin 0:95064759a964 49 ADD R1, R2, #0
fomartin 0:95064759a964 50 ADD R1, R2, #0
fomartin 0:95064759a964 51 ADD R1, R2, #0
fomartin 0:95064759a964 52 ADD R1, R2, #0
fomartin 0:95064759a964 53 ADD R1, R2, #0 ; clock cycle 30
fomartin 0:95064759a964 54 ADD R1, R2, #0
fomartin 0:95064759a964 55 ADD R1, R2, #0
fomartin 0:95064759a964 56 ADD R1, R2, #0
fomartin 0:95064759a964 57 ADD R1, R2, #0
fomartin 0:95064759a964 58 ADD R1, R2, #0
fomartin 0:95064759a964 59 ADD R1, R2, #0
fomartin 0:95064759a964 60 ADD R1, R2, #0
fomartin 0:95064759a964 61 ADD R1, R2, #0
fomartin 0:95064759a964 62 ADD R1, R2, #0
fomartin 0:95064759a964 63 ADD R1, R2, #0 ; clock cycle 50
fomartin 0:95064759a964 64 ADD R1, R2, #0
fomartin 0:95064759a964 65 ADD R1, R2, #0
fomartin 0:95064759a964 66 ADD R1, R2, #0
fomartin 0:95064759a964 67 ADD R1, R2, #0
fomartin 0:95064759a964 68 ADD R1, R2, #0
fomartin 0:95064759a964 69 ADD R1, R2, #0
fomartin 0:95064759a964 70 ADD R1, R2, #0
fomartin 0:95064759a964 71 ADD R1, R2, #0
fomartin 0:95064759a964 72 ADD R1, R2, #0
fomartin 0:95064759a964 73 ADD R1, R2, #0 ; clock cycle 60
fomartin 0:95064759a964 74 ADD R1, R2, #0
fomartin 0:95064759a964 75 ADD R1, R2, #0
fomartin 0:95064759a964 76 ADD R1, R2, #0
fomartin 0:95064759a964 77 ADD R1, R2, #0
fomartin 0:95064759a964 78 ADD R1, R2, #0
fomartin 0:95064759a964 79 ADD R1, R2, #0
fomartin 0:95064759a964 80 ADD R1, R2, #0
fomartin 0:95064759a964 81 ADD R1, R2, #0
fomartin 0:95064759a964 82 ADD R1, R2, #0
fomartin 0:95064759a964 83 ADD R1, R2, #0 ; clock cycle 70
fomartin 0:95064759a964 84 ADD R1, R2, #0
fomartin 0:95064759a964 85 ADD R1, R2, #0
fomartin 0:95064759a964 86 ADD R1, R2, #0
fomartin 0:95064759a964 87 ADD R1, R2, #0
fomartin 0:95064759a964 88 ADD R1, R2, #0
fomartin 0:95064759a964 89 ADD R1, R2, #0
fomartin 0:95064759a964 90 ADD R1, R2, #0
fomartin 0:95064759a964 91 ADD R1, R2, #0
fomartin 0:95064759a964 92 ADD R1, R2, #0
fomartin 0:95064759a964 93 ADD R1, R2, #0 ; clock cycle 80
fomartin 0:95064759a964 94 ADD R1, R2, #0
fomartin 0:95064759a964 95 ADD R1, R2, #0
fomartin 0:95064759a964 96 ADD R1, R2, #0
fomartin 0:95064759a964 97 ADD R1, R2, #0
fomartin 0:95064759a964 98 ADD R1, R2, #0
fomartin 0:95064759a964 99 ADD R1, R2, #0
fomartin 0:95064759a964 100 ADD R1, R2, #0
fomartin 0:95064759a964 101 ADD R1, R2, #0
fomartin 0:95064759a964 102 ADD R1, R2, #0
fomartin 0:95064759a964 103 ADD R1, R2, #0 ; clock cycle 90
fomartin 0:95064759a964 104 ADD R1, R2, #0
fomartin 0:95064759a964 105 ADD R1, R2, #0
fomartin 0:95064759a964 106 ADD R1, R2, #0
fomartin 0:95064759a964 107 ADD R1, R2, #0 ; clock cycle 94
fomartin 0:95064759a964 108
fomartin 0:95064759a964 109 SUBS R0, R0, #1 ; clock cycle 95
fomartin 0:95064759a964 110 BGT WAIT_1_US ; clock cycle 96
fomartin 0:95064759a964 111
fomartin 0:95064759a964 112 BX LR ; return
fomartin 0:95064759a964 113 END