Francisco Martin
The Nintendo 64 Controller Interface is an mbed library that allows one or more Nintendo 64 controllers to be used as input devices for the mbed. With this library, one will be able to control games created for an mbed using a Nintendo 64 controller. In addition, the library can easily be used to forward N64 inputs to a computer. Using the N64 Controller executable, one can communicate with multiple controllers.
Diff: N64Controller/my_wait_us_asm.s
- Revision:
- 0:95064759a964
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/N64Controller/my_wait_us_asm.s Thu Apr 28 00:10:38 2016 +0000 @@ -0,0 +1,113 @@ + AREA asm_func, CODE, READONLY + EXPORT my_wait_us_asm + +my_wait_us_asm + +WAIT_1_US + ; According to ARM spec, NOPs may be removed by the assembler, so they + ; are not a reliable way to eat up time. Instead we simply do empty adds + ; to eat up clock cycles. + + ; The LPC1768 operates at 96 MHz. Assuming each instruction is 1 clock cycle, + ; 96 instructions should take 1 microsecond + + ADD R1, R2, #0 ; clock cycle 1 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 ; clock cycle 10 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 ; clock cycle 20 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 ; clock cycle 20 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 ; clock cycle 30 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 ; clock cycle 50 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 ; clock cycle 60 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 ; clock cycle 70 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 ; clock cycle 80 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 ; clock cycle 90 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 + ADD R1, R2, #0 ; clock cycle 94 + + SUBS R0, R0, #1 ; clock cycle 95 + BGT WAIT_1_US ; clock cycle 96 + + BX LR ; return + END \ No newline at end of file