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TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:
filartrix
Date:
Wed Apr 08 14:12:53 2015 +0000
Revision:
97:4298809c7c9e
Parent:
93:e188a91d3eaa 
First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**
bogdanm 85:024bf7f99721 2 ******************************************************************************
bogdanm 85:024bf7f99721 3 * @file stm32f0xx_hal_dma.h
bogdanm 85:024bf7f99721 4 * @author MCD Application Team
Kojto 93:e188a91d3eaa 5 * @version V1.2.0
Kojto 93:e188a91d3eaa 6 * @date 11-December-2014
bogdanm 85:024bf7f99721 7 * @brief Header file of DMA HAL module.
bogdanm 85:024bf7f99721 8 ******************************************************************************
bogdanm 85:024bf7f99721 9 * @attention
bogdanm 85:024bf7f99721 10 *
bogdanm 85:024bf7f99721 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 85:024bf7f99721 12 *
bogdanm 85:024bf7f99721 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 85:024bf7f99721 14 * are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 85:024bf7f99721 16 * this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 85:024bf7f99721 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 85:024bf7f99721 19 * and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 85:024bf7f99721 21 * may be used to endorse or promote products derived from this software
bogdanm 85:024bf7f99721 22 * without specific prior written permission.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 85:024bf7f99721 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 85:024bf7f99721 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 85:024bf7f99721 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 85:024bf7f99721 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 85:024bf7f99721 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 85:024bf7f99721 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 85:024bf7f99721 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 34 *
bogdanm 85:024bf7f99721 35 ******************************************************************************
bogdanm 85:024bf7f99721 36 */
bogdanm 85:024bf7f99721 37
bogdanm 85:024bf7f99721 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 85:024bf7f99721 39 #ifndef __STM32F0xx_HAL_DMA_H
bogdanm 85:024bf7f99721 40 #define __STM32F0xx_HAL_DMA_H
bogdanm 85:024bf7f99721 41
bogdanm 85:024bf7f99721 42 #ifdef __cplusplus
bogdanm 85:024bf7f99721 43 extern "C" {
bogdanm 85:024bf7f99721 44 #endif
bogdanm 85:024bf7f99721 45
bogdanm 85:024bf7f99721 46 /* Includes ------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 47 #include "stm32f0xx_hal_def.h"
bogdanm 85:024bf7f99721 48
bogdanm 85:024bf7f99721 49 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 85:024bf7f99721 50 * @{
bogdanm 85:024bf7f99721 51 */
bogdanm 85:024bf7f99721 52
bogdanm 85:024bf7f99721 53 /** @addtogroup DMA
bogdanm 85:024bf7f99721 54 * @{
bogdanm 85:024bf7f99721 55 */
bogdanm 85:024bf7f99721 56
bogdanm 85:024bf7f99721 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58 /** @defgroup DMA_Exported_Types DMA Exported Types
bogdanm 92:4fc01daae5a5 59 * @{
bogdanm 92:4fc01daae5a5 60 */
bogdanm 85:024bf7f99721 61
bogdanm 85:024bf7f99721 62 /**
bogdanm 85:024bf7f99721 63 * @brief DMA Configuration Structure definition
bogdanm 85:024bf7f99721 64 */
bogdanm 85:024bf7f99721 65 typedef struct
bogdanm 85:024bf7f99721 66 {
bogdanm 85:024bf7f99721 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 85:024bf7f99721 68 from memory to memory or from peripheral to memory.
bogdanm 85:024bf7f99721 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 85:024bf7f99721 70
bogdanm 85:024bf7f99721 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 85:024bf7f99721 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 85:024bf7f99721 73
bogdanm 85:024bf7f99721 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 85:024bf7f99721 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 85:024bf7f99721 76
bogdanm 85:024bf7f99721 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 85:024bf7f99721 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 85:024bf7f99721 79
bogdanm 85:024bf7f99721 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 85:024bf7f99721 81 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 85:024bf7f99721 82
bogdanm 85:024bf7f99721 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 85:024bf7f99721 84 This parameter can be a value of @ref DMA_mode
bogdanm 85:024bf7f99721 85 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 85:024bf7f99721 86 data transfer is configured on the selected Channel */
bogdanm 85:024bf7f99721 87
bogdanm 85:024bf7f99721 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 85:024bf7f99721 89 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 85:024bf7f99721 90
bogdanm 85:024bf7f99721 91 } DMA_InitTypeDef;
bogdanm 85:024bf7f99721 92
bogdanm 85:024bf7f99721 93 /**
bogdanm 85:024bf7f99721 94 * @brief DMA Configuration enumeration values definition
bogdanm 85:024bf7f99721 95 */
bogdanm 85:024bf7f99721 96 typedef enum
bogdanm 85:024bf7f99721 97 {
bogdanm 85:024bf7f99721 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
bogdanm 85:024bf7f99721 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
bogdanm 85:024bf7f99721 100
bogdanm 85:024bf7f99721 101 } DMA_ControlTypeDef;
bogdanm 85:024bf7f99721 102
bogdanm 92:4fc01daae5a5 103 /**
bogdanm 92:4fc01daae5a5 104 * @brief HAL DMA State structures definition
bogdanm 92:4fc01daae5a5 105 */
bogdanm 85:024bf7f99721 106 typedef enum
bogdanm 85:024bf7f99721 107 {
bogdanm 85:024bf7f99721 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 85:024bf7f99721 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
bogdanm 85:024bf7f99721 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
bogdanm 85:024bf7f99721 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 85:024bf7f99721 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 85:024bf7f99721 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 85:024bf7f99721 114
bogdanm 85:024bf7f99721 115 }HAL_DMA_StateTypeDef;
bogdanm 85:024bf7f99721 116
bogdanm 85:024bf7f99721 117 /**
bogdanm 85:024bf7f99721 118 * @brief HAL DMA Error Code structure definition
bogdanm 85:024bf7f99721 119 */
bogdanm 85:024bf7f99721 120 typedef enum
bogdanm 85:024bf7f99721 121 {
bogdanm 85:024bf7f99721 122 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 85:024bf7f99721 123 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 85:024bf7f99721 124
bogdanm 85:024bf7f99721 125 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 92:4fc01daae5a5 126
bogdanm 85:024bf7f99721 127
bogdanm 85:024bf7f99721 128 /**
bogdanm 85:024bf7f99721 129 * @brief DMA handle Structure definition
bogdanm 85:024bf7f99721 130 */
bogdanm 85:024bf7f99721 131 typedef struct __DMA_HandleTypeDef
bogdanm 85:024bf7f99721 132 {
bogdanm 85:024bf7f99721 133 DMA_Channel_TypeDef *Instance; /*!< Register base address */
bogdanm 85:024bf7f99721 134
bogdanm 85:024bf7f99721 135 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 85:024bf7f99721 136
bogdanm 85:024bf7f99721 137 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 85:024bf7f99721 138
bogdanm 85:024bf7f99721 139 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 85:024bf7f99721 140
bogdanm 85:024bf7f99721 141 void *Parent; /*!< Parent object state */
bogdanm 85:024bf7f99721 142
bogdanm 85:024bf7f99721 143 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 85:024bf7f99721 144
bogdanm 85:024bf7f99721 145 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 92:4fc01daae5a5 146
bogdanm 85:024bf7f99721 147 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 85:024bf7f99721 148
bogdanm 85:024bf7f99721 149 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 85:024bf7f99721 150
bogdanm 85:024bf7f99721 151 } DMA_HandleTypeDef;
bogdanm 92:4fc01daae5a5 152 /**
bogdanm 92:4fc01daae5a5 153 * @}
bogdanm 92:4fc01daae5a5 154 */
bogdanm 85:024bf7f99721 155
bogdanm 85:024bf7f99721 156 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
bogdanm 85:024bf7f99721 158 * @{
bogdanm 85:024bf7f99721 159 */
bogdanm 85:024bf7f99721 160
bogdanm 92:4fc01daae5a5 161 /** @defgroup DMA_Error_Code DMA Error Code
bogdanm 85:024bf7f99721 162 * @{
bogdanm 85:024bf7f99721 163 */
bogdanm 85:024bf7f99721 164 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 85:024bf7f99721 165 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 85:024bf7f99721 166 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 85:024bf7f99721 167 /**
bogdanm 85:024bf7f99721 168 * @}
bogdanm 85:024bf7f99721 169 */
bogdanm 85:024bf7f99721 170
bogdanm 92:4fc01daae5a5 171 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
bogdanm 85:024bf7f99721 172 * @{
bogdanm 85:024bf7f99721 173 */
bogdanm 85:024bf7f99721 174 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 85:024bf7f99721 175 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
bogdanm 85:024bf7f99721 176 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
bogdanm 85:024bf7f99721 177
bogdanm 85:024bf7f99721 178 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
bogdanm 85:024bf7f99721 179 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
bogdanm 85:024bf7f99721 180 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
bogdanm 85:024bf7f99721 181 /**
bogdanm 85:024bf7f99721 182 * @}
bogdanm 85:024bf7f99721 183 */
bogdanm 85:024bf7f99721 184
bogdanm 92:4fc01daae5a5 185 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
bogdanm 85:024bf7f99721 186 * @{
bogdanm 85:024bf7f99721 187 */
bogdanm 85:024bf7f99721 188 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 85:024bf7f99721 189 /**
bogdanm 85:024bf7f99721 190 * @}
bogdanm 85:024bf7f99721 191 */
bogdanm 85:024bf7f99721 192
bogdanm 92:4fc01daae5a5 193 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
bogdanm 85:024bf7f99721 194 * @{
bogdanm 85:024bf7f99721 195 */
bogdanm 85:024bf7f99721 196 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
bogdanm 85:024bf7f99721 197 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
bogdanm 85:024bf7f99721 198
bogdanm 85:024bf7f99721 199 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
bogdanm 85:024bf7f99721 200 ((STATE) == DMA_PINC_DISABLE))
bogdanm 85:024bf7f99721 201 /**
bogdanm 85:024bf7f99721 202 * @}
bogdanm 85:024bf7f99721 203 */
bogdanm 85:024bf7f99721 204
bogdanm 92:4fc01daae5a5 205 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
bogdanm 85:024bf7f99721 206 * @{
bogdanm 85:024bf7f99721 207 */
bogdanm 85:024bf7f99721 208 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
bogdanm 85:024bf7f99721 209 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
bogdanm 85:024bf7f99721 210
bogdanm 85:024bf7f99721 211 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
bogdanm 85:024bf7f99721 212 ((STATE) == DMA_MINC_DISABLE))
bogdanm 85:024bf7f99721 213 /**
bogdanm 85:024bf7f99721 214 * @}
bogdanm 85:024bf7f99721 215 */
bogdanm 85:024bf7f99721 216
bogdanm 92:4fc01daae5a5 217 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
bogdanm 85:024bf7f99721 218 * @{
bogdanm 85:024bf7f99721 219 */
bogdanm 85:024bf7f99721 220 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
bogdanm 85:024bf7f99721 221 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
bogdanm 85:024bf7f99721 222 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
bogdanm 85:024bf7f99721 223
bogdanm 85:024bf7f99721 224 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bogdanm 85:024bf7f99721 225 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
bogdanm 85:024bf7f99721 226 ((SIZE) == DMA_PDATAALIGN_WORD))
bogdanm 85:024bf7f99721 227 /**
bogdanm 85:024bf7f99721 228 * @}
bogdanm 85:024bf7f99721 229 */
bogdanm 85:024bf7f99721 230
bogdanm 85:024bf7f99721 231
bogdanm 92:4fc01daae5a5 232 /** @defgroup DMA_Memory_data_size DMA Memory data size
bogdanm 85:024bf7f99721 233 * @{
bogdanm 85:024bf7f99721 234 */
bogdanm 85:024bf7f99721 235 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
bogdanm 85:024bf7f99721 236 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
bogdanm 85:024bf7f99721 237 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
bogdanm 85:024bf7f99721 238
bogdanm 85:024bf7f99721 239 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
bogdanm 85:024bf7f99721 240 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
bogdanm 85:024bf7f99721 241 ((SIZE) == DMA_MDATAALIGN_WORD ))
bogdanm 85:024bf7f99721 242 /**
bogdanm 85:024bf7f99721 243 * @}
bogdanm 85:024bf7f99721 244 */
bogdanm 85:024bf7f99721 245
bogdanm 92:4fc01daae5a5 246 /** @defgroup DMA_mode DMA mode
bogdanm 85:024bf7f99721 247 * @{
bogdanm 85:024bf7f99721 248 */
bogdanm 92:4fc01daae5a5 249 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
bogdanm 85:024bf7f99721 250 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
bogdanm 85:024bf7f99721 251
bogdanm 85:024bf7f99721 252 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
bogdanm 85:024bf7f99721 253 ((MODE) == DMA_CIRCULAR))
bogdanm 85:024bf7f99721 254 /**
bogdanm 85:024bf7f99721 255 * @}
bogdanm 85:024bf7f99721 256 */
bogdanm 85:024bf7f99721 257
bogdanm 92:4fc01daae5a5 258 /** @defgroup DMA_Priority_level DMA Priority level
bogdanm 85:024bf7f99721 259 * @{
bogdanm 85:024bf7f99721 260 */
bogdanm 85:024bf7f99721 261 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
bogdanm 85:024bf7f99721 262 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
bogdanm 85:024bf7f99721 263 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
bogdanm 85:024bf7f99721 264 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
bogdanm 85:024bf7f99721 265
bogdanm 85:024bf7f99721 266 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
bogdanm 85:024bf7f99721 267 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
bogdanm 85:024bf7f99721 268 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
bogdanm 85:024bf7f99721 269 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
bogdanm 85:024bf7f99721 270 /**
bogdanm 85:024bf7f99721 271 * @}
bogdanm 85:024bf7f99721 272 */
bogdanm 85:024bf7f99721 273
bogdanm 85:024bf7f99721 274
bogdanm 92:4fc01daae5a5 275 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
bogdanm 85:024bf7f99721 276 * @{
bogdanm 85:024bf7f99721 277 */
bogdanm 85:024bf7f99721 278
bogdanm 85:024bf7f99721 279 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
bogdanm 85:024bf7f99721 280 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
bogdanm 85:024bf7f99721 281 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
bogdanm 85:024bf7f99721 282
bogdanm 85:024bf7f99721 283 /**
bogdanm 85:024bf7f99721 284 * @}
bogdanm 85:024bf7f99721 285 */
bogdanm 85:024bf7f99721 286
bogdanm 92:4fc01daae5a5 287 /** @defgroup DMA_flag_definitions DMA flag definitions
bogdanm 85:024bf7f99721 288 * @{
bogdanm 85:024bf7f99721 289 */
bogdanm 85:024bf7f99721 290
Kojto 93:e188a91d3eaa 291 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
Kojto 93:e188a91d3eaa 292 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
Kojto 93:e188a91d3eaa 293 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
Kojto 93:e188a91d3eaa 294 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
Kojto 93:e188a91d3eaa 295 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
Kojto 93:e188a91d3eaa 296 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
Kojto 93:e188a91d3eaa 297 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
Kojto 93:e188a91d3eaa 298 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
Kojto 93:e188a91d3eaa 299 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
Kojto 93:e188a91d3eaa 300 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
Kojto 93:e188a91d3eaa 301 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
Kojto 93:e188a91d3eaa 302 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
Kojto 93:e188a91d3eaa 303 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
Kojto 93:e188a91d3eaa 304 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
Kojto 93:e188a91d3eaa 305 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
Kojto 93:e188a91d3eaa 306 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
Kojto 93:e188a91d3eaa 307 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
Kojto 93:e188a91d3eaa 308 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
Kojto 93:e188a91d3eaa 309 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
Kojto 93:e188a91d3eaa 310 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
Kojto 93:e188a91d3eaa 311 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
Kojto 93:e188a91d3eaa 312 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
Kojto 93:e188a91d3eaa 313 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
Kojto 93:e188a91d3eaa 314 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
Kojto 93:e188a91d3eaa 315 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
Kojto 93:e188a91d3eaa 316 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
Kojto 93:e188a91d3eaa 317 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
Kojto 93:e188a91d3eaa 318 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
bogdanm 85:024bf7f99721 319
bogdanm 85:024bf7f99721 320
bogdanm 85:024bf7f99721 321 /**
bogdanm 85:024bf7f99721 322 * @}
bogdanm 85:024bf7f99721 323 */
bogdanm 85:024bf7f99721 324
bogdanm 85:024bf7f99721 325 /**
bogdanm 85:024bf7f99721 326 * @}
bogdanm 85:024bf7f99721 327 */
bogdanm 92:4fc01daae5a5 328
bogdanm 85:024bf7f99721 329 /* Exported macros -----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 330 /** @defgroup DMA_Exported_Macros DMA Exported Macros
bogdanm 92:4fc01daae5a5 331 * @{
bogdanm 92:4fc01daae5a5 332 */
bogdanm 85:024bf7f99721 333
bogdanm 85:024bf7f99721 334 /** @brief Reset DMA handle state
bogdanm 85:024bf7f99721 335 * @param __HANDLE__: DMA handle.
bogdanm 85:024bf7f99721 336 * @retval None
bogdanm 85:024bf7f99721 337 */
bogdanm 85:024bf7f99721 338 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 85:024bf7f99721 339
bogdanm 85:024bf7f99721 340 /**
bogdanm 85:024bf7f99721 341 * @brief Enable the specified DMA Channel.
bogdanm 85:024bf7f99721 342 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 343 * @retval None.
bogdanm 85:024bf7f99721 344 */
bogdanm 92:4fc01daae5a5 345 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
bogdanm 85:024bf7f99721 346
bogdanm 85:024bf7f99721 347 /**
bogdanm 85:024bf7f99721 348 * @brief Disable the specified DMA Channel.
bogdanm 85:024bf7f99721 349 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 350 * @retval None.
bogdanm 85:024bf7f99721 351 */
bogdanm 92:4fc01daae5a5 352 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
bogdanm 85:024bf7f99721 353
bogdanm 85:024bf7f99721 354
bogdanm 85:024bf7f99721 355 /* Interrupt & Flag management */
bogdanm 85:024bf7f99721 356
bogdanm 85:024bf7f99721 357 /**
bogdanm 85:024bf7f99721 358 * @brief Enables the specified DMA Channel interrupts.
bogdanm 85:024bf7f99721 359 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 360 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 85:024bf7f99721 361 * This parameter can be any combination of the following values:
bogdanm 85:024bf7f99721 362 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 85:024bf7f99721 363 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 85:024bf7f99721 364 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 85:024bf7f99721 365 * @retval None
bogdanm 85:024bf7f99721 366 */
bogdanm 92:4fc01daae5a5 367 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
bogdanm 85:024bf7f99721 368
bogdanm 85:024bf7f99721 369 /**
bogdanm 85:024bf7f99721 370 * @brief Disables the specified DMA Channel interrupts.
bogdanm 85:024bf7f99721 371 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 372 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 85:024bf7f99721 373 * This parameter can be any combination of the following values:
bogdanm 85:024bf7f99721 374 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 85:024bf7f99721 375 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 85:024bf7f99721 376 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 85:024bf7f99721 377 * @retval None
bogdanm 85:024bf7f99721 378 */
bogdanm 92:4fc01daae5a5 379 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
bogdanm 85:024bf7f99721 380
bogdanm 85:024bf7f99721 381 /**
bogdanm 85:024bf7f99721 382 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
bogdanm 85:024bf7f99721 383 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 384 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 85:024bf7f99721 385 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 386 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 85:024bf7f99721 387 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 85:024bf7f99721 388 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 85:024bf7f99721 389 * @retval The state of DMA_IT (SET or RESET).
bogdanm 85:024bf7f99721 390 */
bogdanm 85:024bf7f99721 391 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 85:024bf7f99721 392
bogdanm 85:024bf7f99721 393 /**
bogdanm 85:024bf7f99721 394 * @}
bogdanm 85:024bf7f99721 395 */
bogdanm 85:024bf7f99721 396
bogdanm 85:024bf7f99721 397 /* Include DMA HAL Extension module */
bogdanm 85:024bf7f99721 398 #include "stm32f0xx_hal_dma_ex.h"
bogdanm 85:024bf7f99721 399
bogdanm 85:024bf7f99721 400 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 401 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
bogdanm 92:4fc01daae5a5 402 * @{
bogdanm 92:4fc01daae5a5 403 */
bogdanm 92:4fc01daae5a5 404 /** @addtogroup DMA_Exported_Functions_Group1
bogdanm 92:4fc01daae5a5 405 * @brief Initialization and de-initialization functions
bogdanm 92:4fc01daae5a5 406 * @{
bogdanm 92:4fc01daae5a5 407 */
bogdanm 85:024bf7f99721 408 /* Initialization and de-initialization functions *****************************/
bogdanm 85:024bf7f99721 409 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 410 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 411 /**
bogdanm 92:4fc01daae5a5 412 * @}
bogdanm 92:4fc01daae5a5 413 */
bogdanm 85:024bf7f99721 414
bogdanm 92:4fc01daae5a5 415 /** @addtogroup DMA_Exported_Functions_Group2
bogdanm 92:4fc01daae5a5 416 * @brief I/O operation functions
bogdanm 92:4fc01daae5a5 417 * @{
bogdanm 92:4fc01daae5a5 418 */
bogdanm 85:024bf7f99721 419 /* IO operation functions *****************************************************/
bogdanm 85:024bf7f99721 420 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 85:024bf7f99721 421 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 85:024bf7f99721 422 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 423 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 85:024bf7f99721 424 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 425 /**
bogdanm 92:4fc01daae5a5 426 * @}
bogdanm 92:4fc01daae5a5 427 */
bogdanm 85:024bf7f99721 428
bogdanm 85:024bf7f99721 429 /* Peripheral State and Error functions ***************************************/
bogdanm 92:4fc01daae5a5 430 /** @addtogroup DMA_Exported_Functions_Group3
bogdanm 92:4fc01daae5a5 431 * @brief Peripheral State functions
bogdanm 92:4fc01daae5a5 432 * @{
bogdanm 92:4fc01daae5a5 433 */
bogdanm 85:024bf7f99721 434 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 435 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 436 /**
bogdanm 92:4fc01daae5a5 437 * @}
bogdanm 92:4fc01daae5a5 438 */
bogdanm 92:4fc01daae5a5 439
bogdanm 92:4fc01daae5a5 440 /**
bogdanm 92:4fc01daae5a5 441 * @}
bogdanm 92:4fc01daae5a5 442 */
bogdanm 85:024bf7f99721 443
bogdanm 85:024bf7f99721 444 /**
bogdanm 85:024bf7f99721 445 * @}
bogdanm 85:024bf7f99721 446 */
bogdanm 85:024bf7f99721 447
bogdanm 85:024bf7f99721 448 /**
bogdanm 85:024bf7f99721 449 * @}
bogdanm 85:024bf7f99721 450 */
bogdanm 85:024bf7f99721 451
bogdanm 85:024bf7f99721 452 #ifdef __cplusplus
bogdanm 85:024bf7f99721 453 }
bogdanm 85:024bf7f99721 454 #endif
bogdanm 85:024bf7f99721 455
bogdanm 85:024bf7f99721 456 #endif /* __STM32F0xx_HAL_DMA_H */
bogdanm 85:024bf7f99721 457
bogdanm 85:024bf7f99721 458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 92:4fc01daae5a5 459