Filippo Casamassima / mbed

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TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma.h@85:024bf7f99721, 2014-06-11 (annotated)

Committer:
bogdanm
Date:
Wed Jun 11 15:14:05 2014 +0100
Revision:
85:024bf7f99721
Child:
92:4fc01daae5a5
Release 85 of the mbed library



Main changes:



- K64F Ethernet fixes

- Updated tests

- Fixes for various mbed targets

- Code cleanup: fixed warnings, more consistent code style

- GCC support for K64F



There is a known issue with the I2C interface on some ST targets. If you

find the I2C interface problematic on your ST board, please log a bug

against this on mbed.org.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**
bogdanm 85:024bf7f99721 2 ******************************************************************************
bogdanm 85:024bf7f99721 3 * @file stm32f0xx_hal_dma.h
bogdanm 85:024bf7f99721 4 * @author MCD Application Team
bogdanm 85:024bf7f99721 5 * @version V1.0.0
bogdanm 85:024bf7f99721 6 * @date 28-May-2014
bogdanm 85:024bf7f99721 7 * @brief Header file of DMA HAL module.
bogdanm 85:024bf7f99721 8 ******************************************************************************
bogdanm 85:024bf7f99721 9 * @attention
bogdanm 85:024bf7f99721 10 *
bogdanm 85:024bf7f99721 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 85:024bf7f99721 12 *
bogdanm 85:024bf7f99721 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 85:024bf7f99721 14 * are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 85:024bf7f99721 16 * this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 85:024bf7f99721 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 85:024bf7f99721 19 * and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 85:024bf7f99721 21 * may be used to endorse or promote products derived from this software
bogdanm 85:024bf7f99721 22 * without specific prior written permission.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 85:024bf7f99721 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 85:024bf7f99721 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 85:024bf7f99721 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 85:024bf7f99721 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 85:024bf7f99721 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 85:024bf7f99721 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 85:024bf7f99721 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 34 *
bogdanm 85:024bf7f99721 35 ******************************************************************************
bogdanm 85:024bf7f99721 36 */
bogdanm 85:024bf7f99721 37
bogdanm 85:024bf7f99721 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 85:024bf7f99721 39 #ifndef __STM32F0xx_HAL_DMA_H
bogdanm 85:024bf7f99721 40 #define __STM32F0xx_HAL_DMA_H
bogdanm 85:024bf7f99721 41
bogdanm 85:024bf7f99721 42 #ifdef __cplusplus
bogdanm 85:024bf7f99721 43 extern "C" {
bogdanm 85:024bf7f99721 44 #endif
bogdanm 85:024bf7f99721 45
bogdanm 85:024bf7f99721 46 /* Includes ------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 47 #include "stm32f0xx_hal_def.h"
bogdanm 85:024bf7f99721 48
bogdanm 85:024bf7f99721 49 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 85:024bf7f99721 50 * @{
bogdanm 85:024bf7f99721 51 */
bogdanm 85:024bf7f99721 52
bogdanm 85:024bf7f99721 53 /** @addtogroup DMA
bogdanm 85:024bf7f99721 54 * @{
bogdanm 85:024bf7f99721 55 */
bogdanm 85:024bf7f99721 56
bogdanm 85:024bf7f99721 57 /* Exported types ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 58
bogdanm 85:024bf7f99721 59 /**
bogdanm 85:024bf7f99721 60 * @brief DMA Configuration Structure definition
bogdanm 85:024bf7f99721 61 */
bogdanm 85:024bf7f99721 62 typedef struct
bogdanm 85:024bf7f99721 63 {
bogdanm 85:024bf7f99721 64 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 85:024bf7f99721 65 from memory to memory or from peripheral to memory.
bogdanm 85:024bf7f99721 66 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 85:024bf7f99721 67
bogdanm 85:024bf7f99721 68 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 85:024bf7f99721 69 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 85:024bf7f99721 70
bogdanm 85:024bf7f99721 71 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 85:024bf7f99721 72 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 85:024bf7f99721 73
bogdanm 85:024bf7f99721 74 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 85:024bf7f99721 75 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 85:024bf7f99721 76
bogdanm 85:024bf7f99721 77 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 85:024bf7f99721 78 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 85:024bf7f99721 79
bogdanm 85:024bf7f99721 80 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 85:024bf7f99721 81 This parameter can be a value of @ref DMA_mode
bogdanm 85:024bf7f99721 82 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 85:024bf7f99721 83 data transfer is configured on the selected Channel */
bogdanm 85:024bf7f99721 84
bogdanm 85:024bf7f99721 85 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 85:024bf7f99721 86 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 85:024bf7f99721 87
bogdanm 85:024bf7f99721 88 } DMA_InitTypeDef;
bogdanm 85:024bf7f99721 89
bogdanm 85:024bf7f99721 90 /**
bogdanm 85:024bf7f99721 91 * @brief DMA Configuration enumeration values definition
bogdanm 85:024bf7f99721 92 */
bogdanm 85:024bf7f99721 93 typedef enum
bogdanm 85:024bf7f99721 94 {
bogdanm 85:024bf7f99721 95 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
bogdanm 85:024bf7f99721 96 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
bogdanm 85:024bf7f99721 97
bogdanm 85:024bf7f99721 98 } DMA_ControlTypeDef;
bogdanm 85:024bf7f99721 99
bogdanm 85:024bf7f99721 100 /**
bogdanm 85:024bf7f99721 101 * @brief HAL DMA2D State structures definition
bogdanm 85:024bf7f99721 102 */
bogdanm 85:024bf7f99721 103 typedef enum
bogdanm 85:024bf7f99721 104 {
bogdanm 85:024bf7f99721 105 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 85:024bf7f99721 106 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
bogdanm 85:024bf7f99721 107 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
bogdanm 85:024bf7f99721 108 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 85:024bf7f99721 109 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 85:024bf7f99721 110 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 85:024bf7f99721 111
bogdanm 85:024bf7f99721 112 }HAL_DMA_StateTypeDef;
bogdanm 85:024bf7f99721 113
bogdanm 85:024bf7f99721 114 /**
bogdanm 85:024bf7f99721 115 * @brief HAL DMA Error Code structure definition
bogdanm 85:024bf7f99721 116 */
bogdanm 85:024bf7f99721 117 typedef enum
bogdanm 85:024bf7f99721 118 {
bogdanm 85:024bf7f99721 119 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 85:024bf7f99721 120 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 85:024bf7f99721 121
bogdanm 85:024bf7f99721 122 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 85:024bf7f99721 123
bogdanm 85:024bf7f99721 124
bogdanm 85:024bf7f99721 125 /**
bogdanm 85:024bf7f99721 126 * @brief DMA handle Structure definition
bogdanm 85:024bf7f99721 127 */
bogdanm 85:024bf7f99721 128 typedef struct __DMA_HandleTypeDef
bogdanm 85:024bf7f99721 129 {
bogdanm 85:024bf7f99721 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
bogdanm 85:024bf7f99721 131
bogdanm 85:024bf7f99721 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 85:024bf7f99721 133
bogdanm 85:024bf7f99721 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 85:024bf7f99721 135
bogdanm 85:024bf7f99721 136 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 85:024bf7f99721 137
bogdanm 85:024bf7f99721 138 void *Parent; /*!< Parent object state */
bogdanm 85:024bf7f99721 139
bogdanm 85:024bf7f99721 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 85:024bf7f99721 141
bogdanm 85:024bf7f99721 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 85:024bf7f99721 143
bogdanm 85:024bf7f99721 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 85:024bf7f99721 145
bogdanm 85:024bf7f99721 146 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 85:024bf7f99721 147
bogdanm 85:024bf7f99721 148 } DMA_HandleTypeDef;
bogdanm 85:024bf7f99721 149
bogdanm 85:024bf7f99721 150 /* Exported constants --------------------------------------------------------*/
bogdanm 85:024bf7f99721 151
bogdanm 85:024bf7f99721 152 /** @defgroup DMA_Exported_Constants
bogdanm 85:024bf7f99721 153 * @{
bogdanm 85:024bf7f99721 154 */
bogdanm 85:024bf7f99721 155
bogdanm 85:024bf7f99721 156 /** @defgroup DMA_Error_Code
bogdanm 85:024bf7f99721 157 * @{
bogdanm 85:024bf7f99721 158 */
bogdanm 85:024bf7f99721 159 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 85:024bf7f99721 160 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 85:024bf7f99721 161 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 85:024bf7f99721 162 /**
bogdanm 85:024bf7f99721 163 * @}
bogdanm 85:024bf7f99721 164 */
bogdanm 85:024bf7f99721 165
bogdanm 85:024bf7f99721 166 /** @defgroup DMA_Data_transfer_direction
bogdanm 85:024bf7f99721 167 * @{
bogdanm 85:024bf7f99721 168 */
bogdanm 85:024bf7f99721 169 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 85:024bf7f99721 170 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
bogdanm 85:024bf7f99721 171 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
bogdanm 85:024bf7f99721 172
bogdanm 85:024bf7f99721 173 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
bogdanm 85:024bf7f99721 174 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
bogdanm 85:024bf7f99721 175 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
bogdanm 85:024bf7f99721 176 /**
bogdanm 85:024bf7f99721 177 * @}
bogdanm 85:024bf7f99721 178 */
bogdanm 85:024bf7f99721 179
bogdanm 85:024bf7f99721 180 /** @defgroup DMA_Data_buffer_size
bogdanm 85:024bf7f99721 181 * @{
bogdanm 85:024bf7f99721 182 */
bogdanm 85:024bf7f99721 183 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 85:024bf7f99721 184 /**
bogdanm 85:024bf7f99721 185 * @}
bogdanm 85:024bf7f99721 186 */
bogdanm 85:024bf7f99721 187
bogdanm 85:024bf7f99721 188 /** @defgroup DMA_Peripheral_incremented_mode
bogdanm 85:024bf7f99721 189 * @{
bogdanm 85:024bf7f99721 190 */
bogdanm 85:024bf7f99721 191 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
bogdanm 85:024bf7f99721 192 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
bogdanm 85:024bf7f99721 193
bogdanm 85:024bf7f99721 194 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
bogdanm 85:024bf7f99721 195 ((STATE) == DMA_PINC_DISABLE))
bogdanm 85:024bf7f99721 196 /**
bogdanm 85:024bf7f99721 197 * @}
bogdanm 85:024bf7f99721 198 */
bogdanm 85:024bf7f99721 199
bogdanm 85:024bf7f99721 200 /** @defgroup DMA_Memory_incremented_mode
bogdanm 85:024bf7f99721 201 * @{
bogdanm 85:024bf7f99721 202 */
bogdanm 85:024bf7f99721 203 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
bogdanm 85:024bf7f99721 204 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
bogdanm 85:024bf7f99721 205
bogdanm 85:024bf7f99721 206 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
bogdanm 85:024bf7f99721 207 ((STATE) == DMA_MINC_DISABLE))
bogdanm 85:024bf7f99721 208 /**
bogdanm 85:024bf7f99721 209 * @}
bogdanm 85:024bf7f99721 210 */
bogdanm 85:024bf7f99721 211
bogdanm 85:024bf7f99721 212 /** @defgroup DMA_Peripheral_data_size
bogdanm 85:024bf7f99721 213 * @{
bogdanm 85:024bf7f99721 214 */
bogdanm 85:024bf7f99721 215 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
bogdanm 85:024bf7f99721 216 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
bogdanm 85:024bf7f99721 217 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
bogdanm 85:024bf7f99721 218
bogdanm 85:024bf7f99721 219 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bogdanm 85:024bf7f99721 220 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
bogdanm 85:024bf7f99721 221 ((SIZE) == DMA_PDATAALIGN_WORD))
bogdanm 85:024bf7f99721 222 /**
bogdanm 85:024bf7f99721 223 * @}
bogdanm 85:024bf7f99721 224 */
bogdanm 85:024bf7f99721 225
bogdanm 85:024bf7f99721 226
bogdanm 85:024bf7f99721 227 /** @defgroup DMA_Memory_data_size
bogdanm 85:024bf7f99721 228 * @{
bogdanm 85:024bf7f99721 229 */
bogdanm 85:024bf7f99721 230 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
bogdanm 85:024bf7f99721 231 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
bogdanm 85:024bf7f99721 232 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
bogdanm 85:024bf7f99721 233
bogdanm 85:024bf7f99721 234 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
bogdanm 85:024bf7f99721 235 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
bogdanm 85:024bf7f99721 236 ((SIZE) == DMA_MDATAALIGN_WORD ))
bogdanm 85:024bf7f99721 237 /**
bogdanm 85:024bf7f99721 238 * @}
bogdanm 85:024bf7f99721 239 */
bogdanm 85:024bf7f99721 240
bogdanm 85:024bf7f99721 241 /** @defgroup DMA_mode
bogdanm 85:024bf7f99721 242 * @{
bogdanm 85:024bf7f99721 243 */
bogdanm 85:024bf7f99721 244 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
bogdanm 85:024bf7f99721 245 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
bogdanm 85:024bf7f99721 246
bogdanm 85:024bf7f99721 247 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
bogdanm 85:024bf7f99721 248 ((MODE) == DMA_CIRCULAR))
bogdanm 85:024bf7f99721 249 /**
bogdanm 85:024bf7f99721 250 * @}
bogdanm 85:024bf7f99721 251 */
bogdanm 85:024bf7f99721 252
bogdanm 85:024bf7f99721 253 /** @defgroup DMA_Priority_level
bogdanm 85:024bf7f99721 254 * @{
bogdanm 85:024bf7f99721 255 */
bogdanm 85:024bf7f99721 256 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
bogdanm 85:024bf7f99721 257 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
bogdanm 85:024bf7f99721 258 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
bogdanm 85:024bf7f99721 259 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
bogdanm 85:024bf7f99721 260
bogdanm 85:024bf7f99721 261 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
bogdanm 85:024bf7f99721 262 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
bogdanm 85:024bf7f99721 263 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
bogdanm 85:024bf7f99721 264 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
bogdanm 85:024bf7f99721 265 /**
bogdanm 85:024bf7f99721 266 * @}
bogdanm 85:024bf7f99721 267 */
bogdanm 85:024bf7f99721 268
bogdanm 85:024bf7f99721 269
bogdanm 85:024bf7f99721 270 /** @defgroup DMA_interrupt_enable_definitions
bogdanm 85:024bf7f99721 271 * @{
bogdanm 85:024bf7f99721 272 */
bogdanm 85:024bf7f99721 273
bogdanm 85:024bf7f99721 274 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
bogdanm 85:024bf7f99721 275 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
bogdanm 85:024bf7f99721 276 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
bogdanm 85:024bf7f99721 277
bogdanm 85:024bf7f99721 278 /**
bogdanm 85:024bf7f99721 279 * @}
bogdanm 85:024bf7f99721 280 */
bogdanm 85:024bf7f99721 281
bogdanm 85:024bf7f99721 282 /** @defgroup DMA_flag_definitions
bogdanm 85:024bf7f99721 283 * @{
bogdanm 85:024bf7f99721 284 */
bogdanm 85:024bf7f99721 285
bogdanm 85:024bf7f99721 286 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 85:024bf7f99721 287 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 85:024bf7f99721 288 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 85:024bf7f99721 289 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 85:024bf7f99721 290 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 85:024bf7f99721 291 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 85:024bf7f99721 292 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 85:024bf7f99721 293 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 85:024bf7f99721 294 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 85:024bf7f99721 295 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 85:024bf7f99721 296 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 85:024bf7f99721 297 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 85:024bf7f99721 298 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 85:024bf7f99721 299 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 85:024bf7f99721 300 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 85:024bf7f99721 301 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 85:024bf7f99721 302 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 85:024bf7f99721 303 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 85:024bf7f99721 304 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 85:024bf7f99721 305 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 85:024bf7f99721 306 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 85:024bf7f99721 307 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 85:024bf7f99721 308 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 85:024bf7f99721 309 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 85:024bf7f99721 310 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 85:024bf7f99721 311 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 85:024bf7f99721 312 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 85:024bf7f99721 313 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 85:024bf7f99721 314
bogdanm 85:024bf7f99721 315
bogdanm 85:024bf7f99721 316 /**
bogdanm 85:024bf7f99721 317 * @}
bogdanm 85:024bf7f99721 318 */
bogdanm 85:024bf7f99721 319
bogdanm 85:024bf7f99721 320 /**
bogdanm 85:024bf7f99721 321 * @}
bogdanm 85:024bf7f99721 322 */
bogdanm 85:024bf7f99721 323
bogdanm 85:024bf7f99721 324 /* Exported macros -----------------------------------------------------------*/
bogdanm 85:024bf7f99721 325 /** @defgroup DMA_Exported_Macros
bogdanm 85:024bf7f99721 326 * @{
bogdanm 85:024bf7f99721 327 */
bogdanm 85:024bf7f99721 328
bogdanm 85:024bf7f99721 329 /** @brief Reset DMA handle state
bogdanm 85:024bf7f99721 330 * @param __HANDLE__: DMA handle.
bogdanm 85:024bf7f99721 331 * @retval None
bogdanm 85:024bf7f99721 332 */
bogdanm 85:024bf7f99721 333 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 85:024bf7f99721 334
bogdanm 85:024bf7f99721 335 /**
bogdanm 85:024bf7f99721 336 * @brief Enable the specified DMA Channel.
bogdanm 85:024bf7f99721 337 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 338 * @retval None.
bogdanm 85:024bf7f99721 339 */
bogdanm 85:024bf7f99721 340 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
bogdanm 85:024bf7f99721 341
bogdanm 85:024bf7f99721 342 /**
bogdanm 85:024bf7f99721 343 * @brief Disable the specified DMA Channel.
bogdanm 85:024bf7f99721 344 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 345 * @retval None.
bogdanm 85:024bf7f99721 346 */
bogdanm 85:024bf7f99721 347 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
bogdanm 85:024bf7f99721 348
bogdanm 85:024bf7f99721 349
bogdanm 85:024bf7f99721 350 /* Interrupt & Flag management */
bogdanm 85:024bf7f99721 351
bogdanm 85:024bf7f99721 352 /**
bogdanm 85:024bf7f99721 353 * @brief Enables the specified DMA Channel interrupts.
bogdanm 85:024bf7f99721 354 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 355 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 85:024bf7f99721 356 * This parameter can be any combination of the following values:
bogdanm 85:024bf7f99721 357 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 85:024bf7f99721 358 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 85:024bf7f99721 359 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 85:024bf7f99721 360 * @retval None
bogdanm 85:024bf7f99721 361 */
bogdanm 85:024bf7f99721 362 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
bogdanm 85:024bf7f99721 363
bogdanm 85:024bf7f99721 364 /**
bogdanm 85:024bf7f99721 365 * @brief Disables the specified DMA Channel interrupts.
bogdanm 85:024bf7f99721 366 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 367 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 85:024bf7f99721 368 * This parameter can be any combination of the following values:
bogdanm 85:024bf7f99721 369 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 85:024bf7f99721 370 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 85:024bf7f99721 371 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 85:024bf7f99721 372 * @retval None
bogdanm 85:024bf7f99721 373 */
bogdanm 85:024bf7f99721 374 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
bogdanm 85:024bf7f99721 375
bogdanm 85:024bf7f99721 376 /**
bogdanm 85:024bf7f99721 377 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
bogdanm 85:024bf7f99721 378 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 379 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 85:024bf7f99721 380 * This parameter can be one of the following values:
bogdanm 85:024bf7f99721 381 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 85:024bf7f99721 382 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 85:024bf7f99721 383 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 85:024bf7f99721 384 * @retval The state of DMA_IT (SET or RESET).
bogdanm 85:024bf7f99721 385 */
bogdanm 85:024bf7f99721 386 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 85:024bf7f99721 387
bogdanm 85:024bf7f99721 388 /**
bogdanm 85:024bf7f99721 389 * @}
bogdanm 85:024bf7f99721 390 */
bogdanm 85:024bf7f99721 391
bogdanm 85:024bf7f99721 392 /* Include DMA HAL Extension module */
bogdanm 85:024bf7f99721 393 #include "stm32f0xx_hal_dma_ex.h"
bogdanm 85:024bf7f99721 394
bogdanm 85:024bf7f99721 395 /* Exported functions --------------------------------------------------------*/
bogdanm 85:024bf7f99721 396
bogdanm 85:024bf7f99721 397 /* Initialization and de-initialization functions *****************************/
bogdanm 85:024bf7f99721 398 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 399 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 400
bogdanm 85:024bf7f99721 401 /* IO operation functions *****************************************************/
bogdanm 85:024bf7f99721 402 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 85:024bf7f99721 403 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 85:024bf7f99721 404 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 405 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 85:024bf7f99721 406 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 407
bogdanm 85:024bf7f99721 408 /* Peripheral State and Error functions ***************************************/
bogdanm 85:024bf7f99721 409 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 410 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 85:024bf7f99721 411
bogdanm 85:024bf7f99721 412 /**
bogdanm 85:024bf7f99721 413 * @}
bogdanm 85:024bf7f99721 414 */
bogdanm 85:024bf7f99721 415
bogdanm 85:024bf7f99721 416 /**
bogdanm 85:024bf7f99721 417 * @}
bogdanm 85:024bf7f99721 418 */
bogdanm 85:024bf7f99721 419
bogdanm 85:024bf7f99721 420 #ifdef __cplusplus
bogdanm 85:024bf7f99721 421 }
bogdanm 85:024bf7f99721 422 #endif
bogdanm 85:024bf7f99721 423
bogdanm 85:024bf7f99721 424 #endif /* __STM32F0xx_HAL_DMA_H */
bogdanm 85:024bf7f99721 425
bogdanm 85:024bf7f99721 426 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/