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TARGET_NUCLEO_F072RB/stm32f0xx_hal_dma_ex.h@93:e188a91d3eaa, 2015-02-03 (annotated)

Committer:
Kojto
Date:
Tue Feb 03 15:31:20 2015 +0000
Revision:
93:e188a91d3eaa
Parent:
92:4fc01daae5a5 
Release 93 of the mbed library



Main changes:



- Renesas RZ_A1H bugfixes - i2c, ticker

- new targets - Nucleo F303RE, Nucleo F070RB, BLE SMURFS,

                Dragonfly 411RE,

- BusXXX - is connected method, plus operators addition

- LPC8xx - I2c fixes

- timestamp_t reverted to uint32_t

- RTX - fixes regarding stack (alignment, magic word)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 85:024bf7f99721 1 /**
bogdanm 85:024bf7f99721 2 ******************************************************************************
bogdanm 85:024bf7f99721 3 * @file stm32f0xx_hal_dma_ex.h
bogdanm 85:024bf7f99721 4 * @author MCD Application Team
Kojto 93:e188a91d3eaa 5 * @version V1.2.0
Kojto 93:e188a91d3eaa 6 * @date 11-December-2014
bogdanm 85:024bf7f99721 7 * @brief Header file of DMA HAL Extension module.
bogdanm 85:024bf7f99721 8 ******************************************************************************
bogdanm 85:024bf7f99721 9 * @attention
bogdanm 85:024bf7f99721 10 *
bogdanm 85:024bf7f99721 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 85:024bf7f99721 12 *
bogdanm 85:024bf7f99721 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 85:024bf7f99721 14 * are permitted provided that the following conditions are met:
bogdanm 85:024bf7f99721 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 85:024bf7f99721 16 * this list of conditions and the following disclaimer.
bogdanm 85:024bf7f99721 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 85:024bf7f99721 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 85:024bf7f99721 19 * and/or other materials provided with the distribution.
bogdanm 85:024bf7f99721 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 85:024bf7f99721 21 * may be used to endorse or promote products derived from this software
bogdanm 85:024bf7f99721 22 * without specific prior written permission.
bogdanm 85:024bf7f99721 23 *
bogdanm 85:024bf7f99721 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 85:024bf7f99721 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 85:024bf7f99721 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 85:024bf7f99721 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 85:024bf7f99721 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 85:024bf7f99721 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 85:024bf7f99721 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 85:024bf7f99721 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 85:024bf7f99721 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 85:024bf7f99721 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 85:024bf7f99721 34 *
bogdanm 85:024bf7f99721 35 ******************************************************************************
bogdanm 85:024bf7f99721 36 */
bogdanm 85:024bf7f99721 37
bogdanm 85:024bf7f99721 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 85:024bf7f99721 39 #ifndef __STM32F0xx_HAL_DMA_EX_H
bogdanm 85:024bf7f99721 40 #define __STM32F0xx_HAL_DMA_EX_H
bogdanm 85:024bf7f99721 41
bogdanm 85:024bf7f99721 42 #ifdef __cplusplus
bogdanm 85:024bf7f99721 43 extern "C" {
bogdanm 85:024bf7f99721 44 #endif
bogdanm 85:024bf7f99721 45
bogdanm 85:024bf7f99721 46 /* Includes ------------------------------------------------------------------*/
bogdanm 85:024bf7f99721 47 #include "stm32f0xx_hal_def.h"
bogdanm 85:024bf7f99721 48
bogdanm 85:024bf7f99721 49 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 85:024bf7f99721 50 * @{
bogdanm 85:024bf7f99721 51 */
bogdanm 85:024bf7f99721 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup DMAEx
bogdanm 85:024bf7f99721 54 * @{
bogdanm 85:024bf7f99721 55 */
bogdanm 85:024bf7f99721 56
bogdanm 85:024bf7f99721 57 /* Exported types ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 58 /* Exported constants --------------------------------------------------------*/
Kojto 93:e188a91d3eaa 59 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
bogdanm 92:4fc01daae5a5 60 /** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
bogdanm 92:4fc01daae5a5 61 * @{
bogdanm 92:4fc01daae5a5 62 */
Kojto 93:e188a91d3eaa 63 #define DMA1_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 64 #define DMA1_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 65 #define DMA1_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 66 #define DMA1_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 67 #define DMA1_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 68 #if !defined(STM32F030xC)
Kojto 93:e188a91d3eaa 69 #define DMA1_CHANNEL6_RMP 0x50000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 70 #define DMA1_CHANNEL7_RMP 0x60000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 71 #define DMA2_CHANNEL1_RMP 0x00000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 72 #define DMA2_CHANNEL2_RMP 0x10000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 73 #define DMA2_CHANNEL3_RMP 0x20000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 74 #define DMA2_CHANNEL4_RMP 0x30000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 75 #define DMA2_CHANNEL5_RMP 0x40000000 /*!< Internal define for remaping on STM32F09x/30xC */
Kojto 93:e188a91d3eaa 76 #endif /* !defined(STM32F030xC) */
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78 /****************** DMA1 remap bit field definition********************/
bogdanm 92:4fc01daae5a5 79 /* DMA1 - Channel 1 */
Kojto 93:e188a91d3eaa 80 #define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 93:e188a91d3eaa 81 #define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_ADC) /*!< Remap ADC on DMA1 Channel 1*/
Kojto 93:e188a91d3eaa 82 #define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 83 #define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 84 #define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 85 #define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 86 #define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 87 #define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 88 #define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 89 #define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 90 #if !defined(STM32F030xC)
Kojto 93:e188a91d3eaa 91 #define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 92 #define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP | DMA1_CSELR_CH1_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 1 */
Kojto 93:e188a91d3eaa 93 #endif /* !defined(STM32F030xC) */
Kojto 93:e188a91d3eaa 94
bogdanm 92:4fc01daae5a5 95 /* DMA1 - Channel 2 */
Kojto 93:e188a91d3eaa 96 #define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 93:e188a91d3eaa 97 #define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_ADC) /*!< Remap ADC on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 98 #define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 99 #define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_SPI1_RX) /*!< Remap SPI1 Rx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 100 #define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 101 #define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 102 #define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 103 #define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 104 #define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 105 #define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 106 #define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 107 #define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 108 #define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 109 #if !defined(STM32F030xC)
Kojto 93:e188a91d3eaa 110 #define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 111 #define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP | DMA1_CSELR_CH2_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 2 */
Kojto 93:e188a91d3eaa 112 #endif /* !defined(STM32F030xC) */
Kojto 93:e188a91d3eaa 113
bogdanm 92:4fc01daae5a5 114 /* DMA1 - Channel 3 */
Kojto 93:e188a91d3eaa 115 #define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 93:e188a91d3eaa 116 #define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 117 #if !defined(STM32F030xC)
Kojto 93:e188a91d3eaa 118 #define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_DAC_CH1) /*!< Remap DAC Channel 1on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 119 #endif /* !defined(STM32F030xC) */
Kojto 93:e188a91d3eaa 120 #define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 121 #define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_SPI1_TX) /*!< Remap SPI1 Tx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 122 #define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 123 #if !defined(STM32F030xC)
Kojto 93:e188a91d3eaa 124 #define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 125 #endif /* !defined(STM32F030xC) */
Kojto 93:e188a91d3eaa 126 #define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 127 #define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 128 #define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 129 #define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 130 #define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 131 #define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 132 #define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 133 #define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 134 #if !defined(STM32F030xC)
Kojto 93:e188a91d3eaa 135 #define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 136 #define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP | DMA1_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 3 */
Kojto 93:e188a91d3eaa 137 #endif /* !defined(STM32F030xC) */
Kojto 93:e188a91d3eaa 138
bogdanm 92:4fc01daae5a5 139 /* DMA1 - Channel 4 */
Kojto 93:e188a91d3eaa 140 #define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 93:e188a91d3eaa 141 #define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 142 #if !defined(STM32F030xC)
Kojto 93:e188a91d3eaa 143 #define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_DAC_CH2) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 144 #endif /* !defined(STM32F030xC) */
Kojto 93:e188a91d3eaa 145 #define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_I2C2_TX) /*!< Remap I2C2 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 146 #define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 147 #if !defined(STM32F030xC)
Kojto 93:e188a91d3eaa 148 #define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 149 #endif /* !defined(STM32F030xC) */
Kojto 93:e188a91d3eaa 150 #define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 151 #define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 152 #define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 153 #define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 154 #define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 155 #define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 156 #define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 157 #define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 158 #define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 159 #define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 160 #if !defined(STM32F030xC)
Kojto 93:e188a91d3eaa 161 #define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 162 #define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP | DMA1_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 4 */
Kojto 93:e188a91d3eaa 163 #endif /* !defined(STM32F030xC) */
Kojto 93:e188a91d3eaa 164
bogdanm 92:4fc01daae5a5 165 /* DMA1 - Channel 5 */
Kojto 93:e188a91d3eaa 166 #define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 93:e188a91d3eaa 167 #define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_I2C2_RX) /*!< Remap I2C2 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 168 #define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_SPI2_TX) /*!< Remap SPI1 Tx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 169 #define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 170 #define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 171 #define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 172 #define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 173 #define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 174 #define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 175 #define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 176 #if !defined(STM32F030xC)
Kojto 93:e188a91d3eaa 177 #define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 178 #define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP | DMA1_CSELR_CH5_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 5 */
Kojto 93:e188a91d3eaa 179 #endif /* !defined(STM32F030xC) */
Kojto 93:e188a91d3eaa 180
Kojto 93:e188a91d3eaa 181 #if !defined(STM32F030xC)
bogdanm 92:4fc01daae5a5 182 /* DMA1 - Channel 6 */
Kojto 93:e188a91d3eaa 183 #define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 93:e188a91d3eaa 184 #define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_I2C1_TX) /*!< Remap I2C1 Tx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 185 #define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_SPI2_RX) /*!< Remap SPI2 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 186 #define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH1) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 187 #define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH2) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 188 #define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM1_CH3) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 189 #define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_CH1) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 190 #define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM3_TRIG) /*!< Remap TIM3 Trig on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 191 #define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_CH1) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 192 #define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_TIM16_UP) /*!< Remap TIM16 up on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 193 #define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART1_RX) /*!< Remap USART1 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 194 #define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART2_RX) /*!< Remap USART2 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 195 #define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART3_RX) /*!< Remap USART3 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 196 #define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART4_RX) /*!< Remap USART4 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 197 #define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART5_RX) /*!< Remap USART5 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 198 #define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART6_RX) /*!< Remap USART6 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 199 #define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART7_RX) /*!< Remap USART7 Rx on DMA1 channel 6 */
Kojto 93:e188a91d3eaa 200 #define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP | DMA1_CSELR_CH6_USART8_RX) /*!< Remap USART8 Rx on DMA1 channel 6 */
bogdanm 92:4fc01daae5a5 201 /* DMA1 - Channel 7 */
Kojto 93:e188a91d3eaa 202 #define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_DEFAULT) /*!< Default remap position for DMA1 */
Kojto 93:e188a91d3eaa 203 #define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_I2C1_RX) /*!< Remap I2C1 Rx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 204 #define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_SPI2_TX) /*!< Remap SPI2 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 205 #define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH2) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 206 #define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM2_CH4) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 207 #define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_CH1) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 208 #define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_TIM17_UP) /*!< Remap TIM17 up on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 209 #define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART1_TX) /*!< Remap USART1 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 210 #define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART2_TX) /*!< Remap USART2 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 211 #define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART3_TX) /*!< Remap USART3 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 212 #define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART4_TX) /*!< Remap USART4 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 213 #define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART5_TX) /*!< Remap USART5 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 214 #define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART6_TX) /*!< Remap USART6 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 215 #define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART7_TX) /*!< Remap USART7 Tx on DMA1 channel 7 */
Kojto 93:e188a91d3eaa 216 #define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP | DMA1_CSELR_CH7_USART8_TX) /*!< Remap USART8 Tx on DMA1 channel 7 */
bogdanm 92:4fc01daae5a5 217
bogdanm 92:4fc01daae5a5 218 /****************** DMA2 remap bit field definition********************/
bogdanm 92:4fc01daae5a5 219 /* DMA2 - Channel 1 */
Kojto 93:e188a91d3eaa 220 #define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
Kojto 93:e188a91d3eaa 221 #define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_I2C2_TX) /*!< Remap I2C2 TX on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 222 #define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 223 #define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 224 #define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 225 #define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 226 #define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 227 #define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 228 #define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 1 */
Kojto 93:e188a91d3eaa 229 #define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP | DMA2_CSELR_CH1_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 1 */
bogdanm 92:4fc01daae5a5 230 /* DMA2 - Channel 2 */
Kojto 93:e188a91d3eaa 231 #define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
Kojto 93:e188a91d3eaa 232 #define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_I2C2_RX) /*!< Remap I2C2 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 233 #define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 234 #define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 235 #define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 236 #define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 237 #define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 238 #define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 239 #define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 2 */
Kojto 93:e188a91d3eaa 240 #define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP | DMA2_CSELR_CH2_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 2 */
bogdanm 92:4fc01daae5a5 241 /* DMA2 - Channel 3 */
Kojto 93:e188a91d3eaa 242 #define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
Kojto 93:e188a91d3eaa 243 #define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_TIM6_UP) /*!< Remap TIM6 up on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 244 #define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_DAC_CH1) /*!< Remap DAC channel 1 on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 245 #define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_SPI1_RX) /*!< Remap SPI1 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 246 #define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART1_RX) /*!< Remap USART1 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 247 #define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART2_RX) /*!< Remap USART2 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 248 #define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART3_RX) /*!< Remap USART3 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 249 #define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART4_RX) /*!< Remap USART4 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 250 #define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART5_RX) /*!< Remap USART5 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 251 #define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART6_RX) /*!< Remap USART6 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 252 #define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART7_RX) /*!< Remap USART7 Rx on DMA2 channel 3 */
Kojto 93:e188a91d3eaa 253 #define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP | DMA2_CSELR_CH3_USART8_RX) /*!< Remap USART8 Rx on DMA2 channel 3 */
bogdanm 92:4fc01daae5a5 254 /* DMA2 - Channel 4 */
Kojto 93:e188a91d3eaa 255 #define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
Kojto 93:e188a91d3eaa 256 #define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_TIM7_UP) /*!< Remap TIM7 up on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 257 #define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_DAC_CH2) /*!< Remap DAC channel 2 on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 258 #define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_SPI1_TX) /*!< Remap SPI1 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 259 #define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 260 #define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 261 #define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 262 #define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 263 #define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 264 #define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 265 #define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 4 */
Kojto 93:e188a91d3eaa 266 #define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP | DMA2_CSELR_CH4_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 4 */
bogdanm 92:4fc01daae5a5 267 /* DMA2 - Channel 5 */
Kojto 93:e188a91d3eaa 268 #define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_DEFAULT) /*!< Default remap position for DMA2 */
Kojto 93:e188a91d3eaa 269 #define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_ADC) /*!< Remap ADC on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 270 #define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART1_TX) /*!< Remap USART1 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 271 #define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART2_TX) /*!< Remap USART2 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 272 #define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART3_TX) /*!< Remap USART3 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 273 #define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART4_TX) /*!< Remap USART4 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 274 #define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART5_TX) /*!< Remap USART5 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 275 #define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART6_TX) /*!< Remap USART6 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 276 #define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART7_TX) /*!< Remap USART7 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 277 #define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP | DMA2_CSELR_CH5_USART8_TX) /*!< Remap USART8 Tx on DMA2 channel 5 */
Kojto 93:e188a91d3eaa 278 #endif /* !defined(STM32F030xC) */
bogdanm 92:4fc01daae5a5 279
Kojto 93:e188a91d3eaa 280 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 281 #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 282 ((REQUEST) == HAL_DMA1_CH1_ADC) ||\
bogdanm 92:4fc01daae5a5 283 ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
bogdanm 92:4fc01daae5a5 284 ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
bogdanm 92:4fc01daae5a5 285 ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
bogdanm 92:4fc01daae5a5 286 ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
bogdanm 92:4fc01daae5a5 287 ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
bogdanm 92:4fc01daae5a5 288 ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
bogdanm 92:4fc01daae5a5 289 ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
bogdanm 92:4fc01daae5a5 290 ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
bogdanm 92:4fc01daae5a5 291 ((REQUEST) == HAL_DMA1_CH1_USART7_RX) ||\
bogdanm 92:4fc01daae5a5 292 ((REQUEST) == HAL_DMA1_CH1_USART8_RX) ||\
bogdanm 92:4fc01daae5a5 293 ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 294 ((REQUEST) == HAL_DMA1_CH2_ADC) ||\
bogdanm 92:4fc01daae5a5 295 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
bogdanm 92:4fc01daae5a5 296 ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
bogdanm 92:4fc01daae5a5 297 ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
bogdanm 92:4fc01daae5a5 298 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
bogdanm 92:4fc01daae5a5 299 ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
bogdanm 92:4fc01daae5a5 300 ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
bogdanm 92:4fc01daae5a5 301 ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
bogdanm 92:4fc01daae5a5 302 ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
bogdanm 92:4fc01daae5a5 303 ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
bogdanm 92:4fc01daae5a5 304 ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
bogdanm 92:4fc01daae5a5 305 ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
bogdanm 92:4fc01daae5a5 306 ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
bogdanm 92:4fc01daae5a5 307 ((REQUEST) == HAL_DMA1_CH2_USART7_TX) ||\
bogdanm 92:4fc01daae5a5 308 ((REQUEST) == HAL_DMA1_CH2_USART8_TX) ||\
bogdanm 92:4fc01daae5a5 309 ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 310 ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
bogdanm 92:4fc01daae5a5 311 ((REQUEST) == HAL_DMA1_CH3_DAC_CH1) ||\
bogdanm 92:4fc01daae5a5 312 ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
bogdanm 92:4fc01daae5a5 313 ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
bogdanm 92:4fc01daae5a5 314 ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
bogdanm 92:4fc01daae5a5 315 ((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) ||\
bogdanm 92:4fc01daae5a5 316 ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
bogdanm 92:4fc01daae5a5 317 ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
bogdanm 92:4fc01daae5a5 318 ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
bogdanm 92:4fc01daae5a5 319 ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
bogdanm 92:4fc01daae5a5 320 ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
bogdanm 92:4fc01daae5a5 321 ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
bogdanm 92:4fc01daae5a5 322 ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
bogdanm 92:4fc01daae5a5 323 ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
bogdanm 92:4fc01daae5a5 324 ((REQUEST) == HAL_DMA1_CH3_USART7_RX) ||\
bogdanm 92:4fc01daae5a5 325 ((REQUEST) == HAL_DMA1_CH3_USART8_RX) ||\
bogdanm 92:4fc01daae5a5 326 ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 327 ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
bogdanm 92:4fc01daae5a5 328 ((REQUEST) == HAL_DMA1_CH4_DAC_CH2) ||\
bogdanm 92:4fc01daae5a5 329 ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
bogdanm 92:4fc01daae5a5 330 ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
bogdanm 92:4fc01daae5a5 331 ((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) ||\
bogdanm 92:4fc01daae5a5 332 ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
bogdanm 92:4fc01daae5a5 333 ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
bogdanm 92:4fc01daae5a5 334 ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
bogdanm 92:4fc01daae5a5 335 ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
bogdanm 92:4fc01daae5a5 336 ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
bogdanm 92:4fc01daae5a5 337 ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
bogdanm 92:4fc01daae5a5 338 ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
bogdanm 92:4fc01daae5a5 339 ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
bogdanm 92:4fc01daae5a5 340 ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
bogdanm 92:4fc01daae5a5 341 ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
bogdanm 92:4fc01daae5a5 342 ((REQUEST) == HAL_DMA1_CH4_USART7_TX) ||\
bogdanm 92:4fc01daae5a5 343 ((REQUEST) == HAL_DMA1_CH4_USART8_TX) ||\
bogdanm 92:4fc01daae5a5 344 ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 345 ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
bogdanm 92:4fc01daae5a5 346 ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
bogdanm 92:4fc01daae5a5 347 ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
bogdanm 92:4fc01daae5a5 348 ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
bogdanm 92:4fc01daae5a5 349 ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
bogdanm 92:4fc01daae5a5 350 ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
bogdanm 92:4fc01daae5a5 351 ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
bogdanm 92:4fc01daae5a5 352 ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
bogdanm 92:4fc01daae5a5 353 ((REQUEST) == HAL_DMA1_CH5_USART6_RX) ||\
bogdanm 92:4fc01daae5a5 354 ((REQUEST) == HAL_DMA1_CH5_USART7_RX) ||\
bogdanm 92:4fc01daae5a5 355 ((REQUEST) == HAL_DMA1_CH5_USART8_RX) ||\
bogdanm 92:4fc01daae5a5 356 ((REQUEST) == HAL_DMA1_CH6_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 357 ((REQUEST) == HAL_DMA1_CH6_I2C1_TX) ||\
bogdanm 92:4fc01daae5a5 358 ((REQUEST) == HAL_DMA1_CH6_SPI2_RX) ||\
bogdanm 92:4fc01daae5a5 359 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) ||\
bogdanm 92:4fc01daae5a5 360 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) ||\
bogdanm 92:4fc01daae5a5 361 ((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) ||\
bogdanm 92:4fc01daae5a5 362 ((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) ||\
bogdanm 92:4fc01daae5a5 363 ((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) ||\
bogdanm 92:4fc01daae5a5 364 ((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) ||\
bogdanm 92:4fc01daae5a5 365 ((REQUEST) == HAL_DMA1_CH6_TIM16_UP) ||\
bogdanm 92:4fc01daae5a5 366 ((REQUEST) == HAL_DMA1_CH6_USART1_RX) ||\
bogdanm 92:4fc01daae5a5 367 ((REQUEST) == HAL_DMA1_CH6_USART2_RX) ||\
bogdanm 92:4fc01daae5a5 368 ((REQUEST) == HAL_DMA1_CH6_USART3_RX) ||\
bogdanm 92:4fc01daae5a5 369 ((REQUEST) == HAL_DMA1_CH6_USART4_RX) ||\
bogdanm 92:4fc01daae5a5 370 ((REQUEST) == HAL_DMA1_CH6_USART5_RX) ||\
bogdanm 92:4fc01daae5a5 371 ((REQUEST) == HAL_DMA1_CH6_USART6_RX) ||\
bogdanm 92:4fc01daae5a5 372 ((REQUEST) == HAL_DMA1_CH6_USART7_RX) ||\
bogdanm 92:4fc01daae5a5 373 ((REQUEST) == HAL_DMA1_CH6_USART8_RX) ||\
bogdanm 92:4fc01daae5a5 374 ((REQUEST) == HAL_DMA1_CH7_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 375 ((REQUEST) == HAL_DMA1_CH7_I2C1_RX) ||\
bogdanm 92:4fc01daae5a5 376 ((REQUEST) == HAL_DMA1_CH7_SPI2_TX) ||\
bogdanm 92:4fc01daae5a5 377 ((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) ||\
bogdanm 92:4fc01daae5a5 378 ((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) ||\
bogdanm 92:4fc01daae5a5 379 ((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) ||\
bogdanm 92:4fc01daae5a5 380 ((REQUEST) == HAL_DMA1_CH7_TIM17_UP) ||\
bogdanm 92:4fc01daae5a5 381 ((REQUEST) == HAL_DMA1_CH7_USART1_TX) ||\
bogdanm 92:4fc01daae5a5 382 ((REQUEST) == HAL_DMA1_CH7_USART2_TX) ||\
bogdanm 92:4fc01daae5a5 383 ((REQUEST) == HAL_DMA1_CH7_USART3_TX) ||\
bogdanm 92:4fc01daae5a5 384 ((REQUEST) == HAL_DMA1_CH7_USART4_TX) ||\
bogdanm 92:4fc01daae5a5 385 ((REQUEST) == HAL_DMA1_CH7_USART5_TX) ||\
bogdanm 92:4fc01daae5a5 386 ((REQUEST) == HAL_DMA1_CH7_USART6_TX) ||\
bogdanm 92:4fc01daae5a5 387 ((REQUEST) == HAL_DMA1_CH7_USART7_TX) ||\
bogdanm 92:4fc01daae5a5 388 ((REQUEST) == HAL_DMA1_CH7_USART8_TX))
bogdanm 92:4fc01daae5a5 389
bogdanm 92:4fc01daae5a5 390 #define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 391 ((REQUEST) == HAL_DMA2_CH1_I2C2_TX) ||\
bogdanm 92:4fc01daae5a5 392 ((REQUEST) == HAL_DMA2_CH1_USART1_TX) ||\
bogdanm 92:4fc01daae5a5 393 ((REQUEST) == HAL_DMA2_CH1_USART2_TX) ||\
bogdanm 92:4fc01daae5a5 394 ((REQUEST) == HAL_DMA2_CH1_USART3_TX) ||\
bogdanm 92:4fc01daae5a5 395 ((REQUEST) == HAL_DMA2_CH1_USART4_TX) ||\
bogdanm 92:4fc01daae5a5 396 ((REQUEST) == HAL_DMA2_CH1_USART5_TX) ||\
bogdanm 92:4fc01daae5a5 397 ((REQUEST) == HAL_DMA2_CH1_USART6_TX) ||\
bogdanm 92:4fc01daae5a5 398 ((REQUEST) == HAL_DMA2_CH1_USART7_TX) ||\
bogdanm 92:4fc01daae5a5 399 ((REQUEST) == HAL_DMA2_CH1_USART8_TX) ||\
bogdanm 92:4fc01daae5a5 400 ((REQUEST) == HAL_DMA2_CH2_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 401 ((REQUEST) == HAL_DMA2_CH2_I2C2_RX) ||\
bogdanm 92:4fc01daae5a5 402 ((REQUEST) == HAL_DMA2_CH2_USART1_RX) ||\
bogdanm 92:4fc01daae5a5 403 ((REQUEST) == HAL_DMA2_CH2_USART2_RX) ||\
bogdanm 92:4fc01daae5a5 404 ((REQUEST) == HAL_DMA2_CH2_USART3_RX) ||\
bogdanm 92:4fc01daae5a5 405 ((REQUEST) == HAL_DMA2_CH2_USART4_RX) ||\
bogdanm 92:4fc01daae5a5 406 ((REQUEST) == HAL_DMA2_CH2_USART5_RX) ||\
bogdanm 92:4fc01daae5a5 407 ((REQUEST) == HAL_DMA2_CH2_USART6_RX) ||\
bogdanm 92:4fc01daae5a5 408 ((REQUEST) == HAL_DMA2_CH2_USART7_RX) ||\
bogdanm 92:4fc01daae5a5 409 ((REQUEST) == HAL_DMA2_CH2_USART8_RX) ||\
bogdanm 92:4fc01daae5a5 410 ((REQUEST) == HAL_DMA2_CH3_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 411 ((REQUEST) == HAL_DMA2_CH3_TIM6_UP) ||\
bogdanm 92:4fc01daae5a5 412 ((REQUEST) == HAL_DMA2_CH3_DAC_CH1) ||\
bogdanm 92:4fc01daae5a5 413 ((REQUEST) == HAL_DMA2_CH3_SPI1_RX) ||\
bogdanm 92:4fc01daae5a5 414 ((REQUEST) == HAL_DMA2_CH3_USART1_RX) ||\
bogdanm 92:4fc01daae5a5 415 ((REQUEST) == HAL_DMA2_CH3_USART2_RX) ||\
bogdanm 92:4fc01daae5a5 416 ((REQUEST) == HAL_DMA2_CH3_USART3_RX) ||\
bogdanm 92:4fc01daae5a5 417 ((REQUEST) == HAL_DMA2_CH3_USART4_RX) ||\
bogdanm 92:4fc01daae5a5 418 ((REQUEST) == HAL_DMA2_CH3_USART5_RX) ||\
bogdanm 92:4fc01daae5a5 419 ((REQUEST) == HAL_DMA2_CH3_USART6_RX) ||\
bogdanm 92:4fc01daae5a5 420 ((REQUEST) == HAL_DMA2_CH3_USART7_RX) ||\
bogdanm 92:4fc01daae5a5 421 ((REQUEST) == HAL_DMA2_CH3_USART8_RX) ||\
bogdanm 92:4fc01daae5a5 422 ((REQUEST) == HAL_DMA2_CH4_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 423 ((REQUEST) == HAL_DMA2_CH4_TIM7_UP) ||\
bogdanm 92:4fc01daae5a5 424 ((REQUEST) == HAL_DMA2_CH4_DAC_CH2) ||\
bogdanm 92:4fc01daae5a5 425 ((REQUEST) == HAL_DMA2_CH4_SPI1_TX) ||\
bogdanm 92:4fc01daae5a5 426 ((REQUEST) == HAL_DMA2_CH4_USART1_TX) ||\
bogdanm 92:4fc01daae5a5 427 ((REQUEST) == HAL_DMA2_CH4_USART2_TX) ||\
bogdanm 92:4fc01daae5a5 428 ((REQUEST) == HAL_DMA2_CH4_USART3_TX) ||\
bogdanm 92:4fc01daae5a5 429 ((REQUEST) == HAL_DMA2_CH4_USART4_TX) ||\
bogdanm 92:4fc01daae5a5 430 ((REQUEST) == HAL_DMA2_CH4_USART5_TX) ||\
bogdanm 92:4fc01daae5a5 431 ((REQUEST) == HAL_DMA2_CH4_USART6_TX) ||\
bogdanm 92:4fc01daae5a5 432 ((REQUEST) == HAL_DMA2_CH4_USART7_TX) ||\
bogdanm 92:4fc01daae5a5 433 ((REQUEST) == HAL_DMA2_CH4_USART8_TX) ||\
bogdanm 92:4fc01daae5a5 434 ((REQUEST) == HAL_DMA2_CH5_DEFAULT) ||\
bogdanm 92:4fc01daae5a5 435 ((REQUEST) == HAL_DMA2_CH5_ADC) ||\
bogdanm 92:4fc01daae5a5 436 ((REQUEST) == HAL_DMA2_CH5_USART1_TX) ||\
bogdanm 92:4fc01daae5a5 437 ((REQUEST) == HAL_DMA2_CH5_USART2_TX) ||\
bogdanm 92:4fc01daae5a5 438 ((REQUEST) == HAL_DMA2_CH5_USART3_TX) ||\
bogdanm 92:4fc01daae5a5 439 ((REQUEST) == HAL_DMA2_CH5_USART4_TX) ||\
bogdanm 92:4fc01daae5a5 440 ((REQUEST) == HAL_DMA2_CH5_USART5_TX) ||\
bogdanm 92:4fc01daae5a5 441 ((REQUEST) == HAL_DMA2_CH5_USART6_TX) ||\
bogdanm 92:4fc01daae5a5 442 ((REQUEST) == HAL_DMA2_CH5_USART7_TX) ||\
bogdanm 92:4fc01daae5a5 443 ((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
Kojto 93:e188a91d3eaa 444 #endif /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 445
Kojto 93:e188a91d3eaa 446 #if defined(STM32F030xC)
Kojto 93:e188a91d3eaa 447 #define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) ||\
Kojto 93:e188a91d3eaa 448 ((REQUEST) == HAL_DMA1_CH1_ADC) ||\
Kojto 93:e188a91d3eaa 449 ((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) ||\
Kojto 93:e188a91d3eaa 450 ((REQUEST) == HAL_DMA1_CH1_TIM17_UP) ||\
Kojto 93:e188a91d3eaa 451 ((REQUEST) == HAL_DMA1_CH1_USART1_RX) ||\
Kojto 93:e188a91d3eaa 452 ((REQUEST) == HAL_DMA1_CH1_USART2_RX) ||\
Kojto 93:e188a91d3eaa 453 ((REQUEST) == HAL_DMA1_CH1_USART3_RX) ||\
Kojto 93:e188a91d3eaa 454 ((REQUEST) == HAL_DMA1_CH1_USART4_RX) ||\
Kojto 93:e188a91d3eaa 455 ((REQUEST) == HAL_DMA1_CH1_USART5_RX) ||\
Kojto 93:e188a91d3eaa 456 ((REQUEST) == HAL_DMA1_CH1_USART6_RX) ||\
Kojto 93:e188a91d3eaa 457 ((REQUEST) == HAL_DMA1_CH2_DEFAULT) ||\
Kojto 93:e188a91d3eaa 458 ((REQUEST) == HAL_DMA1_CH2_ADC) ||\
Kojto 93:e188a91d3eaa 459 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
Kojto 93:e188a91d3eaa 460 ((REQUEST) == HAL_DMA1_CH2_SPI1_RX) ||\
Kojto 93:e188a91d3eaa 461 ((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) ||\
Kojto 93:e188a91d3eaa 462 ((REQUEST) == HAL_DMA1_CH2_I2C1_TX) ||\
Kojto 93:e188a91d3eaa 463 ((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) ||\
Kojto 93:e188a91d3eaa 464 ((REQUEST) == HAL_DMA1_CH2_TIM17_UP) ||\
Kojto 93:e188a91d3eaa 465 ((REQUEST) == HAL_DMA1_CH2_USART1_TX) ||\
Kojto 93:e188a91d3eaa 466 ((REQUEST) == HAL_DMA1_CH2_USART2_TX) ||\
Kojto 93:e188a91d3eaa 467 ((REQUEST) == HAL_DMA1_CH2_USART3_TX) ||\
Kojto 93:e188a91d3eaa 468 ((REQUEST) == HAL_DMA1_CH2_USART4_TX) ||\
Kojto 93:e188a91d3eaa 469 ((REQUEST) == HAL_DMA1_CH2_USART5_TX) ||\
Kojto 93:e188a91d3eaa 470 ((REQUEST) == HAL_DMA1_CH2_USART6_TX) ||\
Kojto 93:e188a91d3eaa 471 ((REQUEST) == HAL_DMA1_CH3_DEFAULT) ||\
Kojto 93:e188a91d3eaa 472 ((REQUEST) == HAL_DMA1_CH3_TIM6_UP) ||\
Kojto 93:e188a91d3eaa 473 ((REQUEST) == HAL_DMA1_CH3_I2C1_RX) ||\
Kojto 93:e188a91d3eaa 474 ((REQUEST) == HAL_DMA1_CH3_SPI1_TX) ||\
Kojto 93:e188a91d3eaa 475 ((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) ||\
Kojto 93:e188a91d3eaa 476 ((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) ||\
Kojto 93:e188a91d3eaa 477 ((REQUEST) == HAL_DMA1_CH3_TIM16_UP) ||\
Kojto 93:e188a91d3eaa 478 ((REQUEST) == HAL_DMA1_CH3_USART1_RX) ||\
Kojto 93:e188a91d3eaa 479 ((REQUEST) == HAL_DMA1_CH3_USART2_RX) ||\
Kojto 93:e188a91d3eaa 480 ((REQUEST) == HAL_DMA1_CH3_USART3_RX) ||\
Kojto 93:e188a91d3eaa 481 ((REQUEST) == HAL_DMA1_CH3_USART4_RX) ||\
Kojto 93:e188a91d3eaa 482 ((REQUEST) == HAL_DMA1_CH3_USART5_RX) ||\
Kojto 93:e188a91d3eaa 483 ((REQUEST) == HAL_DMA1_CH3_USART6_RX) ||\
Kojto 93:e188a91d3eaa 484 ((REQUEST) == HAL_DMA1_CH4_DEFAULT) ||\
Kojto 93:e188a91d3eaa 485 ((REQUEST) == HAL_DMA1_CH4_TIM7_UP) ||\
Kojto 93:e188a91d3eaa 486 ((REQUEST) == HAL_DMA1_CH4_I2C2_TX) ||\
Kojto 93:e188a91d3eaa 487 ((REQUEST) == HAL_DMA1_CH4_SPI2_RX) ||\
Kojto 93:e188a91d3eaa 488 ((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) ||\
Kojto 93:e188a91d3eaa 489 ((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) ||\
Kojto 93:e188a91d3eaa 490 ((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) ||\
Kojto 93:e188a91d3eaa 491 ((REQUEST) == HAL_DMA1_CH4_TIM16_UP) ||\
Kojto 93:e188a91d3eaa 492 ((REQUEST) == HAL_DMA1_CH4_USART1_TX) ||\
Kojto 93:e188a91d3eaa 493 ((REQUEST) == HAL_DMA1_CH4_USART2_TX) ||\
Kojto 93:e188a91d3eaa 494 ((REQUEST) == HAL_DMA1_CH4_USART3_TX) ||\
Kojto 93:e188a91d3eaa 495 ((REQUEST) == HAL_DMA1_CH4_USART4_TX) ||\
Kojto 93:e188a91d3eaa 496 ((REQUEST) == HAL_DMA1_CH4_USART5_TX) ||\
Kojto 93:e188a91d3eaa 497 ((REQUEST) == HAL_DMA1_CH4_USART6_TX) ||\
Kojto 93:e188a91d3eaa 498 ((REQUEST) == HAL_DMA1_CH5_DEFAULT) ||\
Kojto 93:e188a91d3eaa 499 ((REQUEST) == HAL_DMA1_CH5_I2C2_RX) ||\
Kojto 93:e188a91d3eaa 500 ((REQUEST) == HAL_DMA1_CH5_SPI2_TX) ||\
Kojto 93:e188a91d3eaa 501 ((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) ||\
Kojto 93:e188a91d3eaa 502 ((REQUEST) == HAL_DMA1_CH5_USART1_RX) ||\
Kojto 93:e188a91d3eaa 503 ((REQUEST) == HAL_DMA1_CH5_USART2_RX) ||\
Kojto 93:e188a91d3eaa 504 ((REQUEST) == HAL_DMA1_CH5_USART3_RX) ||\
Kojto 93:e188a91d3eaa 505 ((REQUEST) == HAL_DMA1_CH5_USART4_RX) ||\
Kojto 93:e188a91d3eaa 506 ((REQUEST) == HAL_DMA1_CH5_USART5_RX) ||\
Kojto 93:e188a91d3eaa 507 ((REQUEST) == HAL_DMA1_CH5_USART6_RX))
Kojto 93:e188a91d3eaa 508 #endif /* STM32F030xC */
Kojto 93:e188a91d3eaa 509
bogdanm 92:4fc01daae5a5 510 /**
bogdanm 92:4fc01daae5a5 511 * @}
bogdanm 92:4fc01daae5a5 512 */
Kojto 93:e188a91d3eaa 513 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
bogdanm 92:4fc01daae5a5 514
bogdanm 85:024bf7f99721 515 /* Exported macros -----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 516
bogdanm 92:4fc01daae5a5 517 /** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
bogdanm 85:024bf7f99721 518 * @{
bogdanm 85:024bf7f99721 519 */
bogdanm 85:024bf7f99721 520 /* Interrupt & Flag management */
bogdanm 85:024bf7f99721 521
bogdanm 85:024bf7f99721 522 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
bogdanm 85:024bf7f99721 523 /**
bogdanm 85:024bf7f99721 524 * @brief Returns the current DMA Channel transfer complete flag.
bogdanm 85:024bf7f99721 525 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 526 * @retval The specified transfer complete flag index.
bogdanm 85:024bf7f99721 527 */
bogdanm 85:024bf7f99721 528 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm 85:024bf7f99721 529 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
bogdanm 85:024bf7f99721 530 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
bogdanm 85:024bf7f99721 531 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
bogdanm 85:024bf7f99721 532 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
bogdanm 85:024bf7f99721 533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
bogdanm 85:024bf7f99721 534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
bogdanm 85:024bf7f99721 535 DMA_FLAG_TC7)
bogdanm 85:024bf7f99721 536
bogdanm 85:024bf7f99721 537 /**
bogdanm 85:024bf7f99721 538 * @brief Returns the current DMA Channel half transfer complete flag.
bogdanm 85:024bf7f99721 539 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 540 * @retval The specified half transfer complete flag index.
bogdanm 85:024bf7f99721 541 */
bogdanm 85:024bf7f99721 542 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm 85:024bf7f99721 543 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
bogdanm 85:024bf7f99721 544 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
bogdanm 85:024bf7f99721 545 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
bogdanm 85:024bf7f99721 546 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
bogdanm 85:024bf7f99721 547 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
bogdanm 85:024bf7f99721 548 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
bogdanm 85:024bf7f99721 549 DMA_FLAG_HT7)
bogdanm 85:024bf7f99721 550
bogdanm 85:024bf7f99721 551 /**
bogdanm 85:024bf7f99721 552 * @brief Returns the current DMA Channel transfer error flag.
bogdanm 85:024bf7f99721 553 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 554 * @retval The specified transfer error flag index.
bogdanm 85:024bf7f99721 555 */
bogdanm 85:024bf7f99721 556 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm 85:024bf7f99721 557 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
bogdanm 85:024bf7f99721 558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
bogdanm 85:024bf7f99721 559 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
bogdanm 85:024bf7f99721 560 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
bogdanm 85:024bf7f99721 561 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
bogdanm 85:024bf7f99721 562 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
bogdanm 85:024bf7f99721 563 DMA_FLAG_TE7)
bogdanm 85:024bf7f99721 564
bogdanm 85:024bf7f99721 565 /**
bogdanm 85:024bf7f99721 566 * @brief Get the DMA Channel pending flags.
bogdanm 85:024bf7f99721 567 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 568 * @param __FLAG__: Get the specified flag.
bogdanm 85:024bf7f99721 569 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 570 * @arg DMA_FLAG_TCx: Transfer complete flag
Kojto 93:e188a91d3eaa 571 * @arg DMA_FLAG_HTx: Half transfer complete flag
Kojto 93:e188a91d3eaa 572 * @arg DMA_FLAG_TEx: Transfer error flag
bogdanm 85:024bf7f99721 573 * Where x can be 1_7 to select the DMA Channel flag.
bogdanm 85:024bf7f99721 574 * @retval The state of FLAG (SET or RESET).
bogdanm 85:024bf7f99721 575 */
bogdanm 85:024bf7f99721 576
bogdanm 85:024bf7f99721 577 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
bogdanm 85:024bf7f99721 578
bogdanm 85:024bf7f99721 579 /**
bogdanm 85:024bf7f99721 580 * @brief Clears the DMA Channel pending flags.
bogdanm 85:024bf7f99721 581 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 582 * @param __FLAG__: specifies the flag to clear.
bogdanm 85:024bf7f99721 583 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 584 * @arg DMA_FLAG_TCx: Transfer complete flag
Kojto 93:e188a91d3eaa 585 * @arg DMA_FLAG_HTx: Half transfer complete flag
Kojto 93:e188a91d3eaa 586 * @arg DMA_FLAG_TEx: Transfer error flag
bogdanm 85:024bf7f99721 587 * Where x can be 1_7 to select the DMA Channel flag.
bogdanm 85:024bf7f99721 588 * @retval None
bogdanm 85:024bf7f99721 589 */
bogdanm 92:4fc01daae5a5 590 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
bogdanm 92:4fc01daae5a5 591
bogdanm 92:4fc01daae5a5 592 #elif defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 593 /**
bogdanm 92:4fc01daae5a5 594 * @brief Returns the current DMA Channel transfer complete flag.
bogdanm 92:4fc01daae5a5 595 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 596 * @retval The specified transfer complete flag index.
bogdanm 92:4fc01daae5a5 597 */
bogdanm 92:4fc01daae5a5 598 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm 92:4fc01daae5a5 599 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
bogdanm 92:4fc01daae5a5 600 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
bogdanm 92:4fc01daae5a5 601 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
bogdanm 92:4fc01daae5a5 602 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
bogdanm 92:4fc01daae5a5 603 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
bogdanm 92:4fc01daae5a5 604 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
bogdanm 92:4fc01daae5a5 605 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
bogdanm 92:4fc01daae5a5 606 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
bogdanm 92:4fc01daae5a5 607 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
bogdanm 92:4fc01daae5a5 608 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
bogdanm 92:4fc01daae5a5 609 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
bogdanm 92:4fc01daae5a5 610 DMA_FLAG_TC5)
bogdanm 92:4fc01daae5a5 611
bogdanm 92:4fc01daae5a5 612 /**
bogdanm 92:4fc01daae5a5 613 * @brief Returns the current DMA Channel half transfer complete flag.
bogdanm 92:4fc01daae5a5 614 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 615 * @retval The specified half transfer complete flag index.
bogdanm 92:4fc01daae5a5 616 */
bogdanm 92:4fc01daae5a5 617 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 618 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
bogdanm 92:4fc01daae5a5 619 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
bogdanm 92:4fc01daae5a5 620 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
bogdanm 92:4fc01daae5a5 621 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
bogdanm 92:4fc01daae5a5 622 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
bogdanm 92:4fc01daae5a5 623 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
bogdanm 92:4fc01daae5a5 624 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
bogdanm 92:4fc01daae5a5 625 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
bogdanm 92:4fc01daae5a5 626 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
bogdanm 92:4fc01daae5a5 627 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
bogdanm 92:4fc01daae5a5 628 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
bogdanm 92:4fc01daae5a5 629 DMA_FLAG_HT5)
bogdanm 92:4fc01daae5a5 630
bogdanm 92:4fc01daae5a5 631 /**
bogdanm 92:4fc01daae5a5 632 * @brief Returns the current DMA Channel transfer error flag.
bogdanm 92:4fc01daae5a5 633 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 634 * @retval The specified transfer error flag index.
bogdanm 92:4fc01daae5a5 635 */
bogdanm 92:4fc01daae5a5 636 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 637 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
bogdanm 92:4fc01daae5a5 638 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
bogdanm 92:4fc01daae5a5 639 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
bogdanm 92:4fc01daae5a5 640 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
bogdanm 92:4fc01daae5a5 641 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
bogdanm 92:4fc01daae5a5 642 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
bogdanm 92:4fc01daae5a5 643 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
bogdanm 92:4fc01daae5a5 644 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
bogdanm 92:4fc01daae5a5 645 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
bogdanm 92:4fc01daae5a5 646 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
bogdanm 92:4fc01daae5a5 647 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
bogdanm 92:4fc01daae5a5 648 DMA_FLAG_TE5)
bogdanm 92:4fc01daae5a5 649
bogdanm 92:4fc01daae5a5 650 /**
bogdanm 92:4fc01daae5a5 651 * @brief Get the DMA Channel pending flags.
bogdanm 92:4fc01daae5a5 652 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 653 * @param __FLAG__: Get the specified flag.
bogdanm 92:4fc01daae5a5 654 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 655 * @arg DMA_FLAG_TCx: Transfer complete flag
Kojto 93:e188a91d3eaa 656 * @arg DMA_FLAG_HTx: Half transfer complete flag
Kojto 93:e188a91d3eaa 657 * @arg DMA_FLAG_TEx: Transfer error flag
bogdanm 92:4fc01daae5a5 658 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
bogdanm 92:4fc01daae5a5 659 * @retval The state of FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 660 */
bogdanm 92:4fc01daae5a5 661
bogdanm 92:4fc01daae5a5 662 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
bogdanm 92:4fc01daae5a5 663 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 664 (DMA1->ISR & (__FLAG__)))
bogdanm 92:4fc01daae5a5 665
bogdanm 92:4fc01daae5a5 666 /**
bogdanm 92:4fc01daae5a5 667 * @brief Clears the DMA Channel pending flags.
bogdanm 92:4fc01daae5a5 668 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 669 * @param __FLAG__: specifies the flag to clear.
bogdanm 92:4fc01daae5a5 670 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 671 * @arg DMA_FLAG_TCx: Transfer complete flag
Kojto 93:e188a91d3eaa 672 * @arg DMA_FLAG_HTx: Half transfer complete flag
Kojto 93:e188a91d3eaa 673 * @arg DMA_FLAG_TEx: Transfer error flag
bogdanm 92:4fc01daae5a5 674 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
bogdanm 92:4fc01daae5a5 675 * @retval None
bogdanm 92:4fc01daae5a5 676 */
bogdanm 92:4fc01daae5a5 677 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
bogdanm 92:4fc01daae5a5 678 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 679 (DMA1->IFCR = (__FLAG__)))
bogdanm 85:024bf7f99721 680
Kojto 93:e188a91d3eaa 681 #else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
bogdanm 85:024bf7f99721 682 /**
bogdanm 85:024bf7f99721 683 * @brief Returns the current DMA Channel transfer complete flag.
bogdanm 85:024bf7f99721 684 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 685 * @retval The specified transfer complete flag index.
bogdanm 85:024bf7f99721 686 */
bogdanm 85:024bf7f99721 687 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm 85:024bf7f99721 688 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
bogdanm 85:024bf7f99721 689 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
bogdanm 85:024bf7f99721 690 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
bogdanm 85:024bf7f99721 691 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
bogdanm 85:024bf7f99721 692 DMA_FLAG_TC5)
bogdanm 85:024bf7f99721 693
bogdanm 85:024bf7f99721 694 /**
bogdanm 85:024bf7f99721 695 * @brief Returns the current DMA Channel half transfer complete flag.
bogdanm 85:024bf7f99721 696 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 697 * @retval The specified half transfer complete flag index.
bogdanm 85:024bf7f99721 698 */
bogdanm 85:024bf7f99721 699 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm 85:024bf7f99721 700 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
bogdanm 85:024bf7f99721 701 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
bogdanm 85:024bf7f99721 702 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
bogdanm 85:024bf7f99721 703 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
bogdanm 85:024bf7f99721 704 DMA_FLAG_HT5)
bogdanm 85:024bf7f99721 705
bogdanm 85:024bf7f99721 706 /**
bogdanm 85:024bf7f99721 707 * @brief Returns the current DMA Channel transfer error flag.
bogdanm 85:024bf7f99721 708 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 709 * @retval The specified transfer error flag index.
bogdanm 85:024bf7f99721 710 */
bogdanm 85:024bf7f99721 711 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm 85:024bf7f99721 712 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
bogdanm 85:024bf7f99721 713 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
bogdanm 85:024bf7f99721 714 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
bogdanm 85:024bf7f99721 715 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
bogdanm 85:024bf7f99721 716 DMA_FLAG_TE5)
bogdanm 85:024bf7f99721 717
bogdanm 85:024bf7f99721 718 /**
bogdanm 85:024bf7f99721 719 * @brief Get the DMA Channel pending flags.
bogdanm 85:024bf7f99721 720 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 721 * @param __FLAG__: Get the specified flag.
bogdanm 85:024bf7f99721 722 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 723 * @arg DMA_FLAG_TCx: Transfer complete flag
Kojto 93:e188a91d3eaa 724 * @arg DMA_FLAG_HTx: Half transfer complete flag
Kojto 93:e188a91d3eaa 725 * @arg DMA_FLAG_TEx: Transfer error flag
bogdanm 85:024bf7f99721 726 * Where x can be 1_5 to select the DMA Channel flag.
bogdanm 85:024bf7f99721 727 * @retval The state of FLAG (SET or RESET).
bogdanm 85:024bf7f99721 728 */
bogdanm 85:024bf7f99721 729
bogdanm 85:024bf7f99721 730 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
bogdanm 85:024bf7f99721 731
bogdanm 85:024bf7f99721 732 /**
bogdanm 85:024bf7f99721 733 * @brief Clears the DMA Channel pending flags.
bogdanm 85:024bf7f99721 734 * @param __HANDLE__: DMA handle
bogdanm 85:024bf7f99721 735 * @param __FLAG__: specifies the flag to clear.
bogdanm 85:024bf7f99721 736 * This parameter can be any combination of the following values:
Kojto 93:e188a91d3eaa 737 * @arg DMA_FLAG_TCx: Transfer complete flag
Kojto 93:e188a91d3eaa 738 * @arg DMA_FLAG_HTx: Half transfer complete flag
Kojto 93:e188a91d3eaa 739 * @arg DMA_FLAG_TEx: Transfer error flag
bogdanm 85:024bf7f99721 740 * Where x can be 1_5 to select the DMA Channel flag.
bogdanm 85:024bf7f99721 741 * @retval None
bogdanm 85:024bf7f99721 742 */
bogdanm 92:4fc01daae5a5 743 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
bogdanm 85:024bf7f99721 744
bogdanm 85:024bf7f99721 745 #endif
bogdanm 85:024bf7f99721 746
bogdanm 92:4fc01daae5a5 747
Kojto 93:e188a91d3eaa 748 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
bogdanm 92:4fc01daae5a5 749 #define __HAL_DMA1_REMAP(__REQUEST__) \
bogdanm 92:4fc01daae5a5 750 do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
Kojto 93:e188a91d3eaa 751 DMA1->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
Kojto 93:e188a91d3eaa 752 DMA1->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
bogdanm 92:4fc01daae5a5 753 }while(0)
bogdanm 92:4fc01daae5a5 754
Kojto 93:e188a91d3eaa 755 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 92:4fc01daae5a5 756 #define __HAL_DMA2_REMAP(__REQUEST__) \
bogdanm 92:4fc01daae5a5 757 do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
Kojto 93:e188a91d3eaa 758 DMA2->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
Kojto 93:e188a91d3eaa 759 DMA2->CSELR |= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
bogdanm 92:4fc01daae5a5 760 }while(0)
Kojto 93:e188a91d3eaa 761 #endif /* STM32F091xC || STM32F098xx */
bogdanm 92:4fc01daae5a5 762
Kojto 93:e188a91d3eaa 763 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
bogdanm 92:4fc01daae5a5 764
bogdanm 85:024bf7f99721 765 /**
bogdanm 85:024bf7f99721 766 * @}
bogdanm 85:024bf7f99721 767 */
bogdanm 85:024bf7f99721 768
bogdanm 85:024bf7f99721 769 /**
bogdanm 85:024bf7f99721 770 * @}
bogdanm 85:024bf7f99721 771 */
bogdanm 85:024bf7f99721 772
bogdanm 85:024bf7f99721 773 /**
bogdanm 85:024bf7f99721 774 * @}
bogdanm 85:024bf7f99721 775 */
bogdanm 85:024bf7f99721 776
bogdanm 85:024bf7f99721 777 #ifdef __cplusplus
bogdanm 85:024bf7f99721 778 }
bogdanm 85:024bf7f99721 779 #endif
bogdanm 85:024bf7f99721 780
bogdanm 85:024bf7f99721 781 #endif /* __STM32F0xx_HAL_DMA_EX_H */
bogdanm 85:024bf7f99721 782
bogdanm 85:024bf7f99721 783 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/