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TARGET_NUCLEO_F072RB/stm32f072xb.h@93:e188a91d3eaa, 2015-02-03 (annotated)

Committer:: Kojto
Date:: Tue Feb 03 15:31:20 2015 +0000
Revision:: 93:e188a91d3eaa
Parent:: 92:4fc01daae5a5

Release 93 of the mbed library



Main changes:



- Renesas RZ_A1H bugfixes - i2c, ticker

- new targets - Nucleo F303RE, Nucleo F070RB, BLE SMURFS,

                Dragonfly 411RE,

- BusXXX - is connected method, plus operators addition

- LPC8xx - I2c fixes

- timestamp_t reverted to uint32_t

- RTX - fixes regarding stack (alignment, magic word)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f072xb.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
Kojto	93:e188a91d3eaa	5	* @version V2.2.0
Kojto	93:e188a91d3eaa	6	* @date 05-December-2014
bogdanm	85:024bf7f99721	7	* @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
bogdanm	85:024bf7f99721	8	*
bogdanm	85:024bf7f99721	9	* This file contains:
bogdanm	85:024bf7f99721	10	* - Data structures and the address mapping for all peripherals
bogdanm	85:024bf7f99721	11	* - Peripheral's registers declarations and bits definition
bogdanm	85:024bf7f99721	12	* - Macros to access peripherals registers hardware
bogdanm	85:024bf7f99721	13	*
bogdanm	85:024bf7f99721	14	******************************************************************************
bogdanm	85:024bf7f99721	15	* @attention
bogdanm	85:024bf7f99721	16	*
bogdanm	85:024bf7f99721	17	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	18	*
bogdanm	85:024bf7f99721	19	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	20	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	21	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	22	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	24	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	25	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	27	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	28	* without specific prior written permission.
bogdanm	85:024bf7f99721	29	*
bogdanm	85:024bf7f99721	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	40	*
bogdanm	85:024bf7f99721	41	******************************************************************************
bogdanm	85:024bf7f99721	42	*/
bogdanm	85:024bf7f99721	43
bogdanm	85:024bf7f99721	44	/** @addtogroup CMSIS_Device
bogdanm	85:024bf7f99721	45	* @{
bogdanm	85:024bf7f99721	46	*/
bogdanm	85:024bf7f99721	47
bogdanm	85:024bf7f99721	48	/** @addtogroup stm32f072xb
bogdanm	85:024bf7f99721	49	* @{
bogdanm	85:024bf7f99721	50	*/
bogdanm	85:024bf7f99721	51
bogdanm	85:024bf7f99721	52	#ifndef __STM32F072xB_H
bogdanm	85:024bf7f99721	53	#define __STM32F072xB_H
bogdanm	85:024bf7f99721	54
bogdanm	85:024bf7f99721	55	#ifdef __cplusplus
bogdanm	85:024bf7f99721	56	extern "C" {
bogdanm	85:024bf7f99721	57	#endif /* __cplusplus */
bogdanm	85:024bf7f99721	58
bogdanm	85:024bf7f99721	59	/** @addtogroup Configuration_section_for_CMSIS
bogdanm	85:024bf7f99721	60	* @{
bogdanm	85:024bf7f99721	61	*/
bogdanm	85:024bf7f99721	62
bogdanm	85:024bf7f99721	63	/**
bogdanm	85:024bf7f99721	64	* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
bogdanm	85:024bf7f99721	65	*/
bogdanm	85:024bf7f99721	66	#define __CM0_REV 0 /!< Core Revision r0p0 /
bogdanm	85:024bf7f99721	67	#define __MPU_PRESENT 0 /!< STM32F0xx do not provide MPU /
bogdanm	85:024bf7f99721	68	#define __NVIC_PRIO_BITS 2 /!< STM32F0xx uses 2 Bits for the Priority Levels /
bogdanm	85:024bf7f99721	69	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
bogdanm	85:024bf7f99721	70
bogdanm	85:024bf7f99721	71	/**
bogdanm	85:024bf7f99721	72	* @}
bogdanm	85:024bf7f99721	73	*/
bogdanm	85:024bf7f99721	74
bogdanm	85:024bf7f99721	75	/** @addtogroup Peripheral_interrupt_number_definition
bogdanm	85:024bf7f99721	76	* @{
bogdanm	85:024bf7f99721	77	*/
bogdanm	85:024bf7f99721	78
bogdanm	85:024bf7f99721	79	/**
bogdanm	85:024bf7f99721	80	* @brief STM32F072x8/STM32F072xB device Interrupt Number Definition
bogdanm	85:024bf7f99721	81	*/
bogdanm	85:024bf7f99721	82	typedef enum
bogdanm	85:024bf7f99721	83	{
bogdanm	85:024bf7f99721	84	/**** Cortex-M0 Processor Exceptions Numbers ************************************************************/
bogdanm	85:024bf7f99721	85	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
bogdanm	85:024bf7f99721	86	HardFault_IRQn = -13, /!< 3 Cortex-M0 Hard Fault Interrupt /
bogdanm	85:024bf7f99721	87	SVC_IRQn = -5, /!< 11 Cortex-M0 SV Call Interrupt /
bogdanm	85:024bf7f99721	88	PendSV_IRQn = -2, /!< 14 Cortex-M0 Pend SV Interrupt /
bogdanm	85:024bf7f99721	89	SysTick_IRQn = -1, /!< 15 Cortex-M0 System Tick Interrupt /
bogdanm	85:024bf7f99721	90
bogdanm	85:024bf7f99721	91	/**** STM32F072x8/STM32F072xB specific Interrupt Numbers ************************************************/
bogdanm	85:024bf7f99721	92	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
bogdanm	85:024bf7f99721	93	PVD_VDDIO2_IRQn = 1, /!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 /
bogdanm	85:024bf7f99721	94	RTC_IRQn = 2, /!< RTC Interrupt through EXTI Lines 17, 19 and 20 /
bogdanm	85:024bf7f99721	95	FLASH_IRQn = 3, /!< FLASH global Interrupt /
bogdanm	85:024bf7f99721	96	RCC_CRS_IRQn = 4, /!< RCC & CRS global Interrupts /
bogdanm	85:024bf7f99721	97	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
bogdanm	85:024bf7f99721	98	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
bogdanm	85:024bf7f99721	99	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
bogdanm	85:024bf7f99721	100	TSC_IRQn = 8, /!< Touch Sensing Controller Interrupts /
bogdanm	85:024bf7f99721	101	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
bogdanm	85:024bf7f99721	102	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
bogdanm	85:024bf7f99721	103	DMA1_Channel4_5_6_7_IRQn = 11, /!< DMA1 Channel 4 to Channel 7 Interrupts /
bogdanm	85:024bf7f99721	104	ADC1_COMP_IRQn = 12, /!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 /
bogdanm	85:024bf7f99721	105	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
bogdanm	85:024bf7f99721	106	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
bogdanm	85:024bf7f99721	107	TIM2_IRQn = 15, /!< TIM2 global Interrupt /
bogdanm	85:024bf7f99721	108	TIM3_IRQn = 16, /!< TIM3 global Interrupt /
bogdanm	85:024bf7f99721	109	TIM6_DAC_IRQn = 17, /!< TIM6 global and DAC channel underrun error Interrupts /
bogdanm	85:024bf7f99721	110	TIM7_IRQn = 18, /!< TIM7 global Interrupt /
bogdanm	85:024bf7f99721	111	TIM14_IRQn = 19, /!< TIM14 global Interrupt /
bogdanm	85:024bf7f99721	112	TIM15_IRQn = 20, /!< TIM15 global Interrupt /
bogdanm	85:024bf7f99721	113	TIM16_IRQn = 21, /!< TIM16 global Interrupt /
bogdanm	85:024bf7f99721	114	TIM17_IRQn = 22, /!< TIM17 global Interrupt /
bogdanm	85:024bf7f99721	115	I2C1_IRQn = 23, /!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) /
bogdanm	92:4fc01daae5a5	116	I2C2_IRQn = 24, /!< I2C2 Event Interrupt /
bogdanm	85:024bf7f99721	117	SPI1_IRQn = 25, /!< SPI1 global Interrupt /
bogdanm	85:024bf7f99721	118	SPI2_IRQn = 26, /!< SPI2 global Interrupt /
bogdanm	85:024bf7f99721	119	USART1_IRQn = 27, /!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) /
bogdanm	85:024bf7f99721	120	USART2_IRQn = 28, /!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) /
bogdanm	85:024bf7f99721	121	USART3_4_IRQn = 29, /!< USART3 and USART4 global Interrupts /
bogdanm	85:024bf7f99721	122	CEC_CAN_IRQn = 30, /!< CEC and CAN global Interrupts & EXTI Line27 Interrupt /
bogdanm	85:024bf7f99721	123	USB_IRQn = 31 /!< USB global Interrupts & EXTI Line18 Interrupt /
bogdanm	85:024bf7f99721	124	} IRQn_Type;
bogdanm	85:024bf7f99721	125
bogdanm	85:024bf7f99721	126	/**
bogdanm	85:024bf7f99721	127	* @}
bogdanm	85:024bf7f99721	128	*/
bogdanm	85:024bf7f99721	129
bogdanm	85:024bf7f99721	130	#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
bogdanm	85:024bf7f99721	131	#include "system_stm32f0xx.h" /* STM32F0xx System Header */
bogdanm	85:024bf7f99721	132	#include <stdint.h>
bogdanm	85:024bf7f99721	133
bogdanm	85:024bf7f99721	134	/** @addtogroup Peripheral_registers_structures
bogdanm	85:024bf7f99721	135	* @{
bogdanm	85:024bf7f99721	136	*/
bogdanm	85:024bf7f99721	137
bogdanm	85:024bf7f99721	138	/**
bogdanm	85:024bf7f99721	139	* @brief Analog to Digital Converter
bogdanm	85:024bf7f99721	140	*/
bogdanm	85:024bf7f99721	141
bogdanm	85:024bf7f99721	142	typedef struct
bogdanm	85:024bf7f99721	143	{
bogdanm	85:024bf7f99721	144	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
bogdanm	85:024bf7f99721	145	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
bogdanm	85:024bf7f99721	146	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
bogdanm	85:024bf7f99721	147	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
bogdanm	85:024bf7f99721	148	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
bogdanm	85:024bf7f99721	149	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
bogdanm	85:024bf7f99721	150	uint32_t RESERVED1; /!< Reserved, 0x18 /
bogdanm	85:024bf7f99721	151	uint32_t RESERVED2; /!< Reserved, 0x1C /
bogdanm	85:024bf7f99721	152	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
bogdanm	85:024bf7f99721	153	uint32_t RESERVED3; /!< Reserved, 0x24 /
bogdanm	85:024bf7f99721	154	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
bogdanm	85:024bf7f99721	155	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
bogdanm	85:024bf7f99721	156	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
bogdanm	85:024bf7f99721	157	}ADC_TypeDef;
bogdanm	85:024bf7f99721	158
bogdanm	85:024bf7f99721	159	typedef struct
bogdanm	85:024bf7f99721	160	{
bogdanm	85:024bf7f99721	161	__IO uint32_t CCR;
bogdanm	85:024bf7f99721	162	}ADC_Common_TypeDef;
bogdanm	85:024bf7f99721	163
bogdanm	85:024bf7f99721	164	/**
bogdanm	85:024bf7f99721	165	* @brief Controller Area Network TxMailBox
bogdanm	85:024bf7f99721	166	*/
bogdanm	85:024bf7f99721	167	typedef struct
bogdanm	85:024bf7f99721	168	{
bogdanm	85:024bf7f99721	169	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
bogdanm	85:024bf7f99721	170	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
bogdanm	85:024bf7f99721	171	__IO uint32_t TDLR; /!< CAN mailbox data low register /
bogdanm	85:024bf7f99721	172	__IO uint32_t TDHR; /!< CAN mailbox data high register /
bogdanm	85:024bf7f99721	173	}CAN_TxMailBox_TypeDef;
bogdanm	85:024bf7f99721	174
bogdanm	85:024bf7f99721	175	/**
bogdanm	85:024bf7f99721	176	* @brief Controller Area Network FIFOMailBox
bogdanm	85:024bf7f99721	177	*/
bogdanm	85:024bf7f99721	178	typedef struct
bogdanm	85:024bf7f99721	179	{
bogdanm	85:024bf7f99721	180	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
bogdanm	85:024bf7f99721	181	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
bogdanm	85:024bf7f99721	182	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
bogdanm	85:024bf7f99721	183	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
bogdanm	85:024bf7f99721	184	}CAN_FIFOMailBox_TypeDef;
bogdanm	85:024bf7f99721	185
bogdanm	85:024bf7f99721	186	/**
bogdanm	85:024bf7f99721	187	* @brief Controller Area Network FilterRegister
bogdanm	85:024bf7f99721	188	*/
bogdanm	85:024bf7f99721	189	typedef struct
bogdanm	85:024bf7f99721	190	{
bogdanm	85:024bf7f99721	191	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
bogdanm	85:024bf7f99721	192	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
bogdanm	85:024bf7f99721	193	}CAN_FilterRegister_TypeDef;
bogdanm	85:024bf7f99721	194
bogdanm	85:024bf7f99721	195	/**
bogdanm	85:024bf7f99721	196	* @brief Controller Area Network
bogdanm	85:024bf7f99721	197	*/
bogdanm	85:024bf7f99721	198	typedef struct
bogdanm	85:024bf7f99721	199	{
bogdanm	85:024bf7f99721	200	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	201	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	202	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	203	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	204	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	205	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
bogdanm	85:024bf7f99721	206	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
bogdanm	85:024bf7f99721	207	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
bogdanm	85:024bf7f99721	208	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
bogdanm	85:024bf7f99721	209	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
bogdanm	85:024bf7f99721	210	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
bogdanm	85:024bf7f99721	211	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
bogdanm	85:024bf7f99721	212	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
bogdanm	85:024bf7f99721	213	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
bogdanm	85:024bf7f99721	214	uint32_t RESERVED2; /!< Reserved, 0x208 /
bogdanm	85:024bf7f99721	215	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
bogdanm	85:024bf7f99721	216	uint32_t RESERVED3; /!< Reserved, 0x210 /
bogdanm	85:024bf7f99721	217	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
bogdanm	85:024bf7f99721	218	uint32_t RESERVED4; /!< Reserved, 0x218 /
bogdanm	85:024bf7f99721	219	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
bogdanm	85:024bf7f99721	220	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
bogdanm	85:024bf7f99721	221	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
bogdanm	85:024bf7f99721	222	}CAN_TypeDef;
bogdanm	85:024bf7f99721	223
bogdanm	85:024bf7f99721	224	/**
bogdanm	85:024bf7f99721	225	* @brief HDMI-CEC
bogdanm	85:024bf7f99721	226	*/
bogdanm	85:024bf7f99721	227
bogdanm	85:024bf7f99721	228	typedef struct
bogdanm	85:024bf7f99721	229	{
bogdanm	85:024bf7f99721	230	__IO uint32_t CR; /!< CEC control register, Address offset:0x00 /
bogdanm	85:024bf7f99721	231	__IO uint32_t CFGR; /!< CEC configuration register, Address offset:0x04 /
bogdanm	85:024bf7f99721	232	__IO uint32_t TXDR; /!< CEC Tx data register , Address offset:0x08 /
bogdanm	85:024bf7f99721	233	__IO uint32_t RXDR; /!< CEC Rx Data Register, Address offset:0x0C /
bogdanm	85:024bf7f99721	234	__IO uint32_t ISR; /!< CEC Interrupt and Status Register, Address offset:0x10 /
bogdanm	85:024bf7f99721	235	__IO uint32_t IER; /!< CEC interrupt enable register, Address offset:0x14 /
bogdanm	85:024bf7f99721	236	}CEC_TypeDef;
bogdanm	85:024bf7f99721	237
bogdanm	85:024bf7f99721	238	/**
bogdanm	85:024bf7f99721	239	* @brief Comparator
bogdanm	85:024bf7f99721	240	*/
bogdanm	85:024bf7f99721	241
bogdanm	85:024bf7f99721	242	typedef struct
bogdanm	85:024bf7f99721	243	{
bogdanm	92:4fc01daae5a5	244	__IO uint32_t CSR; /!< Comparator 1 & 2 control Status register, Address offset: 0x00 /
bogdanm	92:4fc01daae5a5	245	}COMP1_2_TypeDef;
bogdanm	92:4fc01daae5a5	246
bogdanm	92:4fc01daae5a5	247	typedef struct
bogdanm	92:4fc01daae5a5	248	{
bogdanm	92:4fc01daae5a5	249	__IO uint16_t CSR; /!< Comparator control Status register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	250	}COMP_TypeDef;
bogdanm	85:024bf7f99721	251
bogdanm	85:024bf7f99721	252	/**
bogdanm	85:024bf7f99721	253	* @brief CRC calculation unit
bogdanm	85:024bf7f99721	254	*/
bogdanm	85:024bf7f99721	255
bogdanm	85:024bf7f99721	256	typedef struct
bogdanm	85:024bf7f99721	257	{
bogdanm	85:024bf7f99721	258	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	259	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	260	uint8_t RESERVED0; /!< Reserved, 0x05 /
bogdanm	85:024bf7f99721	261	uint16_t RESERVED1; /!< Reserved, 0x06 /
bogdanm	85:024bf7f99721	262	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	263	uint32_t RESERVED2; /!< Reserved, 0x0C /
bogdanm	85:024bf7f99721	264	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	265	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
bogdanm	85:024bf7f99721	266	}CRC_TypeDef;
bogdanm	85:024bf7f99721	267
bogdanm	85:024bf7f99721	268	/**
bogdanm	85:024bf7f99721	269	* @brief Clock Recovery System
bogdanm	85:024bf7f99721	270	*/
bogdanm	85:024bf7f99721	271	typedef struct
bogdanm	85:024bf7f99721	272	{
bogdanm	85:024bf7f99721	273	__IO uint32_t CR; /!< CRS ccontrol register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	274	__IO uint32_t CFGR; /!< CRS configuration register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	275	__IO uint32_t ISR; /!< CRS interrupt and status register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	276	__IO uint32_t ICR; /!< CRS interrupt flag clear register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	277	}CRS_TypeDef;
bogdanm	85:024bf7f99721	278
bogdanm	85:024bf7f99721	279	/**
bogdanm	85:024bf7f99721	280	* @brief Digital to Analog Converter
bogdanm	85:024bf7f99721	281	*/
bogdanm	85:024bf7f99721	282
bogdanm	85:024bf7f99721	283	typedef struct
bogdanm	85:024bf7f99721	284	{
bogdanm	85:024bf7f99721	285	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	286	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	287	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	288	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	289	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	290	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
bogdanm	85:024bf7f99721	291	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
bogdanm	85:024bf7f99721	292	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
bogdanm	85:024bf7f99721	293	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
bogdanm	85:024bf7f99721	294	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
bogdanm	85:024bf7f99721	295	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
bogdanm	85:024bf7f99721	296	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
bogdanm	85:024bf7f99721	297	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
bogdanm	85:024bf7f99721	298	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
bogdanm	85:024bf7f99721	299	}DAC_TypeDef;
bogdanm	85:024bf7f99721	300
bogdanm	85:024bf7f99721	301	/**
bogdanm	85:024bf7f99721	302	* @brief Debug MCU
bogdanm	85:024bf7f99721	303	*/
bogdanm	85:024bf7f99721	304
bogdanm	85:024bf7f99721	305	typedef struct
bogdanm	85:024bf7f99721	306	{
bogdanm	85:024bf7f99721	307	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
bogdanm	85:024bf7f99721	308	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	309	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	310	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	311	}DBGMCU_TypeDef;
bogdanm	85:024bf7f99721	312
bogdanm	85:024bf7f99721	313	/**
bogdanm	85:024bf7f99721	314	* @brief DMA Controller
bogdanm	85:024bf7f99721	315	*/
bogdanm	85:024bf7f99721	316
bogdanm	85:024bf7f99721	317	typedef struct
bogdanm	85:024bf7f99721	318	{
bogdanm	85:024bf7f99721	319	__IO uint32_t CCR; /!< DMA channel x configuration register /
bogdanm	85:024bf7f99721	320	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
bogdanm	85:024bf7f99721	321	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
bogdanm	85:024bf7f99721	322	__IO uint32_t CMAR; /!< DMA channel x memory address register /
bogdanm	85:024bf7f99721	323	}DMA_Channel_TypeDef;
bogdanm	85:024bf7f99721	324
bogdanm	85:024bf7f99721	325	typedef struct
bogdanm	85:024bf7f99721	326	{
bogdanm	85:024bf7f99721	327	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	328	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	329	}DMA_TypeDef;
bogdanm	85:024bf7f99721	330
bogdanm	85:024bf7f99721	331	/**
bogdanm	85:024bf7f99721	332	* @brief External Interrupt/Event Controller
bogdanm	85:024bf7f99721	333	*/
bogdanm	85:024bf7f99721	334
bogdanm	85:024bf7f99721	335	typedef struct
bogdanm	85:024bf7f99721	336	{
bogdanm	85:024bf7f99721	337	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	338	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	339	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
bogdanm	85:024bf7f99721	340	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	341	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	342	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
bogdanm	85:024bf7f99721	343	}EXTI_TypeDef;
bogdanm	85:024bf7f99721	344
bogdanm	85:024bf7f99721	345	/**
bogdanm	85:024bf7f99721	346	* @brief FLASH Registers
bogdanm	85:024bf7f99721	347	*/
bogdanm	85:024bf7f99721	348	typedef struct
bogdanm	85:024bf7f99721	349	{
bogdanm	85:024bf7f99721	350	__IO uint32_t ACR; /!<FLASH access control register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	351	__IO uint32_t KEYR; /!<FLASH key register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	352	__IO uint32_t OPTKEYR; /!<FLASH OPT key register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	353	__IO uint32_t SR; /!<FLASH status register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	354	__IO uint32_t CR; /!<FLASH control register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	355	__IO uint32_t AR; /!<FLASH address register, Address offset: 0x14 /
bogdanm	85:024bf7f99721	356	__IO uint32_t RESERVED; /!< Reserved, 0x18 /
bogdanm	85:024bf7f99721	357	__IO uint32_t OBR; /!<FLASH option bytes register, Address offset: 0x1C /
bogdanm	85:024bf7f99721	358	__IO uint32_t WRPR; /!<FLASH option bytes register, Address offset: 0x20 /
bogdanm	85:024bf7f99721	359	}FLASH_TypeDef;
bogdanm	85:024bf7f99721	360
bogdanm	85:024bf7f99721	361
bogdanm	85:024bf7f99721	362	/**
bogdanm	85:024bf7f99721	363	* @brief Option Bytes Registers
bogdanm	85:024bf7f99721	364	*/
bogdanm	85:024bf7f99721	365	typedef struct
bogdanm	85:024bf7f99721	366	{
bogdanm	85:024bf7f99721	367	__IO uint16_t RDP; /!< FLASH option byte Read protection, Address offset: 0x00 /
bogdanm	85:024bf7f99721	368	__IO uint16_t USER; /!< FLASH option byte user options, Address offset: 0x02 /
bogdanm	85:024bf7f99721	369	__IO uint16_t DATA0; /!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 /
bogdanm	85:024bf7f99721	370	__IO uint16_t DATA1; /!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 /
bogdanm	85:024bf7f99721	371	__IO uint16_t WRP0; /!< FLASH option byte write protection 0, Address offset: 0x08 /
bogdanm	85:024bf7f99721	372	__IO uint16_t WRP1; /!< FLASH option byte write protection 1, Address offset: 0x0A /
bogdanm	85:024bf7f99721	373	__IO uint16_t WRP2; /!< FLASH option byte write protection 2, Address offset: 0x0C /
bogdanm	85:024bf7f99721	374	__IO uint16_t WRP3; /!< FLASH option byte write protection 3, Address offset: 0x0E /
bogdanm	85:024bf7f99721	375	}OB_TypeDef;
bogdanm	85:024bf7f99721	376
bogdanm	85:024bf7f99721	377	/**
bogdanm	85:024bf7f99721	378	* @brief General Purpose I/O
bogdanm	85:024bf7f99721	379	*/
bogdanm	85:024bf7f99721	380
bogdanm	85:024bf7f99721	381	typedef struct
bogdanm	85:024bf7f99721	382	{
bogdanm	92:4fc01daae5a5	383	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
bogdanm	92:4fc01daae5a5	384	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
bogdanm	92:4fc01daae5a5	385	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
bogdanm	92:4fc01daae5a5	386	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
bogdanm	92:4fc01daae5a5	387	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
bogdanm	92:4fc01daae5a5	388	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
bogdanm	92:4fc01daae5a5	389	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x1A /
bogdanm	92:4fc01daae5a5	390	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
bogdanm	92:4fc01daae5a5	391	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
bogdanm	92:4fc01daae5a5	392	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
bogdanm	85:024bf7f99721	393	}GPIO_TypeDef;
bogdanm	85:024bf7f99721	394
bogdanm	85:024bf7f99721	395	/**
bogdanm	85:024bf7f99721	396	* @brief SysTem Configuration
bogdanm	85:024bf7f99721	397	*/
bogdanm	85:024bf7f99721	398
bogdanm	85:024bf7f99721	399	typedef struct
bogdanm	85:024bf7f99721	400	{
bogdanm	85:024bf7f99721	401	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
bogdanm	85:024bf7f99721	402	uint32_t RESERVED; /!< Reserved, 0x04 /
bogdanm	85:024bf7f99721	403	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
bogdanm	85:024bf7f99721	404	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
bogdanm	85:024bf7f99721	405	}SYSCFG_TypeDef;
bogdanm	85:024bf7f99721	406
bogdanm	85:024bf7f99721	407	/**
bogdanm	85:024bf7f99721	408	* @brief Inter-integrated Circuit Interface
bogdanm	85:024bf7f99721	409	*/
bogdanm	85:024bf7f99721	410
bogdanm	85:024bf7f99721	411	typedef struct
bogdanm	85:024bf7f99721	412	{
bogdanm	85:024bf7f99721	413	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
bogdanm	85:024bf7f99721	414	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
bogdanm	85:024bf7f99721	415	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	416	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	417	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	418	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
bogdanm	85:024bf7f99721	419	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
bogdanm	85:024bf7f99721	420	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
bogdanm	85:024bf7f99721	421	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
bogdanm	85:024bf7f99721	422	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
bogdanm	85:024bf7f99721	423	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
bogdanm	85:024bf7f99721	424	}I2C_TypeDef;
bogdanm	85:024bf7f99721	425
bogdanm	85:024bf7f99721	426	/**
bogdanm	85:024bf7f99721	427	* @brief Independent WATCHDOG
bogdanm	85:024bf7f99721	428	*/
bogdanm	85:024bf7f99721	429
bogdanm	85:024bf7f99721	430	typedef struct
bogdanm	85:024bf7f99721	431	{
bogdanm	85:024bf7f99721	432	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	433	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	434	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	435	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	436	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	437	}IWDG_TypeDef;
bogdanm	85:024bf7f99721	438
bogdanm	85:024bf7f99721	439	/**
bogdanm	85:024bf7f99721	440	* @brief Power Control
bogdanm	85:024bf7f99721	441	*/
bogdanm	85:024bf7f99721	442
bogdanm	85:024bf7f99721	443	typedef struct
bogdanm	85:024bf7f99721	444	{
bogdanm	85:024bf7f99721	445	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	446	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	447	}PWR_TypeDef;
bogdanm	85:024bf7f99721	448
bogdanm	85:024bf7f99721	449	/**
bogdanm	85:024bf7f99721	450	* @brief Reset and Clock Control
bogdanm	85:024bf7f99721	451	*/
bogdanm	85:024bf7f99721	452	typedef struct
bogdanm	85:024bf7f99721	453	{
bogdanm	85:024bf7f99721	454	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	455	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	456	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	457	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	458	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	459	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
bogdanm	85:024bf7f99721	460	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
bogdanm	85:024bf7f99721	461	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
bogdanm	85:024bf7f99721	462	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
bogdanm	85:024bf7f99721	463	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
bogdanm	85:024bf7f99721	464	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
bogdanm	85:024bf7f99721	465	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
bogdanm	85:024bf7f99721	466	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
bogdanm	85:024bf7f99721	467	__IO uint32_t CR2; /!< RCC clock control register 2, Address offset: 0x34 /
bogdanm	85:024bf7f99721	468	}RCC_TypeDef;
bogdanm	85:024bf7f99721	469
bogdanm	85:024bf7f99721	470	/**
bogdanm	85:024bf7f99721	471	* @brief Real-Time Clock
bogdanm	85:024bf7f99721	472	*/
bogdanm	85:024bf7f99721	473
bogdanm	85:024bf7f99721	474	typedef struct
bogdanm	85:024bf7f99721	475	{
bogdanm	85:024bf7f99721	476	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	477	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	478	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	479	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	480	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	481	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
bogdanm	85:024bf7f99721	482	uint32_t RESERVED1; /!< Reserved, Address offset: 0x18 /
bogdanm	85:024bf7f99721	483	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
bogdanm	85:024bf7f99721	484	uint32_t RESERVED2; /!< Reserved, Address offset: 0x20 /
bogdanm	85:024bf7f99721	485	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
bogdanm	85:024bf7f99721	486	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
bogdanm	85:024bf7f99721	487	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
bogdanm	85:024bf7f99721	488	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
bogdanm	85:024bf7f99721	489	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
bogdanm	85:024bf7f99721	490	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
bogdanm	85:024bf7f99721	491	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
bogdanm	85:024bf7f99721	492	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
bogdanm	85:024bf7f99721	493	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
bogdanm	85:024bf7f99721	494	uint32_t RESERVED3; /!< Reserved, Address offset: 0x48 /
bogdanm	85:024bf7f99721	495	uint32_t RESERVED4; /!< Reserved, Address offset: 0x4C /
bogdanm	85:024bf7f99721	496	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
bogdanm	85:024bf7f99721	497	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
bogdanm	85:024bf7f99721	498	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
bogdanm	85:024bf7f99721	499	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
bogdanm	85:024bf7f99721	500	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
bogdanm	85:024bf7f99721	501	}RTC_TypeDef;
bogdanm	85:024bf7f99721	502
bogdanm	85:024bf7f99721	503	/**
bogdanm	85:024bf7f99721	504	* @brief Serial Peripheral Interface
bogdanm	85:024bf7f99721	505	*/
bogdanm	85:024bf7f99721	506
bogdanm	85:024bf7f99721	507	typedef struct
bogdanm	85:024bf7f99721	508	{
Kojto	93:e188a91d3eaa	509	__IO uint32_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
Kojto	93:e188a91d3eaa	510	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
Kojto	93:e188a91d3eaa	511	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
Kojto	93:e188a91d3eaa	512	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
Kojto	93:e188a91d3eaa	513	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
Kojto	93:e188a91d3eaa	514	__IO uint32_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
Kojto	93:e188a91d3eaa	515	__IO uint32_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
Kojto	93:e188a91d3eaa	516	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
Kojto	93:e188a91d3eaa	517	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
bogdanm	85:024bf7f99721	518	}SPI_TypeDef;
bogdanm	85:024bf7f99721	519
bogdanm	85:024bf7f99721	520	/**
bogdanm	85:024bf7f99721	521	* @brief TIM
bogdanm	85:024bf7f99721	522	*/
bogdanm	85:024bf7f99721	523	typedef struct
bogdanm	85:024bf7f99721	524	{
bogdanm	92:4fc01daae5a5	525	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
bogdanm	92:4fc01daae5a5	526	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
bogdanm	92:4fc01daae5a5	527	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
bogdanm	92:4fc01daae5a5	528	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
bogdanm	92:4fc01daae5a5	529	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
bogdanm	92:4fc01daae5a5	530	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
bogdanm	92:4fc01daae5a5	531	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
bogdanm	92:4fc01daae5a5	532	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
bogdanm	92:4fc01daae5a5	533	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
bogdanm	85:024bf7f99721	534	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
bogdanm	92:4fc01daae5a5	535	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
bogdanm	85:024bf7f99721	536	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
bogdanm	92:4fc01daae5a5	537	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
bogdanm	85:024bf7f99721	538	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
bogdanm	85:024bf7f99721	539	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
bogdanm	85:024bf7f99721	540	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
bogdanm	85:024bf7f99721	541	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
bogdanm	92:4fc01daae5a5	542	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
bogdanm	92:4fc01daae5a5	543	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
bogdanm	92:4fc01daae5a5	544	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
bogdanm	92:4fc01daae5a5	545	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
bogdanm	85:024bf7f99721	546	}TIM_TypeDef;
bogdanm	85:024bf7f99721	547
bogdanm	85:024bf7f99721	548	/**
bogdanm	85:024bf7f99721	549	* @brief Touch Sensing Controller (TSC)
bogdanm	85:024bf7f99721	550	*/
bogdanm	85:024bf7f99721	551	typedef struct
bogdanm	85:024bf7f99721	552	{
bogdanm	85:024bf7f99721	553	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	554	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	555	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	556	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	557	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	558	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
bogdanm	85:024bf7f99721	559	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
bogdanm	85:024bf7f99721	560	uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
bogdanm	85:024bf7f99721	561	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
bogdanm	85:024bf7f99721	562	uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
bogdanm	85:024bf7f99721	563	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
bogdanm	85:024bf7f99721	564	uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
bogdanm	85:024bf7f99721	565	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
bogdanm	85:024bf7f99721	566	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
bogdanm	85:024bf7f99721	567	}TSC_TypeDef;
bogdanm	85:024bf7f99721	568
bogdanm	85:024bf7f99721	569	/**
bogdanm	85:024bf7f99721	570	* @brief Universal Synchronous Asynchronous Receiver Transmitter
bogdanm	85:024bf7f99721	571	*/
bogdanm	85:024bf7f99721	572
bogdanm	85:024bf7f99721	573	typedef struct
bogdanm	85:024bf7f99721	574	{
bogdanm	85:024bf7f99721	575	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
bogdanm	85:024bf7f99721	576	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
bogdanm	85:024bf7f99721	577	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
bogdanm	92:4fc01daae5a5	578	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
bogdanm	92:4fc01daae5a5	579	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	580	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
bogdanm	92:4fc01daae5a5	581	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
bogdanm	85:024bf7f99721	582	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
bogdanm	85:024bf7f99721	583	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
bogdanm	85:024bf7f99721	584	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
bogdanm	92:4fc01daae5a5	585	uint16_t RESERVED1; /!< Reserved, 0x26 /
bogdanm	85:024bf7f99721	586	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
bogdanm	92:4fc01daae5a5	587	uint16_t RESERVED2; /!< Reserved, 0x2A /
bogdanm	85:024bf7f99721	588	}USART_TypeDef;
bogdanm	85:024bf7f99721	589
bogdanm	85:024bf7f99721	590	/**
bogdanm	85:024bf7f99721	591	* @brief Universal Serial Bus Full Speed Device
bogdanm	85:024bf7f99721	592	*/
bogdanm	85:024bf7f99721	593
bogdanm	85:024bf7f99721	594	typedef struct
bogdanm	85:024bf7f99721	595	{
bogdanm	85:024bf7f99721	596	__IO uint16_t EP0R; /!< USB Endpoint 0 register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	597	__IO uint16_t RESERVED0; /!< Reserved /
bogdanm	85:024bf7f99721	598	__IO uint16_t EP1R; /!< USB Endpoint 1 register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	599	__IO uint16_t RESERVED1; /!< Reserved /
bogdanm	85:024bf7f99721	600	__IO uint16_t EP2R; /!< USB Endpoint 2 register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	601	__IO uint16_t RESERVED2; /!< Reserved /
bogdanm	85:024bf7f99721	602	__IO uint16_t EP3R; /!< USB Endpoint 3 register, Address offset: 0x0C /
bogdanm	85:024bf7f99721	603	__IO uint16_t RESERVED3; /!< Reserved /
bogdanm	85:024bf7f99721	604	__IO uint16_t EP4R; /!< USB Endpoint 4 register, Address offset: 0x10 /
bogdanm	85:024bf7f99721	605	__IO uint16_t RESERVED4; /!< Reserved /
bogdanm	85:024bf7f99721	606	__IO uint16_t EP5R; /!< USB Endpoint 5 register, Address offset: 0x14 /
bogdanm	85:024bf7f99721	607	__IO uint16_t RESERVED5; /!< Reserved /
bogdanm	85:024bf7f99721	608	__IO uint16_t EP6R; /!< USB Endpoint 6 register, Address offset: 0x18 /
bogdanm	85:024bf7f99721	609	__IO uint16_t RESERVED6; /!< Reserved /
bogdanm	85:024bf7f99721	610	__IO uint16_t EP7R; /!< USB Endpoint 7 register, Address offset: 0x1C /
bogdanm	85:024bf7f99721	611	__IO uint16_t RESERVED7[17]; /!< Reserved /
bogdanm	85:024bf7f99721	612	__IO uint16_t CNTR; /!< Control register, Address offset: 0x40 /
bogdanm	85:024bf7f99721	613	__IO uint16_t RESERVED8; /!< Reserved /
bogdanm	85:024bf7f99721	614	__IO uint16_t ISTR; /!< Interrupt status register, Address offset: 0x44 /
bogdanm	85:024bf7f99721	615	__IO uint16_t RESERVED9; /!< Reserved /
bogdanm	85:024bf7f99721	616	__IO uint16_t FNR; /!< Frame number register, Address offset: 0x48 /
bogdanm	85:024bf7f99721	617	__IO uint16_t RESERVEDA; /!< Reserved /
bogdanm	85:024bf7f99721	618	__IO uint16_t DADDR; /!< Device address register, Address offset: 0x4C /
bogdanm	85:024bf7f99721	619	__IO uint16_t RESERVEDB; /!< Reserved /
bogdanm	85:024bf7f99721	620	__IO uint16_t BTABLE; /!< Buffer Table address register, Address offset: 0x50 /
bogdanm	85:024bf7f99721	621	__IO uint16_t RESERVEDC; /!< Reserved /
bogdanm	85:024bf7f99721	622	__IO uint16_t LPMCSR; /!< LPM Control and Status register, Address offset: 0x54 /
bogdanm	85:024bf7f99721	623	__IO uint16_t RESERVEDD; /!< Reserved /
bogdanm	85:024bf7f99721	624	__IO uint16_t BCDR; /!< Battery Charging detector register, Address offset: 0x58 /
bogdanm	85:024bf7f99721	625	__IO uint16_t RESERVEDE; /!< Reserved /
bogdanm	85:024bf7f99721	626	}USB_TypeDef;
bogdanm	85:024bf7f99721	627
bogdanm	85:024bf7f99721	628	/**
bogdanm	85:024bf7f99721	629	* @brief Window WATCHDOG
bogdanm	85:024bf7f99721	630	*/
bogdanm	85:024bf7f99721	631	typedef struct
bogdanm	85:024bf7f99721	632	{
bogdanm	85:024bf7f99721	633	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
bogdanm	85:024bf7f99721	634	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
bogdanm	85:024bf7f99721	635	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
bogdanm	85:024bf7f99721	636	}WWDG_TypeDef;
bogdanm	85:024bf7f99721	637
bogdanm	85:024bf7f99721	638	/**
bogdanm	85:024bf7f99721	639	* @}
bogdanm	85:024bf7f99721	640	*/
bogdanm	85:024bf7f99721	641
bogdanm	85:024bf7f99721	642	/** @addtogroup Peripheral_memory_map
bogdanm	85:024bf7f99721	643	* @{
bogdanm	85:024bf7f99721	644	*/
bogdanm	85:024bf7f99721	645
bogdanm	85:024bf7f99721	646	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
bogdanm	85:024bf7f99721	647	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
bogdanm	85:024bf7f99721	648	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
bogdanm	85:024bf7f99721	649
bogdanm	85:024bf7f99721	650	/!< Peripheral memory map /
bogdanm	85:024bf7f99721	651	#define APBPERIPH_BASE PERIPH_BASE
bogdanm	85:024bf7f99721	652	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
bogdanm	85:024bf7f99721	653	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
bogdanm	85:024bf7f99721	654
bogdanm	85:024bf7f99721	655	#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
bogdanm	85:024bf7f99721	656	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
bogdanm	85:024bf7f99721	657	#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
bogdanm	85:024bf7f99721	658	#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
bogdanm	85:024bf7f99721	659	#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
bogdanm	85:024bf7f99721	660	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
bogdanm	85:024bf7f99721	661	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
bogdanm	85:024bf7f99721	662	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
bogdanm	85:024bf7f99721	663	#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
bogdanm	85:024bf7f99721	664	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
bogdanm	85:024bf7f99721	665	#define USART3_BASE (APBPERIPH_BASE + 0x00004800)
bogdanm	85:024bf7f99721	666	#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
bogdanm	85:024bf7f99721	667	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
bogdanm	85:024bf7f99721	668	#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
bogdanm	85:024bf7f99721	669	#define USB_BASE (APBPERIPH_BASE + 0x00005C00) /!< USB_IP Peripheral Registers base address /
bogdanm	85:024bf7f99721	670	#define USB_PMAADDR (APBPERIPH_BASE + 0x00006000) /!< USB_IP Packet Memory Area base address /
bogdanm	85:024bf7f99721	671	#define CAN_BASE (APBPERIPH_BASE + 0x00006400)
bogdanm	85:024bf7f99721	672	#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
bogdanm	85:024bf7f99721	673	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
bogdanm	85:024bf7f99721	674	#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
bogdanm	85:024bf7f99721	675	#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
bogdanm	85:024bf7f99721	676
bogdanm	85:024bf7f99721	677	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
bogdanm	85:024bf7f99721	678	#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
bogdanm	85:024bf7f99721	679	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
bogdanm	85:024bf7f99721	680	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
bogdanm	85:024bf7f99721	681	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
bogdanm	85:024bf7f99721	682	#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
bogdanm	85:024bf7f99721	683	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
bogdanm	85:024bf7f99721	684	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
bogdanm	85:024bf7f99721	685	#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
bogdanm	85:024bf7f99721	686	#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
bogdanm	85:024bf7f99721	687	#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
bogdanm	85:024bf7f99721	688	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
bogdanm	85:024bf7f99721	689
bogdanm	85:024bf7f99721	690	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
bogdanm	85:024bf7f99721	691	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
bogdanm	85:024bf7f99721	692	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
bogdanm	85:024bf7f99721	693	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
bogdanm	85:024bf7f99721	694	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
bogdanm	85:024bf7f99721	695	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
bogdanm	85:024bf7f99721	696	#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
bogdanm	85:024bf7f99721	697	#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
bogdanm	85:024bf7f99721	698
bogdanm	85:024bf7f99721	699	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
bogdanm	85:024bf7f99721	700	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
bogdanm	85:024bf7f99721	701	#define OB_BASE ((uint32_t)0x1FFFF800) /!< FLASH Option Bytes base address /
bogdanm	85:024bf7f99721	702	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
bogdanm	85:024bf7f99721	703	#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
bogdanm	85:024bf7f99721	704
bogdanm	85:024bf7f99721	705	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
bogdanm	85:024bf7f99721	706	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
bogdanm	85:024bf7f99721	707	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
bogdanm	85:024bf7f99721	708	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
bogdanm	85:024bf7f99721	709	#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
bogdanm	85:024bf7f99721	710	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
bogdanm	85:024bf7f99721	711
bogdanm	85:024bf7f99721	712	/**
bogdanm	85:024bf7f99721	713	* @}
bogdanm	85:024bf7f99721	714	*/
bogdanm	85:024bf7f99721	715
bogdanm	85:024bf7f99721	716	/** @addtogroup Peripheral_declaration
bogdanm	85:024bf7f99721	717	* @{
bogdanm	85:024bf7f99721	718	*/
bogdanm	85:024bf7f99721	719
bogdanm	85:024bf7f99721	720	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
bogdanm	85:024bf7f99721	721	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
bogdanm	85:024bf7f99721	722	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
bogdanm	85:024bf7f99721	723	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
bogdanm	85:024bf7f99721	724	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
bogdanm	85:024bf7f99721	725	#define RTC ((RTC_TypeDef *) RTC_BASE)
bogdanm	85:024bf7f99721	726	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
bogdanm	85:024bf7f99721	727	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
bogdanm	85:024bf7f99721	728	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
bogdanm	85:024bf7f99721	729	#define USART2 ((USART_TypeDef *) USART2_BASE)
bogdanm	85:024bf7f99721	730	#define USART3 ((USART_TypeDef *) USART3_BASE)
bogdanm	85:024bf7f99721	731	#define USART4 ((USART_TypeDef *) USART4_BASE)
bogdanm	85:024bf7f99721	732	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
bogdanm	85:024bf7f99721	733	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
bogdanm	85:024bf7f99721	734	#define CAN ((CAN_TypeDef *) CAN_BASE)
bogdanm	85:024bf7f99721	735	#define CRS ((CRS_TypeDef *) CRS_BASE)
bogdanm	85:024bf7f99721	736	#define PWR ((PWR_TypeDef *) PWR_BASE)
bogdanm	85:024bf7f99721	737	#define DAC ((DAC_TypeDef *) DAC_BASE)
bogdanm	85:024bf7f99721	738	#define CEC ((CEC_TypeDef *) CEC_BASE)
bogdanm	85:024bf7f99721	739	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
bogdanm	92:4fc01daae5a5	740	#define COMP ((COMP1_2_TypeDef *) COMP_BASE)
bogdanm	85:024bf7f99721	741	#define COMP1 ((COMP_TypeDef *) COMP_BASE)
bogdanm	92:4fc01daae5a5	742	#define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
bogdanm	85:024bf7f99721	743	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
bogdanm	85:024bf7f99721	744	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
bogdanm	85:024bf7f99721	745	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
bogdanm	85:024bf7f99721	746	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
bogdanm	85:024bf7f99721	747	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
bogdanm	85:024bf7f99721	748	#define USART1 ((USART_TypeDef *) USART1_BASE)
bogdanm	85:024bf7f99721	749	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
bogdanm	85:024bf7f99721	750	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
bogdanm	85:024bf7f99721	751	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
bogdanm	85:024bf7f99721	752	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
bogdanm	85:024bf7f99721	753	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
bogdanm	85:024bf7f99721	754	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
bogdanm	85:024bf7f99721	755	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
bogdanm	85:024bf7f99721	756	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
bogdanm	85:024bf7f99721	757	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
bogdanm	85:024bf7f99721	758	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
bogdanm	85:024bf7f99721	759	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
bogdanm	85:024bf7f99721	760	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
bogdanm	85:024bf7f99721	761	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
bogdanm	85:024bf7f99721	762	#define OB ((OB_TypeDef *) OB_BASE)
bogdanm	85:024bf7f99721	763	#define RCC ((RCC_TypeDef *) RCC_BASE)
bogdanm	85:024bf7f99721	764	#define CRC ((CRC_TypeDef *) CRC_BASE)
bogdanm	85:024bf7f99721	765	#define TSC ((TSC_TypeDef *) TSC_BASE)
bogdanm	85:024bf7f99721	766	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
bogdanm	85:024bf7f99721	767	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
bogdanm	85:024bf7f99721	768	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
bogdanm	85:024bf7f99721	769	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
bogdanm	85:024bf7f99721	770	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
bogdanm	85:024bf7f99721	771	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
bogdanm	85:024bf7f99721	772	#define USB ((USB_TypeDef *) USB_BASE)
bogdanm	85:024bf7f99721	773	/**
bogdanm	85:024bf7f99721	774	* @}
bogdanm	85:024bf7f99721	775	*/
bogdanm	85:024bf7f99721	776
bogdanm	85:024bf7f99721	777	/** @addtogroup Exported_constants
bogdanm	85:024bf7f99721	778	* @{
bogdanm	85:024bf7f99721	779	*/
bogdanm	85:024bf7f99721	780
bogdanm	85:024bf7f99721	781	/** @addtogroup Peripheral_Registers_Bits_Definition
bogdanm	85:024bf7f99721	782	* @{
bogdanm	85:024bf7f99721	783	*/
bogdanm	85:024bf7f99721	784
bogdanm	85:024bf7f99721	785	/******************************************************************************/
bogdanm	85:024bf7f99721	786	/* Peripheral Registers Bits Definition */
bogdanm	85:024bf7f99721	787	/******************************************************************************/
bogdanm	85:024bf7f99721	788	/******************************************************************************/
bogdanm	85:024bf7f99721	789	/* */
bogdanm	85:024bf7f99721	790	/* Analog to Digital Converter (ADC) */
bogdanm	85:024bf7f99721	791	/* */
bogdanm	85:024bf7f99721	792	/******************************************************************************/
bogdanm	85:024bf7f99721	793	/****************** Bits definition for ADC_ISR register ****************/
bogdanm	85:024bf7f99721	794	#define ADC_ISR_AWD ((uint32_t)0x00000080) /!< Analog watchdog flag /
bogdanm	85:024bf7f99721	795	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< Overrun flag /
bogdanm	85:024bf7f99721	796	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /!< End of Sequence flag /
bogdanm	85:024bf7f99721	797	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< End of Conversion /
bogdanm	85:024bf7f99721	798	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< End of sampling flag /
bogdanm	85:024bf7f99721	799	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready /
bogdanm	85:024bf7f99721	800
bogdanm	85:024bf7f99721	801	/* Old EOSEQ bit definition, maintained for legacy purpose */
bogdanm	85:024bf7f99721	802	#define ADC_ISR_EOS ADC_ISR_EOSEQ
bogdanm	85:024bf7f99721	803
bogdanm	85:024bf7f99721	804	/****************** Bits definition for ADC_IER register ****************/
bogdanm	85:024bf7f99721	805	#define ADC_IER_AWDIE ((uint32_t)0x00000080) /!< Analog Watchdog interrupt enable /
bogdanm	85:024bf7f99721	806	#define ADC_IER_OVRIE ((uint32_t)0x00000010) /!< Overrun interrupt enable /
bogdanm	85:024bf7f99721	807	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /!< End of Sequence of conversion interrupt enable /
bogdanm	85:024bf7f99721	808	#define ADC_IER_EOCIE ((uint32_t)0x00000004) /!< End of Conversion interrupt enable /
bogdanm	85:024bf7f99721	809	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /!< End of sampling interrupt enable /
bogdanm	85:024bf7f99721	810	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /!< ADC Ready interrupt enable /
bogdanm	85:024bf7f99721	811
bogdanm	85:024bf7f99721	812	/* Old EOSEQIE bit definition, maintained for legacy purpose */
bogdanm	85:024bf7f99721	813	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
bogdanm	85:024bf7f99721	814
bogdanm	85:024bf7f99721	815	/****************** Bits definition for ADC_CR register *****************/
bogdanm	85:024bf7f99721	816	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC calibration /
bogdanm	85:024bf7f99721	817	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC stop of conversion command /
bogdanm	85:024bf7f99721	818	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC start of conversion /
bogdanm	85:024bf7f99721	819	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC disable command /
bogdanm	85:024bf7f99721	820	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC enable control /
bogdanm	85:024bf7f99721	821
bogdanm	85:024bf7f99721	822	/***************** Bits definition for ADC_CFGR1 register ***************/
bogdanm	85:024bf7f99721	823	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
bogdanm	85:024bf7f99721	824	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /!< Bit 0 /
bogdanm	85:024bf7f99721	825	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /!< Bit 1 /
bogdanm	85:024bf7f99721	826	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /!< Bit 2 /
bogdanm	85:024bf7f99721	827	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /!< Bit 3 /
bogdanm	85:024bf7f99721	828	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /!< Bit 4 /
bogdanm	85:024bf7f99721	829	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
bogdanm	85:024bf7f99721	830	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /!< Enable the watchdog on a single channel or on all channels /
bogdanm	85:024bf7f99721	831	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /!< Discontinuous mode on regular channels /
bogdanm	85:024bf7f99721	832	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /!< ADC auto power off /
bogdanm	85:024bf7f99721	833	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /!< ADC wait conversion mode /
bogdanm	85:024bf7f99721	834	#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /!< Continuous Conversion /
bogdanm	85:024bf7f99721	835	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /!< Overrun mode /
bogdanm	85:024bf7f99721	836	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
bogdanm	85:024bf7f99721	837	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	85:024bf7f99721	838	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	85:024bf7f99721	839	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
bogdanm	85:024bf7f99721	840	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	85:024bf7f99721	841	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	85:024bf7f99721	842	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /!< Bit 2 /
bogdanm	85:024bf7f99721	843	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /!< Data Alignment /
bogdanm	85:024bf7f99721	844	#define ADC_CFGR1_RES ((uint32_t)0x00000018) /!< RES[1:0] bits (Resolution) /
bogdanm	85:024bf7f99721	845	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	85:024bf7f99721	846	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	85:024bf7f99721	847	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /!< Sequence scan direction /
bogdanm	85:024bf7f99721	848	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /!< Direct memory access configuration /
bogdanm	85:024bf7f99721	849	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /!< Direct memory access enable /
bogdanm	85:024bf7f99721	850
bogdanm	85:024bf7f99721	851	/* Old WAIT bit definition, maintained for legacy purpose */
bogdanm	85:024bf7f99721	852	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
bogdanm	85:024bf7f99721	853
bogdanm	85:024bf7f99721	854	/***************** Bits definition for ADC_CFGR2 register ***************/
bogdanm	85:024bf7f99721	855	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /!< ADC clock mode /
bogdanm	85:024bf7f99721	856	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /!< ADC clocked by PCLK div4 /
bogdanm	85:024bf7f99721	857	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /!< ADC clocked by PCLK div2 /
bogdanm	85:024bf7f99721	858
bogdanm	85:024bf7f99721	859	/* Old bit definition, maintained for legacy purpose */
bogdanm	85:024bf7f99721	860	#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /!< ADC clocked by PCLK div4 /
bogdanm	85:024bf7f99721	861	#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /!< ADC clocked by PCLK div2 /
bogdanm	85:024bf7f99721	862
bogdanm	85:024bf7f99721	863	/**************** Bit definition for ADC_SMPR register ******************/
bogdanm	85:024bf7f99721	864	#define ADC_SMPR_SMP ((uint32_t)0x00000007) /!< SMP[2:0] bits (Sampling time selection) /
bogdanm	85:024bf7f99721	865	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	85:024bf7f99721	866	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	85:024bf7f99721	867	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	85:024bf7f99721	868
bogdanm	85:024bf7f99721	869	/* Old bit definition, maintained for legacy purpose */
bogdanm	85:024bf7f99721	870	#define ADC_SMPR1_SMPR ADC_SMPR_SMP /!< SMP[2:0] bits (Sampling time selection) /
bogdanm	85:024bf7f99721	871	#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /!< Bit 0 /
bogdanm	85:024bf7f99721	872	#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /!< Bit 1 /
bogdanm	85:024bf7f99721	873	#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /!< Bit 2 /
bogdanm	85:024bf7f99721	874
bogdanm	85:024bf7f99721	875	/***************** Bit definition for ADC_TR register ******************/
bogdanm	85:024bf7f99721	876	#define ADC_TR_HT ((uint32_t)0x0FFF0000) /!< Analog watchdog high threshold /
bogdanm	85:024bf7f99721	877	#define ADC_TR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
bogdanm	85:024bf7f99721	878
bogdanm	85:024bf7f99721	879	/* Old bit definition, maintained for legacy purpose */
bogdanm	85:024bf7f99721	880	#define ADC_HTR_HT ADC_TR_HT /!< Analog watchdog high threshold /
bogdanm	85:024bf7f99721	881	#define ADC_LTR_LT ADC_TR_LT /!< Analog watchdog low threshold /
bogdanm	85:024bf7f99721	882
bogdanm	85:024bf7f99721	883	/**************** Bit definition for ADC_CHSELR register ****************/
bogdanm	85:024bf7f99721	884	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /!< Channel 18 selection /
bogdanm	85:024bf7f99721	885	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /!< Channel 17 selection /
bogdanm	85:024bf7f99721	886	#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /!< Channel 16 selection /
bogdanm	85:024bf7f99721	887	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /!< Channel 15 selection /
bogdanm	85:024bf7f99721	888	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /!< Channel 14 selection /
bogdanm	85:024bf7f99721	889	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /!< Channel 13 selection /
bogdanm	85:024bf7f99721	890	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /!< Channel 12 selection /
bogdanm	85:024bf7f99721	891	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /!< Channel 11 selection /
bogdanm	85:024bf7f99721	892	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /!< Channel 10 selection /
bogdanm	85:024bf7f99721	893	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /!< Channel 9 selection /
bogdanm	85:024bf7f99721	894	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /!< Channel 8 selection /
bogdanm	85:024bf7f99721	895	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /!< Channel 7 selection /
bogdanm	85:024bf7f99721	896	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /!< Channel 6 selection /
bogdanm	85:024bf7f99721	897	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /!< Channel 5 selection /
bogdanm	85:024bf7f99721	898	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /!< Channel 4 selection /
bogdanm	85:024bf7f99721	899	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /!< Channel 3 selection /
bogdanm	85:024bf7f99721	900	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /!< Channel 2 selection /
bogdanm	85:024bf7f99721	901	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /!< Channel 1 selection /
bogdanm	85:024bf7f99721	902	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /!< Channel 0 selection /
bogdanm	85:024bf7f99721	903
bogdanm	85:024bf7f99721	904	/****************** Bit definition for ADC_DR register ******************/
bogdanm	85:024bf7f99721	905	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
bogdanm	85:024bf7f99721	906
bogdanm	85:024bf7f99721	907	/***************** Bit definition for ADC_CCR register ******************/
bogdanm	85:024bf7f99721	908	#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /!< Voltage battery enable /
bogdanm	85:024bf7f99721	909	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Tempurature sensore enable /
bogdanm	85:024bf7f99721	910	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< Vrefint enable /
bogdanm	85:024bf7f99721	911
bogdanm	85:024bf7f99721	912	/******************************************************************************/
bogdanm	85:024bf7f99721	913	/* */
bogdanm	85:024bf7f99721	914	/* Controller Area Network (CAN ) */
bogdanm	85:024bf7f99721	915	/* */
bogdanm	85:024bf7f99721	916	/******************************************************************************/
bogdanm	85:024bf7f99721	917	/!<CAN control and status registers /
bogdanm	85:024bf7f99721	918	/***************** Bit definition for CAN_MCR register ******************/
bogdanm	92:4fc01daae5a5	919	#define CAN_MCR_INRQ ((uint32_t)0x00000001) /!<Initialization Request /
bogdanm	92:4fc01daae5a5	920	#define CAN_MCR_SLEEP ((uint32_t)0x00000002) /!<Sleep Mode Request /
bogdanm	92:4fc01daae5a5	921	#define CAN_MCR_TXFP ((uint32_t)0x00000004) /!<Transmit FIFO Priority /
bogdanm	92:4fc01daae5a5	922	#define CAN_MCR_RFLM ((uint32_t)0x00000008) /!<Receive FIFO Locked Mode /
bogdanm	92:4fc01daae5a5	923	#define CAN_MCR_NART ((uint32_t)0x00000010) /!<No Automatic Retransmission /
bogdanm	92:4fc01daae5a5	924	#define CAN_MCR_AWUM ((uint32_t)0x00000020) /!<Automatic Wakeup Mode /
bogdanm	92:4fc01daae5a5	925	#define CAN_MCR_ABOM ((uint32_t)0x00000040) /!<Automatic Bus-Off Management /
bogdanm	92:4fc01daae5a5	926	#define CAN_MCR_TTCM ((uint32_t)0x00000080) /!<Time Triggered Communication Mode /
bogdanm	92:4fc01daae5a5	927	#define CAN_MCR_RESET ((uint32_t)0x00008000) /!<bxCAN software master reset /
bogdanm	85:024bf7f99721	928
bogdanm	85:024bf7f99721	929	/***************** Bit definition for CAN_MSR register ******************/
bogdanm	92:4fc01daae5a5	930	#define CAN_MSR_INAK ((uint32_t)0x00000001) /!<Initialization Acknowledge /
bogdanm	92:4fc01daae5a5	931	#define CAN_MSR_SLAK ((uint32_t)0x00000002) /!<Sleep Acknowledge /
bogdanm	92:4fc01daae5a5	932	#define CAN_MSR_ERRI ((uint32_t)0x00000004) /!<Error Interrupt /
bogdanm	92:4fc01daae5a5	933	#define CAN_MSR_WKUI ((uint32_t)0x00000008) /!<Wakeup Interrupt /
bogdanm	92:4fc01daae5a5	934	#define CAN_MSR_SLAKI ((uint32_t)0x00000010) /!<Sleep Acknowledge Interrupt /
bogdanm	92:4fc01daae5a5	935	#define CAN_MSR_TXM ((uint32_t)0x00000100) /!<Transmit Mode /
bogdanm	92:4fc01daae5a5	936	#define CAN_MSR_RXM ((uint32_t)0x00000200) /!<Receive Mode /
bogdanm	92:4fc01daae5a5	937	#define CAN_MSR_SAMP ((uint32_t)0x00000400) /!<Last Sample Point /
bogdanm	92:4fc01daae5a5	938	#define CAN_MSR_RX ((uint32_t)0x00000800) /!<CAN Rx Signal /
bogdanm	85:024bf7f99721	939
bogdanm	85:024bf7f99721	940	/***************** Bit definition for CAN_TSR register ******************/
bogdanm	85:024bf7f99721	941	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
bogdanm	85:024bf7f99721	942	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
bogdanm	85:024bf7f99721	943	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
bogdanm	85:024bf7f99721	944	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
bogdanm	85:024bf7f99721	945	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
bogdanm	85:024bf7f99721	946	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
bogdanm	85:024bf7f99721	947	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
bogdanm	85:024bf7f99721	948	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
bogdanm	85:024bf7f99721	949	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
bogdanm	85:024bf7f99721	950	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
bogdanm	85:024bf7f99721	951	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
bogdanm	85:024bf7f99721	952	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
bogdanm	85:024bf7f99721	953	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
bogdanm	85:024bf7f99721	954	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
bogdanm	85:024bf7f99721	955	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
bogdanm	85:024bf7f99721	956	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
bogdanm	85:024bf7f99721	957
bogdanm	85:024bf7f99721	958	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
bogdanm	85:024bf7f99721	959	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
bogdanm	85:024bf7f99721	960	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
bogdanm	85:024bf7f99721	961	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
bogdanm	85:024bf7f99721	962
bogdanm	85:024bf7f99721	963	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
bogdanm	85:024bf7f99721	964	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
bogdanm	85:024bf7f99721	965	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
bogdanm	85:024bf7f99721	966	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
bogdanm	85:024bf7f99721	967
bogdanm	85:024bf7f99721	968	/***************** Bit definition for CAN_RF0R register *****************/
bogdanm	92:4fc01daae5a5	969	#define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /!<FIFO 0 Message Pending /
bogdanm	92:4fc01daae5a5	970	#define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /!<FIFO 0 Full /
bogdanm	92:4fc01daae5a5	971	#define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /!<FIFO 0 Overrun /
bogdanm	92:4fc01daae5a5	972	#define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /!<Release FIFO 0 Output Mailbox /
bogdanm	85:024bf7f99721	973
bogdanm	85:024bf7f99721	974	/***************** Bit definition for CAN_RF1R register *****************/
bogdanm	92:4fc01daae5a5	975	#define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /!<FIFO 1 Message Pending /
bogdanm	92:4fc01daae5a5	976	#define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /!<FIFO 1 Full /
bogdanm	92:4fc01daae5a5	977	#define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /!<FIFO 1 Overrun /
bogdanm	92:4fc01daae5a5	978	#define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /!<Release FIFO 1 Output Mailbox /
bogdanm	85:024bf7f99721	979
bogdanm	85:024bf7f99721	980	/****************** Bit definition for CAN_IER register *****************/
bogdanm	85:024bf7f99721	981	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
bogdanm	85:024bf7f99721	982	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
bogdanm	85:024bf7f99721	983	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
bogdanm	85:024bf7f99721	984	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
bogdanm	85:024bf7f99721	985	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
bogdanm	85:024bf7f99721	986	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
bogdanm	85:024bf7f99721	987	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
bogdanm	85:024bf7f99721	988	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
bogdanm	85:024bf7f99721	989	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
bogdanm	85:024bf7f99721	990	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
bogdanm	85:024bf7f99721	991	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
bogdanm	85:024bf7f99721	992	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
bogdanm	85:024bf7f99721	993	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
bogdanm	85:024bf7f99721	994	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
bogdanm	85:024bf7f99721	995
bogdanm	85:024bf7f99721	996	/****************** Bit definition for CAN_ESR register *****************/
bogdanm	85:024bf7f99721	997	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
bogdanm	85:024bf7f99721	998	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
bogdanm	85:024bf7f99721	999	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
bogdanm	85:024bf7f99721	1000
bogdanm	85:024bf7f99721	1001	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
bogdanm	85:024bf7f99721	1002	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	85:024bf7f99721	1003	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	85:024bf7f99721	1004	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	85:024bf7f99721	1005
bogdanm	85:024bf7f99721	1006	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
bogdanm	85:024bf7f99721	1007	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
bogdanm	85:024bf7f99721	1008
bogdanm	85:024bf7f99721	1009	/***************** Bit definition for CAN_BTR register ******************/
bogdanm	85:024bf7f99721	1010	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
bogdanm	85:024bf7f99721	1011	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
bogdanm	85:024bf7f99721	1012	#define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /!<Time Segment 1 (Bit 0) /
bogdanm	85:024bf7f99721	1013	#define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /!<Time Segment 1 (Bit 1) /
bogdanm	85:024bf7f99721	1014	#define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /!<Time Segment 1 (Bit 2) /
bogdanm	85:024bf7f99721	1015	#define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /!<Time Segment 1 (Bit 3) /
bogdanm	85:024bf7f99721	1016	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
bogdanm	85:024bf7f99721	1017	#define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /!<Time Segment 2 (Bit 0) /
bogdanm	85:024bf7f99721	1018	#define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /!<Time Segment 2 (Bit 1) /
bogdanm	85:024bf7f99721	1019	#define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /!<Time Segment 2 (Bit 2) /
bogdanm	85:024bf7f99721	1020	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
bogdanm	85:024bf7f99721	1021	#define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /!<Resynchronization Jump Width (Bit 0) /
bogdanm	85:024bf7f99721	1022	#define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /!<Resynchronization Jump Width (Bit 1) /
bogdanm	85:024bf7f99721	1023	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
bogdanm	85:024bf7f99721	1024	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
bogdanm	85:024bf7f99721	1025
bogdanm	85:024bf7f99721	1026	/!<Mailbox registers /
bogdanm	85:024bf7f99721	1027	/**************** Bit definition for CAN_TI0R register ******************/
bogdanm	85:024bf7f99721	1028	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	85:024bf7f99721	1029	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	85:024bf7f99721	1030	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	85:024bf7f99721	1031	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	85:024bf7f99721	1032	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	85:024bf7f99721	1033
bogdanm	85:024bf7f99721	1034	/**************** Bit definition for CAN_TDT0R register *****************/
bogdanm	85:024bf7f99721	1035	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	85:024bf7f99721	1036	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	85:024bf7f99721	1037	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	85:024bf7f99721	1038
bogdanm	85:024bf7f99721	1039	/**************** Bit definition for CAN_TDL0R register *****************/
bogdanm	85:024bf7f99721	1040	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	85:024bf7f99721	1041	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	85:024bf7f99721	1042	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	85:024bf7f99721	1043	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	85:024bf7f99721	1044
bogdanm	85:024bf7f99721	1045	/**************** Bit definition for CAN_TDH0R register *****************/
bogdanm	85:024bf7f99721	1046	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	85:024bf7f99721	1047	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	85:024bf7f99721	1048	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	85:024bf7f99721	1049	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	85:024bf7f99721	1050
bogdanm	85:024bf7f99721	1051	/***************** Bit definition for CAN_TI1R register *****************/
bogdanm	85:024bf7f99721	1052	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	85:024bf7f99721	1053	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	85:024bf7f99721	1054	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	85:024bf7f99721	1055	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	85:024bf7f99721	1056	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	85:024bf7f99721	1057
bogdanm	85:024bf7f99721	1058	/***************** Bit definition for CAN_TDT1R register ****************/
bogdanm	85:024bf7f99721	1059	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	85:024bf7f99721	1060	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	85:024bf7f99721	1061	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	85:024bf7f99721	1062
bogdanm	85:024bf7f99721	1063	/***************** Bit definition for CAN_TDL1R register ****************/
bogdanm	85:024bf7f99721	1064	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	85:024bf7f99721	1065	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	85:024bf7f99721	1066	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	85:024bf7f99721	1067	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	85:024bf7f99721	1068
bogdanm	85:024bf7f99721	1069	/***************** Bit definition for CAN_TDH1R register ****************/
bogdanm	85:024bf7f99721	1070	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	85:024bf7f99721	1071	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	85:024bf7f99721	1072	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	85:024bf7f99721	1073	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	85:024bf7f99721	1074
bogdanm	85:024bf7f99721	1075	/***************** Bit definition for CAN_TI2R register *****************/
bogdanm	85:024bf7f99721	1076	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
bogdanm	85:024bf7f99721	1077	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	85:024bf7f99721	1078	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	85:024bf7f99721	1079	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
bogdanm	85:024bf7f99721	1080	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	85:024bf7f99721	1081
bogdanm	85:024bf7f99721	1082	/***************** Bit definition for CAN_TDT2R register ****************/
bogdanm	85:024bf7f99721	1083	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	85:024bf7f99721	1084	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
bogdanm	85:024bf7f99721	1085	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	85:024bf7f99721	1086
bogdanm	85:024bf7f99721	1087	/***************** Bit definition for CAN_TDL2R register ****************/
bogdanm	85:024bf7f99721	1088	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	85:024bf7f99721	1089	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	85:024bf7f99721	1090	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	85:024bf7f99721	1091	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	85:024bf7f99721	1092
bogdanm	85:024bf7f99721	1093	/***************** Bit definition for CAN_TDH2R register ****************/
bogdanm	85:024bf7f99721	1094	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	85:024bf7f99721	1095	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	85:024bf7f99721	1096	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	85:024bf7f99721	1097	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	85:024bf7f99721	1098
bogdanm	85:024bf7f99721	1099	/***************** Bit definition for CAN_RI0R register *****************/
bogdanm	85:024bf7f99721	1100	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	85:024bf7f99721	1101	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	85:024bf7f99721	1102	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
bogdanm	85:024bf7f99721	1103	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	85:024bf7f99721	1104
bogdanm	85:024bf7f99721	1105	/***************** Bit definition for CAN_RDT0R register ****************/
bogdanm	85:024bf7f99721	1106	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	85:024bf7f99721	1107	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
bogdanm	85:024bf7f99721	1108	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	85:024bf7f99721	1109
bogdanm	85:024bf7f99721	1110	/***************** Bit definition for CAN_RDL0R register ****************/
bogdanm	85:024bf7f99721	1111	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	85:024bf7f99721	1112	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	85:024bf7f99721	1113	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	85:024bf7f99721	1114	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	85:024bf7f99721	1115
bogdanm	85:024bf7f99721	1116	/***************** Bit definition for CAN_RDH0R register ****************/
bogdanm	85:024bf7f99721	1117	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	85:024bf7f99721	1118	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	85:024bf7f99721	1119	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	85:024bf7f99721	1120	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	85:024bf7f99721	1121
bogdanm	85:024bf7f99721	1122	/***************** Bit definition for CAN_RI1R register *****************/
bogdanm	85:024bf7f99721	1123	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
bogdanm	85:024bf7f99721	1124	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
bogdanm	85:024bf7f99721	1125	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
bogdanm	85:024bf7f99721	1126	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
bogdanm	85:024bf7f99721	1127
bogdanm	85:024bf7f99721	1128	/***************** Bit definition for CAN_RDT1R register ****************/
bogdanm	85:024bf7f99721	1129	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
bogdanm	85:024bf7f99721	1130	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
bogdanm	85:024bf7f99721	1131	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
bogdanm	85:024bf7f99721	1132
bogdanm	85:024bf7f99721	1133	/***************** Bit definition for CAN_RDL1R register ****************/
bogdanm	85:024bf7f99721	1134	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
bogdanm	85:024bf7f99721	1135	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
bogdanm	85:024bf7f99721	1136	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
bogdanm	85:024bf7f99721	1137	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
bogdanm	85:024bf7f99721	1138
bogdanm	85:024bf7f99721	1139	/***************** Bit definition for CAN_RDH1R register ****************/
bogdanm	85:024bf7f99721	1140	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
bogdanm	85:024bf7f99721	1141	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
bogdanm	85:024bf7f99721	1142	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
bogdanm	85:024bf7f99721	1143	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
bogdanm	85:024bf7f99721	1144
bogdanm	85:024bf7f99721	1145	/!<CAN filter registers /
bogdanm	85:024bf7f99721	1146	/***************** Bit definition for CAN_FMR register ******************/
bogdanm	92:4fc01daae5a5	1147	#define CAN_FMR_FINIT ((uint32_t)0x00000001) /!<Filter Init Mode /
bogdanm	85:024bf7f99721	1148
bogdanm	85:024bf7f99721	1149	/***************** Bit definition for CAN_FM1R register *****************/
bogdanm	92:4fc01daae5a5	1150	#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /!<Filter Mode /
bogdanm	92:4fc01daae5a5	1151	#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /!<Filter Init Mode bit 0 /
bogdanm	92:4fc01daae5a5	1152	#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /!<Filter Init Mode bit 1 /
bogdanm	92:4fc01daae5a5	1153	#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /!<Filter Init Mode bit 2 /
bogdanm	92:4fc01daae5a5	1154	#define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /!<Filter Init Mode bit 3 /
bogdanm	92:4fc01daae5a5	1155	#define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /!<Filter Init Mode bit 4 /
bogdanm	92:4fc01daae5a5	1156	#define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /!<Filter Init Mode bit 5 /
bogdanm	92:4fc01daae5a5	1157	#define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /!<Filter Init Mode bit 6 /
bogdanm	92:4fc01daae5a5	1158	#define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /!<Filter Init Mode bit 7 /
bogdanm	92:4fc01daae5a5	1159	#define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /!<Filter Init Mode bit 8 /
bogdanm	92:4fc01daae5a5	1160	#define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /!<Filter Init Mode bit 9 /
bogdanm	92:4fc01daae5a5	1161	#define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /!<Filter Init Mode bit 10 /
bogdanm	92:4fc01daae5a5	1162	#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /!<Filter Init Mode bit 11 /
bogdanm	92:4fc01daae5a5	1163	#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /!<Filter Init Mode bit 12 /
bogdanm	92:4fc01daae5a5	1164	#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /!<Filter Init Mode bit 13 /
bogdanm	85:024bf7f99721	1165
bogdanm	85:024bf7f99721	1166	/***************** Bit definition for CAN_FS1R register *****************/
bogdanm	92:4fc01daae5a5	1167	#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /!<Filter Scale Configuration /
bogdanm	92:4fc01daae5a5	1168	#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /!<Filter Scale Configuration bit 0 /
bogdanm	92:4fc01daae5a5	1169	#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /!<Filter Scale Configuration bit 1 /
bogdanm	92:4fc01daae5a5	1170	#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /!<Filter Scale Configuration bit 2 /
bogdanm	92:4fc01daae5a5	1171	#define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /!<Filter Scale Configuration bit 3 /
bogdanm	92:4fc01daae5a5	1172	#define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /!<Filter Scale Configuration bit 4 /
bogdanm	92:4fc01daae5a5	1173	#define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /!<Filter Scale Configuration bit 5 /
bogdanm	92:4fc01daae5a5	1174	#define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /!<Filter Scale Configuration bit 6 /
bogdanm	92:4fc01daae5a5	1175	#define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /!<Filter Scale Configuration bit 7 /
bogdanm	92:4fc01daae5a5	1176	#define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /!<Filter Scale Configuration bit 8 /
bogdanm	92:4fc01daae5a5	1177	#define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /!<Filter Scale Configuration bit 9 /
bogdanm	92:4fc01daae5a5	1178	#define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /!<Filter Scale Configuration bit 10 /
bogdanm	92:4fc01daae5a5	1179	#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /!<Filter Scale Configuration bit 11 /
bogdanm	92:4fc01daae5a5	1180	#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /!<Filter Scale Configuration bit 12 /
bogdanm	92:4fc01daae5a5	1181	#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /!<Filter Scale Configuration bit 13 /
bogdanm	85:024bf7f99721	1182
bogdanm	85:024bf7f99721	1183	/**************** Bit definition for CAN_FFA1R register *****************/
bogdanm	92:4fc01daae5a5	1184	#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /!<Filter FIFO Assignment /
bogdanm	92:4fc01daae5a5	1185	#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /!<Filter FIFO Assignment for Filter 0 /
bogdanm	92:4fc01daae5a5	1186	#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /!<Filter FIFO Assignment for Filter 1 /
bogdanm	92:4fc01daae5a5	1187	#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /!<Filter FIFO Assignment for Filter 2 /
bogdanm	92:4fc01daae5a5	1188	#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /!<Filter FIFO Assignment for Filter 3 /
bogdanm	92:4fc01daae5a5	1189	#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /!<Filter FIFO Assignment for Filter 4 /
bogdanm	92:4fc01daae5a5	1190	#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /!<Filter FIFO Assignment for Filter 5 /
bogdanm	92:4fc01daae5a5	1191	#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /!<Filter FIFO Assignment for Filter 6 /
bogdanm	92:4fc01daae5a5	1192	#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /!<Filter FIFO Assignment for Filter 7 /
bogdanm	92:4fc01daae5a5	1193	#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /!<Filter FIFO Assignment for Filter 8 /
bogdanm	92:4fc01daae5a5	1194	#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /!<Filter FIFO Assignment for Filter 9 /
bogdanm	92:4fc01daae5a5	1195	#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /!<Filter FIFO Assignment for Filter 10 /
bogdanm	92:4fc01daae5a5	1196	#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /!<Filter FIFO Assignment for Filter 11 /
bogdanm	92:4fc01daae5a5	1197	#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /!<Filter FIFO Assignment for Filter 12 /
bogdanm	92:4fc01daae5a5	1198	#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /!<Filter FIFO Assignment for Filter 13 /
bogdanm	85:024bf7f99721	1199
bogdanm	85:024bf7f99721	1200	/***************** Bit definition for CAN_FA1R register *****************/
bogdanm	92:4fc01daae5a5	1201	#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /!<Filter Active /
bogdanm	92:4fc01daae5a5	1202	#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /!<Filter 0 Active /
bogdanm	92:4fc01daae5a5	1203	#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /!<Filter 1 Active /
bogdanm	92:4fc01daae5a5	1204	#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /!<Filter 2 Active /
bogdanm	92:4fc01daae5a5	1205	#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /!<Filter 3 Active /
bogdanm	92:4fc01daae5a5	1206	#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /!<Filter 4 Active /
bogdanm	92:4fc01daae5a5	1207	#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /!<Filter 5 Active /
bogdanm	92:4fc01daae5a5	1208	#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /!<Filter 6 Active /
bogdanm	92:4fc01daae5a5	1209	#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /!<Filter 7 Active /
bogdanm	92:4fc01daae5a5	1210	#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /!<Filter 8 Active /
bogdanm	92:4fc01daae5a5	1211	#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /!<Filter 9 Active /
bogdanm	92:4fc01daae5a5	1212	#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /!<Filter 10 Active /
bogdanm	92:4fc01daae5a5	1213	#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /!<Filter 11 Active /
bogdanm	92:4fc01daae5a5	1214	#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /!<Filter 12 Active /
bogdanm	92:4fc01daae5a5	1215	#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /!<Filter 13 Active /
bogdanm	85:024bf7f99721	1216
bogdanm	85:024bf7f99721	1217	/***************** Bit definition for CAN_F0R1 register *****************/
bogdanm	85:024bf7f99721	1218	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1219	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1220	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1221	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1222	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1223	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1224	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1225	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1226	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1227	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1228	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1229	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1230	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1231	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1232	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1233	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1234	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1235	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1236	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1237	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1238	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1239	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1240	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1241	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1242	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1243	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1244	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1245	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1246	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1247	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1248	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1249	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1250
bogdanm	85:024bf7f99721	1251	/***************** Bit definition for CAN_F1R1 register *****************/
bogdanm	85:024bf7f99721	1252	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1253	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1254	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1255	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1256	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1257	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1258	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1259	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1260	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1261	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1262	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1263	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1264	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1265	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1266	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1267	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1268	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1269	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1270	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1271	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1272	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1273	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1274	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1275	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1276	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1277	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1278	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1279	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1280	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1281	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1282	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1283	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1284
bogdanm	85:024bf7f99721	1285	/***************** Bit definition for CAN_F2R1 register *****************/
bogdanm	85:024bf7f99721	1286	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1287	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1288	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1289	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1290	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1291	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1292	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1293	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1294	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1295	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1296	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1297	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1298	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1299	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1300	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1301	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1302	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1303	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1304	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1305	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1306	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1307	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1308	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1309	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1310	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1311	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1312	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1313	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1314	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1315	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1316	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1317	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1318
bogdanm	85:024bf7f99721	1319	/***************** Bit definition for CAN_F3R1 register *****************/
bogdanm	85:024bf7f99721	1320	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1321	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1322	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1323	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1324	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1325	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1326	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1327	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1328	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1329	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1330	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1331	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1332	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1333	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1334	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1335	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1336	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1337	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1338	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1339	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1340	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1341	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1342	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1343	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1344	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1345	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1346	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1347	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1348	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1349	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1350	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1351	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1352
bogdanm	85:024bf7f99721	1353	/***************** Bit definition for CAN_F4R1 register *****************/
bogdanm	85:024bf7f99721	1354	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1355	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1356	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1357	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1358	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1359	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1360	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1361	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1362	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1363	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1364	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1365	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1366	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1367	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1368	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1369	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1370	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1371	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1372	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1373	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1374	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1375	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1376	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1377	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1378	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1379	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1380	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1381	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1382	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1383	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1384	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1385	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1386
bogdanm	85:024bf7f99721	1387	/***************** Bit definition for CAN_F5R1 register *****************/
bogdanm	85:024bf7f99721	1388	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1389	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1390	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1391	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1392	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1393	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1394	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1395	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1396	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1397	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1398	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1399	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1400	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1401	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1402	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1403	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1404	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1405	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1406	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1407	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1408	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1409	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1410	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1411	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1412	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1413	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1414	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1415	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1416	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1417	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1418	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1419	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1420
bogdanm	85:024bf7f99721	1421	/***************** Bit definition for CAN_F6R1 register *****************/
bogdanm	85:024bf7f99721	1422	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1423	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1424	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1425	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1426	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1427	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1428	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1429	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1430	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1431	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1432	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1433	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1434	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1435	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1436	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1437	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1438	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1439	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1440	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1441	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1442	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1443	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1444	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1445	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1446	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1447	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1448	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1449	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1450	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1451	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1452	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1453	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1454
bogdanm	85:024bf7f99721	1455	/***************** Bit definition for CAN_F7R1 register *****************/
bogdanm	85:024bf7f99721	1456	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1457	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1458	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1459	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1460	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1461	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1462	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1463	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1464	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1465	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1466	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1467	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1468	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1469	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1470	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1471	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1472	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1473	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1474	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1475	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1476	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1477	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1478	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1479	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1480	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1481	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1482	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1483	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1484	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1485	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1486	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1487	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1488
bogdanm	85:024bf7f99721	1489	/***************** Bit definition for CAN_F8R1 register *****************/
bogdanm	85:024bf7f99721	1490	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1491	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1492	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1493	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1494	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1495	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1496	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1497	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1498	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1499	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1500	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1501	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1502	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1503	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1504	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1505	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1506	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1507	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1508	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1509	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1510	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1511	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1512	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1513	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1514	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1515	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1516	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1517	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1518	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1519	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1520	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1521	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1522
bogdanm	85:024bf7f99721	1523	/***************** Bit definition for CAN_F9R1 register *****************/
bogdanm	85:024bf7f99721	1524	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1525	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1526	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1527	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1528	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1529	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1530	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1531	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1532	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1533	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1534	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1535	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1536	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1537	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1538	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1539	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1540	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1541	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1542	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1543	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1544	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1545	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1546	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1547	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1548	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1549	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1550	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1551	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1552	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1553	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1554	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1555	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1556
bogdanm	85:024bf7f99721	1557	/***************** Bit definition for CAN_F10R1 register ****************/
bogdanm	85:024bf7f99721	1558	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1559	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1560	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1561	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1562	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1563	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1564	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1565	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1566	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1567	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1568	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1569	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1570	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1571	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1572	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1573	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1574	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1575	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1576	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1577	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1578	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1579	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1580	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1581	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1582	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1583	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1584	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1585	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1586	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1587	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1588	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1589	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1590
bogdanm	85:024bf7f99721	1591	/***************** Bit definition for CAN_F11R1 register ****************/
bogdanm	85:024bf7f99721	1592	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1593	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1594	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1595	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1596	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1597	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1598	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1599	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1600	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1601	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1602	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1603	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1604	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1605	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1606	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1607	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1608	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1609	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1610	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1611	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1612	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1613	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1614	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1615	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1616	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1617	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1618	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1619	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1620	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1621	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1622	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1623	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1624
bogdanm	85:024bf7f99721	1625	/***************** Bit definition for CAN_F12R1 register ****************/
bogdanm	85:024bf7f99721	1626	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1627	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1628	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1629	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1630	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1631	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1632	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1633	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1634	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1635	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1636	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1637	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1638	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1639	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1640	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1641	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1642	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1643	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1644	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1645	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1646	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1647	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1648	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1649	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1650	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1651	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1652	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1653	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1654	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1655	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1656	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1657	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1658
bogdanm	85:024bf7f99721	1659	/***************** Bit definition for CAN_F13R1 register ****************/
bogdanm	85:024bf7f99721	1660	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1661	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1662	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1663	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1664	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1665	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1666	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1667	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1668	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1669	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1670	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1671	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1672	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1673	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1674	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1675	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1676	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1677	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1678	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1679	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1680	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1681	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1682	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1683	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1684	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1685	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1686	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1687	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1688	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1689	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1690	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1691	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1692
bogdanm	85:024bf7f99721	1693	/***************** Bit definition for CAN_F0R2 register *****************/
bogdanm	85:024bf7f99721	1694	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1695	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1696	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1697	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1698	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1699	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1700	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1701	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1702	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1703	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1704	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1705	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1706	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1707	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1708	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1709	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1710	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1711	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1712	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1713	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1714	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1715	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1716	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1717	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1718	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1719	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1720	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1721	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1722	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1723	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1724	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1725	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1726
bogdanm	85:024bf7f99721	1727	/***************** Bit definition for CAN_F1R2 register *****************/
bogdanm	85:024bf7f99721	1728	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1729	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1730	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1731	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1732	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1733	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1734	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1735	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1736	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1737	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1738	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1739	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1740	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1741	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1742	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1743	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1744	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1745	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1746	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1747	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1748	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1749	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1750	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1751	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1752	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1753	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1754	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1755	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1756	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1757	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1758	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1759	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1760
bogdanm	85:024bf7f99721	1761	/***************** Bit definition for CAN_F2R2 register *****************/
bogdanm	85:024bf7f99721	1762	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1763	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1764	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1765	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1766	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1767	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1768	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1769	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1770	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1771	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1772	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1773	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1774	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1775	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1776	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1777	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1778	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1779	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1780	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1781	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1782	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1783	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1784	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1785	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1786	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1787	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1788	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1789	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1790	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1791	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1792	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1793	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1794
bogdanm	85:024bf7f99721	1795	/***************** Bit definition for CAN_F3R2 register *****************/
bogdanm	85:024bf7f99721	1796	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1797	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1798	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1799	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1800	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1801	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1802	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1803	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1804	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1805	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1806	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1807	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1808	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1809	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1810	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1811	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1812	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1813	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1814	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1815	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1816	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1817	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1818	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1819	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1820	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1821	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1822	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1823	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1824	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1825	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1826	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1827	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1828
bogdanm	85:024bf7f99721	1829	/***************** Bit definition for CAN_F4R2 register *****************/
bogdanm	85:024bf7f99721	1830	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1831	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1832	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1833	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1834	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1835	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1836	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1837	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1838	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1839	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1840	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1841	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1842	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1843	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1844	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1845	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1846	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1847	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1848	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1849	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1850	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1851	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1852	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1853	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1854	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1855	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1856	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1857	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1858	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1859	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1860	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1861	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1862
bogdanm	85:024bf7f99721	1863	/***************** Bit definition for CAN_F5R2 register *****************/
bogdanm	85:024bf7f99721	1864	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1865	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1866	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1867	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1868	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1869	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1870	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1871	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1872	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1873	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1874	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1875	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1876	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1877	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1878	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1879	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1880	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1881	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1882	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1883	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1884	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1885	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1886	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1887	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1888	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1889	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1890	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1891	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1892	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1893	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1894	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1895	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1896
bogdanm	85:024bf7f99721	1897	/***************** Bit definition for CAN_F6R2 register *****************/
bogdanm	85:024bf7f99721	1898	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1899	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1900	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1901	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1902	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1903	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1904	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1905	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1906	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1907	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1908	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1909	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1910	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1911	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1912	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1913	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1914	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1915	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1916	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1917	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1918	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1919	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1920	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1921	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1922	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1923	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1924	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1925	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1926	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1927	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1928	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1929	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1930
bogdanm	85:024bf7f99721	1931	/***************** Bit definition for CAN_F7R2 register *****************/
bogdanm	85:024bf7f99721	1932	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1933	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1934	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1935	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1936	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1937	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1938	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1939	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1940	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1941	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1942	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1943	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1944	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1945	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1946	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1947	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1948	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1949	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1950	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1951	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1952	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1953	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1954	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1955	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1956	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1957	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1958	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1959	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1960	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1961	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1962	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1963	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1964
bogdanm	85:024bf7f99721	1965	/***************** Bit definition for CAN_F8R2 register *****************/
bogdanm	85:024bf7f99721	1966	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	1967	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	1968	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	1969	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	1970	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	1971	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	1972	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	1973	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	1974	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	1975	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	1976	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	1977	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	1978	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	1979	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	1980	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	1981	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	1982	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	1983	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	1984	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	1985	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	1986	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	1987	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	1988	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	1989	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	1990	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	1991	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	1992	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	1993	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	1994	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	1995	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	1996	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	1997	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	1998
bogdanm	85:024bf7f99721	1999	/***************** Bit definition for CAN_F9R2 register *****************/
bogdanm	85:024bf7f99721	2000	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	2001	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	2002	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	2003	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	2004	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	2005	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	2006	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	2007	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	2008	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	2009	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	2010	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	2011	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	2012	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	2013	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	2014	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	2015	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	2016	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	2017	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	2018	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	2019	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	2020	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	2021	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	2022	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	2023	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	2024	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	2025	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	2026	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	2027	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	2028	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	2029	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	2030	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	2031	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	2032
bogdanm	85:024bf7f99721	2033	/***************** Bit definition for CAN_F10R2 register ****************/
bogdanm	85:024bf7f99721	2034	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	2035	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	2036	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	2037	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	2038	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	2039	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	2040	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	2041	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	2042	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	2043	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	2044	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	2045	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	2046	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	2047	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	2048	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	2049	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	2050	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	2051	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	2052	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	2053	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	2054	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	2055	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	2056	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	2057	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	2058	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	2059	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	2060	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	2061	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	2062	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	2063	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	2064	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	2065	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	2066
bogdanm	85:024bf7f99721	2067	/***************** Bit definition for CAN_F11R2 register ****************/
bogdanm	85:024bf7f99721	2068	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	2069	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	2070	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	2071	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	2072	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	2073	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	2074	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	2075	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	2076	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	2077	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	2078	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	2079	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	2080	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	2081	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	2082	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	2083	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	2084	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	2085	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	2086	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	2087	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	2088	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	2089	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	2090	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	2091	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	2092	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	2093	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	2094	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	2095	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	2096	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	2097	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	2098	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	2099	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	2100
bogdanm	85:024bf7f99721	2101	/***************** Bit definition for CAN_F12R2 register ****************/
bogdanm	85:024bf7f99721	2102	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	2103	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	2104	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	2105	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	2106	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	2107	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	2108	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	2109	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	2110	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	2111	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	2112	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	2113	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	2114	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	2115	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	2116	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	2117	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	2118	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	2119	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	2120	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	2121	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	2122	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	2123	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	2124	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	2125	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	2126	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	2127	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	2128	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	2129	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	2130	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	2131	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	2132	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	2133	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	2134
bogdanm	85:024bf7f99721	2135	/***************** Bit definition for CAN_F13R2 register ****************/
bogdanm	85:024bf7f99721	2136	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
bogdanm	85:024bf7f99721	2137	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
bogdanm	85:024bf7f99721	2138	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
bogdanm	85:024bf7f99721	2139	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
bogdanm	85:024bf7f99721	2140	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
bogdanm	85:024bf7f99721	2141	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
bogdanm	85:024bf7f99721	2142	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
bogdanm	85:024bf7f99721	2143	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
bogdanm	85:024bf7f99721	2144	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
bogdanm	85:024bf7f99721	2145	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
bogdanm	85:024bf7f99721	2146	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
bogdanm	85:024bf7f99721	2147	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
bogdanm	85:024bf7f99721	2148	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
bogdanm	85:024bf7f99721	2149	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
bogdanm	85:024bf7f99721	2150	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
bogdanm	85:024bf7f99721	2151	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
bogdanm	85:024bf7f99721	2152	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
bogdanm	85:024bf7f99721	2153	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
bogdanm	85:024bf7f99721	2154	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
bogdanm	85:024bf7f99721	2155	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
bogdanm	85:024bf7f99721	2156	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
bogdanm	85:024bf7f99721	2157	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
bogdanm	85:024bf7f99721	2158	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
bogdanm	85:024bf7f99721	2159	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
bogdanm	85:024bf7f99721	2160	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
bogdanm	85:024bf7f99721	2161	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
bogdanm	85:024bf7f99721	2162	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
bogdanm	85:024bf7f99721	2163	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
bogdanm	85:024bf7f99721	2164	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
bogdanm	85:024bf7f99721	2165	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
bogdanm	85:024bf7f99721	2166	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
bogdanm	85:024bf7f99721	2167	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
bogdanm	85:024bf7f99721	2168
bogdanm	85:024bf7f99721	2169	/******************************************************************************/
bogdanm	85:024bf7f99721	2170	/* */
bogdanm	85:024bf7f99721	2171	/* HDMI-CEC (CEC) */
bogdanm	85:024bf7f99721	2172	/* */
bogdanm	85:024bf7f99721	2173	/******************************************************************************/
bogdanm	85:024bf7f99721	2174
bogdanm	85:024bf7f99721	2175	/***************** Bit definition for CEC_CR register *******************/
bogdanm	85:024bf7f99721	2176	#define CEC_CR_CECEN ((uint32_t)0x00000001) /!< CEC Enable /
bogdanm	85:024bf7f99721	2177	#define CEC_CR_TXSOM ((uint32_t)0x00000002) /!< CEC Tx Start Of Message /
bogdanm	85:024bf7f99721	2178	#define CEC_CR_TXEOM ((uint32_t)0x00000004) /!< CEC Tx End Of Message /
bogdanm	85:024bf7f99721	2179
bogdanm	85:024bf7f99721	2180	/***************** Bit definition for CEC_CFGR register *****************/
bogdanm	85:024bf7f99721	2181	#define CEC_CFGR_SFT ((uint32_t)0x00000007) /!< CEC Signal Free Time /
bogdanm	85:024bf7f99721	2182	#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /!< CEC Tolerance /
bogdanm	85:024bf7f99721	2183	#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /!< CEC Rx Stop /
bogdanm	85:024bf7f99721	2184	#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /!< CEC Bit Rising Error generation /
bogdanm	85:024bf7f99721	2185	#define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /!< CEC Long Bit Period Error gener. /
bogdanm	85:024bf7f99721	2186	#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /!< CEC Broadcast No Error generation /
bogdanm	85:024bf7f99721	2187	#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /!< CEC Signal Free Time optional /
bogdanm	85:024bf7f99721	2188	#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /!< CEC Own Address /
bogdanm	85:024bf7f99721	2189	#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /!< CEC Listen mode /
bogdanm	85:024bf7f99721	2190
bogdanm	85:024bf7f99721	2191	/***************** Bit definition for CEC_TXDR register *****************/
bogdanm	85:024bf7f99721	2192	#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /!< CEC Tx Data /
bogdanm	85:024bf7f99721	2193
bogdanm	85:024bf7f99721	2194	/***************** Bit definition for CEC_RXDR register *****************/
bogdanm	85:024bf7f99721	2195	#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /!< CEC Rx Data /
bogdanm	85:024bf7f99721	2196
bogdanm	85:024bf7f99721	2197	/***************** Bit definition for CEC_ISR register ******************/
bogdanm	85:024bf7f99721	2198	#define CEC_ISR_RXBR ((uint32_t)0x00000001) /!< CEC Rx-Byte Received /
bogdanm	85:024bf7f99721	2199	#define CEC_ISR_RXEND ((uint32_t)0x00000002) /!< CEC End Of Reception /
bogdanm	85:024bf7f99721	2200	#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /!< CEC Rx-Overrun /
bogdanm	85:024bf7f99721	2201	#define CEC_ISR_BRE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error /
bogdanm	85:024bf7f99721	2202	#define CEC_ISR_SBPE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error /
bogdanm	85:024bf7f99721	2203	#define CEC_ISR_LBPE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error /
bogdanm	85:024bf7f99721	2204	#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge /
bogdanm	85:024bf7f99721	2205	#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /!< CEC Arbitration Lost /
bogdanm	85:024bf7f99721	2206	#define CEC_ISR_TXBR ((uint32_t)0x00000100) /!< CEC Tx Byte Request /
bogdanm	85:024bf7f99721	2207	#define CEC_ISR_TXEND ((uint32_t)0x00000200) /!< CEC End of Transmission /
bogdanm	85:024bf7f99721	2208	#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun /
bogdanm	85:024bf7f99721	2209	#define CEC_ISR_TXERR ((uint32_t)0x00000800) /!< CEC Tx-Error /
bogdanm	85:024bf7f99721	2210	#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge /
bogdanm	85:024bf7f99721	2211
bogdanm	85:024bf7f99721	2212	/***************** Bit definition for CEC_IER register ******************/
bogdanm	85:024bf7f99721	2213	#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /!< CEC Rx-Byte Received IT Enable /
bogdanm	85:024bf7f99721	2214	#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /!< CEC End Of Reception IT Enable /
bogdanm	85:024bf7f99721	2215	#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /!< CEC Rx-Overrun IT Enable /
bogdanm	85:024bf7f99721	2216	#define CEC_IER_BREIE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error IT Enable /
bogdanm	85:024bf7f99721	2217	#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error IT Enable/
bogdanm	85:024bf7f99721	2218	#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error IT Enable /
bogdanm	85:024bf7f99721	2219	#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge IT Enable /
bogdanm	85:024bf7f99721	2220	#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /!< CEC Arbitration Lost IT Enable /
bogdanm	85:024bf7f99721	2221	#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /!< CEC Tx Byte Request IT Enable /
bogdanm	85:024bf7f99721	2222	#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /!< CEC End of Transmission IT Enable /
bogdanm	85:024bf7f99721	2223	#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun IT Enable /
bogdanm	85:024bf7f99721	2224	#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /!< CEC Tx-Error IT Enable /
bogdanm	85:024bf7f99721	2225	#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge IT Enable /
bogdanm	85:024bf7f99721	2226
bogdanm	85:024bf7f99721	2227
bogdanm	85:024bf7f99721	2228	/******************************************************************************/
bogdanm	85:024bf7f99721	2229	/* */
bogdanm	85:024bf7f99721	2230	/* Analog Comparators (COMP) */
bogdanm	85:024bf7f99721	2231	/* */
bogdanm	85:024bf7f99721	2232	/******************************************************************************/
bogdanm	85:024bf7f99721	2233	/********************* Bit definition for COMP_CSR register *************/
bogdanm	85:024bf7f99721	2234	/* COMP1 bits definition */
bogdanm	85:024bf7f99721	2235	#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /!< COMP1 enable /
bogdanm	85:024bf7f99721	2236	#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /!< SW1 switch control /
bogdanm	85:024bf7f99721	2237	#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /!< COMP1 power mode /
bogdanm	85:024bf7f99721	2238	#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /!< COMP1 power mode bit 0 /
bogdanm	85:024bf7f99721	2239	#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /!< COMP1 power mode bit 1 /
bogdanm	85:024bf7f99721	2240	#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /!< COMP1 inverting input select /
bogdanm	85:024bf7f99721	2241	#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /!< COMP1 inverting input select bit 0 /
bogdanm	85:024bf7f99721	2242	#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /!< COMP1 inverting input select bit 1 /
bogdanm	85:024bf7f99721	2243	#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /!< COMP1 inverting input select bit 2 /
bogdanm	85:024bf7f99721	2244	#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /!< COMP1 output select /
bogdanm	85:024bf7f99721	2245	#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /!< COMP1 output select bit 0 /
bogdanm	85:024bf7f99721	2246	#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /!< COMP1 output select bit 1 /
bogdanm	85:024bf7f99721	2247	#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /!< COMP1 output select bit 2 /
bogdanm	85:024bf7f99721	2248	#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /!< COMP1 output polarity /
bogdanm	85:024bf7f99721	2249	#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /!< COMP1 hysteresis /
bogdanm	85:024bf7f99721	2250	#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /!< COMP1 hysteresis bit 0 /
bogdanm	85:024bf7f99721	2251	#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /!< COMP1 hysteresis bit 1 /
bogdanm	85:024bf7f99721	2252	#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /!< COMP1 output level /
bogdanm	85:024bf7f99721	2253	#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /!< COMP1 lock /
bogdanm	85:024bf7f99721	2254	/* COMP2 bits definition */
bogdanm	85:024bf7f99721	2255	#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /!< COMP2 enable /
bogdanm	85:024bf7f99721	2256	#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /!< COMP2 power mode /
bogdanm	85:024bf7f99721	2257	#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /!< COMP2 power mode bit 0 /
bogdanm	85:024bf7f99721	2258	#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /!< COMP2 power mode bit 1 /
bogdanm	85:024bf7f99721	2259	#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /!< COMP2 inverting input select /
bogdanm	85:024bf7f99721	2260	#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /!< COMP2 inverting input select bit 0 /
bogdanm	85:024bf7f99721	2261	#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /!< COMP2 inverting input select bit 1 /
bogdanm	85:024bf7f99721	2262	#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /!< COMP2 inverting input select bit 2 /
bogdanm	85:024bf7f99721	2263	#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /!< Comparators window mode enable /
bogdanm	85:024bf7f99721	2264	#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /!< COMP2 output select /
bogdanm	85:024bf7f99721	2265	#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /!< COMP2 output select bit 0 /
bogdanm	85:024bf7f99721	2266	#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /!< COMP2 output select bit 1 /
bogdanm	85:024bf7f99721	2267	#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /!< COMP2 output select bit 2 /
bogdanm	85:024bf7f99721	2268	#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /!< COMP2 output polarity /
bogdanm	85:024bf7f99721	2269	#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /!< COMP2 hysteresis /
bogdanm	85:024bf7f99721	2270	#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /!< COMP2 hysteresis bit 0 /
bogdanm	85:024bf7f99721	2271	#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /!< COMP2 hysteresis bit 1 /
bogdanm	85:024bf7f99721	2272	#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /!< COMP2 output level /
bogdanm	85:024bf7f99721	2273	#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /!< COMP2 lock /
bogdanm	85:024bf7f99721	2274	/* COMPx bits definition */
bogdanm	92:4fc01daae5a5	2275	#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /!< COMPx enable /
bogdanm	92:4fc01daae5a5	2276	#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /!< COMPx power mode /
bogdanm	92:4fc01daae5a5	2277	#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /!< COMPx power mode bit 0 /
bogdanm	92:4fc01daae5a5	2278	#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /!< COMPx power mode bit 1 /
bogdanm	92:4fc01daae5a5	2279	#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /!< COMPx inverting input select /
bogdanm	92:4fc01daae5a5	2280	#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /!< COMPx inverting input select bit 0 /
bogdanm	92:4fc01daae5a5	2281	#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /!< COMPx inverting input select bit 1 /
bogdanm	92:4fc01daae5a5	2282	#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /!< COMPx inverting input select bit 2 /
bogdanm	92:4fc01daae5a5	2283	#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /!< COMPx output select /
bogdanm	92:4fc01daae5a5	2284	#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /!< COMPx output select bit 0 /
bogdanm	92:4fc01daae5a5	2285	#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /!< COMPx output select bit 1 /
bogdanm	92:4fc01daae5a5	2286	#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /!< COMPx output select bit 2 /
bogdanm	92:4fc01daae5a5	2287	#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /!< COMPx output polarity /
bogdanm	92:4fc01daae5a5	2288	#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /!< COMPx hysteresis /
bogdanm	92:4fc01daae5a5	2289	#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /!< COMPx hysteresis bit 0 /
bogdanm	92:4fc01daae5a5	2290	#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /!< COMPx hysteresis bit 1 /
bogdanm	92:4fc01daae5a5	2291	#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /!< COMPx output level /
bogdanm	92:4fc01daae5a5	2292	#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /!< COMPx lock /
bogdanm	85:024bf7f99721	2293
bogdanm	85:024bf7f99721	2294	/******************************************************************************/
bogdanm	85:024bf7f99721	2295	/* */
bogdanm	85:024bf7f99721	2296	/* CRC calculation unit (CRC) */
bogdanm	85:024bf7f99721	2297	/* */
bogdanm	85:024bf7f99721	2298	/******************************************************************************/
bogdanm	85:024bf7f99721	2299	/***************** Bit definition for CRC_DR register *******************/
bogdanm	85:024bf7f99721	2300	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
bogdanm	85:024bf7f99721	2301
bogdanm	85:024bf7f99721	2302	/***************** Bit definition for CRC_IDR register ******************/
bogdanm	85:024bf7f99721	2303	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
bogdanm	85:024bf7f99721	2304
bogdanm	85:024bf7f99721	2305	/****************** Bit definition for CRC_CR register ******************/
bogdanm	85:024bf7f99721	2306	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
bogdanm	85:024bf7f99721	2307	#define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /!< Polynomial size bits /
bogdanm	85:024bf7f99721	2308	#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /!< Polynomial size bit 0 /
bogdanm	85:024bf7f99721	2309	#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /!< Polynomial size bit 1 /
bogdanm	85:024bf7f99721	2310	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
bogdanm	85:024bf7f99721	2311	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< REV_IN Bit 0 /
bogdanm	85:024bf7f99721	2312	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< REV_IN Bit 1 /
bogdanm	85:024bf7f99721	2313	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
bogdanm	85:024bf7f99721	2314
bogdanm	85:024bf7f99721	2315	/***************** Bit definition for CRC_INIT register *****************/
bogdanm	85:024bf7f99721	2316	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
bogdanm	85:024bf7f99721	2317
bogdanm	85:024bf7f99721	2318	/***************** Bit definition for CRC_POL register ******************/
bogdanm	85:024bf7f99721	2319	#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /!< Coefficients of the polynomial /
bogdanm	85:024bf7f99721	2320
bogdanm	85:024bf7f99721	2321	/******************************************************************************/
bogdanm	85:024bf7f99721	2322	/* */
bogdanm	85:024bf7f99721	2323	/* CRS Clock Recovery System */
bogdanm	85:024bf7f99721	2324	/******************************************************************************/
bogdanm	85:024bf7f99721	2325
bogdanm	85:024bf7f99721	2326	/***************** Bit definition for CRS_CR register *******************/
bogdanm	85:024bf7f99721	2327	#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
bogdanm	85:024bf7f99721	2328	#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
bogdanm	85:024bf7f99721	2329	#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
bogdanm	85:024bf7f99721	2330	#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
bogdanm	85:024bf7f99721	2331	#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
bogdanm	85:024bf7f99721	2332	#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
bogdanm	85:024bf7f99721	2333	#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
bogdanm	85:024bf7f99721	2334	#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
bogdanm	85:024bf7f99721	2335
bogdanm	85:024bf7f99721	2336	/***************** Bit definition for CRS_CFGR register *******************/
bogdanm	85:024bf7f99721	2337	#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
bogdanm	85:024bf7f99721	2338	#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
bogdanm	85:024bf7f99721	2339
bogdanm	85:024bf7f99721	2340	#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
bogdanm	85:024bf7f99721	2341	#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
bogdanm	85:024bf7f99721	2342	#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
bogdanm	85:024bf7f99721	2343	#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
bogdanm	85:024bf7f99721	2344
bogdanm	85:024bf7f99721	2345	#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
bogdanm	85:024bf7f99721	2346	#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
bogdanm	85:024bf7f99721	2347	#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
bogdanm	85:024bf7f99721	2348
bogdanm	85:024bf7f99721	2349	#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
bogdanm	85:024bf7f99721	2350
bogdanm	85:024bf7f99721	2351	/***************** Bit definition for CRS_ISR register *******************/
bogdanm	85:024bf7f99721	2352	#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
bogdanm	85:024bf7f99721	2353	#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
bogdanm	85:024bf7f99721	2354	#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
bogdanm	85:024bf7f99721	2355	#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
bogdanm	85:024bf7f99721	2356	#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
bogdanm	85:024bf7f99721	2357	#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
bogdanm	85:024bf7f99721	2358	#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
bogdanm	85:024bf7f99721	2359	#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
bogdanm	85:024bf7f99721	2360	#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
bogdanm	85:024bf7f99721	2361
bogdanm	85:024bf7f99721	2362	/***************** Bit definition for CRS_ICR register *******************/
bogdanm	85:024bf7f99721	2363	#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
bogdanm	85:024bf7f99721	2364	#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
bogdanm	85:024bf7f99721	2365	#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
bogdanm	85:024bf7f99721	2366	#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
bogdanm	85:024bf7f99721	2367
bogdanm	85:024bf7f99721	2368	/******************************************************************************/
bogdanm	85:024bf7f99721	2369	/* */
bogdanm	85:024bf7f99721	2370	/* Digital to Analog Converter (DAC) */
bogdanm	85:024bf7f99721	2371	/* */
bogdanm	85:024bf7f99721	2372	/******************************************************************************/
bogdanm	85:024bf7f99721	2373	/****************** Bit definition for DAC_CR register ******************/
bogdanm	85:024bf7f99721	2374	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
bogdanm	85:024bf7f99721	2375	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
bogdanm	85:024bf7f99721	2376	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
bogdanm	85:024bf7f99721	2377
bogdanm	85:024bf7f99721	2378	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
bogdanm	85:024bf7f99721	2379	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	85:024bf7f99721	2380	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	85:024bf7f99721	2381	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
bogdanm	85:024bf7f99721	2382
bogdanm	85:024bf7f99721	2383	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
bogdanm	85:024bf7f99721	2384	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!< Bit 0 /
bogdanm	85:024bf7f99721	2385	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!< Bit 1 /
bogdanm	85:024bf7f99721	2386
bogdanm	85:024bf7f99721	2387	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
bogdanm	85:024bf7f99721	2388	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	85:024bf7f99721	2389	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	85:024bf7f99721	2390	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	85:024bf7f99721	2391	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!< Bit 3 /
bogdanm	85:024bf7f99721	2392
bogdanm	85:024bf7f99721	2393	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
bogdanm	85:024bf7f99721	2394	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!< DAC channel1 DMA Underrun Interrupt enable /
bogdanm	85:024bf7f99721	2395
bogdanm	85:024bf7f99721	2396	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!< DAC channel2 enable /
bogdanm	85:024bf7f99721	2397	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!< DAC channel2 output buffer disable /
bogdanm	85:024bf7f99721	2398	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!< DAC channel2 Trigger enable /
bogdanm	85:024bf7f99721	2399
bogdanm	85:024bf7f99721	2400	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
bogdanm	85:024bf7f99721	2401	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!< Bit 0 /
bogdanm	85:024bf7f99721	2402	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!< Bit 1 /
bogdanm	85:024bf7f99721	2403	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!< Bit 2 /
bogdanm	85:024bf7f99721	2404
bogdanm	85:024bf7f99721	2405	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
bogdanm	85:024bf7f99721	2406	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!< Bit 0 /
bogdanm	85:024bf7f99721	2407	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!< Bit 1 /
bogdanm	85:024bf7f99721	2408
bogdanm	85:024bf7f99721	2409	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
bogdanm	85:024bf7f99721	2410	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	85:024bf7f99721	2411	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	85:024bf7f99721	2412	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!< Bit 2 /
bogdanm	85:024bf7f99721	2413	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!< Bit 3 /
bogdanm	85:024bf7f99721	2414
bogdanm	85:024bf7f99721	2415	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!< DAC channel2 DMA enabled /
bogdanm	85:024bf7f99721	2416	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /!< DAC channel2 DMA Underrun Interrupt enable /
bogdanm	85:024bf7f99721	2417
bogdanm	85:024bf7f99721	2418	/*************** Bit definition for DAC_SWTRIGR register ****************/
bogdanm	92:4fc01daae5a5	2419	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!< DAC channel1 software trigger /
bogdanm	92:4fc01daae5a5	2420	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!< DAC channel2 software trigger /
bogdanm	85:024bf7f99721	2421
bogdanm	85:024bf7f99721	2422	/*************** Bit definition for DAC_DHR12R1 register ****************/
bogdanm	92:4fc01daae5a5	2423	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
bogdanm	85:024bf7f99721	2424
bogdanm	85:024bf7f99721	2425	/*************** Bit definition for DAC_DHR12L1 register ****************/
bogdanm	92:4fc01daae5a5	2426	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
bogdanm	85:024bf7f99721	2427
bogdanm	85:024bf7f99721	2428	/**************** Bit definition for DAC_DHR8R1 register ****************/
bogdanm	92:4fc01daae5a5	2429	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
bogdanm	85:024bf7f99721	2430
bogdanm	85:024bf7f99721	2431	/*************** Bit definition for DAC_DHR12R2 register ****************/
bogdanm	92:4fc01daae5a5	2432	#define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /!< DAC channel2 12-bit Right aligned data /
bogdanm	85:024bf7f99721	2433
bogdanm	85:024bf7f99721	2434	/*************** Bit definition for DAC_DHR12L2 register ****************/
bogdanm	92:4fc01daae5a5	2435	#define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /!< DAC channel2 12-bit Left aligned data /
bogdanm	85:024bf7f99721	2436
bogdanm	85:024bf7f99721	2437	/**************** Bit definition for DAC_DHR8R2 register ****************/
bogdanm	92:4fc01daae5a5	2438	#define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /!< DAC channel2 8-bit Right aligned data /
bogdanm	85:024bf7f99721	2439
bogdanm	85:024bf7f99721	2440	/*************** Bit definition for DAC_DHR12RD register ****************/
bogdanm	85:024bf7f99721	2441	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
bogdanm	85:024bf7f99721	2442	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!< DAC channel2 12-bit Right aligned data /
bogdanm	85:024bf7f99721	2443
bogdanm	85:024bf7f99721	2444	/*************** Bit definition for DAC_DHR12LD register ****************/
bogdanm	85:024bf7f99721	2445	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
bogdanm	85:024bf7f99721	2446	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!< DAC channel2 12-bit Left aligned data /
bogdanm	85:024bf7f99721	2447
bogdanm	85:024bf7f99721	2448	/**************** Bit definition for DAC_DHR8RD register ****************/
bogdanm	92:4fc01daae5a5	2449	#define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /!< DAC channel1 8-bit Right aligned data /
bogdanm	92:4fc01daae5a5	2450	#define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /!< DAC channel2 8-bit Right aligned data /
bogdanm	85:024bf7f99721	2451
bogdanm	85:024bf7f99721	2452	/***************** Bit definition for DAC_DOR1 register *****************/
bogdanm	92:4fc01daae5a5	2453	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!< DAC channel1 data output /
bogdanm	85:024bf7f99721	2454
bogdanm	85:024bf7f99721	2455	/***************** Bit definition for DAC_DOR2 register *****************/
bogdanm	92:4fc01daae5a5	2456	#define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /!< DAC channel2 data output /
bogdanm	85:024bf7f99721	2457
bogdanm	85:024bf7f99721	2458	/****************** Bit definition for DAC_SR register ******************/
bogdanm	85:024bf7f99721	2459	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun flag /
bogdanm	85:024bf7f99721	2460	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!< DAC channel2 DMA underrun flag /
bogdanm	85:024bf7f99721	2461
bogdanm	85:024bf7f99721	2462	/******************************************************************************/
bogdanm	85:024bf7f99721	2463	/* */
bogdanm	85:024bf7f99721	2464	/* Debug MCU (DBGMCU) */
bogdanm	85:024bf7f99721	2465	/* */
bogdanm	85:024bf7f99721	2466	/******************************************************************************/
bogdanm	85:024bf7f99721	2467
bogdanm	85:024bf7f99721	2468	/************** Bit definition for DBGMCU_IDCODE register ***************/
bogdanm	85:024bf7f99721	2469	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
bogdanm	85:024bf7f99721	2470
bogdanm	85:024bf7f99721	2471	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
bogdanm	85:024bf7f99721	2472	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	85:024bf7f99721	2473	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	85:024bf7f99721	2474	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
bogdanm	85:024bf7f99721	2475	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
bogdanm	85:024bf7f99721	2476	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
bogdanm	85:024bf7f99721	2477	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
bogdanm	85:024bf7f99721	2478	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
bogdanm	85:024bf7f99721	2479	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
bogdanm	85:024bf7f99721	2480	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
bogdanm	85:024bf7f99721	2481	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
bogdanm	85:024bf7f99721	2482	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
bogdanm	85:024bf7f99721	2483	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
bogdanm	85:024bf7f99721	2484	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
bogdanm	85:024bf7f99721	2485	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
bogdanm	85:024bf7f99721	2486	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
bogdanm	85:024bf7f99721	2487	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
bogdanm	85:024bf7f99721	2488
bogdanm	85:024bf7f99721	2489	/**************** Bit definition for DBGMCU_CR register *****************/
bogdanm	85:024bf7f99721	2490	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
bogdanm	85:024bf7f99721	2491	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
bogdanm	85:024bf7f99721	2492
bogdanm	85:024bf7f99721	2493	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
bogdanm	85:024bf7f99721	2494	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /!< TIM2 counter stopped when core is halted /
bogdanm	85:024bf7f99721	2495	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
bogdanm	85:024bf7f99721	2496	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /!< TIM6 counter stopped when core is halted /
bogdanm	85:024bf7f99721	2497	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /!< TIM7 counter stopped when core is halted /
bogdanm	85:024bf7f99721	2498	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /!< TIM14 counter stopped when core is halted /
bogdanm	85:024bf7f99721	2499	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Calendar frozen when core is halted /
bogdanm	85:024bf7f99721	2500	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
bogdanm	85:024bf7f99721	2501	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
bogdanm	85:024bf7f99721	2502	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
bogdanm	85:024bf7f99721	2503	#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /!< CAN debug stopped when Core is halted /
bogdanm	85:024bf7f99721	2504
bogdanm	85:024bf7f99721	2505	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
bogdanm	85:024bf7f99721	2506	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /!< TIM1 counter stopped when core is halted /
bogdanm	85:024bf7f99721	2507	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /!< TIM15 counter stopped when core is halted /
bogdanm	85:024bf7f99721	2508	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /!< TIM16 counter stopped when core is halted /
bogdanm	85:024bf7f99721	2509	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /!< TIM17 counter stopped when core is halted /
bogdanm	85:024bf7f99721	2510
bogdanm	85:024bf7f99721	2511	/******************************************************************************/
bogdanm	85:024bf7f99721	2512	/* */
bogdanm	85:024bf7f99721	2513	/* DMA Controller (DMA) */
bogdanm	85:024bf7f99721	2514	/* */
bogdanm	85:024bf7f99721	2515	/******************************************************************************/
bogdanm	85:024bf7f99721	2516	/***************** Bit definition for DMA_ISR register ******************/
bogdanm	85:024bf7f99721	2517	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
bogdanm	85:024bf7f99721	2518	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
bogdanm	85:024bf7f99721	2519	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
bogdanm	85:024bf7f99721	2520	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
bogdanm	85:024bf7f99721	2521	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
bogdanm	85:024bf7f99721	2522	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
bogdanm	85:024bf7f99721	2523	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
bogdanm	85:024bf7f99721	2524	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
bogdanm	85:024bf7f99721	2525	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
bogdanm	85:024bf7f99721	2526	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
bogdanm	85:024bf7f99721	2527	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
bogdanm	85:024bf7f99721	2528	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
bogdanm	85:024bf7f99721	2529	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
bogdanm	85:024bf7f99721	2530	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
bogdanm	85:024bf7f99721	2531	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
bogdanm	85:024bf7f99721	2532	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
bogdanm	85:024bf7f99721	2533	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
bogdanm	85:024bf7f99721	2534	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
bogdanm	85:024bf7f99721	2535	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
bogdanm	85:024bf7f99721	2536	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
bogdanm	85:024bf7f99721	2537	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
bogdanm	85:024bf7f99721	2538	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
bogdanm	85:024bf7f99721	2539	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
bogdanm	85:024bf7f99721	2540	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
bogdanm	85:024bf7f99721	2541	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
bogdanm	85:024bf7f99721	2542	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
bogdanm	85:024bf7f99721	2543	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
bogdanm	85:024bf7f99721	2544	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
bogdanm	85:024bf7f99721	2545
bogdanm	85:024bf7f99721	2546	/***************** Bit definition for DMA_IFCR register *****************/
bogdanm	85:024bf7f99721	2547	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
bogdanm	85:024bf7f99721	2548	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
bogdanm	85:024bf7f99721	2549	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
bogdanm	85:024bf7f99721	2550	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
bogdanm	85:024bf7f99721	2551	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
bogdanm	85:024bf7f99721	2552	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
bogdanm	85:024bf7f99721	2553	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
bogdanm	85:024bf7f99721	2554	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
bogdanm	85:024bf7f99721	2555	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
bogdanm	85:024bf7f99721	2556	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
bogdanm	85:024bf7f99721	2557	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
bogdanm	85:024bf7f99721	2558	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
bogdanm	85:024bf7f99721	2559	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
bogdanm	85:024bf7f99721	2560	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
bogdanm	85:024bf7f99721	2561	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
bogdanm	85:024bf7f99721	2562	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
bogdanm	85:024bf7f99721	2563	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
bogdanm	85:024bf7f99721	2564	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
bogdanm	85:024bf7f99721	2565	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
bogdanm	85:024bf7f99721	2566	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
bogdanm	85:024bf7f99721	2567	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
bogdanm	85:024bf7f99721	2568	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
bogdanm	85:024bf7f99721	2569	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
bogdanm	85:024bf7f99721	2570	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
bogdanm	85:024bf7f99721	2571	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
bogdanm	85:024bf7f99721	2572	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
bogdanm	85:024bf7f99721	2573	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
bogdanm	85:024bf7f99721	2574	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
bogdanm	85:024bf7f99721	2575
bogdanm	85:024bf7f99721	2576	/***************** Bit definition for DMA_CCR register ******************/
bogdanm	85:024bf7f99721	2577	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
bogdanm	85:024bf7f99721	2578	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
bogdanm	85:024bf7f99721	2579	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
bogdanm	85:024bf7f99721	2580	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
bogdanm	85:024bf7f99721	2581	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
bogdanm	85:024bf7f99721	2582	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
bogdanm	85:024bf7f99721	2583	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
bogdanm	85:024bf7f99721	2584	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
bogdanm	85:024bf7f99721	2585
bogdanm	85:024bf7f99721	2586	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
bogdanm	85:024bf7f99721	2587	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	85:024bf7f99721	2588	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	85:024bf7f99721	2589
bogdanm	85:024bf7f99721	2590	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
bogdanm	85:024bf7f99721	2591	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
bogdanm	85:024bf7f99721	2592	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
bogdanm	85:024bf7f99721	2593
bogdanm	85:024bf7f99721	2594	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
bogdanm	85:024bf7f99721	2595	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	85:024bf7f99721	2596	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	85:024bf7f99721	2597
bogdanm	85:024bf7f99721	2598	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
bogdanm	85:024bf7f99721	2599
bogdanm	85:024bf7f99721	2600	/**************** Bit definition for DMA_CNDTR register *****************/
bogdanm	85:024bf7f99721	2601	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
bogdanm	85:024bf7f99721	2602
bogdanm	85:024bf7f99721	2603	/**************** Bit definition for DMA_CPAR register ******************/
bogdanm	85:024bf7f99721	2604	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
bogdanm	85:024bf7f99721	2605
bogdanm	85:024bf7f99721	2606	/**************** Bit definition for DMA_CMAR register ******************/
bogdanm	85:024bf7f99721	2607	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
bogdanm	85:024bf7f99721	2608
bogdanm	85:024bf7f99721	2609	/******************************************************************************/
bogdanm	85:024bf7f99721	2610	/* */
bogdanm	85:024bf7f99721	2611	/* External Interrupt/Event Controller (EXTI) */
bogdanm	85:024bf7f99721	2612	/* */
bogdanm	85:024bf7f99721	2613	/******************************************************************************/
bogdanm	85:024bf7f99721	2614	/***************** Bit definition for EXTI_IMR register *****************/
bogdanm	85:024bf7f99721	2615	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
bogdanm	85:024bf7f99721	2616	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
bogdanm	85:024bf7f99721	2617	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
bogdanm	85:024bf7f99721	2618	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
bogdanm	85:024bf7f99721	2619	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
bogdanm	85:024bf7f99721	2620	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
bogdanm	85:024bf7f99721	2621	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
bogdanm	85:024bf7f99721	2622	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
bogdanm	85:024bf7f99721	2623	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
bogdanm	85:024bf7f99721	2624	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
bogdanm	85:024bf7f99721	2625	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
bogdanm	85:024bf7f99721	2626	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
bogdanm	85:024bf7f99721	2627	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
bogdanm	85:024bf7f99721	2628	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
bogdanm	85:024bf7f99721	2629	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
bogdanm	85:024bf7f99721	2630	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
bogdanm	85:024bf7f99721	2631	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
bogdanm	85:024bf7f99721	2632	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
bogdanm	85:024bf7f99721	2633	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
bogdanm	85:024bf7f99721	2634	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
bogdanm	85:024bf7f99721	2635	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
bogdanm	85:024bf7f99721	2636	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
bogdanm	85:024bf7f99721	2637	#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
bogdanm	85:024bf7f99721	2638	#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
bogdanm	85:024bf7f99721	2639
bogdanm	85:024bf7f99721	2640	/**************** Bit definition for EXTI_EMR register ******************/
bogdanm	85:024bf7f99721	2641	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
bogdanm	85:024bf7f99721	2642	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
bogdanm	85:024bf7f99721	2643	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
bogdanm	85:024bf7f99721	2644	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
bogdanm	85:024bf7f99721	2645	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
bogdanm	85:024bf7f99721	2646	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
bogdanm	85:024bf7f99721	2647	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
bogdanm	85:024bf7f99721	2648	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
bogdanm	85:024bf7f99721	2649	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
bogdanm	85:024bf7f99721	2650	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
bogdanm	85:024bf7f99721	2651	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
bogdanm	85:024bf7f99721	2652	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
bogdanm	85:024bf7f99721	2653	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
bogdanm	85:024bf7f99721	2654	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
bogdanm	85:024bf7f99721	2655	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
bogdanm	85:024bf7f99721	2656	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
bogdanm	85:024bf7f99721	2657	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
bogdanm	85:024bf7f99721	2658	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
bogdanm	85:024bf7f99721	2659	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
bogdanm	85:024bf7f99721	2660	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
bogdanm	85:024bf7f99721	2661	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
bogdanm	85:024bf7f99721	2662	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
bogdanm	85:024bf7f99721	2663	#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
bogdanm	85:024bf7f99721	2664	#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
bogdanm	85:024bf7f99721	2665
bogdanm	85:024bf7f99721	2666	/***************** Bit definition for EXTI_RTSR register ****************/
bogdanm	85:024bf7f99721	2667	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
bogdanm	85:024bf7f99721	2668	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
bogdanm	85:024bf7f99721	2669	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
bogdanm	85:024bf7f99721	2670	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
bogdanm	85:024bf7f99721	2671	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
bogdanm	85:024bf7f99721	2672	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
bogdanm	85:024bf7f99721	2673	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
bogdanm	85:024bf7f99721	2674	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
bogdanm	85:024bf7f99721	2675	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
bogdanm	85:024bf7f99721	2676	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
bogdanm	85:024bf7f99721	2677	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
bogdanm	85:024bf7f99721	2678	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
bogdanm	85:024bf7f99721	2679	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
bogdanm	85:024bf7f99721	2680	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
bogdanm	85:024bf7f99721	2681	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
bogdanm	85:024bf7f99721	2682	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
bogdanm	85:024bf7f99721	2683	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
bogdanm	85:024bf7f99721	2684	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
bogdanm	85:024bf7f99721	2685	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
bogdanm	85:024bf7f99721	2686
bogdanm	85:024bf7f99721	2687	/***************** Bit definition for EXTI_FTSR register *****************/
bogdanm	85:024bf7f99721	2688	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
bogdanm	85:024bf7f99721	2689	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
bogdanm	85:024bf7f99721	2690	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
bogdanm	85:024bf7f99721	2691	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
bogdanm	85:024bf7f99721	2692	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
bogdanm	85:024bf7f99721	2693	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
bogdanm	85:024bf7f99721	2694	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
bogdanm	85:024bf7f99721	2695	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
bogdanm	85:024bf7f99721	2696	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
bogdanm	85:024bf7f99721	2697	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
bogdanm	85:024bf7f99721	2698	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
bogdanm	85:024bf7f99721	2699	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
bogdanm	85:024bf7f99721	2700	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
bogdanm	85:024bf7f99721	2701	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
bogdanm	85:024bf7f99721	2702	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
bogdanm	85:024bf7f99721	2703	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
bogdanm	85:024bf7f99721	2704	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
bogdanm	85:024bf7f99721	2705	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
bogdanm	85:024bf7f99721	2706	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
bogdanm	85:024bf7f99721	2707
bogdanm	85:024bf7f99721	2708	/***************** Bit definition for EXTI_SWIER register *****************/
bogdanm	85:024bf7f99721	2709	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
bogdanm	85:024bf7f99721	2710	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
bogdanm	85:024bf7f99721	2711	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
bogdanm	85:024bf7f99721	2712	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
bogdanm	85:024bf7f99721	2713	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
bogdanm	85:024bf7f99721	2714	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
bogdanm	85:024bf7f99721	2715	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
bogdanm	85:024bf7f99721	2716	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
bogdanm	85:024bf7f99721	2717	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
bogdanm	85:024bf7f99721	2718	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
bogdanm	85:024bf7f99721	2719	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
bogdanm	85:024bf7f99721	2720	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
bogdanm	85:024bf7f99721	2721	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
bogdanm	85:024bf7f99721	2722	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
bogdanm	85:024bf7f99721	2723	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
bogdanm	85:024bf7f99721	2724	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
bogdanm	85:024bf7f99721	2725	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
bogdanm	85:024bf7f99721	2726	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
bogdanm	85:024bf7f99721	2727	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
bogdanm	85:024bf7f99721	2728
bogdanm	85:024bf7f99721	2729	/**************** Bit definition for EXTI_PR register *******************/
bogdanm	85:024bf7f99721	2730	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
bogdanm	85:024bf7f99721	2731	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
bogdanm	85:024bf7f99721	2732	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
bogdanm	85:024bf7f99721	2733	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
bogdanm	85:024bf7f99721	2734	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
bogdanm	85:024bf7f99721	2735	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
bogdanm	85:024bf7f99721	2736	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
bogdanm	85:024bf7f99721	2737	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
bogdanm	85:024bf7f99721	2738	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
bogdanm	85:024bf7f99721	2739	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
bogdanm	85:024bf7f99721	2740	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
bogdanm	85:024bf7f99721	2741	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
bogdanm	85:024bf7f99721	2742	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
bogdanm	85:024bf7f99721	2743	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
bogdanm	85:024bf7f99721	2744	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
bogdanm	85:024bf7f99721	2745	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
bogdanm	85:024bf7f99721	2746	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
bogdanm	85:024bf7f99721	2747	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
bogdanm	85:024bf7f99721	2748	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
bogdanm	85:024bf7f99721	2749
bogdanm	85:024bf7f99721	2750	/******************************************************************************/
bogdanm	85:024bf7f99721	2751	/* */
bogdanm	85:024bf7f99721	2752	/* FLASH and Option Bytes Registers */
bogdanm	85:024bf7f99721	2753	/* */
bogdanm	85:024bf7f99721	2754	/******************************************************************************/
bogdanm	85:024bf7f99721	2755
bogdanm	85:024bf7f99721	2756	/***************** Bit definition for FLASH_ACR register ****************/
bogdanm	85:024bf7f99721	2757	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< LATENCY bit (Latency) /
bogdanm	85:024bf7f99721	2758
bogdanm	85:024bf7f99721	2759	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
bogdanm	85:024bf7f99721	2760	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
bogdanm	85:024bf7f99721	2761
bogdanm	85:024bf7f99721	2762	/**************** Bit definition for FLASH_KEYR register ****************/
bogdanm	85:024bf7f99721	2763	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
bogdanm	85:024bf7f99721	2764
bogdanm	85:024bf7f99721	2765	/*************** Bit definition for FLASH_OPTKEYR register **************/
bogdanm	85:024bf7f99721	2766	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
bogdanm	85:024bf7f99721	2767
bogdanm	85:024bf7f99721	2768	/**************** FLASH Keys ********************************************/
bogdanm	85:024bf7f99721	2769	#define FLASH_FKEY1 ((uint32_t)0x45670123) /!< Flash program erase key1 /
bogdanm	85:024bf7f99721	2770	#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
bogdanm	85:024bf7f99721	2771	to unlock the write access to the FPEC. */
bogdanm	85:024bf7f99721	2772
bogdanm	85:024bf7f99721	2773	#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /!< Flash option key1 /
bogdanm	85:024bf7f99721	2774	#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
bogdanm	85:024bf7f99721	2775	unlock the write access to the option byte block */
bogdanm	85:024bf7f99721	2776
bogdanm	85:024bf7f99721	2777	/**************** Bit definition for FLASH_SR register *****************/
bogdanm	85:024bf7f99721	2778	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
bogdanm	85:024bf7f99721	2779	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
bogdanm	85:024bf7f99721	2780	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
bogdanm	85:024bf7f99721	2781	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
bogdanm	85:024bf7f99721	2782	#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /!< Legacy of Write Protection Error /
bogdanm	85:024bf7f99721	2783
bogdanm	85:024bf7f99721	2784	/***************** Bit definition for FLASH_CR register *****************/
bogdanm	85:024bf7f99721	2785	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
bogdanm	85:024bf7f99721	2786	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
bogdanm	85:024bf7f99721	2787	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
bogdanm	85:024bf7f99721	2788	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
bogdanm	85:024bf7f99721	2789	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
bogdanm	85:024bf7f99721	2790	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
bogdanm	85:024bf7f99721	2791	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
bogdanm	85:024bf7f99721	2792	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
bogdanm	85:024bf7f99721	2793	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
bogdanm	85:024bf7f99721	2794	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
bogdanm	85:024bf7f99721	2795	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< Option Bytes Loader Launch /
bogdanm	85:024bf7f99721	2796
bogdanm	85:024bf7f99721	2797	/***************** Bit definition for FLASH_AR register *****************/
bogdanm	85:024bf7f99721	2798	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
bogdanm	85:024bf7f99721	2799
bogdanm	85:024bf7f99721	2800	/**************** Bit definition for FLASH_OBR register *****************/
bogdanm	85:024bf7f99721	2801	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
bogdanm	85:024bf7f99721	2802	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level 1 /
bogdanm	85:024bf7f99721	2803	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level 2 /
bogdanm	85:024bf7f99721	2804
bogdanm	85:024bf7f99721	2805	#define FLASH_OBR_USER ((uint32_t)0x00003700) /!< User Option Bytes /
bogdanm	85:024bf7f99721	2806	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
bogdanm	85:024bf7f99721	2807	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
bogdanm	85:024bf7f99721	2808	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
bogdanm	85:024bf7f99721	2809	#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /!< nBOOT1 /
bogdanm	85:024bf7f99721	2810	#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /!< VDDA power supply supervisor /
bogdanm	85:024bf7f99721	2811
bogdanm	85:024bf7f99721	2812	/* Old BOOT1 bit definition, maintained for legacy purpose */
bogdanm	85:024bf7f99721	2813	#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
bogdanm	85:024bf7f99721	2814
bogdanm	85:024bf7f99721	2815	/* Old OBR_VDDA bit definition, maintained for legacy purpose */
bogdanm	85:024bf7f99721	2816	#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
bogdanm	85:024bf7f99721	2817
bogdanm	85:024bf7f99721	2818	/**************** Bit definition for FLASH_WRPR register ****************/
bogdanm	85:024bf7f99721	2819	#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /!< Write Protect /
bogdanm	85:024bf7f99721	2820
bogdanm	85:024bf7f99721	2821	/----------------------------------------------------------------------------/
bogdanm	85:024bf7f99721	2822
bogdanm	85:024bf7f99721	2823	/**************** Bit definition for OB_RDP register ********************/
bogdanm	85:024bf7f99721	2824	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
bogdanm	85:024bf7f99721	2825	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
bogdanm	85:024bf7f99721	2826
bogdanm	85:024bf7f99721	2827	/**************** Bit definition for OB_USER register *******************/
bogdanm	85:024bf7f99721	2828	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
bogdanm	85:024bf7f99721	2829	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
bogdanm	85:024bf7f99721	2830
bogdanm	85:024bf7f99721	2831	/**************** Bit definition for OB_WRP0 register *******************/
bogdanm	85:024bf7f99721	2832	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
bogdanm	85:024bf7f99721	2833	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
bogdanm	85:024bf7f99721	2834
bogdanm	85:024bf7f99721	2835	/**************** Bit definition for OB_WRP1 register *******************/
bogdanm	85:024bf7f99721	2836	#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
bogdanm	85:024bf7f99721	2837	#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
bogdanm	85:024bf7f99721	2838
bogdanm	85:024bf7f99721	2839	/**************** Bit definition for OB_WRP2 register *******************/
bogdanm	85:024bf7f99721	2840	#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
bogdanm	85:024bf7f99721	2841	#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
bogdanm	85:024bf7f99721	2842
bogdanm	85:024bf7f99721	2843	/**************** Bit definition for OB_WRP3 register *******************/
bogdanm	85:024bf7f99721	2844	#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
bogdanm	85:024bf7f99721	2845	#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
bogdanm	85:024bf7f99721	2846
bogdanm	85:024bf7f99721	2847	/******************************************************************************/
bogdanm	85:024bf7f99721	2848	/* */
bogdanm	85:024bf7f99721	2849	/* General Purpose IOs (GPIO) */
bogdanm	85:024bf7f99721	2850	/* */
bogdanm	85:024bf7f99721	2851	/******************************************************************************/
bogdanm	85:024bf7f99721	2852	/***************** Bit definition for GPIO_MODER register ***************/
bogdanm	85:024bf7f99721	2853	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
bogdanm	85:024bf7f99721	2854	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	2855	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	2856	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
bogdanm	85:024bf7f99721	2857	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	2858	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	2859	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
bogdanm	85:024bf7f99721	2860	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	2861	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	2862	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
bogdanm	85:024bf7f99721	2863	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	2864	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	2865	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
bogdanm	85:024bf7f99721	2866	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	2867	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	2868	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
bogdanm	85:024bf7f99721	2869	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	2870	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	2871	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
bogdanm	85:024bf7f99721	2872	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	2873	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	2874	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
bogdanm	85:024bf7f99721	2875	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	2876	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	2877	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
bogdanm	85:024bf7f99721	2878	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	2879	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	2880	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
bogdanm	85:024bf7f99721	2881	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	2882	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
bogdanm	85:024bf7f99721	2883	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
bogdanm	85:024bf7f99721	2884	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
bogdanm	85:024bf7f99721	2885	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
bogdanm	85:024bf7f99721	2886	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
bogdanm	85:024bf7f99721	2887	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
bogdanm	85:024bf7f99721	2888	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
bogdanm	85:024bf7f99721	2889	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
bogdanm	85:024bf7f99721	2890	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
bogdanm	85:024bf7f99721	2891	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
bogdanm	85:024bf7f99721	2892	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
bogdanm	85:024bf7f99721	2893	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
bogdanm	85:024bf7f99721	2894	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
bogdanm	85:024bf7f99721	2895	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
bogdanm	85:024bf7f99721	2896	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
bogdanm	85:024bf7f99721	2897	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
bogdanm	85:024bf7f99721	2898	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
bogdanm	85:024bf7f99721	2899	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
bogdanm	85:024bf7f99721	2900	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
bogdanm	85:024bf7f99721	2901
bogdanm	85:024bf7f99721	2902	/**************** Bit definition for GPIO_OTYPER register ***************/
bogdanm	85:024bf7f99721	2903	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	2904	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	2905	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	2906	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	2907	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	2908	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	2909	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	2910	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	2911	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	2912	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	2913	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	2914	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	2915	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	2916	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	2917	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	2918	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	2919
bogdanm	85:024bf7f99721	2920	/************** Bit definition for GPIO_OSPEEDR register ****************/
bogdanm	85:024bf7f99721	2921	#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
bogdanm	85:024bf7f99721	2922	#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	2923	#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	2924	#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
bogdanm	85:024bf7f99721	2925	#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	2926	#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	2927	#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
bogdanm	85:024bf7f99721	2928	#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	2929	#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	2930	#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
bogdanm	85:024bf7f99721	2931	#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	2932	#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	2933	#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
bogdanm	85:024bf7f99721	2934	#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	2935	#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	2936	#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
bogdanm	85:024bf7f99721	2937	#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	2938	#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	2939	#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
bogdanm	85:024bf7f99721	2940	#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	2941	#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	2942	#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
bogdanm	85:024bf7f99721	2943	#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	2944	#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	2945	#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
bogdanm	85:024bf7f99721	2946	#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	2947	#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	2948	#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
bogdanm	85:024bf7f99721	2949	#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	2950	#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
bogdanm	85:024bf7f99721	2951	#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
bogdanm	85:024bf7f99721	2952	#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
bogdanm	85:024bf7f99721	2953	#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
bogdanm	85:024bf7f99721	2954	#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
bogdanm	85:024bf7f99721	2955	#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
bogdanm	85:024bf7f99721	2956	#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
bogdanm	85:024bf7f99721	2957	#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
bogdanm	85:024bf7f99721	2958	#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
bogdanm	85:024bf7f99721	2959	#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
bogdanm	85:024bf7f99721	2960	#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
bogdanm	85:024bf7f99721	2961	#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
bogdanm	85:024bf7f99721	2962	#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
bogdanm	85:024bf7f99721	2963	#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
bogdanm	85:024bf7f99721	2964	#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
bogdanm	85:024bf7f99721	2965	#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
bogdanm	85:024bf7f99721	2966	#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
bogdanm	85:024bf7f99721	2967	#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
bogdanm	85:024bf7f99721	2968	#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
bogdanm	85:024bf7f99721	2969
bogdanm	85:024bf7f99721	2970	/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
bogdanm	85:024bf7f99721	2971	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
bogdanm	85:024bf7f99721	2972	#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
bogdanm	85:024bf7f99721	2973	#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
bogdanm	85:024bf7f99721	2974	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
bogdanm	85:024bf7f99721	2975	#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
bogdanm	85:024bf7f99721	2976	#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
bogdanm	85:024bf7f99721	2977	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
bogdanm	85:024bf7f99721	2978	#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
bogdanm	85:024bf7f99721	2979	#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
bogdanm	85:024bf7f99721	2980	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
bogdanm	85:024bf7f99721	2981	#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
bogdanm	85:024bf7f99721	2982	#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
bogdanm	85:024bf7f99721	2983	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
bogdanm	85:024bf7f99721	2984	#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
bogdanm	85:024bf7f99721	2985	#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
bogdanm	85:024bf7f99721	2986	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
bogdanm	85:024bf7f99721	2987	#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
bogdanm	85:024bf7f99721	2988	#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
bogdanm	85:024bf7f99721	2989	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
bogdanm	85:024bf7f99721	2990	#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
bogdanm	85:024bf7f99721	2991	#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
bogdanm	85:024bf7f99721	2992	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
bogdanm	85:024bf7f99721	2993	#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
bogdanm	85:024bf7f99721	2994	#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
bogdanm	85:024bf7f99721	2995	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
bogdanm	85:024bf7f99721	2996	#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
bogdanm	85:024bf7f99721	2997	#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
bogdanm	85:024bf7f99721	2998	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
bogdanm	85:024bf7f99721	2999	#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
bogdanm	85:024bf7f99721	3000	#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
bogdanm	85:024bf7f99721	3001	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
bogdanm	85:024bf7f99721	3002	#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
bogdanm	85:024bf7f99721	3003	#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
bogdanm	85:024bf7f99721	3004	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
bogdanm	85:024bf7f99721	3005	#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
bogdanm	85:024bf7f99721	3006	#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
bogdanm	85:024bf7f99721	3007	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
bogdanm	85:024bf7f99721	3008	#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
bogdanm	85:024bf7f99721	3009	#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
bogdanm	85:024bf7f99721	3010	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
bogdanm	85:024bf7f99721	3011	#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
bogdanm	85:024bf7f99721	3012	#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
bogdanm	85:024bf7f99721	3013	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
bogdanm	85:024bf7f99721	3014	#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
bogdanm	85:024bf7f99721	3015	#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
bogdanm	85:024bf7f99721	3016	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
bogdanm	85:024bf7f99721	3017	#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
bogdanm	85:024bf7f99721	3018	#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
bogdanm	85:024bf7f99721	3019
bogdanm	85:024bf7f99721	3020	/***************** Bit definition for GPIO_PUPDR register ****************/
bogdanm	85:024bf7f99721	3021	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
bogdanm	85:024bf7f99721	3022	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3023	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3024	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
bogdanm	85:024bf7f99721	3025	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3026	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3027	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
bogdanm	85:024bf7f99721	3028	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3029	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3030	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
bogdanm	85:024bf7f99721	3031	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3032	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	3033	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
bogdanm	85:024bf7f99721	3034	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3035	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3036	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
bogdanm	85:024bf7f99721	3037	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3038	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3039	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
bogdanm	85:024bf7f99721	3040	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3041	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3042	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
bogdanm	85:024bf7f99721	3043	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3044	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3045	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
bogdanm	85:024bf7f99721	3046	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	3047	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	3048	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
bogdanm	85:024bf7f99721	3049	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	3050	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
bogdanm	85:024bf7f99721	3051	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
bogdanm	85:024bf7f99721	3052	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
bogdanm	85:024bf7f99721	3053	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
bogdanm	85:024bf7f99721	3054	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
bogdanm	85:024bf7f99721	3055	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
bogdanm	85:024bf7f99721	3056	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
bogdanm	85:024bf7f99721	3057	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
bogdanm	85:024bf7f99721	3058	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
bogdanm	85:024bf7f99721	3059	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
bogdanm	85:024bf7f99721	3060	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
bogdanm	85:024bf7f99721	3061	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
bogdanm	85:024bf7f99721	3062	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
bogdanm	85:024bf7f99721	3063	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
bogdanm	85:024bf7f99721	3064	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
bogdanm	85:024bf7f99721	3065	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
bogdanm	85:024bf7f99721	3066	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
bogdanm	85:024bf7f99721	3067	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
bogdanm	85:024bf7f99721	3068	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
bogdanm	85:024bf7f99721	3069
bogdanm	85:024bf7f99721	3070	/***************** Bit definition for GPIO_IDR register *****************/
bogdanm	85:024bf7f99721	3071	#define GPIO_IDR_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3072	#define GPIO_IDR_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3073	#define GPIO_IDR_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3074	#define GPIO_IDR_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3075	#define GPIO_IDR_4 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3076	#define GPIO_IDR_5 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3077	#define GPIO_IDR_6 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3078	#define GPIO_IDR_7 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	3079	#define GPIO_IDR_8 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3080	#define GPIO_IDR_9 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3081	#define GPIO_IDR_10 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3082	#define GPIO_IDR_11 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3083	#define GPIO_IDR_12 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3084	#define GPIO_IDR_13 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3085	#define GPIO_IDR_14 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3086	#define GPIO_IDR_15 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3087
bogdanm	85:024bf7f99721	3088	/**************** Bit definition for GPIO_ODR register ******************/
bogdanm	85:024bf7f99721	3089	#define GPIO_ODR_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3090	#define GPIO_ODR_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3091	#define GPIO_ODR_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3092	#define GPIO_ODR_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3093	#define GPIO_ODR_4 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3094	#define GPIO_ODR_5 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3095	#define GPIO_ODR_6 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3096	#define GPIO_ODR_7 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	3097	#define GPIO_ODR_8 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3098	#define GPIO_ODR_9 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3099	#define GPIO_ODR_10 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3100	#define GPIO_ODR_11 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3101	#define GPIO_ODR_12 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3102	#define GPIO_ODR_13 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3103	#define GPIO_ODR_14 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3104	#define GPIO_ODR_15 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3105
bogdanm	85:024bf7f99721	3106	/**************** Bit definition for GPIO_BSRR register ******************/
bogdanm	85:024bf7f99721	3107	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3108	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3109	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3110	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3111	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3112	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3113	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3114	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	3115	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3116	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3117	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3118	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3119	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3120	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3121	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3122	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3123	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	3124	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	3125	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	3126	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
bogdanm	85:024bf7f99721	3127	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
bogdanm	85:024bf7f99721	3128	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
bogdanm	85:024bf7f99721	3129	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
bogdanm	85:024bf7f99721	3130	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
bogdanm	85:024bf7f99721	3131	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
bogdanm	85:024bf7f99721	3132	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
bogdanm	85:024bf7f99721	3133	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
bogdanm	85:024bf7f99721	3134	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
bogdanm	85:024bf7f99721	3135	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
bogdanm	85:024bf7f99721	3136	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
bogdanm	85:024bf7f99721	3137	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
bogdanm	85:024bf7f99721	3138	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
bogdanm	85:024bf7f99721	3139
bogdanm	85:024bf7f99721	3140	/**************** Bit definition for GPIO_LCKR register ******************/
bogdanm	85:024bf7f99721	3141	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3142	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3143	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3144	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3145	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3146	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3147	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3148	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	3149	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3150	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3151	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3152	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3153	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3154	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3155	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3156	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3157	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	3158
bogdanm	85:024bf7f99721	3159	/**************** Bit definition for GPIO_AFRL register ******************/
bogdanm	85:024bf7f99721	3160	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
bogdanm	85:024bf7f99721	3161	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
bogdanm	85:024bf7f99721	3162	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
bogdanm	85:024bf7f99721	3163	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
bogdanm	85:024bf7f99721	3164	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
bogdanm	85:024bf7f99721	3165	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
bogdanm	85:024bf7f99721	3166	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
bogdanm	85:024bf7f99721	3167	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
bogdanm	85:024bf7f99721	3168
bogdanm	85:024bf7f99721	3169	/**************** Bit definition for GPIO_AFRH register ******************/
bogdanm	85:024bf7f99721	3170	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
bogdanm	85:024bf7f99721	3171	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
bogdanm	85:024bf7f99721	3172	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
bogdanm	85:024bf7f99721	3173	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
bogdanm	85:024bf7f99721	3174	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
bogdanm	85:024bf7f99721	3175	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
bogdanm	85:024bf7f99721	3176	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
bogdanm	85:024bf7f99721	3177	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
bogdanm	85:024bf7f99721	3178
bogdanm	85:024bf7f99721	3179	/**************** Bit definition for GPIO_BRR register *******************/
bogdanm	85:024bf7f99721	3180	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3181	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3182	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3183	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3184	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3185	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3186	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3187	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	3188	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3189	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3190	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3191	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3192	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3193	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3194	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3195	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3196
bogdanm	85:024bf7f99721	3197	/******************************************************************************/
bogdanm	85:024bf7f99721	3198	/* */
bogdanm	85:024bf7f99721	3199	/* Inter-integrated Circuit Interface (I2C) */
bogdanm	85:024bf7f99721	3200	/* */
bogdanm	85:024bf7f99721	3201	/******************************************************************************/
bogdanm	85:024bf7f99721	3202
bogdanm	85:024bf7f99721	3203	/***************** Bit definition for I2C_CR1 register *****************/
bogdanm	85:024bf7f99721	3204	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
bogdanm	85:024bf7f99721	3205	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
bogdanm	85:024bf7f99721	3206	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
bogdanm	85:024bf7f99721	3207	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
bogdanm	85:024bf7f99721	3208	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
bogdanm	85:024bf7f99721	3209	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
bogdanm	85:024bf7f99721	3210	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
bogdanm	85:024bf7f99721	3211	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
bogdanm	85:024bf7f99721	3212	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
bogdanm	85:024bf7f99721	3213	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
bogdanm	85:024bf7f99721	3214	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
bogdanm	85:024bf7f99721	3215	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
bogdanm	85:024bf7f99721	3216	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
bogdanm	85:024bf7f99721	3217	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
bogdanm	85:024bf7f99721	3218	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
bogdanm	85:024bf7f99721	3219	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
bogdanm	85:024bf7f99721	3220	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
bogdanm	85:024bf7f99721	3221	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
bogdanm	85:024bf7f99721	3222	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
bogdanm	85:024bf7f99721	3223	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
bogdanm	85:024bf7f99721	3224	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
bogdanm	85:024bf7f99721	3225
bogdanm	85:024bf7f99721	3226	/**************** Bit definition for I2C_CR2 register ******************/
bogdanm	85:024bf7f99721	3227	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
bogdanm	85:024bf7f99721	3228	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
bogdanm	85:024bf7f99721	3229	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
bogdanm	85:024bf7f99721	3230	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
bogdanm	85:024bf7f99721	3231	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
bogdanm	85:024bf7f99721	3232	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
bogdanm	85:024bf7f99721	3233	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
bogdanm	85:024bf7f99721	3234	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
bogdanm	85:024bf7f99721	3235	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
bogdanm	85:024bf7f99721	3236	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
bogdanm	85:024bf7f99721	3237	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
bogdanm	85:024bf7f99721	3238
bogdanm	85:024bf7f99721	3239	/***************** Bit definition for I2C_OAR1 register ****************/
bogdanm	85:024bf7f99721	3240	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
bogdanm	85:024bf7f99721	3241	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
bogdanm	85:024bf7f99721	3242	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
bogdanm	85:024bf7f99721	3243
bogdanm	85:024bf7f99721	3244	/***************** Bit definition for I2C_OAR2 register ****************/
bogdanm	85:024bf7f99721	3245	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
bogdanm	85:024bf7f99721	3246	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
bogdanm	85:024bf7f99721	3247	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
bogdanm	85:024bf7f99721	3248
bogdanm	85:024bf7f99721	3249	/***************** Bit definition for I2C_TIMINGR register **************/
bogdanm	85:024bf7f99721	3250	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
bogdanm	85:024bf7f99721	3251	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
bogdanm	85:024bf7f99721	3252	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
bogdanm	85:024bf7f99721	3253	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
bogdanm	85:024bf7f99721	3254	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
bogdanm	85:024bf7f99721	3255
bogdanm	85:024bf7f99721	3256	/***************** Bit definition for I2C_TIMEOUTR register **************/
bogdanm	85:024bf7f99721	3257	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
bogdanm	85:024bf7f99721	3258	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
bogdanm	85:024bf7f99721	3259	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
bogdanm	85:024bf7f99721	3260	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
bogdanm	85:024bf7f99721	3261	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
bogdanm	85:024bf7f99721	3262
bogdanm	85:024bf7f99721	3263	/**************** Bit definition for I2C_ISR register ******************/
bogdanm	85:024bf7f99721	3264	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
bogdanm	85:024bf7f99721	3265	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
bogdanm	85:024bf7f99721	3266	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
bogdanm	85:024bf7f99721	3267	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
bogdanm	85:024bf7f99721	3268	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
bogdanm	85:024bf7f99721	3269	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
bogdanm	85:024bf7f99721	3270	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
bogdanm	85:024bf7f99721	3271	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
bogdanm	85:024bf7f99721	3272	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
bogdanm	85:024bf7f99721	3273	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
bogdanm	85:024bf7f99721	3274	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
bogdanm	85:024bf7f99721	3275	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
bogdanm	85:024bf7f99721	3276	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
bogdanm	85:024bf7f99721	3277	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
bogdanm	85:024bf7f99721	3278	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
bogdanm	85:024bf7f99721	3279	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
bogdanm	85:024bf7f99721	3280	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
bogdanm	85:024bf7f99721	3281
bogdanm	85:024bf7f99721	3282	/**************** Bit definition for I2C_ICR register ******************/
bogdanm	85:024bf7f99721	3283	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
bogdanm	85:024bf7f99721	3284	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
bogdanm	85:024bf7f99721	3285	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
bogdanm	85:024bf7f99721	3286	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
bogdanm	85:024bf7f99721	3287	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
bogdanm	85:024bf7f99721	3288	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
bogdanm	85:024bf7f99721	3289	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
bogdanm	85:024bf7f99721	3290	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
bogdanm	85:024bf7f99721	3291	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
bogdanm	85:024bf7f99721	3292
bogdanm	85:024bf7f99721	3293	/**************** Bit definition for I2C_PECR register *****************/
bogdanm	85:024bf7f99721	3294	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
bogdanm	85:024bf7f99721	3295
bogdanm	85:024bf7f99721	3296	/**************** Bit definition for I2C_RXDR register *******************/
bogdanm	85:024bf7f99721	3297	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
bogdanm	85:024bf7f99721	3298
bogdanm	85:024bf7f99721	3299	/**************** Bit definition for I2C_TXDR register *****************/
bogdanm	85:024bf7f99721	3300	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
bogdanm	85:024bf7f99721	3301
bogdanm	85:024bf7f99721	3302	/*****************************************************************************/
bogdanm	85:024bf7f99721	3303	/* */
bogdanm	85:024bf7f99721	3304	/* Independent WATCHDOG (IWDG) */
bogdanm	85:024bf7f99721	3305	/* */
bogdanm	85:024bf7f99721	3306	/*****************************************************************************/
bogdanm	85:024bf7f99721	3307	/***************** Bit definition for IWDG_KR register *****************/
bogdanm	85:024bf7f99721	3308	#define IWDG_KR_KEY ((uint32_t)0xFFFF) /!< Key value (write only, read 0000h) /
bogdanm	85:024bf7f99721	3309
bogdanm	85:024bf7f99721	3310	/***************** Bit definition for IWDG_PR register *****************/
bogdanm	85:024bf7f99721	3311	#define IWDG_PR_PR ((uint32_t)0x07) /!< PR[2:0] (Prescaler divider) /
bogdanm	85:024bf7f99721	3312	#define IWDG_PR_PR_0 ((uint32_t)0x01) /!< Bit 0 /
bogdanm	85:024bf7f99721	3313	#define IWDG_PR_PR_1 ((uint32_t)0x02) /!< Bit 1 /
bogdanm	85:024bf7f99721	3314	#define IWDG_PR_PR_2 ((uint32_t)0x04) /!< Bit 2 /
bogdanm	85:024bf7f99721	3315
bogdanm	85:024bf7f99721	3316	/***************** Bit definition for IWDG_RLR register ****************/
bogdanm	85:024bf7f99721	3317	#define IWDG_RLR_RL ((uint32_t)0x0FFF) /!< Watchdog counter reload value /
bogdanm	85:024bf7f99721	3318
bogdanm	85:024bf7f99721	3319	/***************** Bit definition for IWDG_SR register *****************/
bogdanm	85:024bf7f99721	3320	#define IWDG_SR_PVU ((uint32_t)0x01) /!< Watchdog prescaler value update /
bogdanm	85:024bf7f99721	3321	#define IWDG_SR_RVU ((uint32_t)0x02) /!< Watchdog counter reload value update /
bogdanm	85:024bf7f99721	3322	#define IWDG_SR_WVU ((uint32_t)0x04) /!< Watchdog counter window value update /
bogdanm	85:024bf7f99721	3323
bogdanm	85:024bf7f99721	3324	/***************** Bit definition for IWDG_KR register *****************/
bogdanm	85:024bf7f99721	3325	#define IWDG_WINR_WIN ((uint32_t)0x0FFF) /!< Watchdog counter window value /
bogdanm	85:024bf7f99721	3326
bogdanm	85:024bf7f99721	3327	/*****************************************************************************/
bogdanm	85:024bf7f99721	3328	/* */
bogdanm	85:024bf7f99721	3329	/* Power Control (PWR) */
bogdanm	85:024bf7f99721	3330	/* */
bogdanm	85:024bf7f99721	3331	/*****************************************************************************/
bogdanm	85:024bf7f99721	3332
bogdanm	85:024bf7f99721	3333	/****************** Bit definition for PWR_CR register *****************/
bogdanm	85:024bf7f99721	3334	#define PWR_CR_LPDS ((uint32_t)0x00000001) /!< Low-power Deepsleep /
bogdanm	85:024bf7f99721	3335	#define PWR_CR_PDDS ((uint32_t)0x00000002) /!< Power Down Deepsleep /
bogdanm	85:024bf7f99721	3336	#define PWR_CR_CWUF ((uint32_t)0x00000004) /!< Clear Wakeup Flag /
bogdanm	85:024bf7f99721	3337	#define PWR_CR_CSBF ((uint32_t)0x00000008) /!< Clear Standby Flag /
bogdanm	85:024bf7f99721	3338	#define PWR_CR_PVDE ((uint32_t)0x00000010) /!< Power Voltage Detector Enable /
bogdanm	85:024bf7f99721	3339
bogdanm	85:024bf7f99721	3340	#define PWR_CR_PLS ((uint32_t)0x000000E0) /!< PLS[2:0] bits (PVD Level Selection) /
bogdanm	85:024bf7f99721	3341	#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /!< Bit 0 /
bogdanm	85:024bf7f99721	3342	#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /!< Bit 1 /
bogdanm	85:024bf7f99721	3343	#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /!< Bit 2 /
bogdanm	85:024bf7f99721	3344
bogdanm	85:024bf7f99721	3345	/!< PVD level configuration /
bogdanm	85:024bf7f99721	3346	#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /!< PVD level 0 /
bogdanm	85:024bf7f99721	3347	#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /!< PVD level 1 /
bogdanm	85:024bf7f99721	3348	#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /!< PVD level 2 /
bogdanm	85:024bf7f99721	3349	#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /!< PVD level 3 /
bogdanm	85:024bf7f99721	3350	#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /!< PVD level 4 /
bogdanm	85:024bf7f99721	3351	#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /!< PVD level 5 /
bogdanm	85:024bf7f99721	3352	#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /!< PVD level 6 /
bogdanm	85:024bf7f99721	3353	#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /!< PVD level 7 /
bogdanm	85:024bf7f99721	3354
bogdanm	85:024bf7f99721	3355	#define PWR_CR_DBP ((uint32_t)0x00000100) /!< Disable Backup Domain write protection /
bogdanm	85:024bf7f99721	3356
bogdanm	85:024bf7f99721	3357	/***************** Bit definition for PWR_CSR register *****************/
bogdanm	85:024bf7f99721	3358	#define PWR_CSR_WUF ((uint32_t)0x00000001) /!< Wakeup Flag /
bogdanm	85:024bf7f99721	3359	#define PWR_CSR_SBF ((uint32_t)0x00000002) /!< Standby Flag /
bogdanm	85:024bf7f99721	3360	#define PWR_CSR_PVDO ((uint32_t)0x00000004) /!< PVD Output /
bogdanm	85:024bf7f99721	3361	#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /!< Internal voltage reference (VREFINT) ready flag /
bogdanm	85:024bf7f99721	3362
bogdanm	85:024bf7f99721	3363	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /!< Enable WKUP pin 1 /
bogdanm	85:024bf7f99721	3364	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /!< Enable WKUP pin 2 /
bogdanm	85:024bf7f99721	3365	#define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /!< Enable WKUP pin 3 /
bogdanm	85:024bf7f99721	3366	#define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /!< Enable WKUP pin 4 /
bogdanm	85:024bf7f99721	3367	#define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /!< Enable WKUP pin 5 /
bogdanm	85:024bf7f99721	3368	#define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /!< Enable WKUP pin 6 /
bogdanm	85:024bf7f99721	3369	#define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /!< Enable WKUP pin 7 /
bogdanm	85:024bf7f99721	3370	#define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /!< Enable WKUP pin 8 /
bogdanm	85:024bf7f99721	3371
bogdanm	85:024bf7f99721	3372	/*****************************************************************************/
bogdanm	85:024bf7f99721	3373	/* */
bogdanm	85:024bf7f99721	3374	/* Reset and Clock Control */
bogdanm	85:024bf7f99721	3375	/* */
bogdanm	85:024bf7f99721	3376	/*****************************************************************************/
bogdanm	85:024bf7f99721	3377
bogdanm	85:024bf7f99721	3378	/****************** Bit definition for RCC_CR register *****************/
bogdanm	85:024bf7f99721	3379	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
bogdanm	85:024bf7f99721	3380	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
bogdanm	85:024bf7f99721	3381
bogdanm	85:024bf7f99721	3382	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
bogdanm	85:024bf7f99721	3383	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /!<Bit 0 /
bogdanm	85:024bf7f99721	3384	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /!<Bit 1 /
bogdanm	85:024bf7f99721	3385	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /!<Bit 2 /
bogdanm	85:024bf7f99721	3386	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /!<Bit 3 /
bogdanm	85:024bf7f99721	3387	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /!<Bit 4 /
bogdanm	85:024bf7f99721	3388
bogdanm	85:024bf7f99721	3389	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
bogdanm	85:024bf7f99721	3390	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	85:024bf7f99721	3391	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	85:024bf7f99721	3392	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	85:024bf7f99721	3393	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	85:024bf7f99721	3394	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	85:024bf7f99721	3395	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /!<Bit 5 /
bogdanm	85:024bf7f99721	3396	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /!<Bit 6 /
bogdanm	85:024bf7f99721	3397	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /!<Bit 7 /
bogdanm	85:024bf7f99721	3398
bogdanm	85:024bf7f99721	3399	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
bogdanm	85:024bf7f99721	3400	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
bogdanm	85:024bf7f99721	3401	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
bogdanm	85:024bf7f99721	3402	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
bogdanm	85:024bf7f99721	3403	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
bogdanm	85:024bf7f99721	3404	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
bogdanm	85:024bf7f99721	3405
bogdanm	85:024bf7f99721	3406	/****************** Bit definition for RCC_CFGR register ***************/
bogdanm	85:024bf7f99721	3407	/!< SW configuration /
bogdanm	85:024bf7f99721	3408	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
bogdanm	85:024bf7f99721	3409	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	85:024bf7f99721	3410	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	85:024bf7f99721	3411
bogdanm	85:024bf7f99721	3412	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
bogdanm	85:024bf7f99721	3413	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
bogdanm	85:024bf7f99721	3414	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
bogdanm	85:024bf7f99721	3415	#define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /!< HSI48 selected as system clock /
bogdanm	85:024bf7f99721	3416
bogdanm	85:024bf7f99721	3417	/!< SWS configuration /
bogdanm	85:024bf7f99721	3418	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
bogdanm	85:024bf7f99721	3419	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
bogdanm	85:024bf7f99721	3420	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
bogdanm	85:024bf7f99721	3421
bogdanm	85:024bf7f99721	3422	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
bogdanm	85:024bf7f99721	3423	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
bogdanm	85:024bf7f99721	3424	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
bogdanm	85:024bf7f99721	3425	#define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /!< HSI48 oscillator used as system clock /
bogdanm	85:024bf7f99721	3426
bogdanm	85:024bf7f99721	3427	/!< HPRE configuration /
bogdanm	85:024bf7f99721	3428	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
bogdanm	85:024bf7f99721	3429	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
bogdanm	85:024bf7f99721	3430	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
bogdanm	85:024bf7f99721	3431	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
bogdanm	85:024bf7f99721	3432	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
bogdanm	85:024bf7f99721	3433
bogdanm	85:024bf7f99721	3434	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
bogdanm	85:024bf7f99721	3435	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
bogdanm	85:024bf7f99721	3436	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
bogdanm	85:024bf7f99721	3437	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
bogdanm	85:024bf7f99721	3438	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
bogdanm	85:024bf7f99721	3439	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
bogdanm	85:024bf7f99721	3440	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
bogdanm	85:024bf7f99721	3441	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
bogdanm	85:024bf7f99721	3442	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
bogdanm	85:024bf7f99721	3443
bogdanm	85:024bf7f99721	3444	/!< PPRE configuration /
bogdanm	85:024bf7f99721	3445	#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /!< PRE[2:0] bits (APB prescaler) /
bogdanm	85:024bf7f99721	3446	#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	85:024bf7f99721	3447	#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	85:024bf7f99721	3448	#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	85:024bf7f99721	3449
bogdanm	85:024bf7f99721	3450	#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
bogdanm	85:024bf7f99721	3451	#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
bogdanm	85:024bf7f99721	3452	#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
bogdanm	85:024bf7f99721	3453	#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
bogdanm	85:024bf7f99721	3454	#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
bogdanm	85:024bf7f99721	3455
bogdanm	85:024bf7f99721	3456	/!< ADCPPRE configuration /
bogdanm	85:024bf7f99721	3457	#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /!< ADCPRE bit (ADC prescaler) /
bogdanm	85:024bf7f99721	3458
bogdanm	85:024bf7f99721	3459	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK divided by 2 /
bogdanm	85:024bf7f99721	3460	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK divided by 4 /
bogdanm	85:024bf7f99721	3461
bogdanm	85:024bf7f99721	3462	#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /!< PLL entry clock source /
bogdanm	85:024bf7f99721	3463	#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
bogdanm	85:024bf7f99721	3464	#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /!< HSI/PREDIV clock selected as PLL entry clock source /
bogdanm	85:024bf7f99721	3465	#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /!< HSE/PREDIV clock selected as PLL entry clock source /
bogdanm	85:024bf7f99721	3466	#define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /!< HSI48/PREDIV clock selected as PLL entry clock source /
bogdanm	85:024bf7f99721	3467
bogdanm	85:024bf7f99721	3468	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
bogdanm	85:024bf7f99721	3469	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /!< HSE/PREDIV clock not divided for PLL entry /
bogdanm	85:024bf7f99721	3470	#define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /!< HSE/PREDIV clock divided by 2 for PLL entry /
bogdanm	85:024bf7f99721	3471
bogdanm	85:024bf7f99721	3472	/!< PLLMUL configuration /
bogdanm	85:024bf7f99721	3473	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
bogdanm	85:024bf7f99721	3474	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
bogdanm	85:024bf7f99721	3475	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
bogdanm	85:024bf7f99721	3476	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
bogdanm	85:024bf7f99721	3477	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
bogdanm	85:024bf7f99721	3478
bogdanm	85:024bf7f99721	3479	#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
bogdanm	85:024bf7f99721	3480	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
bogdanm	85:024bf7f99721	3481	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
bogdanm	85:024bf7f99721	3482	#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
bogdanm	85:024bf7f99721	3483	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
bogdanm	85:024bf7f99721	3484	#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
bogdanm	85:024bf7f99721	3485	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
bogdanm	85:024bf7f99721	3486	#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
bogdanm	85:024bf7f99721	3487	#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
bogdanm	85:024bf7f99721	3488	#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
bogdanm	85:024bf7f99721	3489	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
bogdanm	85:024bf7f99721	3490	#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
bogdanm	85:024bf7f99721	3491	#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
bogdanm	85:024bf7f99721	3492	#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
bogdanm	85:024bf7f99721	3493	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
bogdanm	85:024bf7f99721	3494
bogdanm	85:024bf7f99721	3495	/!< USB configuration /
bogdanm	85:024bf7f99721	3496	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB prescaler /
bogdanm	85:024bf7f99721	3497
bogdanm	85:024bf7f99721	3498	/!< MCO configuration /
bogdanm	85:024bf7f99721	3499	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[3:0] bits (Microcontroller Clock Output) /
bogdanm	85:024bf7f99721	3500	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
bogdanm	85:024bf7f99721	3501	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
bogdanm	85:024bf7f99721	3502	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
bogdanm	85:024bf7f99721	3503	#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /!< Bit 3 /
bogdanm	85:024bf7f99721	3504
bogdanm	85:024bf7f99721	3505	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
bogdanm	85:024bf7f99721	3506	#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /!< HSI14 clock selected as MCO source /
bogdanm	85:024bf7f99721	3507	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
bogdanm	85:024bf7f99721	3508	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
bogdanm	85:024bf7f99721	3509	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
bogdanm	85:024bf7f99721	3510	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
bogdanm	85:024bf7f99721	3511	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
bogdanm	85:024bf7f99721	3512	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
bogdanm	85:024bf7f99721	3513	#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /!< HSI48 clock selected as MCO source /
bogdanm	85:024bf7f99721	3514
bogdanm	85:024bf7f99721	3515	#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /!< MCO prescaler /
bogdanm	85:024bf7f99721	3516	#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /!< MCO is divided by 1 /
bogdanm	85:024bf7f99721	3517	#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /!< MCO is divided by 2 /
bogdanm	85:024bf7f99721	3518	#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /!< MCO is divided by 4 /
bogdanm	85:024bf7f99721	3519	#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /!< MCO is divided by 8 /
bogdanm	85:024bf7f99721	3520	#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /!< MCO is divided by 16 /
bogdanm	85:024bf7f99721	3521	#define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /!< MCO is divided by 32 /
bogdanm	85:024bf7f99721	3522	#define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /!< MCO is divided by 64 /
bogdanm	85:024bf7f99721	3523	#define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /!< MCO is divided by 128 /
bogdanm	85:024bf7f99721	3524
bogdanm	85:024bf7f99721	3525	#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /!< PLL is not divided to MCO /
bogdanm	85:024bf7f99721	3526
bogdanm	85:024bf7f99721	3527	/!<*************** Bit definition for RCC_CIR register ***************/
bogdanm	85:024bf7f99721	3528	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
bogdanm	85:024bf7f99721	3529	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
bogdanm	85:024bf7f99721	3530	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
bogdanm	85:024bf7f99721	3531	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
bogdanm	85:024bf7f99721	3532	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
bogdanm	85:024bf7f99721	3533	#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /!< HSI14 Ready Interrupt flag /
bogdanm	85:024bf7f99721	3534	#define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /!< HSI48 Ready Interrupt flag /
bogdanm	85:024bf7f99721	3535	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
bogdanm	85:024bf7f99721	3536	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
bogdanm	85:024bf7f99721	3537	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
bogdanm	85:024bf7f99721	3538	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
bogdanm	85:024bf7f99721	3539	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
bogdanm	85:024bf7f99721	3540	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
bogdanm	85:024bf7f99721	3541	#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /!< HSI14 Ready Interrupt Enable /
bogdanm	85:024bf7f99721	3542	#define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /!< HSI48 Ready Interrupt Enable /
bogdanm	85:024bf7f99721	3543	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
bogdanm	85:024bf7f99721	3544	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
bogdanm	85:024bf7f99721	3545	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
bogdanm	85:024bf7f99721	3546	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
bogdanm	85:024bf7f99721	3547	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
bogdanm	85:024bf7f99721	3548	#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /!< HSI14 Ready Interrupt Clear /
bogdanm	85:024bf7f99721	3549	#define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /!< HSI48 Ready Interrupt Clear /
bogdanm	85:024bf7f99721	3550	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
bogdanm	85:024bf7f99721	3551
bogdanm	85:024bf7f99721	3552	/*************** Bit definition for RCC_APB2RSTR register **************/
bogdanm	85:024bf7f99721	3553	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG clock reset /
bogdanm	85:024bf7f99721	3554	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /!< ADC clock reset /
bogdanm	85:024bf7f99721	3555	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 clock reset /
bogdanm	85:024bf7f99721	3556	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 clock reset /
bogdanm	85:024bf7f99721	3557	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 clock reset /
bogdanm	85:024bf7f99721	3558	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 clock reset /
bogdanm	85:024bf7f99721	3559	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 clock reset /
bogdanm	85:024bf7f99721	3560	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 clock reset /
bogdanm	85:024bf7f99721	3561	#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /!< DBGMCU clock reset /
bogdanm	85:024bf7f99721	3562
bogdanm	85:024bf7f99721	3563	/!< Old ADC1 clock reset bit definition maintained for legacy purpose /
bogdanm	85:024bf7f99721	3564	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
bogdanm	85:024bf7f99721	3565
bogdanm	85:024bf7f99721	3566	/*************** Bit definition for RCC_APB1RSTR register **************/
bogdanm	85:024bf7f99721	3567	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 clock reset /
bogdanm	85:024bf7f99721	3568	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 clock reset /
bogdanm	85:024bf7f99721	3569	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 clock reset /
bogdanm	85:024bf7f99721	3570	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 clock reset /
bogdanm	85:024bf7f99721	3571	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< Timer 14 clock reset /
bogdanm	85:024bf7f99721	3572	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog clock reset /
bogdanm	85:024bf7f99721	3573	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI2 clock reset /
bogdanm	85:024bf7f99721	3574	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 clock reset /
bogdanm	85:024bf7f99721	3575	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 clock reset /
bogdanm	85:024bf7f99721	3576	#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /!< USART 4 clock reset /
bogdanm	85:024bf7f99721	3577	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 clock reset /
bogdanm	85:024bf7f99721	3578	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 clock reset /
bogdanm	85:024bf7f99721	3579	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB clock reset /
bogdanm	85:024bf7f99721	3580	#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /!< CAN clock reset /
bogdanm	85:024bf7f99721	3581	#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /!< CRS clock reset /
bogdanm	85:024bf7f99721	3582	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR clock reset /
bogdanm	85:024bf7f99721	3583	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC clock reset /
bogdanm	85:024bf7f99721	3584	#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /!< CEC clock reset /
bogdanm	85:024bf7f99721	3585
bogdanm	85:024bf7f99721	3586	/**************** Bit definition for RCC_AHBENR register ***************/
bogdanm	85:024bf7f99721	3587	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /!< DMA1 clock enable /
bogdanm	85:024bf7f99721	3588	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
bogdanm	85:024bf7f99721	3589	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
bogdanm	85:024bf7f99721	3590	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
bogdanm	85:024bf7f99721	3591	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
bogdanm	85:024bf7f99721	3592	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
bogdanm	85:024bf7f99721	3593	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
bogdanm	85:024bf7f99721	3594	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /!< GPIOD clock enable /
bogdanm	85:024bf7f99721	3595	#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /!< GPIOE clock enable /
bogdanm	85:024bf7f99721	3596	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
bogdanm	85:024bf7f99721	3597	#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /!< TS controller clock enable /
bogdanm	85:024bf7f99721	3598
bogdanm	85:024bf7f99721	3599	/* Old Bit definition maintained for legacy purpose */
bogdanm	85:024bf7f99721	3600	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
bogdanm	85:024bf7f99721	3601	#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /!< TS clock enable /
bogdanm	85:024bf7f99721	3602
bogdanm	85:024bf7f99721	3603	/*************** Bit definition for RCC_APB2ENR register ***************/
bogdanm	85:024bf7f99721	3604	#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /!< SYSCFG and comparator clock enable /
bogdanm	85:024bf7f99721	3605	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /!< ADC1 clock enable /
bogdanm	85:024bf7f99721	3606	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
bogdanm	85:024bf7f99721	3607	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
bogdanm	85:024bf7f99721	3608	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
bogdanm	85:024bf7f99721	3609	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 clock enable /
bogdanm	85:024bf7f99721	3610	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
bogdanm	85:024bf7f99721	3611	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
bogdanm	85:024bf7f99721	3612	#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /!< DBGMCU clock enable /
bogdanm	85:024bf7f99721	3613
bogdanm	85:024bf7f99721	3614	/* Old Bit definition maintained for legacy purpose */
bogdanm	85:024bf7f99721	3615	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /!< SYSCFG clock enable /
bogdanm	85:024bf7f99721	3616	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
bogdanm	85:024bf7f99721	3617
bogdanm	85:024bf7f99721	3618	/*************** Bit definition for RCC_APB1ENR register ***************/
bogdanm	85:024bf7f99721	3619	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enable /
bogdanm	85:024bf7f99721	3620	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
bogdanm	85:024bf7f99721	3621	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
bogdanm	85:024bf7f99721	3622	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
bogdanm	85:024bf7f99721	3623	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< Timer 14 clock enable /
bogdanm	85:024bf7f99721	3624	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
bogdanm	85:024bf7f99721	3625	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI2 clock enable /
bogdanm	85:024bf7f99721	3626	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART2 clock enable /
bogdanm	85:024bf7f99721	3627	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART3 clock enable /
bogdanm	85:024bf7f99721	3628	#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /!< USART4 clock enable /
bogdanm	85:024bf7f99721	3629	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C1 clock enable /
bogdanm	85:024bf7f99721	3630	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C2 clock enable /
bogdanm	85:024bf7f99721	3631	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB clock enable /
bogdanm	85:024bf7f99721	3632	#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /!< CAN clock enable /
bogdanm	85:024bf7f99721	3633	#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /!< CRS clock enable /
bogdanm	85:024bf7f99721	3634	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
bogdanm	85:024bf7f99721	3635	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC clock enable /
bogdanm	85:024bf7f99721	3636	#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /!< CEC clock enable /
bogdanm	85:024bf7f99721	3637
bogdanm	85:024bf7f99721	3638	/***************** Bit definition for RCC_BDCR register ****************/
bogdanm	85:024bf7f99721	3639	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
bogdanm	85:024bf7f99721	3640	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
bogdanm	85:024bf7f99721	3641	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
bogdanm	85:024bf7f99721	3642
bogdanm	85:024bf7f99721	3643	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
bogdanm	85:024bf7f99721	3644	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	85:024bf7f99721	3645	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	85:024bf7f99721	3646
bogdanm	85:024bf7f99721	3647	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
bogdanm	85:024bf7f99721	3648	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	85:024bf7f99721	3649	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	85:024bf7f99721	3650
bogdanm	85:024bf7f99721	3651	/!< RTC configuration /
bogdanm	85:024bf7f99721	3652	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
bogdanm	85:024bf7f99721	3653	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
bogdanm	85:024bf7f99721	3654	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
bogdanm	85:024bf7f99721	3655	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
bogdanm	85:024bf7f99721	3656
bogdanm	85:024bf7f99721	3657	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
bogdanm	85:024bf7f99721	3658	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
bogdanm	85:024bf7f99721	3659
bogdanm	85:024bf7f99721	3660	/***************** Bit definition for RCC_CSR register *****************/
bogdanm	85:024bf7f99721	3661	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
bogdanm	85:024bf7f99721	3662	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
bogdanm	85:024bf7f99721	3663	#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /!< V1.8 power domain reset flag /
bogdanm	85:024bf7f99721	3664	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
bogdanm	85:024bf7f99721	3665	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
bogdanm	85:024bf7f99721	3666	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
bogdanm	85:024bf7f99721	3667	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
bogdanm	85:024bf7f99721	3668	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
bogdanm	85:024bf7f99721	3669	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
bogdanm	85:024bf7f99721	3670	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
bogdanm	85:024bf7f99721	3671	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
bogdanm	85:024bf7f99721	3672
bogdanm	85:024bf7f99721	3673	/* Old Bit definition maintained for legacy purpose */
bogdanm	85:024bf7f99721	3674	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
bogdanm	85:024bf7f99721	3675
bogdanm	85:024bf7f99721	3676	/***************** Bit definition for RCC_AHBRSTR register *************/
bogdanm	85:024bf7f99721	3677	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA clock reset /
bogdanm	85:024bf7f99721	3678	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB clock reset /
bogdanm	85:024bf7f99721	3679	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC clock reset /
bogdanm	85:024bf7f99721	3680	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /!< GPIOD clock reset /
bogdanm	85:024bf7f99721	3681	#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /!< GPIOE clock reset /
bogdanm	85:024bf7f99721	3682	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /!< GPIOF clock reset /
bogdanm	85:024bf7f99721	3683	#define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /!< TS clock reset /
bogdanm	85:024bf7f99721	3684
bogdanm	85:024bf7f99721	3685	/* Old Bit definition maintained for legacy purpose */
bogdanm	85:024bf7f99721	3686	#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /!< TS clock reset /
bogdanm	85:024bf7f99721	3687
bogdanm	85:024bf7f99721	3688	/***************** Bit definition for RCC_CFGR2 register ***************/
bogdanm	85:024bf7f99721	3689	/!< PREDIV configuration /
bogdanm	85:024bf7f99721	3690	#define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /!< PREDIV[3:0] bits /
bogdanm	85:024bf7f99721	3691	#define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	85:024bf7f99721	3692	#define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	85:024bf7f99721	3693	#define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /!< Bit 2 /
bogdanm	85:024bf7f99721	3694	#define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /!< Bit 3 /
bogdanm	85:024bf7f99721	3695
bogdanm	85:024bf7f99721	3696	#define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /!< PREDIV input clock not divided /
bogdanm	85:024bf7f99721	3697	#define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /!< PREDIV input clock divided by 2 /
bogdanm	85:024bf7f99721	3698	#define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /!< PREDIV input clock divided by 3 /
bogdanm	85:024bf7f99721	3699	#define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /!< PREDIV input clock divided by 4 /
bogdanm	85:024bf7f99721	3700	#define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /!< PREDIV input clock divided by 5 /
bogdanm	85:024bf7f99721	3701	#define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /!< PREDIV input clock divided by 6 /
bogdanm	85:024bf7f99721	3702	#define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /!< PREDIV input clock divided by 7 /
bogdanm	85:024bf7f99721	3703	#define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /!< PREDIV input clock divided by 8 /
bogdanm	85:024bf7f99721	3704	#define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /!< PREDIV input clock divided by 9 /
bogdanm	85:024bf7f99721	3705	#define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /!< PREDIV input clock divided by 10 /
bogdanm	85:024bf7f99721	3706	#define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /!< PREDIV input clock divided by 11 /
bogdanm	85:024bf7f99721	3707	#define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /!< PREDIV input clock divided by 12 /
bogdanm	85:024bf7f99721	3708	#define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /!< PREDIV input clock divided by 13 /
bogdanm	85:024bf7f99721	3709	#define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /!< PREDIV input clock divided by 14 /
bogdanm	85:024bf7f99721	3710	#define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /!< PREDIV input clock divided by 15 /
bogdanm	85:024bf7f99721	3711	#define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /!< PREDIV input clock divided by 16 /
bogdanm	85:024bf7f99721	3712
bogdanm	85:024bf7f99721	3713	/***************** Bit definition for RCC_CFGR3 register ***************/
bogdanm	85:024bf7f99721	3714	/!< USART1 Clock source selection /
bogdanm	85:024bf7f99721	3715	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
bogdanm	85:024bf7f99721	3716	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
bogdanm	85:024bf7f99721	3717	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
bogdanm	85:024bf7f99721	3718
bogdanm	85:024bf7f99721	3719	#define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART1 clock source /
bogdanm	85:024bf7f99721	3720	#define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /!< System clock selected as USART1 clock source /
bogdanm	85:024bf7f99721	3721	#define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /!< LSE oscillator clock used as USART1 clock source /
bogdanm	85:024bf7f99721	3722	#define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /!< HSI oscillator clock used as USART1 clock source /
bogdanm	85:024bf7f99721	3723
bogdanm	85:024bf7f99721	3724	/!< I2C1 Clock source selection /
bogdanm	85:024bf7f99721	3725	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
bogdanm	85:024bf7f99721	3726
bogdanm	85:024bf7f99721	3727	#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /!< HSI oscillator clock used as I2C1 clock source /
bogdanm	85:024bf7f99721	3728	#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /!< System clock selected as I2C1 clock source /
bogdanm	85:024bf7f99721	3729
bogdanm	85:024bf7f99721	3730	/!< CEC Clock source selection /
bogdanm	85:024bf7f99721	3731	#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /!< CECSW bits /
bogdanm	85:024bf7f99721	3732
bogdanm	85:024bf7f99721	3733	#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /!< HSI clock divided by 244 selected as HDMI CEC entry clock source /
bogdanm	85:024bf7f99721	3734	#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /!< LSE clock selected as HDMI CEC entry clock source /
bogdanm	85:024bf7f99721	3735
bogdanm	85:024bf7f99721	3736	/!< USB Clock source selection /
bogdanm	85:024bf7f99721	3737	#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /!< USBSW bits /
bogdanm	85:024bf7f99721	3738
bogdanm	85:024bf7f99721	3739	#define RCC_CFGR3_USBSW_HSI48 ((uint32_t)0x00000000) /!< HSI48 oscillator clock used as USB clock source /
bogdanm	85:024bf7f99721	3740	#define RCC_CFGR3_USBSW_PLLCLK ((uint32_t)0x00000080) /!< PLLCLK selected as USB clock source /
bogdanm	85:024bf7f99721	3741
bogdanm	85:024bf7f99721	3742	/!< USART2 Clock source selection /
bogdanm	85:024bf7f99721	3743	#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /!< USART2SW[1:0] bits /
bogdanm	85:024bf7f99721	3744	#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	85:024bf7f99721	3745	#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	85:024bf7f99721	3746
bogdanm	85:024bf7f99721	3747	#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /!< PCLK clock used as USART2 clock source /
bogdanm	85:024bf7f99721	3748	#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /!< System clock selected as USART2 clock source /
bogdanm	85:024bf7f99721	3749	#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /!< LSE oscillator clock used as USART2 clock source /
bogdanm	85:024bf7f99721	3750	#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /!< HSI oscillator clock used as USART2 clock source /
bogdanm	85:024bf7f99721	3751
bogdanm	85:024bf7f99721	3752	/***************** Bit definition for RCC_CR2 register *****************/
bogdanm	85:024bf7f99721	3753	#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /!< Internal High Speed 14MHz clock enable /
bogdanm	85:024bf7f99721	3754	#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /!< Internal High Speed 14MHz clock ready flag /
bogdanm	85:024bf7f99721	3755	#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /!< Internal High Speed 14MHz clock disable /
bogdanm	85:024bf7f99721	3756	#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /!< Internal High Speed 14MHz clock trimming /
bogdanm	85:024bf7f99721	3757	#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /!< Internal High Speed 14MHz clock Calibration /
bogdanm	85:024bf7f99721	3758	#define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /!< Internal High Speed 48MHz clock enable /
bogdanm	85:024bf7f99721	3759	#define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /!< Internal High Speed 48MHz clock ready flag /
bogdanm	85:024bf7f99721	3760	#define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /!< Internal High Speed 48MHz clock Calibration /
bogdanm	85:024bf7f99721	3761
bogdanm	85:024bf7f99721	3762	/*****************************************************************************/
bogdanm	85:024bf7f99721	3763	/* */
bogdanm	85:024bf7f99721	3764	/* Real-Time Clock (RTC) */
bogdanm	85:024bf7f99721	3765	/* */
bogdanm	85:024bf7f99721	3766	/*****************************************************************************/
bogdanm	85:024bf7f99721	3767	/****************** Bits definition for RTC_TR register ****************/
bogdanm	85:024bf7f99721	3768	#define RTC_TR_PM ((uint32_t)0x00400000)
bogdanm	85:024bf7f99721	3769	#define RTC_TR_HT ((uint32_t)0x00300000)
bogdanm	85:024bf7f99721	3770	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
bogdanm	85:024bf7f99721	3771	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
bogdanm	85:024bf7f99721	3772	#define RTC_TR_HU ((uint32_t)0x000F0000)
bogdanm	85:024bf7f99721	3773	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	3774	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	3775	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	3776	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
bogdanm	85:024bf7f99721	3777	#define RTC_TR_MNT ((uint32_t)0x00007000)
bogdanm	85:024bf7f99721	3778	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3779	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3780	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3781	#define RTC_TR_MNU ((uint32_t)0x00000F00)
bogdanm	85:024bf7f99721	3782	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3783	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3784	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3785	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3786	#define RTC_TR_ST ((uint32_t)0x00000070)
bogdanm	85:024bf7f99721	3787	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3788	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3789	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3790	#define RTC_TR_SU ((uint32_t)0x0000000F)
bogdanm	85:024bf7f99721	3791	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3792	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3793	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3794	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3795
bogdanm	85:024bf7f99721	3796	/****************** Bits definition for RTC_DR register ****************/
bogdanm	85:024bf7f99721	3797	#define RTC_DR_YT ((uint32_t)0x00F00000)
bogdanm	85:024bf7f99721	3798	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
bogdanm	85:024bf7f99721	3799	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
bogdanm	85:024bf7f99721	3800	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
bogdanm	85:024bf7f99721	3801	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
bogdanm	85:024bf7f99721	3802	#define RTC_DR_YU ((uint32_t)0x000F0000)
bogdanm	85:024bf7f99721	3803	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	3804	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	3805	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	3806	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
bogdanm	85:024bf7f99721	3807	#define RTC_DR_WDU ((uint32_t)0x0000E000)
bogdanm	85:024bf7f99721	3808	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3809	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3810	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3811	#define RTC_DR_MT ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3812	#define RTC_DR_MU ((uint32_t)0x00000F00)
bogdanm	85:024bf7f99721	3813	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3814	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3815	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3816	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3817	#define RTC_DR_DT ((uint32_t)0x00000030)
bogdanm	85:024bf7f99721	3818	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3819	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3820	#define RTC_DR_DU ((uint32_t)0x0000000F)
bogdanm	85:024bf7f99721	3821	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3822	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3823	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3824	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3825
bogdanm	85:024bf7f99721	3826	/****************** Bits definition for RTC_CR register ****************/
bogdanm	85:024bf7f99721	3827	#define RTC_CR_COE ((uint32_t)0x00800000)
bogdanm	85:024bf7f99721	3828	#define RTC_CR_OSEL ((uint32_t)0x00600000)
bogdanm	85:024bf7f99721	3829	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
bogdanm	85:024bf7f99721	3830	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
bogdanm	85:024bf7f99721	3831	#define RTC_CR_POL ((uint32_t)0x00100000)
bogdanm	85:024bf7f99721	3832	#define RTC_CR_COSEL ((uint32_t)0x00080000)
bogdanm	85:024bf7f99721	3833	#define RTC_CR_BCK ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	3834	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	3835	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	3836	#define RTC_CR_TSIE ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3837	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3838	#define RTC_CR_TSE ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3839	#define RTC_CR_WUTE ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3840	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3841	#define RTC_CR_FMT ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3842	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3843	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3844	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3845	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
bogdanm	85:024bf7f99721	3846	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3847	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3848	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3849
bogdanm	85:024bf7f99721	3850	/****************** Bits definition for RTC_ISR register ***************/
bogdanm	85:024bf7f99721	3851	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	3852	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3853	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3854	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3855	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3856	#define RTC_ISR_TSF ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3857	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3858	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3859	#define RTC_ISR_INIT ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	3860	#define RTC_ISR_INITF ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3861	#define RTC_ISR_RSF ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3862	#define RTC_ISR_INITS ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3863	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3864	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3865	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3866
bogdanm	85:024bf7f99721	3867	/****************** Bits definition for RTC_PRER register **************/
bogdanm	85:024bf7f99721	3868	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
bogdanm	85:024bf7f99721	3869	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
bogdanm	85:024bf7f99721	3870
bogdanm	85:024bf7f99721	3871	/****************** Bits definition for RTC_WUTR register **************/
bogdanm	85:024bf7f99721	3872	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
bogdanm	85:024bf7f99721	3873
bogdanm	85:024bf7f99721	3874	/****************** Bits definition for RTC_ALRMAR register ************/
bogdanm	85:024bf7f99721	3875	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
bogdanm	85:024bf7f99721	3876	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
bogdanm	85:024bf7f99721	3877	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
bogdanm	85:024bf7f99721	3878	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
bogdanm	85:024bf7f99721	3879	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
bogdanm	85:024bf7f99721	3880	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
bogdanm	85:024bf7f99721	3881	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
bogdanm	85:024bf7f99721	3882	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
bogdanm	85:024bf7f99721	3883	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
bogdanm	85:024bf7f99721	3884	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
bogdanm	85:024bf7f99721	3885	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
bogdanm	85:024bf7f99721	3886	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
bogdanm	85:024bf7f99721	3887	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
bogdanm	85:024bf7f99721	3888	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
bogdanm	85:024bf7f99721	3889	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
bogdanm	85:024bf7f99721	3890	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
bogdanm	85:024bf7f99721	3891	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	3892	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	3893	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	3894	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
bogdanm	85:024bf7f99721	3895	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3896	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
bogdanm	85:024bf7f99721	3897	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3898	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3899	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3900	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
bogdanm	85:024bf7f99721	3901	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3902	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3903	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3904	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3905	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	3906	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
bogdanm	85:024bf7f99721	3907	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3908	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3909	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3910	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
bogdanm	85:024bf7f99721	3911	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3912	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3913	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3914	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3915
bogdanm	85:024bf7f99721	3916	/****************** Bits definition for RTC_WPR register ***************/
bogdanm	85:024bf7f99721	3917	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
bogdanm	85:024bf7f99721	3918
bogdanm	85:024bf7f99721	3919	/****************** Bits definition for RTC_SSR register ***************/
bogdanm	85:024bf7f99721	3920	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
bogdanm	85:024bf7f99721	3921
bogdanm	85:024bf7f99721	3922	/****************** Bits definition for RTC_SHIFTR register ************/
bogdanm	85:024bf7f99721	3923	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
bogdanm	85:024bf7f99721	3924	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
bogdanm	85:024bf7f99721	3925
bogdanm	85:024bf7f99721	3926	/****************** Bits definition for RTC_TSTR register **************/
bogdanm	85:024bf7f99721	3927	#define RTC_TSTR_PM ((uint32_t)0x00400000)
bogdanm	85:024bf7f99721	3928	#define RTC_TSTR_HT ((uint32_t)0x00300000)
bogdanm	85:024bf7f99721	3929	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
bogdanm	85:024bf7f99721	3930	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
bogdanm	85:024bf7f99721	3931	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
bogdanm	85:024bf7f99721	3932	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	3933	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	3934	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	3935	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
bogdanm	85:024bf7f99721	3936	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
bogdanm	85:024bf7f99721	3937	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3938	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3939	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3940	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
bogdanm	85:024bf7f99721	3941	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3942	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3943	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3944	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3945	#define RTC_TSTR_ST ((uint32_t)0x00000070)
bogdanm	85:024bf7f99721	3946	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3947	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3948	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3949	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
bogdanm	85:024bf7f99721	3950	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3951	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3952	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3953	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3954
bogdanm	85:024bf7f99721	3955	/****************** Bits definition for RTC_TSDR register **************/
bogdanm	85:024bf7f99721	3956	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
bogdanm	85:024bf7f99721	3957	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3958	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3959	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3960	#define RTC_TSDR_MT ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	3961	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
bogdanm	85:024bf7f99721	3962	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3963	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	3964	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	3965	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	3966	#define RTC_TSDR_DT ((uint32_t)0x00000030)
bogdanm	85:024bf7f99721	3967	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3968	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3969	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
bogdanm	85:024bf7f99721	3970	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3971	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3972	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3973	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3974
bogdanm	85:024bf7f99721	3975	/****************** Bits definition for RTC_TSSSR register *************/
bogdanm	85:024bf7f99721	3976	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
bogdanm	85:024bf7f99721	3977
bogdanm	85:024bf7f99721	3978	/****************** Bits definition for RTC_CALR register **************/
bogdanm	85:024bf7f99721	3979	#define RTC_CALR_CALP ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3980	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3981	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3982	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
bogdanm	85:024bf7f99721	3983	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	3984	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	3985	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	3986	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	3987	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	3988	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	3989	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	3990	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	3991	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	3992
bogdanm	85:024bf7f99721	3993	/****************** Bits definition for RTC_TAFCR register *************/
bogdanm	85:024bf7f99721	3994	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	3995	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
bogdanm	85:024bf7f99721	3996	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
bogdanm	85:024bf7f99721	3997	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
bogdanm	85:024bf7f99721	3998	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
bogdanm	85:024bf7f99721	3999	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
bogdanm	85:024bf7f99721	4000	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
bogdanm	85:024bf7f99721	4001	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
bogdanm	85:024bf7f99721	4002	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
bogdanm	85:024bf7f99721	4003	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
bogdanm	85:024bf7f99721	4004	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
bogdanm	85:024bf7f99721	4005	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	4006	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
bogdanm	85:024bf7f99721	4007	#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
bogdanm	85:024bf7f99721	4008	#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	4009	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
bogdanm	85:024bf7f99721	4010	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
bogdanm	85:024bf7f99721	4011	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
bogdanm	85:024bf7f99721	4012	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	4013	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	4014
bogdanm	85:024bf7f99721	4015	/****************** Bits definition for RTC_ALRMASSR register **********/
bogdanm	85:024bf7f99721	4016	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
bogdanm	85:024bf7f99721	4017	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
bogdanm	85:024bf7f99721	4018	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
bogdanm	85:024bf7f99721	4019	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
bogdanm	85:024bf7f99721	4020	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
bogdanm	85:024bf7f99721	4021	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
bogdanm	85:024bf7f99721	4022
bogdanm	85:024bf7f99721	4023	/****************** Bits definition for RTC_BKP0R register *************/
bogdanm	85:024bf7f99721	4024	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
bogdanm	85:024bf7f99721	4025
bogdanm	85:024bf7f99721	4026	/****************** Bits definition for RTC_BKP1R register *************/
bogdanm	85:024bf7f99721	4027	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
bogdanm	85:024bf7f99721	4028
bogdanm	85:024bf7f99721	4029	/****************** Bits definition for RTC_BKP2R register *************/
bogdanm	85:024bf7f99721	4030	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
bogdanm	85:024bf7f99721	4031
bogdanm	85:024bf7f99721	4032	/****************** Bits definition for RTC_BKP3R register *************/
bogdanm	85:024bf7f99721	4033	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
bogdanm	85:024bf7f99721	4034
bogdanm	85:024bf7f99721	4035	/****************** Bits definition for RTC_BKP4R register *************/
bogdanm	85:024bf7f99721	4036	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
bogdanm	85:024bf7f99721	4037
bogdanm	85:024bf7f99721	4038	/****************** Number of backup registers ****************************/
bogdanm	85:024bf7f99721	4039	#define RTC_BKP_NUMBER ((uint32_t)0x00000005)
bogdanm	85:024bf7f99721	4040
bogdanm	85:024bf7f99721	4041	/*****************************************************************************/
bogdanm	85:024bf7f99721	4042	/* */
bogdanm	85:024bf7f99721	4043	/* Serial Peripheral Interface (SPI) */
bogdanm	85:024bf7f99721	4044	/* */
bogdanm	85:024bf7f99721	4045	/*****************************************************************************/
bogdanm	85:024bf7f99721	4046	/***************** Bit definition for SPI_CR1 register *****************/
bogdanm	92:4fc01daae5a5	4047	#define SPI_CR1_CPHA ((uint32_t)0x00000001) /!< Clock Phase /
bogdanm	92:4fc01daae5a5	4048	#define SPI_CR1_CPOL ((uint32_t)0x00000002) /!< Clock Polarity /
bogdanm	92:4fc01daae5a5	4049	#define SPI_CR1_MSTR ((uint32_t)0x00000004) /!< Master Selection /
bogdanm	92:4fc01daae5a5	4050	#define SPI_CR1_BR ((uint32_t)0x00000038) /!< BR[2:0] bits (Baud Rate Control) /
bogdanm	92:4fc01daae5a5	4051	#define SPI_CR1_BR_0 ((uint32_t)0x00000008) /!< Bit 0 /
bogdanm	92:4fc01daae5a5	4052	#define SPI_CR1_BR_1 ((uint32_t)0x00000010) /!< Bit 1 /
bogdanm	92:4fc01daae5a5	4053	#define SPI_CR1_BR_2 ((uint32_t)0x00000020) /!< Bit 2 /
bogdanm	92:4fc01daae5a5	4054	#define SPI_CR1_SPE ((uint32_t)0x00000040) /!< SPI Enable /
bogdanm	92:4fc01daae5a5	4055	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /!< Frame Format /
bogdanm	92:4fc01daae5a5	4056	#define SPI_CR1_SSI ((uint32_t)0x00000100) /!< Internal slave select /
bogdanm	92:4fc01daae5a5	4057	#define SPI_CR1_SSM ((uint32_t)0x00000200) /!< Software slave management /
bogdanm	92:4fc01daae5a5	4058	#define SPI_CR1_RXONLY ((uint32_t)0x00000400) /!< Receive only /
bogdanm	92:4fc01daae5a5	4059	#define SPI_CR1_CRCL ((uint32_t)0x00000800) /!< CRC Length /
bogdanm	92:4fc01daae5a5	4060	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /!< Transmit CRC next /
bogdanm	92:4fc01daae5a5	4061	#define SPI_CR1_CRCEN ((uint32_t)0x00002000) /!< Hardware CRC calculation enable /
bogdanm	92:4fc01daae5a5	4062	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /!< Output enable in bidirectional mode /
bogdanm	92:4fc01daae5a5	4063	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /!< Bidirectional data mode enable /
bogdanm	85:024bf7f99721	4064
bogdanm	85:024bf7f99721	4065	/***************** Bit definition for SPI_CR2 register *****************/
bogdanm	92:4fc01daae5a5	4066	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /!< Rx Buffer DMA Enable /
bogdanm	92:4fc01daae5a5	4067	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /!< Tx Buffer DMA Enable /
bogdanm	92:4fc01daae5a5	4068	#define SPI_CR2_SSOE ((uint32_t)0x00000004) /!< SS Output Enable /
bogdanm	92:4fc01daae5a5	4069	#define SPI_CR2_NSSP ((uint32_t)0x00000008) /!< NSS pulse management Enable /
bogdanm	92:4fc01daae5a5	4070	#define SPI_CR2_FRF ((uint32_t)0x00000010) /!< Frame Format Enable /
bogdanm	92:4fc01daae5a5	4071	#define SPI_CR2_ERRIE ((uint32_t)0x00000020) /!< Error Interrupt Enable /
bogdanm	92:4fc01daae5a5	4072	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /!< RX buffer Not Empty Interrupt Enable /
bogdanm	92:4fc01daae5a5	4073	#define SPI_CR2_TXEIE ((uint32_t)0x00000080) /!< Tx buffer Empty Interrupt Enable /
bogdanm	92:4fc01daae5a5	4074	#define SPI_CR2_DS ((uint32_t)0x00000F00) /!< DS[3:0] Data Size /
bogdanm	92:4fc01daae5a5	4075	#define SPI_CR2_DS_0 ((uint32_t)0x00000100) /!< Bit 0 /
bogdanm	92:4fc01daae5a5	4076	#define SPI_CR2_DS_1 ((uint32_t)0x00000200) /!< Bit 1 /
bogdanm	92:4fc01daae5a5	4077	#define SPI_CR2_DS_2 ((uint32_t)0x00000400) /!< Bit 2 /
bogdanm	92:4fc01daae5a5	4078	#define SPI_CR2_DS_3 ((uint32_t)0x00000800) /!< Bit 3 /
bogdanm	92:4fc01daae5a5	4079	#define SPI_CR2_FRXTH ((uint32_t)0x00001000) /!< FIFO reception Threshold /
bogdanm	92:4fc01daae5a5	4080	#define SPI_CR2_LDMARX ((uint32_t)0x00002000) /!< Last DMA transfer for reception /
bogdanm	92:4fc01daae5a5	4081	#define SPI_CR2_LDMATX ((uint32_t)0x00004000) /!< Last DMA transfer for transmission /
bogdanm	85:024bf7f99721	4082
bogdanm	85:024bf7f99721	4083	/****************** Bit definition for SPI_SR register *****************/
bogdanm	92:4fc01daae5a5	4084	#define SPI_SR_RXNE ((uint32_t)0x00000001) /!< Receive buffer Not Empty /
bogdanm	92:4fc01daae5a5	4085	#define SPI_SR_TXE ((uint32_t)0x00000002) /!< Transmit buffer Empty /
bogdanm	92:4fc01daae5a5	4086	#define SPI_SR_CHSIDE ((uint32_t)0x00000004) /!< Channel side /
bogdanm	92:4fc01daae5a5	4087	#define SPI_SR_UDR ((uint32_t)0x00000008) /!< Underrun flag /
bogdanm	92:4fc01daae5a5	4088	#define SPI_SR_CRCERR ((uint32_t)0x00000010) /!< CRC Error flag /
bogdanm	92:4fc01daae5a5	4089	#define SPI_SR_MODF ((uint32_t)0x00000020) /!< Mode fault /
bogdanm	92:4fc01daae5a5	4090	#define SPI_SR_OVR ((uint32_t)0x00000040) /!< Overrun flag /
bogdanm	92:4fc01daae5a5	4091	#define SPI_SR_BSY ((uint32_t)0x00000080) /!< Busy flag /
bogdanm	92:4fc01daae5a5	4092	#define SPI_SR_FRE ((uint32_t)0x00000100) /!< TI frame format error /
bogdanm	92:4fc01daae5a5	4093	#define SPI_SR_FRLVL ((uint32_t)0x00000600) /!< FIFO Reception Level /
bogdanm	92:4fc01daae5a5	4094	#define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /!< Bit 0 /
bogdanm	92:4fc01daae5a5	4095	#define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /!< Bit 1 /
bogdanm	92:4fc01daae5a5	4096	#define SPI_SR_FTLVL ((uint32_t)0x00001800) /!< FIFO Transmission Level /
bogdanm	92:4fc01daae5a5	4097	#define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /!< Bit 0 /
bogdanm	92:4fc01daae5a5	4098	#define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /!< Bit 1 /
bogdanm	85:024bf7f99721	4099
bogdanm	85:024bf7f99721	4100	/****************** Bit definition for SPI_DR register *****************/
bogdanm	92:4fc01daae5a5	4101	#define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data Register /
bogdanm	85:024bf7f99721	4102
bogdanm	85:024bf7f99721	4103	/***************** Bit definition for SPI_CRCPR register ***************/
bogdanm	92:4fc01daae5a5	4104	#define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /!< CRC polynomial register /
bogdanm	85:024bf7f99721	4105
bogdanm	85:024bf7f99721	4106	/**************** Bit definition for SPI_RXCRCR register ***************/
bogdanm	92:4fc01daae5a5	4107	#define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /!< Rx CRC Register /
bogdanm	85:024bf7f99721	4108
bogdanm	85:024bf7f99721	4109	/**************** Bit definition for SPI_TXCRCR register ***************/
bogdanm	92:4fc01daae5a5	4110	#define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /!< Tx CRC Register /
bogdanm	85:024bf7f99721	4111
bogdanm	85:024bf7f99721	4112	/**************** Bit definition for SPI_I2SCFGR register **************/
bogdanm	92:4fc01daae5a5	4113	#define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /!<Channel length (number of bits per audio channel) /
bogdanm	92:4fc01daae5a5	4114	#define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /!<DATLEN[1:0] bits (Data length to be transferred) /
bogdanm	92:4fc01daae5a5	4115	#define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4116	#define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4117	#define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /!<steady state clock polarity /
bogdanm	92:4fc01daae5a5	4118	#define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /!<I2SSTD[1:0] bits (I2S standard selection) /
bogdanm	92:4fc01daae5a5	4119	#define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4120	#define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4121	#define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /!<PCM frame synchronization /
bogdanm	92:4fc01daae5a5	4122	#define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
bogdanm	92:4fc01daae5a5	4123	#define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4124	#define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4125	#define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /!<I2S Enable /
bogdanm	92:4fc01daae5a5	4126	#define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /!<I2S mode selection /
bogdanm	85:024bf7f99721	4127
bogdanm	85:024bf7f99721	4128	/**************** Bit definition for SPI_I2SPR register ****************/
bogdanm	92:4fc01daae5a5	4129	#define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /!<I2S Linear prescaler /
bogdanm	92:4fc01daae5a5	4130	#define SPI_I2SPR_ODD ((uint32_t)0x00000100) /!<Odd factor for the prescaler /
bogdanm	92:4fc01daae5a5	4131	#define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /!<Master Clock Output Enable /
bogdanm	85:024bf7f99721	4132
bogdanm	85:024bf7f99721	4133	/*****************************************************************************/
bogdanm	85:024bf7f99721	4134	/* */
bogdanm	85:024bf7f99721	4135	/* System Configuration (SYSCFG) */
bogdanm	85:024bf7f99721	4136	/* */
bogdanm	85:024bf7f99721	4137	/*****************************************************************************/
bogdanm	85:024bf7f99721	4138	/*************** Bit definition for SYSCFG_CFGR1 register **************/
bogdanm	85:024bf7f99721	4139	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
bogdanm	85:024bf7f99721	4140	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< SYSCFG_Memory Remap Config Bit 0 /
bogdanm	85:024bf7f99721	4141	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< SYSCFG_Memory Remap Config Bit 1 /
bogdanm	92:4fc01daae5a5	4142
bogdanm	92:4fc01daae5a5	4143	#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x7F007F00) /!< DMA remap mask /
bogdanm	85:024bf7f99721	4144	#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /!< ADC DMA remap /
bogdanm	85:024bf7f99721	4145	#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /!< USART1 TX DMA remap /
bogdanm	85:024bf7f99721	4146	#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /!< USART1 RX DMA remap /
bogdanm	85:024bf7f99721	4147	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
bogdanm	85:024bf7f99721	4148	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
bogdanm	85:024bf7f99721	4149	#define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /!< Timer 16 DMA remap 2 /
bogdanm	85:024bf7f99721	4150	#define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /!< Timer 17 DMA remap 2 /
bogdanm	85:024bf7f99721	4151	#define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /!< SPI2 DMA remap /
bogdanm	85:024bf7f99721	4152	#define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /!< USART2 DMA remap /
bogdanm	85:024bf7f99721	4153	#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /!< USART3 DMA remap /
bogdanm	85:024bf7f99721	4154	#define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /!< I2C1 DMA remap /
bogdanm	85:024bf7f99721	4155	#define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /!< TIM1 DMA remap /
bogdanm	85:024bf7f99721	4156	#define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /!< TIM2 DMA remap /
bogdanm	85:024bf7f99721	4157	#define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /!< TIM3 DMA remap /
bogdanm	85:024bf7f99721	4158
bogdanm	92:4fc01daae5a5	4159	#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
bogdanm	92:4fc01daae5a5	4160	#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
bogdanm	92:4fc01daae5a5	4161	#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
bogdanm	92:4fc01daae5a5	4162	#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
bogdanm	92:4fc01daae5a5	4163	#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 /
bogdanm	92:4fc01daae5a5	4164	#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /!< Enable I2C2 Fast mode plus /
bogdanm	92:4fc01daae5a5	4165
bogdanm	85:024bf7f99721	4166	/*************** Bit definition for SYSCFG_EXTICR1 register ************/
bogdanm	85:024bf7f99721	4167	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!< EXTI 0 configuration /
bogdanm	85:024bf7f99721	4168	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!< EXTI 1 configuration /
bogdanm	85:024bf7f99721	4169	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!< EXTI 2 configuration /
bogdanm	85:024bf7f99721	4170	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!< EXTI 3 configuration /
bogdanm	85:024bf7f99721	4171
bogdanm	85:024bf7f99721	4172	/**
bogdanm	85:024bf7f99721	4173	* @brief EXTI0 configuration
bogdanm	85:024bf7f99721	4174	*/
bogdanm	85:024bf7f99721	4175	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!< PA[0] pin /
bogdanm	85:024bf7f99721	4176	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!< PB[0] pin /
bogdanm	85:024bf7f99721	4177	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!< PC[0] pin /
bogdanm	85:024bf7f99721	4178	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!< PD[0] pin /
bogdanm	85:024bf7f99721	4179	#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /!< PE[0] pin /
bogdanm	85:024bf7f99721	4180	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!< PF[0] pin /
bogdanm	85:024bf7f99721	4181
bogdanm	85:024bf7f99721	4182	/**
bogdanm	85:024bf7f99721	4183	* @brief EXTI1 configuration
bogdanm	85:024bf7f99721	4184	*/
bogdanm	85:024bf7f99721	4185	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!< PA[1] pin /
bogdanm	85:024bf7f99721	4186	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!< PB[1] pin /
bogdanm	85:024bf7f99721	4187	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!< PC[1] pin /
bogdanm	85:024bf7f99721	4188	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!< PD[1] pin /
bogdanm	85:024bf7f99721	4189	#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /!< PE[1] pin /
bogdanm	85:024bf7f99721	4190	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!< PF[1] pin /
bogdanm	85:024bf7f99721	4191
bogdanm	85:024bf7f99721	4192	/**
bogdanm	85:024bf7f99721	4193	* @brief EXTI2 configuration
bogdanm	85:024bf7f99721	4194	*/
bogdanm	85:024bf7f99721	4195	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!< PA[2] pin /
bogdanm	85:024bf7f99721	4196	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!< PB[2] pin /
bogdanm	85:024bf7f99721	4197	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!< PC[2] pin /
bogdanm	85:024bf7f99721	4198	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!< PD[2] pin /
bogdanm	85:024bf7f99721	4199	#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /!< PE[2] pin /
bogdanm	85:024bf7f99721	4200	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!< PF[2] pin /
bogdanm	85:024bf7f99721	4201
bogdanm	85:024bf7f99721	4202	/**
bogdanm	85:024bf7f99721	4203	* @brief EXTI3 configuration
bogdanm	85:024bf7f99721	4204	*/
bogdanm	85:024bf7f99721	4205	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!< PA[3] pin /
bogdanm	85:024bf7f99721	4206	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!< PB[3] pin /
bogdanm	85:024bf7f99721	4207	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!< PC[3] pin /
bogdanm	85:024bf7f99721	4208	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!< PD[3] pin /
bogdanm	85:024bf7f99721	4209	#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /!< PE[3] pin /
bogdanm	85:024bf7f99721	4210	#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /!< PF[3] pin /
bogdanm	85:024bf7f99721	4211
bogdanm	85:024bf7f99721	4212	/*************** Bit definition for SYSCFG_EXTICR2 register ************/
bogdanm	85:024bf7f99721	4213	#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /!< EXTI 4 configuration /
bogdanm	85:024bf7f99721	4214	#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /!< EXTI 5 configuration /
bogdanm	85:024bf7f99721	4215	#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /!< EXTI 6 configuration /
bogdanm	85:024bf7f99721	4216	#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /!< EXTI 7 configuration /
bogdanm	85:024bf7f99721	4217
bogdanm	85:024bf7f99721	4218	/**
bogdanm	85:024bf7f99721	4219	* @brief EXTI4 configuration
bogdanm	85:024bf7f99721	4220	*/
bogdanm	85:024bf7f99721	4221	#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /!< PA[4] pin /
bogdanm	85:024bf7f99721	4222	#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /!< PB[4] pin /
bogdanm	85:024bf7f99721	4223	#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /!< PC[4] pin /
bogdanm	85:024bf7f99721	4224	#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /!< PD[4] pin /
bogdanm	85:024bf7f99721	4225	#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /!< PE[4] pin /
bogdanm	85:024bf7f99721	4226	#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /!< PF[4] pin /
bogdanm	85:024bf7f99721	4227
bogdanm	85:024bf7f99721	4228	/**
bogdanm	85:024bf7f99721	4229	* @brief EXTI5 configuration
bogdanm	85:024bf7f99721	4230	*/
bogdanm	85:024bf7f99721	4231	#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /!< PA[5] pin /
bogdanm	85:024bf7f99721	4232	#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /!< PB[5] pin /
bogdanm	85:024bf7f99721	4233	#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /!< PC[5] pin /
bogdanm	85:024bf7f99721	4234	#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /!< PD[5] pin /
bogdanm	85:024bf7f99721	4235	#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /!< PE[5] pin /
bogdanm	85:024bf7f99721	4236	#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /!< PF[5] pin /
bogdanm	85:024bf7f99721	4237
bogdanm	85:024bf7f99721	4238	/**
bogdanm	85:024bf7f99721	4239	* @brief EXTI6 configuration
bogdanm	85:024bf7f99721	4240	*/
bogdanm	85:024bf7f99721	4241	#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /!< PA[6] pin /
bogdanm	85:024bf7f99721	4242	#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /!< PB[6] pin /
bogdanm	85:024bf7f99721	4243	#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /!< PC[6] pin /
bogdanm	85:024bf7f99721	4244	#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /!< PD[6] pin /
bogdanm	85:024bf7f99721	4245	#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /!< PE[6] pin /
bogdanm	85:024bf7f99721	4246	#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /!< PF[6] pin /
bogdanm	85:024bf7f99721	4247
bogdanm	85:024bf7f99721	4248	/**
bogdanm	85:024bf7f99721	4249	* @brief EXTI7 configuration
bogdanm	85:024bf7f99721	4250	*/
bogdanm	85:024bf7f99721	4251	#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /!< PA[7] pin /
bogdanm	85:024bf7f99721	4252	#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /!< PB[7] pin /
bogdanm	85:024bf7f99721	4253	#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /!< PC[7] pin /
bogdanm	85:024bf7f99721	4254	#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /!< PD[7] pin /
bogdanm	85:024bf7f99721	4255	#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /!< PE[7] pin /
bogdanm	85:024bf7f99721	4256	#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /!< PF[7] pin /
bogdanm	85:024bf7f99721	4257
bogdanm	85:024bf7f99721	4258	/*************** Bit definition for SYSCFG_EXTICR3 register ************/
bogdanm	85:024bf7f99721	4259	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!< EXTI 8 configuration /
bogdanm	85:024bf7f99721	4260	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!< EXTI 9 configuration /
bogdanm	85:024bf7f99721	4261	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!< EXTI 10 configuration /
bogdanm	85:024bf7f99721	4262	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!< EXTI 11 configuration /
bogdanm	85:024bf7f99721	4263
bogdanm	85:024bf7f99721	4264	/**
bogdanm	85:024bf7f99721	4265	* @brief EXTI8 configuration
bogdanm	85:024bf7f99721	4266	*/
bogdanm	85:024bf7f99721	4267	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!< PA[8] pin /
bogdanm	85:024bf7f99721	4268	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!< PB[8] pin /
bogdanm	85:024bf7f99721	4269	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!< PC[8] pin /
bogdanm	85:024bf7f99721	4270	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!< PD[8] pin /
bogdanm	85:024bf7f99721	4271	#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /!< PE[8] pin /
bogdanm	85:024bf7f99721	4272
bogdanm	85:024bf7f99721	4273	/**
bogdanm	85:024bf7f99721	4274	* @brief EXTI9 configuration
bogdanm	85:024bf7f99721	4275	*/
bogdanm	85:024bf7f99721	4276	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!< PA[9] pin /
bogdanm	85:024bf7f99721	4277	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!< PB[9] pin /
bogdanm	85:024bf7f99721	4278	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!< PC[9] pin /
bogdanm	85:024bf7f99721	4279	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!< PD[9] pin /
bogdanm	85:024bf7f99721	4280	#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /!< PE[9] pin /
bogdanm	85:024bf7f99721	4281	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!< PF[9] pin /
bogdanm	85:024bf7f99721	4282
bogdanm	85:024bf7f99721	4283	/**
bogdanm	85:024bf7f99721	4284	* @brief EXTI10 configuration
bogdanm	85:024bf7f99721	4285	*/
bogdanm	85:024bf7f99721	4286	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!< PA[10] pin /
bogdanm	85:024bf7f99721	4287	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!< PB[10] pin /
bogdanm	85:024bf7f99721	4288	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!< PC[10] pin /
bogdanm	85:024bf7f99721	4289	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!< PE[10] pin /
bogdanm	85:024bf7f99721	4290	#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /!< PD[10] pin /
bogdanm	85:024bf7f99721	4291	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!< PF[10] pin /
bogdanm	85:024bf7f99721	4292
bogdanm	85:024bf7f99721	4293	/**
bogdanm	85:024bf7f99721	4294	* @brief EXTI11 configuration
bogdanm	85:024bf7f99721	4295	*/
bogdanm	85:024bf7f99721	4296	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!< PA[11] pin /
bogdanm	85:024bf7f99721	4297	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!< PB[11] pin /
bogdanm	85:024bf7f99721	4298	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!< PC[11] pin /
bogdanm	85:024bf7f99721	4299	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!< PD[11] pin /
bogdanm	85:024bf7f99721	4300	#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /!< PE[11] pin /
bogdanm	85:024bf7f99721	4301
bogdanm	85:024bf7f99721	4302	/*************** Bit definition for SYSCFG_EXTICR4 register ************/
bogdanm	85:024bf7f99721	4303	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!< EXTI 12 configuration /
bogdanm	85:024bf7f99721	4304	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!< EXTI 13 configuration /
bogdanm	85:024bf7f99721	4305	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!< EXTI 14 configuration /
bogdanm	85:024bf7f99721	4306	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!< EXTI 15 configuration /
bogdanm	85:024bf7f99721	4307
bogdanm	85:024bf7f99721	4308	/**
bogdanm	85:024bf7f99721	4309	* @brief EXTI12 configuration
bogdanm	85:024bf7f99721	4310	*/
bogdanm	85:024bf7f99721	4311	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!< PA[12] pin /
bogdanm	85:024bf7f99721	4312	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!< PB[12] pin /
bogdanm	85:024bf7f99721	4313	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!< PC[12] pin /
bogdanm	85:024bf7f99721	4314	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!< PD[12] pin /
bogdanm	85:024bf7f99721	4315	#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /!< PE[12] pin /
bogdanm	85:024bf7f99721	4316
bogdanm	85:024bf7f99721	4317	/**
bogdanm	85:024bf7f99721	4318	* @brief EXTI13 configuration
bogdanm	85:024bf7f99721	4319	*/
bogdanm	85:024bf7f99721	4320	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!< PA[13] pin /
bogdanm	85:024bf7f99721	4321	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!< PB[13] pin /
bogdanm	85:024bf7f99721	4322	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!< PC[13] pin /
bogdanm	85:024bf7f99721	4323	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!< PD[13] pin /
bogdanm	85:024bf7f99721	4324	#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /!< PE[13] pin /
bogdanm	85:024bf7f99721	4325
bogdanm	85:024bf7f99721	4326	/**
bogdanm	85:024bf7f99721	4327	* @brief EXTI14 configuration
bogdanm	85:024bf7f99721	4328	*/
bogdanm	85:024bf7f99721	4329	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!< PA[14] pin /
bogdanm	85:024bf7f99721	4330	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!< PB[14] pin /
bogdanm	85:024bf7f99721	4331	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!< PC[14] pin /
bogdanm	85:024bf7f99721	4332	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!< PD[14] pin /
bogdanm	85:024bf7f99721	4333	#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /!< PE[14] pin /
bogdanm	85:024bf7f99721	4334
bogdanm	85:024bf7f99721	4335	/**
bogdanm	85:024bf7f99721	4336	* @brief EXTI15 configuration
bogdanm	85:024bf7f99721	4337	*/
bogdanm	85:024bf7f99721	4338	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!< PA[15] pin /
bogdanm	85:024bf7f99721	4339	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!< PB[15] pin /
bogdanm	85:024bf7f99721	4340	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!< PC[15] pin /
bogdanm	85:024bf7f99721	4341	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!< PD[15] pin /
bogdanm	85:024bf7f99721	4342	#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /!< PE[15] pin /
bogdanm	85:024bf7f99721	4343
bogdanm	85:024bf7f99721	4344	/*************** Bit definition for SYSCFG_CFGR2 register **************/
bogdanm	85:024bf7f99721	4345	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 /
bogdanm	85:024bf7f99721	4346	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 /
bogdanm	85:024bf7f99721	4347	#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface /
bogdanm	85:024bf7f99721	4348	#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /!< SRAM Parity error flag /
bogdanm	85:024bf7f99721	4349	#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /!< SRAM Parity error flag (define maintained for legacy purpose) /
bogdanm	85:024bf7f99721	4350
bogdanm	85:024bf7f99721	4351	/*****************************************************************************/
bogdanm	85:024bf7f99721	4352	/* */
bogdanm	85:024bf7f99721	4353	/* Timers (TIM) */
bogdanm	85:024bf7f99721	4354	/* */
bogdanm	85:024bf7f99721	4355	/*****************************************************************************/
bogdanm	85:024bf7f99721	4356	/***************** Bit definition for TIM_CR1 register *****************/
bogdanm	92:4fc01daae5a5	4357	#define TIM_CR1_CEN ((uint32_t)0x00000001) /!<Counter enable /
bogdanm	92:4fc01daae5a5	4358	#define TIM_CR1_UDIS ((uint32_t)0x00000002) /!<Update disable /
bogdanm	92:4fc01daae5a5	4359	#define TIM_CR1_URS ((uint32_t)0x00000004) /!<Update request source /
bogdanm	92:4fc01daae5a5	4360	#define TIM_CR1_OPM ((uint32_t)0x00000008) /!<One pulse mode /
bogdanm	92:4fc01daae5a5	4361	#define TIM_CR1_DIR ((uint32_t)0x00000010) /!<Direction /
bogdanm	92:4fc01daae5a5	4362
bogdanm	92:4fc01daae5a5	4363	#define TIM_CR1_CMS ((uint32_t)0x00000060) /!<CMS[1:0] bits (Center-aligned mode selection) /
bogdanm	92:4fc01daae5a5	4364	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4365	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4366
bogdanm	92:4fc01daae5a5	4367	#define TIM_CR1_ARPE ((uint32_t)0x00000080) /!<Auto-reload preload enable /
bogdanm	92:4fc01daae5a5	4368
bogdanm	92:4fc01daae5a5	4369	#define TIM_CR1_CKD ((uint32_t)0x00000300) /!<CKD[1:0] bits (clock division) /
bogdanm	92:4fc01daae5a5	4370	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4371	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	85:024bf7f99721	4372
bogdanm	85:024bf7f99721	4373	/***************** Bit definition for TIM_CR2 register *****************/
bogdanm	92:4fc01daae5a5	4374	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
bogdanm	92:4fc01daae5a5	4375	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
bogdanm	92:4fc01daae5a5	4376	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
bogdanm	92:4fc01daae5a5	4377
bogdanm	92:4fc01daae5a5	4378	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
bogdanm	92:4fc01daae5a5	4379	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4380	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4381	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4382
bogdanm	92:4fc01daae5a5	4383	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
bogdanm	92:4fc01daae5a5	4384	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
bogdanm	92:4fc01daae5a5	4385	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
bogdanm	92:4fc01daae5a5	4386	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
bogdanm	92:4fc01daae5a5	4387	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
bogdanm	92:4fc01daae5a5	4388	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
bogdanm	92:4fc01daae5a5	4389	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
bogdanm	92:4fc01daae5a5	4390	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
bogdanm	85:024bf7f99721	4391
bogdanm	85:024bf7f99721	4392	/***************** Bit definition for TIM_SMCR register ****************/
bogdanm	92:4fc01daae5a5	4393	#define TIM_SMCR_SMS ((uint32_t)0x00000007) /!<SMS[2:0] bits (Slave mode selection) /
bogdanm	92:4fc01daae5a5	4394	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4395	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4396	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4397
bogdanm	92:4fc01daae5a5	4398	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
bogdanm	92:4fc01daae5a5	4399
bogdanm	92:4fc01daae5a5	4400	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
bogdanm	92:4fc01daae5a5	4401	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4402	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4403	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4404
bogdanm	92:4fc01daae5a5	4405	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
bogdanm	92:4fc01daae5a5	4406
bogdanm	92:4fc01daae5a5	4407	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
bogdanm	92:4fc01daae5a5	4408	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4409	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4410	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4411	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	92:4fc01daae5a5	4412
bogdanm	92:4fc01daae5a5	4413	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
bogdanm	92:4fc01daae5a5	4414	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4415	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4416
bogdanm	92:4fc01daae5a5	4417	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
bogdanm	92:4fc01daae5a5	4418	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
bogdanm	85:024bf7f99721	4419
bogdanm	85:024bf7f99721	4420	/***************** Bit definition for TIM_DIER register ****************/
bogdanm	92:4fc01daae5a5	4421	#define TIM_DIER_UIE ((uint32_t)0x00000001) /!<Update interrupt enable /
bogdanm	92:4fc01daae5a5	4422	#define TIM_DIER_CC1IE ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt enable /
bogdanm	92:4fc01daae5a5	4423	#define TIM_DIER_CC2IE ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt enable /
bogdanm	92:4fc01daae5a5	4424	#define TIM_DIER_CC3IE ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt enable /
bogdanm	92:4fc01daae5a5	4425	#define TIM_DIER_CC4IE ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt enable /
bogdanm	92:4fc01daae5a5	4426	#define TIM_DIER_COMIE ((uint32_t)0x00000020) /!<COM interrupt enable /
bogdanm	92:4fc01daae5a5	4427	#define TIM_DIER_TIE ((uint32_t)0x00000040) /!<Trigger interrupt enable /
bogdanm	92:4fc01daae5a5	4428	#define TIM_DIER_BIE ((uint32_t)0x00000080) /!<Break interrupt enable /
bogdanm	92:4fc01daae5a5	4429	#define TIM_DIER_UDE ((uint32_t)0x00000100) /!<Update DMA request enable /
bogdanm	92:4fc01daae5a5	4430	#define TIM_DIER_CC1DE ((uint32_t)0x00000200) /!<Capture/Compare 1 DMA request enable /
bogdanm	92:4fc01daae5a5	4431	#define TIM_DIER_CC2DE ((uint32_t)0x00000400) /!<Capture/Compare 2 DMA request enable /
bogdanm	92:4fc01daae5a5	4432	#define TIM_DIER_CC3DE ((uint32_t)0x00000800) /!<Capture/Compare 3 DMA request enable /
bogdanm	92:4fc01daae5a5	4433	#define TIM_DIER_CC4DE ((uint32_t)0x00001000) /!<Capture/Compare 4 DMA request enable /
bogdanm	92:4fc01daae5a5	4434	#define TIM_DIER_COMDE ((uint32_t)0x00002000) /!<COM DMA request enable /
bogdanm	92:4fc01daae5a5	4435	#define TIM_DIER_TDE ((uint32_t)0x00004000) /!<Trigger DMA request enable /
bogdanm	85:024bf7f99721	4436
bogdanm	85:024bf7f99721	4437	/****************** Bit definition for TIM_SR register *****************/
bogdanm	92:4fc01daae5a5	4438	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
bogdanm	92:4fc01daae5a5	4439	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
bogdanm	92:4fc01daae5a5	4440	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
bogdanm	92:4fc01daae5a5	4441	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
bogdanm	92:4fc01daae5a5	4442	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
bogdanm	92:4fc01daae5a5	4443	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
bogdanm	92:4fc01daae5a5	4444	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
bogdanm	92:4fc01daae5a5	4445	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
bogdanm	92:4fc01daae5a5	4446	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Overcapture Flag /
bogdanm	92:4fc01daae5a5	4447	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Overcapture Flag /
bogdanm	92:4fc01daae5a5	4448	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Overcapture Flag /
bogdanm	92:4fc01daae5a5	4449	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Overcapture Flag /
bogdanm	85:024bf7f99721	4450
bogdanm	85:024bf7f99721	4451	/***************** Bit definition for TIM_EGR register *****************/
bogdanm	92:4fc01daae5a5	4452	#define TIM_EGR_UG ((uint32_t)0x00000001) /!<Update Generation /
bogdanm	92:4fc01daae5a5	4453	#define TIM_EGR_CC1G ((uint32_t)0x00000002) /!<Capture/Compare 1 Generation /
bogdanm	92:4fc01daae5a5	4454	#define TIM_EGR_CC2G ((uint32_t)0x00000004) /!<Capture/Compare 2 Generation /
bogdanm	92:4fc01daae5a5	4455	#define TIM_EGR_CC3G ((uint32_t)0x00000008) /!<Capture/Compare 3 Generation /
bogdanm	92:4fc01daae5a5	4456	#define TIM_EGR_CC4G ((uint32_t)0x00000010) /!<Capture/Compare 4 Generation /
bogdanm	92:4fc01daae5a5	4457	#define TIM_EGR_COMG ((uint32_t)0x00000020) /!<Capture/Compare Control Update Generation /
bogdanm	92:4fc01daae5a5	4458	#define TIM_EGR_TG ((uint32_t)0x00000040) /!<Trigger Generation /
bogdanm	92:4fc01daae5a5	4459	#define TIM_EGR_BG ((uint32_t)0x00000080) /!<Break Generation /
bogdanm	85:024bf7f99721	4460
bogdanm	85:024bf7f99721	4461	/**************** Bit definition for TIM_CCMR1 register ****************/
bogdanm	92:4fc01daae5a5	4462	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
bogdanm	92:4fc01daae5a5	4463	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4464	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4465
bogdanm	92:4fc01daae5a5	4466	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
bogdanm	92:4fc01daae5a5	4467	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
bogdanm	92:4fc01daae5a5	4468
bogdanm	92:4fc01daae5a5	4469	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
bogdanm	92:4fc01daae5a5	4470	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4471	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4472	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4473
bogdanm	92:4fc01daae5a5	4474	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
bogdanm	92:4fc01daae5a5	4475
bogdanm	92:4fc01daae5a5	4476	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
bogdanm	92:4fc01daae5a5	4477	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4478	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4479
bogdanm	92:4fc01daae5a5	4480	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
bogdanm	92:4fc01daae5a5	4481	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
bogdanm	92:4fc01daae5a5	4482
bogdanm	92:4fc01daae5a5	4483	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
bogdanm	92:4fc01daae5a5	4484	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4485	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4486	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4487
bogdanm	92:4fc01daae5a5	4488	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
bogdanm	85:024bf7f99721	4489
bogdanm	85:024bf7f99721	4490	/---------------------------------------------------------------------------/
bogdanm	85:024bf7f99721	4491
bogdanm	92:4fc01daae5a5	4492	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
bogdanm	92:4fc01daae5a5	4493	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4494	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4495
bogdanm	92:4fc01daae5a5	4496	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
bogdanm	92:4fc01daae5a5	4497	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4498	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4499	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4500	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	92:4fc01daae5a5	4501
bogdanm	92:4fc01daae5a5	4502	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
bogdanm	92:4fc01daae5a5	4503	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4504	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4505
bogdanm	92:4fc01daae5a5	4506	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
bogdanm	92:4fc01daae5a5	4507	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4508	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4509	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4510	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
bogdanm	85:024bf7f99721	4511
bogdanm	85:024bf7f99721	4512	/**************** Bit definition for TIM_CCMR2 register ****************/
bogdanm	92:4fc01daae5a5	4513	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
bogdanm	92:4fc01daae5a5	4514	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4515	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4516
bogdanm	92:4fc01daae5a5	4517	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
bogdanm	92:4fc01daae5a5	4518	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
bogdanm	92:4fc01daae5a5	4519
bogdanm	92:4fc01daae5a5	4520	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
bogdanm	92:4fc01daae5a5	4521	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4522	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4523	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4524
bogdanm	92:4fc01daae5a5	4525	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
bogdanm	92:4fc01daae5a5	4526
bogdanm	92:4fc01daae5a5	4527	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
bogdanm	92:4fc01daae5a5	4528	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4529	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4530
bogdanm	92:4fc01daae5a5	4531	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
bogdanm	92:4fc01daae5a5	4532	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
bogdanm	92:4fc01daae5a5	4533
bogdanm	92:4fc01daae5a5	4534	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
bogdanm	92:4fc01daae5a5	4535	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4536	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4537	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4538
bogdanm	92:4fc01daae5a5	4539	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
bogdanm	85:024bf7f99721	4540
bogdanm	85:024bf7f99721	4541	/---------------------------------------------------------------------------/
bogdanm	85:024bf7f99721	4542
bogdanm	92:4fc01daae5a5	4543	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
bogdanm	92:4fc01daae5a5	4544	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4545	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4546
bogdanm	92:4fc01daae5a5	4547	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
bogdanm	92:4fc01daae5a5	4548	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4549	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4550	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4551	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /!<Bit 3 /
bogdanm	92:4fc01daae5a5	4552
bogdanm	92:4fc01daae5a5	4553	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
bogdanm	92:4fc01daae5a5	4554	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4555	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4556
bogdanm	92:4fc01daae5a5	4557	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
bogdanm	92:4fc01daae5a5	4558	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4559	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4560	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4561	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /!<Bit 3 /
bogdanm	85:024bf7f99721	4562
bogdanm	85:024bf7f99721	4563	/***************** Bit definition for TIM_CCER register ****************/
bogdanm	92:4fc01daae5a5	4564	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
bogdanm	92:4fc01daae5a5	4565	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
bogdanm	92:4fc01daae5a5	4566	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
bogdanm	92:4fc01daae5a5	4567	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
bogdanm	92:4fc01daae5a5	4568	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
bogdanm	92:4fc01daae5a5	4569	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
bogdanm	92:4fc01daae5a5	4570	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
bogdanm	92:4fc01daae5a5	4571	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
bogdanm	92:4fc01daae5a5	4572	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
bogdanm	92:4fc01daae5a5	4573	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
bogdanm	92:4fc01daae5a5	4574	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
bogdanm	92:4fc01daae5a5	4575	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
bogdanm	92:4fc01daae5a5	4576	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
bogdanm	92:4fc01daae5a5	4577	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
bogdanm	92:4fc01daae5a5	4578	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
bogdanm	85:024bf7f99721	4579
bogdanm	85:024bf7f99721	4580	/***************** Bit definition for TIM_CNT register *****************/
bogdanm	92:4fc01daae5a5	4581	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
bogdanm	85:024bf7f99721	4582
bogdanm	85:024bf7f99721	4583	/***************** Bit definition for TIM_PSC register *****************/
bogdanm	92:4fc01daae5a5	4584	#define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /!<Prescaler Value /
bogdanm	85:024bf7f99721	4585
bogdanm	85:024bf7f99721	4586	/***************** Bit definition for TIM_ARR register *****************/
bogdanm	92:4fc01daae5a5	4587	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
bogdanm	85:024bf7f99721	4588
bogdanm	85:024bf7f99721	4589	/***************** Bit definition for TIM_RCR register *****************/
bogdanm	92:4fc01daae5a5	4590	#define TIM_RCR_REP ((uint32_t)0x000000FF) /!<Repetition Counter Value /
bogdanm	85:024bf7f99721	4591
bogdanm	85:024bf7f99721	4592	/***************** Bit definition for TIM_CCR1 register ****************/
bogdanm	92:4fc01daae5a5	4593	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /!<Capture/Compare 1 Value /
bogdanm	85:024bf7f99721	4594
bogdanm	85:024bf7f99721	4595	/***************** Bit definition for TIM_CCR2 register ****************/
bogdanm	92:4fc01daae5a5	4596	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /!<Capture/Compare 2 Value /
bogdanm	85:024bf7f99721	4597
bogdanm	85:024bf7f99721	4598	/***************** Bit definition for TIM_CCR3 register ****************/
bogdanm	92:4fc01daae5a5	4599	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /!<Capture/Compare 3 Value /
bogdanm	85:024bf7f99721	4600
bogdanm	85:024bf7f99721	4601	/***************** Bit definition for TIM_CCR4 register ****************/
bogdanm	92:4fc01daae5a5	4602	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /!<Capture/Compare 4 Value /
bogdanm	85:024bf7f99721	4603
bogdanm	85:024bf7f99721	4604	/***************** Bit definition for TIM_BDTR register ****************/
bogdanm	92:4fc01daae5a5	4605	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
bogdanm	92:4fc01daae5a5	4606	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4607	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4608	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4609	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	92:4fc01daae5a5	4610	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	92:4fc01daae5a5	4611	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
bogdanm	92:4fc01daae5a5	4612	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
bogdanm	92:4fc01daae5a5	4613	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
bogdanm	92:4fc01daae5a5	4614
bogdanm	92:4fc01daae5a5	4615	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
bogdanm	92:4fc01daae5a5	4616	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4617	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4618
bogdanm	92:4fc01daae5a5	4619	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
bogdanm	92:4fc01daae5a5	4620	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
bogdanm	92:4fc01daae5a5	4621	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable /
bogdanm	92:4fc01daae5a5	4622	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity /
bogdanm	92:4fc01daae5a5	4623	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
bogdanm	92:4fc01daae5a5	4624	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
bogdanm	85:024bf7f99721	4625
bogdanm	85:024bf7f99721	4626	/***************** Bit definition for TIM_DCR register *****************/
bogdanm	92:4fc01daae5a5	4627	#define TIM_DCR_DBA ((uint32_t)0x0000001F) /!<DBA[4:0] bits (DMA Base Address) /
bogdanm	92:4fc01daae5a5	4628	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4629	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4630	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4631	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /!<Bit 3 /
bogdanm	92:4fc01daae5a5	4632	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /!<Bit 4 /
bogdanm	92:4fc01daae5a5	4633
bogdanm	92:4fc01daae5a5	4634	#define TIM_DCR_DBL ((uint32_t)0x00001F00) /!<DBL[4:0] bits (DMA Burst Length) /
bogdanm	92:4fc01daae5a5	4635	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4636	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /!<Bit 1 /
bogdanm	92:4fc01daae5a5	4637	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /!<Bit 2 /
bogdanm	92:4fc01daae5a5	4638	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /!<Bit 3 /
bogdanm	92:4fc01daae5a5	4639	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /!<Bit 4 /
bogdanm	85:024bf7f99721	4640
bogdanm	85:024bf7f99721	4641	/***************** Bit definition for TIM_DMAR register ****************/
bogdanm	92:4fc01daae5a5	4642	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /!<DMA register for burst accesses /
bogdanm	92:4fc01daae5a5	4643
bogdanm	92:4fc01daae5a5	4644	/***************** Bit definition for TIM14_OR register ******************/
bogdanm	92:4fc01daae5a5	4645	#define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) /
bogdanm	92:4fc01daae5a5	4646	#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /!<Bit 0 /
bogdanm	92:4fc01daae5a5	4647	#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /!<Bit 1 /
bogdanm	85:024bf7f99721	4648
bogdanm	85:024bf7f99721	4649	/******************************************************************************/
bogdanm	85:024bf7f99721	4650	/* */
bogdanm	85:024bf7f99721	4651	/* Touch Sensing Controller (TSC) */
bogdanm	85:024bf7f99721	4652	/* */
bogdanm	85:024bf7f99721	4653	/******************************************************************************/
bogdanm	85:024bf7f99721	4654	/***************** Bit definition for TSC_CR register *******************/
bogdanm	85:024bf7f99721	4655	#define TSC_CR_TSCE ((uint32_t)0x00000001) /!<Touch sensing controller enable /
bogdanm	85:024bf7f99721	4656	#define TSC_CR_START ((uint32_t)0x00000002) /!<Start acquisition /
bogdanm	85:024bf7f99721	4657	#define TSC_CR_AM ((uint32_t)0x00000004) /!<Acquisition mode /
bogdanm	85:024bf7f99721	4658	#define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /!<Synchronization pin polarity /
bogdanm	85:024bf7f99721	4659	#define TSC_CR_IODEF ((uint32_t)0x00000010) /!<IO default mode /
bogdanm	85:024bf7f99721	4660
bogdanm	85:024bf7f99721	4661	#define TSC_CR_MCV ((uint32_t)0x000000E0) /!<MCV[2:0] bits (Max Count Value) /
bogdanm	85:024bf7f99721	4662	#define TSC_CR_MCV_0 ((uint32_t)0x00000020) /!<Bit 0 /
bogdanm	85:024bf7f99721	4663	#define TSC_CR_MCV_1 ((uint32_t)0x00000040) /!<Bit 1 /
bogdanm	85:024bf7f99721	4664	#define TSC_CR_MCV_2 ((uint32_t)0x00000080) /!<Bit 2 /
bogdanm	85:024bf7f99721	4665
bogdanm	85:024bf7f99721	4666	#define TSC_CR_PGPSC ((uint32_t)0x00007000) /!<PGPSC[2:0] bits (Pulse Generator Prescaler) /
bogdanm	85:024bf7f99721	4667	#define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /!<Bit 0 /
bogdanm	85:024bf7f99721	4668	#define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /!<Bit 1 /
bogdanm	85:024bf7f99721	4669	#define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /!<Bit 2 /
bogdanm	85:024bf7f99721	4670
bogdanm	85:024bf7f99721	4671	#define TSC_CR_SSPSC ((uint32_t)0x00008000) /!<Spread Spectrum Prescaler /
bogdanm	85:024bf7f99721	4672	#define TSC_CR_SSE ((uint32_t)0x00010000) /!<Spread Spectrum Enable /
bogdanm	85:024bf7f99721	4673
bogdanm	85:024bf7f99721	4674	#define TSC_CR_SSD ((uint32_t)0x00FE0000) /!<SSD[6:0] bits (Spread Spectrum Deviation) /
bogdanm	85:024bf7f99721	4675	#define TSC_CR_SSD_0 ((uint32_t)0x00020000) /!<Bit 0 /
bogdanm	85:024bf7f99721	4676	#define TSC_CR_SSD_1 ((uint32_t)0x00040000) /!<Bit 1 /
bogdanm	85:024bf7f99721	4677	#define TSC_CR_SSD_2 ((uint32_t)0x00080000) /!<Bit 2 /
bogdanm	85:024bf7f99721	4678	#define TSC_CR_SSD_3 ((uint32_t)0x00100000) /!<Bit 3 /
bogdanm	85:024bf7f99721	4679	#define TSC_CR_SSD_4 ((uint32_t)0x00200000) /!<Bit 4 /
bogdanm	85:024bf7f99721	4680	#define TSC_CR_SSD_5 ((uint32_t)0x00400000) /!<Bit 5 /
bogdanm	85:024bf7f99721	4681	#define TSC_CR_SSD_6 ((uint32_t)0x00800000) /!<Bit 6 /
bogdanm	85:024bf7f99721	4682
bogdanm	85:024bf7f99721	4683	#define TSC_CR_CTPL ((uint32_t)0x0F000000) /!<CTPL[3:0] bits (Charge Transfer pulse low) /
bogdanm	85:024bf7f99721	4684	#define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /!<Bit 0 /
bogdanm	85:024bf7f99721	4685	#define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /!<Bit 1 /
bogdanm	85:024bf7f99721	4686	#define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /!<Bit 2 /
bogdanm	85:024bf7f99721	4687	#define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /!<Bit 3 /
bogdanm	85:024bf7f99721	4688
bogdanm	85:024bf7f99721	4689	#define TSC_CR_CTPH ((uint32_t)0xF0000000) /!<CTPH[3:0] bits (Charge Transfer pulse high) /
bogdanm	85:024bf7f99721	4690	#define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /!<Bit 0 /
bogdanm	85:024bf7f99721	4691	#define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /!<Bit 1 /
bogdanm	85:024bf7f99721	4692	#define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /!<Bit 2 /
bogdanm	85:024bf7f99721	4693	#define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /!<Bit 3 /
bogdanm	85:024bf7f99721	4694
bogdanm	85:024bf7f99721	4695	/***************** Bit definition for TSC_IER register ******************/
bogdanm	85:024bf7f99721	4696	#define TSC_IER_EOAIE ((uint32_t)0x00000001) /!<End of acquisition interrupt enable /
bogdanm	85:024bf7f99721	4697	#define TSC_IER_MCEIE ((uint32_t)0x00000002) /!<Max count error interrupt enable /
bogdanm	85:024bf7f99721	4698
bogdanm	85:024bf7f99721	4699	/***************** Bit definition for TSC_ICR register ******************/
bogdanm	85:024bf7f99721	4700	#define TSC_ICR_EOAIC ((uint32_t)0x00000001) /!<End of acquisition interrupt clear /
bogdanm	85:024bf7f99721	4701	#define TSC_ICR_MCEIC ((uint32_t)0x00000002) /!<Max count error interrupt clear /
bogdanm	85:024bf7f99721	4702
bogdanm	85:024bf7f99721	4703	/***************** Bit definition for TSC_ISR register ******************/
bogdanm	85:024bf7f99721	4704	#define TSC_ISR_EOAF ((uint32_t)0x00000001) /!<End of acquisition flag /
bogdanm	85:024bf7f99721	4705	#define TSC_ISR_MCEF ((uint32_t)0x00000002) /!<Max count error flag /
bogdanm	85:024bf7f99721	4706
bogdanm	85:024bf7f99721	4707	/***************** Bit definition for TSC_IOHCR register ****************/
bogdanm	85:024bf7f99721	4708	#define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4709	#define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4710	#define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4711	#define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4712	#define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4713	#define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4714	#define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4715	#define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4716	#define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4717	#define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4718	#define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4719	#define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4720	#define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4721	#define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4722	#define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4723	#define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4724	#define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4725	#define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4726	#define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4727	#define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4728	#define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4729	#define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4730	#define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4731	#define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4732	#define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4733	#define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4734	#define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4735	#define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4736	#define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4737	#define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4738	#define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4739	#define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 schmitt trigger hysteresis mode /
bogdanm	85:024bf7f99721	4740
bogdanm	85:024bf7f99721	4741	/***************** Bit definition for TSC_IOASCR register ***************/
bogdanm	85:024bf7f99721	4742	#define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 analog switch enable /
bogdanm	85:024bf7f99721	4743	#define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 analog switch enable /
bogdanm	85:024bf7f99721	4744	#define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 analog switch enable /
bogdanm	85:024bf7f99721	4745	#define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 analog switch enable /
bogdanm	85:024bf7f99721	4746	#define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 analog switch enable /
bogdanm	85:024bf7f99721	4747	#define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 analog switch enable /
bogdanm	85:024bf7f99721	4748	#define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 analog switch enable /
bogdanm	85:024bf7f99721	4749	#define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 analog switch enable /
bogdanm	85:024bf7f99721	4750	#define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 analog switch enable /
bogdanm	85:024bf7f99721	4751	#define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 analog switch enable /
bogdanm	85:024bf7f99721	4752	#define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 analog switch enable /
bogdanm	85:024bf7f99721	4753	#define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 analog switch enable /
bogdanm	85:024bf7f99721	4754	#define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 analog switch enable /
bogdanm	85:024bf7f99721	4755	#define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 analog switch enable /
bogdanm	85:024bf7f99721	4756	#define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 analog switch enable /
bogdanm	85:024bf7f99721	4757	#define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 analog switch enable /
bogdanm	85:024bf7f99721	4758	#define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 analog switch enable /
bogdanm	85:024bf7f99721	4759	#define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 analog switch enable /
bogdanm	85:024bf7f99721	4760	#define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 analog switch enable /
bogdanm	85:024bf7f99721	4761	#define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 analog switch enable /
bogdanm	85:024bf7f99721	4762	#define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 analog switch enable /
bogdanm	85:024bf7f99721	4763	#define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 analog switch enable /
bogdanm	85:024bf7f99721	4764	#define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 analog switch enable /
bogdanm	85:024bf7f99721	4765	#define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 analog switch enable /
bogdanm	85:024bf7f99721	4766	#define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 analog switch enable /
bogdanm	85:024bf7f99721	4767	#define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 analog switch enable /
bogdanm	85:024bf7f99721	4768	#define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 analog switch enable /
bogdanm	85:024bf7f99721	4769	#define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 analog switch enable /
bogdanm	85:024bf7f99721	4770	#define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 analog switch enable /
bogdanm	85:024bf7f99721	4771	#define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 analog switch enable /
bogdanm	85:024bf7f99721	4772	#define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 analog switch enable /
bogdanm	85:024bf7f99721	4773	#define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 analog switch enable /
bogdanm	85:024bf7f99721	4774
bogdanm	85:024bf7f99721	4775	/***************** Bit definition for TSC_IOSCR register ****************/
bogdanm	85:024bf7f99721	4776	#define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 sampling mode /
bogdanm	85:024bf7f99721	4777	#define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 sampling mode /
bogdanm	85:024bf7f99721	4778	#define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 sampling mode /
bogdanm	85:024bf7f99721	4779	#define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 sampling mode /
bogdanm	85:024bf7f99721	4780	#define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 sampling mode /
bogdanm	85:024bf7f99721	4781	#define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 sampling mode /
bogdanm	85:024bf7f99721	4782	#define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 sampling mode /
bogdanm	85:024bf7f99721	4783	#define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 sampling mode /
bogdanm	85:024bf7f99721	4784	#define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 sampling mode /
bogdanm	85:024bf7f99721	4785	#define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 sampling mode /
bogdanm	85:024bf7f99721	4786	#define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 sampling mode /
bogdanm	85:024bf7f99721	4787	#define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 sampling mode /
bogdanm	85:024bf7f99721	4788	#define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 sampling mode /
bogdanm	85:024bf7f99721	4789	#define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 sampling mode /
bogdanm	85:024bf7f99721	4790	#define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 sampling mode /
bogdanm	85:024bf7f99721	4791	#define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 sampling mode /
bogdanm	85:024bf7f99721	4792	#define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 sampling mode /
bogdanm	85:024bf7f99721	4793	#define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 sampling mode /
bogdanm	85:024bf7f99721	4794	#define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 sampling mode /
bogdanm	85:024bf7f99721	4795	#define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 sampling mode /
bogdanm	85:024bf7f99721	4796	#define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 sampling mode /
bogdanm	85:024bf7f99721	4797	#define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 sampling mode /
bogdanm	85:024bf7f99721	4798	#define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 sampling mode /
bogdanm	85:024bf7f99721	4799	#define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 sampling mode /
bogdanm	85:024bf7f99721	4800	#define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 sampling mode /
bogdanm	85:024bf7f99721	4801	#define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 sampling mode /
bogdanm	85:024bf7f99721	4802	#define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 sampling mode /
bogdanm	85:024bf7f99721	4803	#define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 sampling mode /
bogdanm	85:024bf7f99721	4804	#define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 sampling mode /
bogdanm	85:024bf7f99721	4805	#define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 sampling mode /
bogdanm	85:024bf7f99721	4806	#define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 sampling mode /
bogdanm	85:024bf7f99721	4807	#define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 sampling mode /
bogdanm	85:024bf7f99721	4808
bogdanm	85:024bf7f99721	4809	/***************** Bit definition for TSC_IOCCR register ****************/
bogdanm	85:024bf7f99721	4810	#define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /!<GROUP1_IO1 channel mode /
bogdanm	85:024bf7f99721	4811	#define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /!<GROUP1_IO2 channel mode /
bogdanm	85:024bf7f99721	4812	#define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /!<GROUP1_IO3 channel mode /
bogdanm	85:024bf7f99721	4813	#define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /!<GROUP1_IO4 channel mode /
bogdanm	85:024bf7f99721	4814	#define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /!<GROUP2_IO1 channel mode /
bogdanm	85:024bf7f99721	4815	#define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /!<GROUP2_IO2 channel mode /
bogdanm	85:024bf7f99721	4816	#define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /!<GROUP2_IO3 channel mode /
bogdanm	85:024bf7f99721	4817	#define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /!<GROUP2_IO4 channel mode /
bogdanm	85:024bf7f99721	4818	#define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /!<GROUP3_IO1 channel mode /
bogdanm	85:024bf7f99721	4819	#define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /!<GROUP3_IO2 channel mode /
bogdanm	85:024bf7f99721	4820	#define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /!<GROUP3_IO3 channel mode /
bogdanm	85:024bf7f99721	4821	#define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /!<GROUP3_IO4 channel mode /
bogdanm	85:024bf7f99721	4822	#define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /!<GROUP4_IO1 channel mode /
bogdanm	85:024bf7f99721	4823	#define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /!<GROUP4_IO2 channel mode /
bogdanm	85:024bf7f99721	4824	#define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /!<GROUP4_IO3 channel mode /
bogdanm	85:024bf7f99721	4825	#define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /!<GROUP4_IO4 channel mode /
bogdanm	85:024bf7f99721	4826	#define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /!<GROUP5_IO1 channel mode /
bogdanm	85:024bf7f99721	4827	#define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /!<GROUP5_IO2 channel mode /
bogdanm	85:024bf7f99721	4828	#define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /!<GROUP5_IO3 channel mode /
bogdanm	85:024bf7f99721	4829	#define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /!<GROUP5_IO4 channel mode /
bogdanm	85:024bf7f99721	4830	#define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /!<GROUP6_IO1 channel mode /
bogdanm	85:024bf7f99721	4831	#define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /!<GROUP6_IO2 channel mode /
bogdanm	85:024bf7f99721	4832	#define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /!<GROUP6_IO3 channel mode /
bogdanm	85:024bf7f99721	4833	#define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /!<GROUP6_IO4 channel mode /
bogdanm	85:024bf7f99721	4834	#define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /!<GROUP7_IO1 channel mode /
bogdanm	85:024bf7f99721	4835	#define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /!<GROUP7_IO2 channel mode /
bogdanm	85:024bf7f99721	4836	#define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /!<GROUP7_IO3 channel mode /
bogdanm	85:024bf7f99721	4837	#define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /!<GROUP7_IO4 channel mode /
bogdanm	85:024bf7f99721	4838	#define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /!<GROUP8_IO1 channel mode /
bogdanm	85:024bf7f99721	4839	#define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /!<GROUP8_IO2 channel mode /
bogdanm	85:024bf7f99721	4840	#define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /!<GROUP8_IO3 channel mode /
bogdanm	85:024bf7f99721	4841	#define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /!<GROUP8_IO4 channel mode /
bogdanm	85:024bf7f99721	4842
bogdanm	85:024bf7f99721	4843	/***************** Bit definition for TSC_IOGCSR register ***************/
bogdanm	85:024bf7f99721	4844	#define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /!<Analog IO GROUP1 enable /
bogdanm	85:024bf7f99721	4845	#define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /!<Analog IO GROUP2 enable /
bogdanm	85:024bf7f99721	4846	#define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /!<Analog IO GROUP3 enable /
bogdanm	85:024bf7f99721	4847	#define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /!<Analog IO GROUP4 enable /
bogdanm	85:024bf7f99721	4848	#define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /!<Analog IO GROUP5 enable /
bogdanm	85:024bf7f99721	4849	#define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /!<Analog IO GROUP6 enable /
bogdanm	85:024bf7f99721	4850	#define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /!<Analog IO GROUP7 enable /
bogdanm	85:024bf7f99721	4851	#define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /!<Analog IO GROUP8 enable /
bogdanm	85:024bf7f99721	4852	#define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /!<Analog IO GROUP1 status /
bogdanm	85:024bf7f99721	4853	#define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /!<Analog IO GROUP2 status /
bogdanm	85:024bf7f99721	4854	#define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /!<Analog IO GROUP3 status /
bogdanm	85:024bf7f99721	4855	#define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /!<Analog IO GROUP4 status /
bogdanm	85:024bf7f99721	4856	#define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /!<Analog IO GROUP5 status /
bogdanm	85:024bf7f99721	4857	#define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /!<Analog IO GROUP6 status /
bogdanm	85:024bf7f99721	4858	#define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /!<Analog IO GROUP7 status /
bogdanm	85:024bf7f99721	4859	#define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /!<Analog IO GROUP8 status /
bogdanm	85:024bf7f99721	4860
bogdanm	85:024bf7f99721	4861	/***************** Bit definition for TSC_IOGXCR register ***************/
bogdanm	85:024bf7f99721	4862	#define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /!<CNT[13:0] bits (Counter value) /
bogdanm	85:024bf7f99721	4863
bogdanm	85:024bf7f99721	4864	/******************************************************************************/
bogdanm	85:024bf7f99721	4865	/* */
bogdanm	85:024bf7f99721	4866	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
bogdanm	85:024bf7f99721	4867	/* */
bogdanm	85:024bf7f99721	4868	/******************************************************************************/
bogdanm	85:024bf7f99721	4869	/**************** Bit definition for USART_CR1 register *****************/
bogdanm	85:024bf7f99721	4870	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
bogdanm	85:024bf7f99721	4871	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
bogdanm	85:024bf7f99721	4872	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
bogdanm	85:024bf7f99721	4873	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
bogdanm	85:024bf7f99721	4874	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
bogdanm	85:024bf7f99721	4875	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
bogdanm	85:024bf7f99721	4876	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
bogdanm	85:024bf7f99721	4877	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
bogdanm	85:024bf7f99721	4878	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
bogdanm	85:024bf7f99721	4879	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
bogdanm	85:024bf7f99721	4880	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
bogdanm	85:024bf7f99721	4881	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
bogdanm	85:024bf7f99721	4882	#define USART_CR1_M0 ((uint32_t)0x00001000) /!< Word length bit 0 /
bogdanm	85:024bf7f99721	4883	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
bogdanm	85:024bf7f99721	4884	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
bogdanm	85:024bf7f99721	4885	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
bogdanm	85:024bf7f99721	4886	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
bogdanm	85:024bf7f99721	4887	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
bogdanm	85:024bf7f99721	4888	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
bogdanm	85:024bf7f99721	4889	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
bogdanm	85:024bf7f99721	4890	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
bogdanm	85:024bf7f99721	4891	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
bogdanm	85:024bf7f99721	4892	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
bogdanm	85:024bf7f99721	4893	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
bogdanm	85:024bf7f99721	4894	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
bogdanm	85:024bf7f99721	4895	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
bogdanm	85:024bf7f99721	4896	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
bogdanm	85:024bf7f99721	4897	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
bogdanm	85:024bf7f99721	4898	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
bogdanm	85:024bf7f99721	4899	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
bogdanm	85:024bf7f99721	4900	#define USART_CR1_M1 ((uint32_t)0x10000000) /!< Word length bit 1 /
bogdanm	85:024bf7f99721	4901	#define USART_CR1_M ((uint32_t)0x10001000) /!< [M1:M0] Word length /
bogdanm	85:024bf7f99721	4902
bogdanm	85:024bf7f99721	4903	/**************** Bit definition for USART_CR2 register *****************/
bogdanm	85:024bf7f99721	4904	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
bogdanm	85:024bf7f99721	4905	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
bogdanm	85:024bf7f99721	4906	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
bogdanm	85:024bf7f99721	4907	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
bogdanm	85:024bf7f99721	4908	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
bogdanm	85:024bf7f99721	4909	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
bogdanm	85:024bf7f99721	4910	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
bogdanm	85:024bf7f99721	4911	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
bogdanm	85:024bf7f99721	4912	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
bogdanm	85:024bf7f99721	4913	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
bogdanm	85:024bf7f99721	4914	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
bogdanm	85:024bf7f99721	4915	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
bogdanm	85:024bf7f99721	4916	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
bogdanm	85:024bf7f99721	4917	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
bogdanm	85:024bf7f99721	4918	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
bogdanm	85:024bf7f99721	4919	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
bogdanm	85:024bf7f99721	4920	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
bogdanm	85:024bf7f99721	4921	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
bogdanm	85:024bf7f99721	4922	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
bogdanm	85:024bf7f99721	4923	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
bogdanm	85:024bf7f99721	4924	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
bogdanm	85:024bf7f99721	4925	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
bogdanm	85:024bf7f99721	4926
bogdanm	85:024bf7f99721	4927	/**************** Bit definition for USART_CR3 register *****************/
bogdanm	85:024bf7f99721	4928	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
bogdanm	85:024bf7f99721	4929	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
bogdanm	85:024bf7f99721	4930	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
bogdanm	85:024bf7f99721	4931	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
bogdanm	85:024bf7f99721	4932	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
bogdanm	85:024bf7f99721	4933	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
bogdanm	85:024bf7f99721	4934	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
bogdanm	85:024bf7f99721	4935	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
bogdanm	85:024bf7f99721	4936	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
bogdanm	85:024bf7f99721	4937	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
bogdanm	85:024bf7f99721	4938	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
bogdanm	85:024bf7f99721	4939	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
bogdanm	85:024bf7f99721	4940	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
bogdanm	85:024bf7f99721	4941	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
bogdanm	85:024bf7f99721	4942	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
bogdanm	85:024bf7f99721	4943	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
bogdanm	85:024bf7f99721	4944	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
bogdanm	85:024bf7f99721	4945	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
bogdanm	85:024bf7f99721	4946	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
bogdanm	85:024bf7f99721	4947	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
bogdanm	85:024bf7f99721	4948	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
bogdanm	85:024bf7f99721	4949	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
bogdanm	85:024bf7f99721	4950	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
bogdanm	85:024bf7f99721	4951	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
bogdanm	85:024bf7f99721	4952
bogdanm	85:024bf7f99721	4953	/**************** Bit definition for USART_BRR register *****************/
bogdanm	92:4fc01daae5a5	4954	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /!< Fraction of USARTDIV /
bogdanm	92:4fc01daae5a5	4955	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /!< Mantissa of USARTDIV /
bogdanm	85:024bf7f99721	4956
bogdanm	85:024bf7f99721	4957	/**************** Bit definition for USART_GTPR register ****************/
bogdanm	92:4fc01daae5a5	4958	#define USART_GTPR_PSC ((uint32_t)0x000000FF) /!< PSC[7:0] bits (Prescaler value) /
bogdanm	92:4fc01daae5a5	4959	#define USART_GTPR_GT ((uint32_t)0x0000FF00) /!< GT[7:0] bits (Guard time value) /
bogdanm	85:024bf7f99721	4960
bogdanm	85:024bf7f99721	4961
bogdanm	85:024bf7f99721	4962	/***************** Bit definition for USART_RTOR register ***************/
bogdanm	85:024bf7f99721	4963	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
bogdanm	85:024bf7f99721	4964	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
bogdanm	85:024bf7f99721	4965
bogdanm	85:024bf7f99721	4966	/***************** Bit definition for USART_RQR register ****************/
bogdanm	92:4fc01daae5a5	4967	#define USART_RQR_ABRRQ ((uint32_t)0x00000001) /!< Auto-Baud Rate Request /
bogdanm	92:4fc01daae5a5	4968	#define USART_RQR_SBKRQ ((uint32_t)0x00000002) /!< Send Break Request /
bogdanm	92:4fc01daae5a5	4969	#define USART_RQR_MMRQ ((uint32_t)0x00000004) /!< Mute Mode Request /
bogdanm	92:4fc01daae5a5	4970	#define USART_RQR_RXFRQ ((uint32_t)0x00000008) /!< Receive Data flush Request /
bogdanm	92:4fc01daae5a5	4971	#define USART_RQR_TXFRQ ((uint32_t)0x00000010) /!< Transmit data flush Request /
bogdanm	85:024bf7f99721	4972
bogdanm	85:024bf7f99721	4973	/***************** Bit definition for USART_ISR register ****************/
bogdanm	85:024bf7f99721	4974	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
bogdanm	85:024bf7f99721	4975	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
bogdanm	85:024bf7f99721	4976	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
bogdanm	85:024bf7f99721	4977	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
bogdanm	85:024bf7f99721	4978	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
bogdanm	85:024bf7f99721	4979	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
bogdanm	85:024bf7f99721	4980	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
bogdanm	85:024bf7f99721	4981	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
bogdanm	85:024bf7f99721	4982	#define USART_ISR_LBDF ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
bogdanm	85:024bf7f99721	4983	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
bogdanm	85:024bf7f99721	4984	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
bogdanm	85:024bf7f99721	4985	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
bogdanm	85:024bf7f99721	4986	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
bogdanm	85:024bf7f99721	4987	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
bogdanm	85:024bf7f99721	4988	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
bogdanm	85:024bf7f99721	4989	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
bogdanm	85:024bf7f99721	4990	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
bogdanm	85:024bf7f99721	4991	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
bogdanm	85:024bf7f99721	4992	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
bogdanm	85:024bf7f99721	4993	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
bogdanm	85:024bf7f99721	4994	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
bogdanm	85:024bf7f99721	4995	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
bogdanm	85:024bf7f99721	4996
bogdanm	85:024bf7f99721	4997	/***************** Bit definition for USART_ICR register ****************/
bogdanm	85:024bf7f99721	4998	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
bogdanm	85:024bf7f99721	4999	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
bogdanm	85:024bf7f99721	5000	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
bogdanm	85:024bf7f99721	5001	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
bogdanm	85:024bf7f99721	5002	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
bogdanm	85:024bf7f99721	5003	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
bogdanm	85:024bf7f99721	5004	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
bogdanm	85:024bf7f99721	5005	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
bogdanm	85:024bf7f99721	5006	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
bogdanm	85:024bf7f99721	5007	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
bogdanm	85:024bf7f99721	5008	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
bogdanm	85:024bf7f99721	5009	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
bogdanm	85:024bf7f99721	5010
bogdanm	85:024bf7f99721	5011	/***************** Bit definition for USART_RDR register ****************/
bogdanm	85:024bf7f99721	5012	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
bogdanm	85:024bf7f99721	5013
bogdanm	85:024bf7f99721	5014	/***************** Bit definition for USART_TDR register ****************/
bogdanm	85:024bf7f99721	5015	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
bogdanm	85:024bf7f99721	5016
bogdanm	85:024bf7f99721	5017	/******************************************************************************/
bogdanm	85:024bf7f99721	5018	/* */
bogdanm	85:024bf7f99721	5019	/* USB Device General registers */
bogdanm	85:024bf7f99721	5020	/* */
bogdanm	85:024bf7f99721	5021	/******************************************************************************/
bogdanm	85:024bf7f99721	5022	#define USB_CNTR (USB_BASE + 0x40) /!< Control register /
bogdanm	85:024bf7f99721	5023	#define USB_ISTR (USB_BASE + 0x44) /!< Interrupt status register /
bogdanm	85:024bf7f99721	5024	#define USB_FNR (USB_BASE + 0x48) /!< Frame number register /
bogdanm	85:024bf7f99721	5025	#define USB_DADDR (USB_BASE + 0x4C) /!< Device address register /
bogdanm	85:024bf7f99721	5026	#define USB_BTABLE (USB_BASE + 0x50) /!< Buffer Table address register /
bogdanm	85:024bf7f99721	5027	#define USB_LPMCSR (USB_BASE + 0x54) /!< LPM Control and Status register /
bogdanm	85:024bf7f99721	5028	#define USB_BCDR (USB_BASE + 0x58) /!< Battery Charging detector register/
bogdanm	85:024bf7f99721	5029
bogdanm	85:024bf7f99721	5030	/************************** ISTR interrupt events ***********************/
bogdanm	85:024bf7f99721	5031	#define USB_ISTR_CTR ((uint16_t)0x8000) /!< Correct TRansfer (clear-only bit) /
bogdanm	85:024bf7f99721	5032	#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /!< DMA OVeR/underrun (clear-only bit) /
bogdanm	85:024bf7f99721	5033	#define USB_ISTR_ERR ((uint16_t)0x2000) /!< ERRor (clear-only bit) /
bogdanm	85:024bf7f99721	5034	#define USB_ISTR_WKUP ((uint16_t)0x1000) /!< WaKe UP (clear-only bit) /
bogdanm	85:024bf7f99721	5035	#define USB_ISTR_SUSP ((uint16_t)0x0800) /!< SUSPend (clear-only bit) /
bogdanm	85:024bf7f99721	5036	#define USB_ISTR_RESET ((uint16_t)0x0400) /!< RESET (clear-only bit) /
bogdanm	85:024bf7f99721	5037	#define USB_ISTR_SOF ((uint16_t)0x0200) /!< Start Of Frame (clear-only bit) /
bogdanm	85:024bf7f99721	5038	#define USB_ISTR_ESOF ((uint16_t)0x0100) /!< Expected Start Of Frame (clear-only bit) /
bogdanm	85:024bf7f99721	5039	#define USB_ISTR_L1REQ ((uint16_t)0x0080) /!< LPM L1 state request /
bogdanm	85:024bf7f99721	5040	#define USB_ISTR_DIR ((uint16_t)0x0010) /!< DIRection of transaction (read-only bit) /
bogdanm	85:024bf7f99721	5041	#define USB_ISTR_EP_ID ((uint16_t)0x000F) /!< EndPoint IDentifier (read-only bit) /
bogdanm	85:024bf7f99721	5042
bogdanm	85:024bf7f99721	5043	#define USB_CLR_CTR (~USB_ISTR_CTR) /!< clear Correct TRansfer bit /
bogdanm	85:024bf7f99721	5044	#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /!< clear DMA OVeR/underrun bit/
bogdanm	85:024bf7f99721	5045	#define USB_CLR_ERR (~USB_ISTR_ERR) /!< clear ERRor bit /
bogdanm	85:024bf7f99721	5046	#define USB_CLR_WKUP (~USB_ISTR_WKUP) /!< clear WaKe UP bit /
bogdanm	85:024bf7f99721	5047	#define USB_CLR_SUSP (~USB_ISTR_SUSP) /!< clear SUSPend bit /
bogdanm	85:024bf7f99721	5048	#define USB_CLR_RESET (~USB_ISTR_RESET) /!< clear RESET bit /
bogdanm	85:024bf7f99721	5049	#define USB_CLR_SOF (~USB_ISTR_SOF) /!< clear Start Of Frame bit /
bogdanm	85:024bf7f99721	5050	#define USB_CLR_ESOF (~USB_ISTR_ESOF) /!< clear Expected Start Of Frame bit /
bogdanm	85:024bf7f99721	5051	#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /!< clear LPM L1 bit /
bogdanm	85:024bf7f99721	5052
bogdanm	85:024bf7f99721	5053	/*********************** CNTR control register bits definitions *********/
bogdanm	85:024bf7f99721	5054	#define USB_CNTR_CTRM ((uint16_t)0x8000) /!< Correct TRansfer Mask /
bogdanm	85:024bf7f99721	5055	#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /!< DMA OVeR/underrun Mask /
bogdanm	85:024bf7f99721	5056	#define USB_CNTR_ERRM ((uint16_t)0x2000) /!< ERRor Mask /
bogdanm	85:024bf7f99721	5057	#define USB_CNTR_WKUPM ((uint16_t)0x1000) /!< WaKe UP Mask /
bogdanm	85:024bf7f99721	5058	#define USB_CNTR_SUSPM ((uint16_t)0x0800) /!< SUSPend Mask /
bogdanm	85:024bf7f99721	5059	#define USB_CNTR_RESETM ((uint16_t)0x0400) /!< RESET Mask /
bogdanm	85:024bf7f99721	5060	#define USB_CNTR_SOFM ((uint16_t)0x0200) /!< Start Of Frame Mask /
bogdanm	85:024bf7f99721	5061	#define USB_CNTR_ESOFM ((uint16_t)0x0100) /!< Expected Start Of Frame Mask /
bogdanm	85:024bf7f99721	5062	#define USB_CNTR_L1REQM ((uint16_t)0x0080) /!< LPM L1 state request interrupt mask /
bogdanm	85:024bf7f99721	5063	#define USB_CNTR_L1RESUME ((uint16_t)0x0020) /!< LPM L1 Resume request /
bogdanm	85:024bf7f99721	5064	#define USB_CNTR_RESUME ((uint16_t)0x0010) /!< RESUME request /
bogdanm	85:024bf7f99721	5065	#define USB_CNTR_FSUSP ((uint16_t)0x0008) /!< Force SUSPend /
bogdanm	85:024bf7f99721	5066	#define USB_CNTR_LPMODE ((uint16_t)0x0004) /!< Low-power MODE /
bogdanm	85:024bf7f99721	5067	#define USB_CNTR_PDWN ((uint16_t)0x0002) /!< Power DoWN /
bogdanm	85:024bf7f99721	5068	#define USB_CNTR_FRES ((uint16_t)0x0001) /!< Force USB RESet /
bogdanm	85:024bf7f99721	5069
bogdanm	85:024bf7f99721	5070	/*********************** BCDR control register bits definitions *********/
bogdanm	85:024bf7f99721	5071	#define USB_BCDR_DPPU ((uint16_t)0x8000) /!< DP Pull-up Enable /
bogdanm	85:024bf7f99721	5072	#define USB_BCDR_PS2DET ((uint16_t)0x0080) /!< PS2 port or proprietary charger detected /
bogdanm	85:024bf7f99721	5073	#define USB_BCDR_SDET ((uint16_t)0x0040) /!< Secondary detection (SD) status /
bogdanm	85:024bf7f99721	5074	#define USB_BCDR_PDET ((uint16_t)0x0020) /!< Primary detection (PD) status /
bogdanm	85:024bf7f99721	5075	#define USB_BCDR_DCDET ((uint16_t)0x0010) /!< Data contact detection (DCD) status /
bogdanm	85:024bf7f99721	5076	#define USB_BCDR_SDEN ((uint16_t)0x0008) /!< Secondary detection (SD) mode enable /
bogdanm	85:024bf7f99721	5077	#define USB_BCDR_PDEN ((uint16_t)0x0004) /!< Primary detection (PD) mode enable /
bogdanm	85:024bf7f99721	5078	#define USB_BCDR_DCDEN ((uint16_t)0x0002) /!< Data contact detection (DCD) mode enable /
bogdanm	85:024bf7f99721	5079	#define USB_BCDR_BCDEN ((uint16_t)0x0001) /!< Battery charging detector (BCD) enable /
bogdanm	85:024bf7f99721	5080
bogdanm	85:024bf7f99721	5081	/************************* LPM register bits definitions ****************/
bogdanm	85:024bf7f99721	5082	#define USB_LPMCSR_BESL ((uint16_t)0x00F0) /!< BESL value received with last ACKed LPM Token /
bogdanm	85:024bf7f99721	5083	#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008) /!< bRemoteWake value received with last ACKed LPM Token /
bogdanm	85:024bf7f99721	5084	#define USB_LPMCSR_LPMACK ((uint16_t)0x0002) /!< LPM Token acknowledge enable/
bogdanm	85:024bf7f99721	5085	#define USB_LPMCSR_LMPEN ((uint16_t)0x0001) /!< LPM support enable /
bogdanm	85:024bf7f99721	5086
bogdanm	85:024bf7f99721	5087	/****************** FNR Frame Number Register bit definitions **********/
bogdanm	85:024bf7f99721	5088	#define USB_FNR_RXDP ((uint16_t)0x8000) /!< status of D+ data line /
bogdanm	85:024bf7f99721	5089	#define USB_FNR_RXDM ((uint16_t)0x4000) /!< status of D- data line /
bogdanm	85:024bf7f99721	5090	#define USB_FNR_LCK ((uint16_t)0x2000) /!< LoCKed /
bogdanm	85:024bf7f99721	5091	#define USB_FNR_LSOF ((uint16_t)0x1800) /!< Lost SOF /
bogdanm	85:024bf7f99721	5092	#define USB_FNR_FN ((uint16_t)0x07FF) /!< Frame Number /
bogdanm	85:024bf7f99721	5093
bogdanm	85:024bf7f99721	5094	/****************** DADDR Device ADDRess bit definitions **************/
bogdanm	85:024bf7f99721	5095	#define USB_DADDR_EF ((uint8_t)0x80) /!< USB device address Enable Function /
bogdanm	85:024bf7f99721	5096	#define USB_DADDR_ADD ((uint8_t)0x7F) /!< USB device address /
bogdanm	85:024bf7f99721	5097
bogdanm	85:024bf7f99721	5098	/**************************** Endpoint register ***********************/
bogdanm	85:024bf7f99721	5099	#define USB_EP0R USB_BASE /!< endpoint 0 register address /
bogdanm	85:024bf7f99721	5100	#define USB_EP1R (USB_BASE + 0x04) /!< endpoint 1 register address /
bogdanm	85:024bf7f99721	5101	#define USB_EP2R (USB_BASE + 0x08) /!< endpoint 2 register address /
bogdanm	85:024bf7f99721	5102	#define USB_EP3R (USB_BASE + 0x0C) /!< endpoint 3 register address /
bogdanm	85:024bf7f99721	5103	#define USB_EP4R (USB_BASE + 0x10) /!< endpoint 4 register address /
bogdanm	85:024bf7f99721	5104	#define USB_EP5R (USB_BASE + 0x14) /!< endpoint 5 register address /
bogdanm	85:024bf7f99721	5105	#define USB_EP6R (USB_BASE + 0x18) /!< endpoint 6 register address /
bogdanm	85:024bf7f99721	5106	#define USB_EP7R (USB_BASE + 0x1C) /!< endpoint 7 register address /
bogdanm	85:024bf7f99721	5107	/* bit positions */
bogdanm	85:024bf7f99721	5108	#define USB_EP_CTR_RX ((uint16_t)0x8000) /!< EndPoint Correct TRansfer RX /
bogdanm	85:024bf7f99721	5109	#define USB_EP_DTOG_RX ((uint16_t)0x4000) /!< EndPoint Data TOGGLE RX /
bogdanm	85:024bf7f99721	5110	#define USB_EPRX_STAT ((uint16_t)0x3000) /!< EndPoint RX STATus bit field /
bogdanm	85:024bf7f99721	5111	#define USB_EP_SETUP ((uint16_t)0x0800) /!< EndPoint SETUP /
bogdanm	85:024bf7f99721	5112	#define USB_EP_T_FIELD ((uint16_t)0x0600) /!< EndPoint TYPE /
bogdanm	85:024bf7f99721	5113	#define USB_EP_KIND ((uint16_t)0x0100) /!< EndPoint KIND /
bogdanm	85:024bf7f99721	5114	#define USB_EP_CTR_TX ((uint16_t)0x0080) /!< EndPoint Correct TRansfer TX /
bogdanm	85:024bf7f99721	5115	#define USB_EP_DTOG_TX ((uint16_t)0x0040) /!< EndPoint Data TOGGLE TX /
bogdanm	85:024bf7f99721	5116	#define USB_EPTX_STAT ((uint16_t)0x0030) /!< EndPoint TX STATus bit field /
bogdanm	85:024bf7f99721	5117	#define USB_EPADDR_FIELD ((uint16_t)0x000F) /!< EndPoint ADDRess FIELD /
bogdanm	85:024bf7f99721	5118
bogdanm	85:024bf7f99721	5119	/* EndPoint REGister MASK (no toggle fields) */
bogdanm	85:024bf7f99721	5120	#define USB_EPREG_MASK (USB_EP_CTR_RX\|USB_EP_SETUP\|USB_EP_T_FIELD\|USB_EP_KIND\|USB_EP_CTR_TX\|USB_EPADDR_FIELD)
bogdanm	85:024bf7f99721	5121	/!< EP_TYPE[1:0] EndPoint TYPE /
bogdanm	85:024bf7f99721	5122	#define USB_EP_TYPE_MASK ((uint16_t)0x0600) /!< EndPoint TYPE Mask /
bogdanm	85:024bf7f99721	5123	#define USB_EP_BULK ((uint16_t)0x0000) /!< EndPoint BULK /
bogdanm	85:024bf7f99721	5124	#define USB_EP_CONTROL ((uint16_t)0x0200) /!< EndPoint CONTROL /
bogdanm	85:024bf7f99721	5125	#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /!< EndPoint ISOCHRONOUS /
bogdanm	85:024bf7f99721	5126	#define USB_EP_INTERRUPT ((uint16_t)0x0600) /!< EndPoint INTERRUPT /
bogdanm	85:024bf7f99721	5127	#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
bogdanm	85:024bf7f99721	5128
bogdanm	85:024bf7f99721	5129	#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /!< EP_KIND EndPoint KIND /
bogdanm	85:024bf7f99721	5130	/!< STAT_TX[1:0] STATus for TX transfer /
bogdanm	85:024bf7f99721	5131	#define USB_EP_TX_DIS ((uint16_t)0x0000) /!< EndPoint TX DISabled /
bogdanm	85:024bf7f99721	5132	#define USB_EP_TX_STALL ((uint16_t)0x0010) /!< EndPoint TX STALLed /
bogdanm	85:024bf7f99721	5133	#define USB_EP_TX_NAK ((uint16_t)0x0020) /!< EndPoint TX NAKed /
bogdanm	85:024bf7f99721	5134	#define USB_EP_TX_VALID ((uint16_t)0x0030) /!< EndPoint TX VALID /
bogdanm	85:024bf7f99721	5135	#define USB_EPTX_DTOG1 ((uint16_t)0x0010) /!< EndPoint TX Data TOGgle bit1 /
bogdanm	85:024bf7f99721	5136	#define USB_EPTX_DTOG2 ((uint16_t)0x0020) /!< EndPoint TX Data TOGgle bit2 /
bogdanm	85:024bf7f99721	5137	#define USB_EPTX_DTOGMASK (USB_EPTX_STAT\|USB_EPREG_MASK)
bogdanm	85:024bf7f99721	5138	/!< STAT_RX[1:0] STATus for RX transfer /
bogdanm	85:024bf7f99721	5139	#define USB_EP_RX_DIS ((uint16_t)0x0000) /!< EndPoint RX DISabled /
bogdanm	85:024bf7f99721	5140	#define USB_EP_RX_STALL ((uint16_t)0x1000) /!< EndPoint RX STALLed /
bogdanm	85:024bf7f99721	5141	#define USB_EP_RX_NAK ((uint16_t)0x2000) /!< EndPoint RX NAKed /
bogdanm	85:024bf7f99721	5142	#define USB_EP_RX_VALID ((uint16_t)0x3000) /!< EndPoint RX VALID /
bogdanm	85:024bf7f99721	5143	#define USB_EPRX_DTOG1 ((uint16_t)0x1000) /!< EndPoint RX Data TOGgle bit1 /
bogdanm	85:024bf7f99721	5144	#define USB_EPRX_DTOG2 ((uint16_t)0x2000) /!< EndPoint RX Data TOGgle bit1 /
bogdanm	85:024bf7f99721	5145	#define USB_EPRX_DTOGMASK (USB_EPRX_STAT\|USB_EPREG_MASK)
bogdanm	85:024bf7f99721	5146
bogdanm	85:024bf7f99721	5147	/******************************************************************************/
bogdanm	85:024bf7f99721	5148	/* */
bogdanm	85:024bf7f99721	5149	/* Window WATCHDOG (WWDG) */
bogdanm	85:024bf7f99721	5150	/* */
bogdanm	85:024bf7f99721	5151	/******************************************************************************/
bogdanm	85:024bf7f99721	5152	/***************** Bit definition for WWDG_CR register ******************/
bogdanm	85:024bf7f99721	5153	#define WWDG_CR_T ((uint32_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
bogdanm	85:024bf7f99721	5154	#define WWDG_CR_T0 ((uint32_t)0x01) /!<Bit 0 /
bogdanm	85:024bf7f99721	5155	#define WWDG_CR_T1 ((uint32_t)0x02) /!<Bit 1 /
bogdanm	85:024bf7f99721	5156	#define WWDG_CR_T2 ((uint32_t)0x04) /!<Bit 2 /
bogdanm	85:024bf7f99721	5157	#define WWDG_CR_T3 ((uint32_t)0x08) /!<Bit 3 /
bogdanm	85:024bf7f99721	5158	#define WWDG_CR_T4 ((uint32_t)0x10) /!<Bit 4 /
bogdanm	85:024bf7f99721	5159	#define WWDG_CR_T5 ((uint32_t)0x20) /!<Bit 5 /
bogdanm	85:024bf7f99721	5160	#define WWDG_CR_T6 ((uint32_t)0x40) /!<Bit 6 /
bogdanm	85:024bf7f99721	5161
bogdanm	85:024bf7f99721	5162	#define WWDG_CR_WDGA ((uint32_t)0x80) /!<Activation bit /
bogdanm	85:024bf7f99721	5163
bogdanm	85:024bf7f99721	5164	/***************** Bit definition for WWDG_CFR register *****************/
bogdanm	85:024bf7f99721	5165	#define WWDG_CFR_W ((uint32_t)0x007F) /!<W[6:0] bits (7-bit window value) /
bogdanm	85:024bf7f99721	5166	#define WWDG_CFR_W0 ((uint32_t)0x0001) /!<Bit 0 /
bogdanm	85:024bf7f99721	5167	#define WWDG_CFR_W1 ((uint32_t)0x0002) /!<Bit 1 /
bogdanm	85:024bf7f99721	5168	#define WWDG_CFR_W2 ((uint32_t)0x0004) /!<Bit 2 /
bogdanm	85:024bf7f99721	5169	#define WWDG_CFR_W3 ((uint32_t)0x0008) /!<Bit 3 /
bogdanm	85:024bf7f99721	5170	#define WWDG_CFR_W4 ((uint32_t)0x0010) /!<Bit 4 /
bogdanm	85:024bf7f99721	5171	#define WWDG_CFR_W5 ((uint32_t)0x0020) /!<Bit 5 /
bogdanm	85:024bf7f99721	5172	#define WWDG_CFR_W6 ((uint32_t)0x0040) /!<Bit 6 /
bogdanm	85:024bf7f99721	5173
bogdanm	85:024bf7f99721	5174	#define WWDG_CFR_WDGTB ((uint32_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
bogdanm	85:024bf7f99721	5175	#define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /!<Bit 0 /
bogdanm	85:024bf7f99721	5176	#define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /!<Bit 1 /
bogdanm	85:024bf7f99721	5177
bogdanm	85:024bf7f99721	5178	#define WWDG_CFR_EWI ((uint32_t)0x0200) /!<Early Wakeup Interrupt /
bogdanm	85:024bf7f99721	5179
bogdanm	85:024bf7f99721	5180	/***************** Bit definition for WWDG_SR register ******************/
bogdanm	85:024bf7f99721	5181	#define WWDG_SR_EWIF ((uint32_t)0x01) /!<Early Wakeup Interrupt Flag /
bogdanm	85:024bf7f99721	5182
bogdanm	85:024bf7f99721	5183	/**
bogdanm	85:024bf7f99721	5184	* @}
bogdanm	85:024bf7f99721	5185	*/
bogdanm	85:024bf7f99721	5186
bogdanm	85:024bf7f99721	5187	/**
bogdanm	85:024bf7f99721	5188	* @}
bogdanm	85:024bf7f99721	5189	*/
bogdanm	85:024bf7f99721	5190
bogdanm	85:024bf7f99721	5191
bogdanm	85:024bf7f99721	5192	/** @addtogroup Exported_macro
bogdanm	85:024bf7f99721	5193	* @{
bogdanm	85:024bf7f99721	5194	*/
bogdanm	85:024bf7f99721	5195
bogdanm	85:024bf7f99721	5196	/**************************** ADC Instances *******************************/
bogdanm	85:024bf7f99721	5197	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
bogdanm	85:024bf7f99721	5198
bogdanm	85:024bf7f99721	5199	#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
bogdanm	85:024bf7f99721	5200
bogdanm	85:024bf7f99721	5201	/***************************** CAN Instances ******************************/
bogdanm	85:024bf7f99721	5202	#define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
bogdanm	85:024bf7f99721	5203
bogdanm	85:024bf7f99721	5204	/**************************** COMP Instances *******************************/
bogdanm	85:024bf7f99721	5205	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
bogdanm	85:024bf7f99721	5206	((INSTANCE) == COMP2))
bogdanm	92:4fc01daae5a5	5207
bogdanm	92:4fc01daae5a5	5208	#define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
bogdanm	92:4fc01daae5a5	5209
bogdanm	85:024bf7f99721	5210	#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
bogdanm	85:024bf7f99721	5211
bogdanm	85:024bf7f99721	5212	/**************************** CEC Instances *******************************/
bogdanm	85:024bf7f99721	5213	#define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
bogdanm	85:024bf7f99721	5214
bogdanm	85:024bf7f99721	5215	/**************************** CRC Instances *******************************/
bogdanm	85:024bf7f99721	5216	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
bogdanm	85:024bf7f99721	5217
bogdanm	85:024bf7f99721	5218	/***************************** DAC Instances ******************************/
bogdanm	85:024bf7f99721	5219	#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
bogdanm	85:024bf7f99721	5220
bogdanm	85:024bf7f99721	5221	/***************************** DMA Instances ****************************/
bogdanm	85:024bf7f99721	5222	#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) \|\| \
bogdanm	85:024bf7f99721	5223	((INSTANCE) == DMA1_Channel2) \|\| \
bogdanm	85:024bf7f99721	5224	((INSTANCE) == DMA1_Channel3) \|\| \
bogdanm	85:024bf7f99721	5225	((INSTANCE) == DMA1_Channel4) \|\| \
bogdanm	85:024bf7f99721	5226	((INSTANCE) == DMA1_Channel5) \|\| \
bogdanm	85:024bf7f99721	5227	((INSTANCE) == DMA1_Channel6) \|\| \
bogdanm	85:024bf7f99721	5228	((INSTANCE) == DMA1_Channel7))
bogdanm	85:024bf7f99721	5229
bogdanm	85:024bf7f99721	5230	/**************************** GPIO Instances ******************************/
Kojto	93:e188a91d3eaa	5231	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
Kojto	93:e188a91d3eaa	5232	((INSTANCE) == GPIOB) \|\| \
Kojto	93:e188a91d3eaa	5233	((INSTANCE) == GPIOC) \|\| \
Kojto	93:e188a91d3eaa	5234	((INSTANCE) == GPIOD) \|\| \
Kojto	93:e188a91d3eaa	5235	((INSTANCE) == GPIOE) \|\| \
Kojto	93:e188a91d3eaa	5236	((INSTANCE) == GPIOF))
Kojto	93:e188a91d3eaa	5237
Kojto	93:e188a91d3eaa	5238	#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
Kojto	93:e188a91d3eaa	5239	((INSTANCE) == GPIOB) \|\| \
Kojto	93:e188a91d3eaa	5240	((INSTANCE) == GPIOC) \|\| \
Kojto	93:e188a91d3eaa	5241	((INSTANCE) == GPIOD) \|\| \
Kojto	93:e188a91d3eaa	5242	((INSTANCE) == GPIOE))
Kojto	93:e188a91d3eaa	5243
bogdanm	92:4fc01daae5a5	5244	#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
bogdanm	92:4fc01daae5a5	5245	((INSTANCE) == GPIOB))
bogdanm	92:4fc01daae5a5	5246
bogdanm	85:024bf7f99721	5247	/**************************** I2C Instances *******************************/
bogdanm	85:024bf7f99721	5248	#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) \|\| \
bogdanm	85:024bf7f99721	5249	((INSTANCE) == I2C2))
bogdanm	85:024bf7f99721	5250
bogdanm	85:024bf7f99721	5251	/**************************** I2S Instances *******************************/
bogdanm	85:024bf7f99721	5252	#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
bogdanm	85:024bf7f99721	5253	((INSTANCE) == SPI2))
bogdanm	85:024bf7f99721	5254
bogdanm	85:024bf7f99721	5255	/**************************** IWDG Instances ******************************/
bogdanm	85:024bf7f99721	5256	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
bogdanm	85:024bf7f99721	5257
bogdanm	85:024bf7f99721	5258	/**************************** RTC Instances *******************************/
bogdanm	85:024bf7f99721	5259	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
bogdanm	85:024bf7f99721	5260
bogdanm	85:024bf7f99721	5261	/**************************** SMBUS Instances *******************************/
bogdanm	85:024bf7f99721	5262	#define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
bogdanm	85:024bf7f99721	5263
bogdanm	85:024bf7f99721	5264	/**************************** SPI Instances *******************************/
bogdanm	85:024bf7f99721	5265	#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) \|\| \
bogdanm	85:024bf7f99721	5266	((INSTANCE) == SPI2))
bogdanm	85:024bf7f99721	5267
bogdanm	85:024bf7f99721	5268	/**************************** TIM Instances *******************************/
bogdanm	85:024bf7f99721	5269	#define IS_TIM_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5270	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5271	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5272	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5273	((INSTANCE) == TIM6) \|\| \
bogdanm	85:024bf7f99721	5274	((INSTANCE) == TIM7) \|\| \
bogdanm	85:024bf7f99721	5275	((INSTANCE) == TIM14) \|\| \
bogdanm	85:024bf7f99721	5276	((INSTANCE) == TIM15) \|\| \
bogdanm	85:024bf7f99721	5277	((INSTANCE) == TIM16) \|\| \
bogdanm	85:024bf7f99721	5278	((INSTANCE) == TIM17))
bogdanm	85:024bf7f99721	5279
bogdanm	85:024bf7f99721	5280	#define IS_TIM_CC1_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5281	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5282	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5283	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5284	((INSTANCE) == TIM14) \|\| \
bogdanm	85:024bf7f99721	5285	((INSTANCE) == TIM15) \|\| \
bogdanm	85:024bf7f99721	5286	((INSTANCE) == TIM16) \|\| \
bogdanm	85:024bf7f99721	5287	((INSTANCE) == TIM17))
bogdanm	85:024bf7f99721	5288
bogdanm	85:024bf7f99721	5289	#define IS_TIM_CC2_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5290	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5291	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5292	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5293	((INSTANCE) == TIM15))
bogdanm	85:024bf7f99721	5294
bogdanm	85:024bf7f99721	5295	#define IS_TIM_CC3_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5296	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5297	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5298	((INSTANCE) == TIM3))
bogdanm	85:024bf7f99721	5299
bogdanm	85:024bf7f99721	5300	#define IS_TIM_CC4_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5301	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5302	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5303	((INSTANCE) == TIM3))
bogdanm	85:024bf7f99721	5304
bogdanm	85:024bf7f99721	5305	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5306	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5307	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5308	((INSTANCE) == TIM3))
bogdanm	85:024bf7f99721	5309
bogdanm	85:024bf7f99721	5310	#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5311	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5312	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5313	((INSTANCE) == TIM3))
bogdanm	85:024bf7f99721	5314
bogdanm	85:024bf7f99721	5315	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5316	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5317	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5318	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5319	((INSTANCE) == TIM15))
bogdanm	85:024bf7f99721	5320
bogdanm	85:024bf7f99721	5321	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5322	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5323	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5324	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5325	((INSTANCE) == TIM15))
bogdanm	85:024bf7f99721	5326
bogdanm	85:024bf7f99721	5327	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5328	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5329	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5330	((INSTANCE) == TIM3))
bogdanm	85:024bf7f99721	5331
bogdanm	85:024bf7f99721	5332	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5333	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5334	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5335	((INSTANCE) == TIM3))
bogdanm	85:024bf7f99721	5336
bogdanm	85:024bf7f99721	5337	#define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5338	(((INSTANCE) == TIM1))
bogdanm	85:024bf7f99721	5339
bogdanm	85:024bf7f99721	5340	#define IS_TIM_XOR_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5341	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5342	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5343	((INSTANCE) == TIM3))
bogdanm	85:024bf7f99721	5344
bogdanm	85:024bf7f99721	5345	#define IS_TIM_MASTER_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5346	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5347	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5348	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5349	((INSTANCE) == TIM6) \|\| \
bogdanm	85:024bf7f99721	5350	((INSTANCE) == TIM7) \|\| \
bogdanm	85:024bf7f99721	5351	((INSTANCE) == TIM15))
bogdanm	85:024bf7f99721	5352
bogdanm	85:024bf7f99721	5353	#define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5354	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5355	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5356	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5357	((INSTANCE) == TIM15))
bogdanm	85:024bf7f99721	5358
bogdanm	85:024bf7f99721	5359	#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5360	((INSTANCE) == TIM2)
bogdanm	85:024bf7f99721	5361
bogdanm	85:024bf7f99721	5362	#define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5363	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5364	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5365	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5366	((INSTANCE) == TIM15) \|\| \
bogdanm	85:024bf7f99721	5367	((INSTANCE) == TIM16) \|\| \
bogdanm	85:024bf7f99721	5368	((INSTANCE) == TIM17))
bogdanm	85:024bf7f99721	5369
bogdanm	85:024bf7f99721	5370	#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5371	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5372	((INSTANCE) == TIM15) \|\| \
bogdanm	85:024bf7f99721	5373	((INSTANCE) == TIM16) \|\| \
bogdanm	85:024bf7f99721	5374	((INSTANCE) == TIM17))
bogdanm	85:024bf7f99721	5375
bogdanm	85:024bf7f99721	5376	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
bogdanm	85:024bf7f99721	5377	((((INSTANCE) == TIM1) && \
bogdanm	85:024bf7f99721	5378	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	85:024bf7f99721	5379	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	85:024bf7f99721	5380	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	85:024bf7f99721	5381	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	85:024bf7f99721	5382	\|\| \
bogdanm	85:024bf7f99721	5383	(((INSTANCE) == TIM2) && \
bogdanm	85:024bf7f99721	5384	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	85:024bf7f99721	5385	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	85:024bf7f99721	5386	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	85:024bf7f99721	5387	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	85:024bf7f99721	5388	\|\| \
bogdanm	85:024bf7f99721	5389	(((INSTANCE) == TIM3) && \
bogdanm	85:024bf7f99721	5390	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	85:024bf7f99721	5391	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	85:024bf7f99721	5392	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	85:024bf7f99721	5393	((CHANNEL) == TIM_CHANNEL_4))) \
bogdanm	85:024bf7f99721	5394	\|\| \
bogdanm	85:024bf7f99721	5395	(((INSTANCE) == TIM14) && \
bogdanm	85:024bf7f99721	5396	(((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm	85:024bf7f99721	5397	\|\| \
bogdanm	85:024bf7f99721	5398	(((INSTANCE) == TIM15) && \
bogdanm	85:024bf7f99721	5399	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	85:024bf7f99721	5400	((CHANNEL) == TIM_CHANNEL_2))) \
bogdanm	85:024bf7f99721	5401	\|\| \
bogdanm	85:024bf7f99721	5402	(((INSTANCE) == TIM16) && \
bogdanm	85:024bf7f99721	5403	(((CHANNEL) == TIM_CHANNEL_1))) \
bogdanm	85:024bf7f99721	5404	\|\| \
bogdanm	85:024bf7f99721	5405	(((INSTANCE) == TIM17) && \
bogdanm	85:024bf7f99721	5406	(((CHANNEL) == TIM_CHANNEL_1))))
bogdanm	85:024bf7f99721	5407
bogdanm	85:024bf7f99721	5408	#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
bogdanm	85:024bf7f99721	5409	((((INSTANCE) == TIM1) && \
bogdanm	85:024bf7f99721	5410	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	85:024bf7f99721	5411	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	85:024bf7f99721	5412	((CHANNEL) == TIM_CHANNEL_3))) \
bogdanm	85:024bf7f99721	5413	\|\| \
bogdanm	85:024bf7f99721	5414	(((INSTANCE) == TIM15) && \
bogdanm	85:024bf7f99721	5415	((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm	85:024bf7f99721	5416	\|\| \
bogdanm	85:024bf7f99721	5417	(((INSTANCE) == TIM16) && \
bogdanm	85:024bf7f99721	5418	((CHANNEL) == TIM_CHANNEL_1)) \
bogdanm	85:024bf7f99721	5419	\|\| \
bogdanm	85:024bf7f99721	5420	(((INSTANCE) == TIM17) && \
bogdanm	85:024bf7f99721	5421	((CHANNEL) == TIM_CHANNEL_1)))
bogdanm	85:024bf7f99721	5422
bogdanm	85:024bf7f99721	5423	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5424	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5425	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5426	((INSTANCE) == TIM3))
bogdanm	85:024bf7f99721	5427
bogdanm	85:024bf7f99721	5428	#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5429	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5430	((INSTANCE) == TIM15) \|\| \
bogdanm	85:024bf7f99721	5431	((INSTANCE) == TIM16) \|\| \
bogdanm	85:024bf7f99721	5432	((INSTANCE) == TIM17))
bogdanm	85:024bf7f99721	5433
bogdanm	85:024bf7f99721	5434	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5435	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5436	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5437	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5438	((INSTANCE) == TIM14) \|\| \
bogdanm	85:024bf7f99721	5439	((INSTANCE) == TIM15) \|\| \
bogdanm	85:024bf7f99721	5440	((INSTANCE) == TIM16) \|\| \
bogdanm	85:024bf7f99721	5441	((INSTANCE) == TIM17))
bogdanm	85:024bf7f99721	5442
bogdanm	85:024bf7f99721	5443	#define IS_TIM_DMA_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5444	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5445	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5446	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5447	((INSTANCE) == TIM6) \|\| \
bogdanm	85:024bf7f99721	5448	((INSTANCE) == TIM7) \|\| \
bogdanm	85:024bf7f99721	5449	((INSTANCE) == TIM15) \|\| \
bogdanm	85:024bf7f99721	5450	((INSTANCE) == TIM16) \|\| \
bogdanm	85:024bf7f99721	5451	((INSTANCE) == TIM17))
bogdanm	85:024bf7f99721	5452
bogdanm	85:024bf7f99721	5453	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5454	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5455	((INSTANCE) == TIM2) \|\| \
bogdanm	85:024bf7f99721	5456	((INSTANCE) == TIM3) \|\| \
bogdanm	85:024bf7f99721	5457	((INSTANCE) == TIM15) \|\| \
bogdanm	85:024bf7f99721	5458	((INSTANCE) == TIM16) \|\| \
bogdanm	85:024bf7f99721	5459	((INSTANCE) == TIM17))
bogdanm	85:024bf7f99721	5460
bogdanm	85:024bf7f99721	5461	#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5462	(((INSTANCE) == TIM1) \|\| \
bogdanm	85:024bf7f99721	5463	((INSTANCE) == TIM15) \|\| \
bogdanm	85:024bf7f99721	5464	((INSTANCE) == TIM16) \|\| \
bogdanm	85:024bf7f99721	5465	((INSTANCE) == TIM17))
bogdanm	85:024bf7f99721	5466
bogdanm	85:024bf7f99721	5467	#define IS_TIM_REMAP_INSTANCE(INSTANCE)\
bogdanm	85:024bf7f99721	5468	((INSTANCE) == TIM14)
bogdanm	85:024bf7f99721	5469
bogdanm	85:024bf7f99721	5470	/**************************** TSC Instances *******************************/
bogdanm	85:024bf7f99721	5471	#define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
bogdanm	85:024bf7f99721	5472
bogdanm	85:024bf7f99721	5473	/********************* UART Instances : IRDA mode *************************/
bogdanm	85:024bf7f99721	5474	#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	85:024bf7f99721	5475	((INSTANCE) == USART2))
bogdanm	85:024bf7f99721	5476
bogdanm	85:024bf7f99721	5477	/******************* UART Instances : Smard card mode *********************/
bogdanm	85:024bf7f99721	5478	#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	85:024bf7f99721	5479	((INSTANCE) == USART2))
bogdanm	85:024bf7f99721	5480
bogdanm	85:024bf7f99721	5481	/****************** USART Instances : Synchronous mode ********************/
bogdanm	85:024bf7f99721	5482	#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	85:024bf7f99721	5483	((INSTANCE) == USART2) \|\| \
bogdanm	85:024bf7f99721	5484	((INSTANCE) == USART3) \|\| \
bogdanm	85:024bf7f99721	5485	((INSTANCE) == USART4))
bogdanm	85:024bf7f99721	5486
bogdanm	85:024bf7f99721	5487	/****************** USART Instances : auto Baud rate detection ************/
bogdanm	85:024bf7f99721	5488	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	85:024bf7f99721	5489	((INSTANCE) == USART2))
bogdanm	85:024bf7f99721	5490
bogdanm	85:024bf7f99721	5491	/****************** UART Instances : Asynchronous mode ********************/
bogdanm	85:024bf7f99721	5492	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	85:024bf7f99721	5493	((INSTANCE) == USART2) \|\| \
bogdanm	85:024bf7f99721	5494	((INSTANCE) == USART3) \|\| \
bogdanm	85:024bf7f99721	5495	((INSTANCE) == USART4))
bogdanm	92:4fc01daae5a5	5496
bogdanm	92:4fc01daae5a5	5497	/****************** UART Instances : Half-Duplex mode ********************/
bogdanm	92:4fc01daae5a5	5498	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	92:4fc01daae5a5	5499	((INSTANCE) == USART2) \|\| \
bogdanm	92:4fc01daae5a5	5500	((INSTANCE) == USART3) \|\| \
bogdanm	92:4fc01daae5a5	5501	((INSTANCE) == USART4))
bogdanm	85:024bf7f99721	5502
bogdanm	85:024bf7f99721	5503	/**************** UART Instances : Hardware Flow control ******************/
bogdanm	85:024bf7f99721	5504	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	85:024bf7f99721	5505	((INSTANCE) == USART2) \|\| \
bogdanm	85:024bf7f99721	5506	((INSTANCE) == USART3) \|\| \
bogdanm	85:024bf7f99721	5507	((INSTANCE) == USART4))
bogdanm	85:024bf7f99721	5508
bogdanm	92:4fc01daae5a5	5509	/**************** UART Instances : LIN mode ******************/
bogdanm	92:4fc01daae5a5	5510	#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	92:4fc01daae5a5	5511	((INSTANCE) == USART2))
bogdanm	92:4fc01daae5a5	5512
bogdanm	92:4fc01daae5a5	5513	/**************** UART Instances : wakeup from stop mode ******************/
bogdanm	92:4fc01daae5a5	5514	#define IS_UART_WAKEUP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	92:4fc01daae5a5	5515	((INSTANCE) == USART2))
bogdanm	92:4fc01daae5a5	5516
bogdanm	85:024bf7f99721	5517	/**************** UART Instances : Auto Baud Rate detection ******************/
bogdanm	85:024bf7f99721	5518	#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	85:024bf7f99721	5519	((INSTANCE) == USART2))
bogdanm	85:024bf7f99721	5520
bogdanm	85:024bf7f99721	5521	/**************** UART Instances : Driver enable detection ******************/
bogdanm	85:024bf7f99721	5522	#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) \|\| \
bogdanm	85:024bf7f99721	5523	((INSTANCE) == USART2) \|\| \
bogdanm	85:024bf7f99721	5524	((INSTANCE) == USART3) \|\| \
bogdanm	85:024bf7f99721	5525	((INSTANCE) == USART4))
bogdanm	85:024bf7f99721	5526
bogdanm	85:024bf7f99721	5527	/**************************** USB Instances ******************************/
bogdanm	85:024bf7f99721	5528	#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
bogdanm	85:024bf7f99721	5529
bogdanm	85:024bf7f99721	5530	/**************************** WWDG Instances ******************************/
bogdanm	85:024bf7f99721	5531	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
bogdanm	85:024bf7f99721	5532
bogdanm	85:024bf7f99721	5533	/**
bogdanm	85:024bf7f99721	5534	* @}
bogdanm	85:024bf7f99721	5535	*/
bogdanm	85:024bf7f99721	5536
bogdanm	85:024bf7f99721	5537
bogdanm	85:024bf7f99721	5538	/******************************************************************************/
bogdanm	85:024bf7f99721	5539	/* For a painless codes migration between the STM32F0xx device product */
bogdanm	85:024bf7f99721	5540	/* lines, the aliases defined below are put in place to overcome the */
bogdanm	85:024bf7f99721	5541	/* differences in the interrupt handlers and IRQn definitions. */
bogdanm	85:024bf7f99721	5542	/* No need to update developed interrupt code when moving across */
bogdanm	85:024bf7f99721	5543	/* product lines within the same STM32F0 Family */
bogdanm	85:024bf7f99721	5544	/******************************************************************************/
bogdanm	85:024bf7f99721	5545
bogdanm	85:024bf7f99721	5546	/* Aliases for __IRQn */
bogdanm	85:024bf7f99721	5547	#define PVD_IRQn PVD_VDDIO2_IRQn
bogdanm	92:4fc01daae5a5	5548	#define VDDIO2_IRQn PVD_VDDIO2_IRQn
bogdanm	85:024bf7f99721	5549	#define RCC_IRQn RCC_CRS_IRQn
bogdanm	85:024bf7f99721	5550	#define DMA1_Channel4_5_IRQn DMA1_Channel4_5_6_7_IRQn
bogdanm	85:024bf7f99721	5551	#define ADC1_IRQn ADC1_COMP_IRQn
bogdanm	85:024bf7f99721	5552	#define TIM6_IRQn TIM6_DAC_IRQn
bogdanm	85:024bf7f99721	5553
bogdanm	85:024bf7f99721	5554	/* Aliases for __IRQHandler */
bogdanm	85:024bf7f99721	5555	#define PVD_IRQHandler PVD_VDDIO2_IRQHandler
bogdanm	92:4fc01daae5a5	5556	#define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
bogdanm	85:024bf7f99721	5557	#define RCC_IRQHandler RCC_CRS_IRQHandler
bogdanm	85:024bf7f99721	5558	#define DMA1_Channel4_5_IRQHandler DMA1_Channel4_5_6_7_IRQHandler
bogdanm	85:024bf7f99721	5559	#define ADC1_IRQHandler ADC1_COMP_IRQHandler
bogdanm	85:024bf7f99721	5560	#define TIM6_IRQHandler TIM6_DAC_IRQHandler
bogdanm	85:024bf7f99721	5561
bogdanm	85:024bf7f99721	5562	#ifdef __cplusplus
bogdanm	85:024bf7f99721	5563	}
bogdanm	85:024bf7f99721	5564	#endif /* __cplusplus */
bogdanm	85:024bf7f99721	5565
bogdanm	85:024bf7f99721	5566	#endif /* __STM32F072xB_H */
bogdanm	85:024bf7f99721	5567
bogdanm	85:024bf7f99721	5568	/**
bogdanm	85:024bf7f99721	5569	* @}
bogdanm	85:024bf7f99721	5570	*/
bogdanm	85:024bf7f99721	5571
bogdanm	85:024bf7f99721	5572	/**
bogdanm	85:024bf7f99721	5573	* @}
bogdanm	85:024bf7f99721	5574	*/
bogdanm	85:024bf7f99721	5575
bogdanm	85:024bf7f99721	5576	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F072RB/stm32f072xb.h@93:e188a91d3eaa, 2015-02-03 (annotated)

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