Filippo Casamassima / mbed

my fork

Dependents:   Nucleo_blueNRG

Fork of mbed by mbed official

TARGET_NRF51_DONGLE/nrf51.h@93:e188a91d3eaa, 2015-02-03 (annotated)

Committer:
Kojto
Date:
Tue Feb 03 15:31:20 2015 +0000
Revision:
93:e188a91d3eaa
Parent:
91:031413cf7a89 
Release 93 of the mbed library



Main changes:



- Renesas RZ_A1H bugfixes - i2c, ticker

- new targets - Nucleo F303RE, Nucleo F070RB, BLE SMURFS,

                Dragonfly 411RE,

- BusXXX - is connected method, plus operators addition

- LPC8xx - I2c fixes

- timestamp_t reverted to uint32_t

- RTX - fixes regarding stack (alignment, magic word)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 91:031413cf7a89 1 /* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
Kojto 91:031413cf7a89 2 *
Kojto 91:031413cf7a89 3 * The information contained herein is property of Nordic Semiconductor ASA.
Kojto 91:031413cf7a89 4 * Terms and conditions of usage are described in detail in NORDIC
Kojto 91:031413cf7a89 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
Kojto 91:031413cf7a89 6 *
Kojto 91:031413cf7a89 7 * Licensees are granted free, non-transferable use of the information. NO
Kojto 91:031413cf7a89 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
Kojto 91:031413cf7a89 9 * the file.
Kojto 91:031413cf7a89 10 *
Kojto 91:031413cf7a89 11 */
Kojto 91:031413cf7a89 12
Kojto 91:031413cf7a89 13
Kojto 91:031413cf7a89 14
Kojto 91:031413cf7a89 15 /** @addtogroup Nordic Semiconductor
Kojto 91:031413cf7a89 16 * @{
Kojto 91:031413cf7a89 17 */
Kojto 91:031413cf7a89 18
Kojto 91:031413cf7a89 19 /** @addtogroup nRF51
Kojto 91:031413cf7a89 20 * @{
Kojto 91:031413cf7a89 21 */
Kojto 91:031413cf7a89 22
Kojto 91:031413cf7a89 23 #ifndef NRF51_H
Kojto 91:031413cf7a89 24 #define NRF51_H
Kojto 91:031413cf7a89 25
Kojto 91:031413cf7a89 26 #ifdef __cplusplus
Kojto 91:031413cf7a89 27 extern "C" {
Kojto 91:031413cf7a89 28 #endif
Kojto 91:031413cf7a89 29
Kojto 91:031413cf7a89 30
Kojto 91:031413cf7a89 31 /* ------------------------- Interrupt Number Definition ------------------------ */
Kojto 91:031413cf7a89 32
Kojto 91:031413cf7a89 33 typedef enum {
Kojto 91:031413cf7a89 34 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
Kojto 91:031413cf7a89 35 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
Kojto 91:031413cf7a89 36 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
Kojto 91:031413cf7a89 37 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
Kojto 91:031413cf7a89 38 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
Kojto 91:031413cf7a89 39 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
Kojto 91:031413cf7a89 40 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
Kojto 91:031413cf7a89 41 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
Kojto 91:031413cf7a89 42 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
Kojto 91:031413cf7a89 43 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
Kojto 91:031413cf7a89 44 RADIO_IRQn = 1, /*!< 1 RADIO */
Kojto 91:031413cf7a89 45 UART0_IRQn = 2, /*!< 2 UART0 */
Kojto 91:031413cf7a89 46 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
Kojto 91:031413cf7a89 47 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
Kojto 91:031413cf7a89 48 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
Kojto 91:031413cf7a89 49 ADC_IRQn = 7, /*!< 7 ADC */
Kojto 91:031413cf7a89 50 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
Kojto 91:031413cf7a89 51 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
Kojto 91:031413cf7a89 52 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
Kojto 91:031413cf7a89 53 RTC0_IRQn = 11, /*!< 11 RTC0 */
Kojto 91:031413cf7a89 54 TEMP_IRQn = 12, /*!< 12 TEMP */
Kojto 91:031413cf7a89 55 RNG_IRQn = 13, /*!< 13 RNG */
Kojto 91:031413cf7a89 56 ECB_IRQn = 14, /*!< 14 ECB */
Kojto 91:031413cf7a89 57 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
Kojto 91:031413cf7a89 58 WDT_IRQn = 16, /*!< 16 WDT */
Kojto 91:031413cf7a89 59 RTC1_IRQn = 17, /*!< 17 RTC1 */
Kojto 91:031413cf7a89 60 QDEC_IRQn = 18, /*!< 18 QDEC */
Kojto 91:031413cf7a89 61 LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
Kojto 91:031413cf7a89 62 SWI0_IRQn = 20, /*!< 20 SWI0 */
Kojto 91:031413cf7a89 63 SWI1_IRQn = 21, /*!< 21 SWI1 */
Kojto 91:031413cf7a89 64 SWI2_IRQn = 22, /*!< 22 SWI2 */
Kojto 91:031413cf7a89 65 SWI3_IRQn = 23, /*!< 23 SWI3 */
Kojto 91:031413cf7a89 66 SWI4_IRQn = 24, /*!< 24 SWI4 */
Kojto 91:031413cf7a89 67 SWI5_IRQn = 25 /*!< 25 SWI5 */
Kojto 91:031413cf7a89 68 } IRQn_Type;
Kojto 91:031413cf7a89 69
Kojto 91:031413cf7a89 70
Kojto 91:031413cf7a89 71 /** @addtogroup Configuration_of_CMSIS
Kojto 91:031413cf7a89 72 * @{
Kojto 91:031413cf7a89 73 */
Kojto 91:031413cf7a89 74
Kojto 91:031413cf7a89 75
Kojto 91:031413cf7a89 76 /* ================================================================================ */
Kojto 91:031413cf7a89 77 /* ================ Processor and Core Peripheral Section ================ */
Kojto 91:031413cf7a89 78 /* ================================================================================ */
Kojto 91:031413cf7a89 79
Kojto 91:031413cf7a89 80 /* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
Kojto 91:031413cf7a89 81 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
Kojto 91:031413cf7a89 82 #define __MPU_PRESENT 0 /*!< MPU present or not */
Kojto 91:031413cf7a89 83 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
Kojto 91:031413cf7a89 84 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 91:031413cf7a89 85 /** @} */ /* End of group Configuration_of_CMSIS */
Kojto 91:031413cf7a89 86
Kojto 91:031413cf7a89 87 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
Kojto 91:031413cf7a89 88 #include "system_nrf51822.h" /*!< nRF51 System */
Kojto 91:031413cf7a89 89
Kojto 91:031413cf7a89 90
Kojto 91:031413cf7a89 91 /* ================================================================================ */
Kojto 91:031413cf7a89 92 /* ================ Device Specific Peripheral Section ================ */
Kojto 91:031413cf7a89 93 /* ================================================================================ */
Kojto 91:031413cf7a89 94
Kojto 91:031413cf7a89 95
Kojto 91:031413cf7a89 96 /** @addtogroup Device_Peripheral_Registers
Kojto 91:031413cf7a89 97 * @{
Kojto 91:031413cf7a89 98 */
Kojto 91:031413cf7a89 99
Kojto 91:031413cf7a89 100
Kojto 91:031413cf7a89 101 /* ------------------- Start of section using anonymous unions ------------------ */
Kojto 91:031413cf7a89 102 #if defined(__CC_ARM)
Kojto 91:031413cf7a89 103 #pragma push
Kojto 91:031413cf7a89 104 #pragma anon_unions
Kojto 91:031413cf7a89 105 #elif defined(__ICCARM__)
Kojto 91:031413cf7a89 106 #pragma language=extended
Kojto 91:031413cf7a89 107 #elif defined(__GNUC__)
Kojto 91:031413cf7a89 108 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 109 #elif defined(__TMS470__)
Kojto 91:031413cf7a89 110 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 111 #elif defined(__TASKING__)
Kojto 91:031413cf7a89 112 #pragma warning 586
Kojto 91:031413cf7a89 113 #else
Kojto 91:031413cf7a89 114 #warning Not supported compiler type
Kojto 91:031413cf7a89 115 #endif
Kojto 91:031413cf7a89 116
Kojto 91:031413cf7a89 117
Kojto 91:031413cf7a89 118 typedef struct {
Kojto 91:031413cf7a89 119 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
Kojto 91:031413cf7a89 120 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
Kojto 91:031413cf7a89 121 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
Kojto 91:031413cf7a89 122 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
Kojto 91:031413cf7a89 123 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
Kojto 91:031413cf7a89 124 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
Kojto 91:031413cf7a89 125 } AMLI_RAMPRI_Type;
Kojto 91:031413cf7a89 126
Kojto 91:031413cf7a89 127 typedef struct {
Kojto 91:031413cf7a89 128 __O uint32_t EN; /*!< Enable channel group. */
Kojto 91:031413cf7a89 129 __O uint32_t DIS; /*!< Disable channel group. */
Kojto 91:031413cf7a89 130 } PPI_TASKS_CHG_Type;
Kojto 91:031413cf7a89 131
Kojto 91:031413cf7a89 132 typedef struct {
Kojto 91:031413cf7a89 133 __IO uint32_t EEP; /*!< Channel event end-point. */
Kojto 91:031413cf7a89 134 __IO uint32_t TEP; /*!< Channel task end-point. */
Kojto 91:031413cf7a89 135 } PPI_CH_Type;
Kojto 91:031413cf7a89 136
Kojto 91:031413cf7a89 137
Kojto 91:031413cf7a89 138 /* ================================================================================ */
Kojto 91:031413cf7a89 139 /* ================ POWER ================ */
Kojto 91:031413cf7a89 140 /* ================================================================================ */
Kojto 91:031413cf7a89 141
Kojto 91:031413cf7a89 142
Kojto 91:031413cf7a89 143 /**
Kojto 91:031413cf7a89 144 * @brief Power Control. (POWER)
Kojto 91:031413cf7a89 145 */
Kojto 91:031413cf7a89 146
Kojto 91:031413cf7a89 147 typedef struct { /*!< POWER Structure */
Kojto 91:031413cf7a89 148 __I uint32_t RESERVED0[30];
Kojto 91:031413cf7a89 149 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
Kojto 91:031413cf7a89 150 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
Kojto 91:031413cf7a89 151 __I uint32_t RESERVED1[34];
Kojto 91:031413cf7a89 152 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
Kojto 91:031413cf7a89 153 __I uint32_t RESERVED2[126];
Kojto 91:031413cf7a89 154 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 155 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 156 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 157 __IO uint32_t RESETREAS; /*!< Reset reason. */
Kojto 91:031413cf7a89 158 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 159 __O uint32_t SYSTEMOFF; /*!< System off register. */
Kojto 91:031413cf7a89 160 __I uint32_t RESERVED5[3];
Kojto 91:031413cf7a89 161 __IO uint32_t POFCON; /*!< Power failure configuration. */
Kojto 91:031413cf7a89 162 __I uint32_t RESERVED6[2];
Kojto 91:031413cf7a89 163 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
Kojto 91:031413cf7a89 164 register. */
Kojto 91:031413cf7a89 165 __I uint32_t RESERVED7;
Kojto 91:031413cf7a89 166 __IO uint32_t RAMON; /*!< Ram on/off. */
Kojto 91:031413cf7a89 167 __I uint32_t RESERVED8[7];
Kojto 91:031413cf7a89 168 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
Kojto 91:031413cf7a89 169 is a retained register. */
Kojto 91:031413cf7a89 170 __I uint32_t RESERVED9[12];
Kojto 91:031413cf7a89 171 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
Kojto 91:031413cf7a89 172 } NRF_POWER_Type;
Kojto 91:031413cf7a89 173
Kojto 91:031413cf7a89 174
Kojto 91:031413cf7a89 175 /* ================================================================================ */
Kojto 91:031413cf7a89 176 /* ================ CLOCK ================ */
Kojto 91:031413cf7a89 177 /* ================================================================================ */
Kojto 91:031413cf7a89 178
Kojto 91:031413cf7a89 179
Kojto 91:031413cf7a89 180 /**
Kojto 91:031413cf7a89 181 * @brief Clock control. (CLOCK)
Kojto 91:031413cf7a89 182 */
Kojto 91:031413cf7a89 183
Kojto 91:031413cf7a89 184 typedef struct { /*!< CLOCK Structure */
Kojto 91:031413cf7a89 185 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
Kojto 91:031413cf7a89 186 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
Kojto 91:031413cf7a89 187 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
Kojto 91:031413cf7a89 188 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
Kojto 91:031413cf7a89 189 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
Kojto 91:031413cf7a89 190 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
Kojto 91:031413cf7a89 191 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
Kojto 91:031413cf7a89 192 __I uint32_t RESERVED0[57];
Kojto 91:031413cf7a89 193 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
Kojto 91:031413cf7a89 194 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
Kojto 91:031413cf7a89 195 __I uint32_t RESERVED1;
Kojto 91:031413cf7a89 196 __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
Kojto 91:031413cf7a89 197 __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
Kojto 91:031413cf7a89 198 __I uint32_t RESERVED2[124];
Kojto 91:031413cf7a89 199 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 200 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 201 __I uint32_t RESERVED3[64];
Kojto 91:031413cf7a89 202 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
Kojto 91:031413cf7a89 203 __I uint32_t RESERVED4[2];
Kojto 91:031413cf7a89 204 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
Kojto 91:031413cf7a89 205 __I uint32_t RESERVED5[63];
Kojto 91:031413cf7a89 206 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
Kojto 91:031413cf7a89 207 __I uint32_t RESERVED6[7];
Kojto 91:031413cf7a89 208 __IO uint32_t CTIV; /*!< Calibration timer interval. */
Kojto 91:031413cf7a89 209 __I uint32_t RESERVED7[5];
Kojto 91:031413cf7a89 210 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
Kojto 91:031413cf7a89 211 } NRF_CLOCK_Type;
Kojto 91:031413cf7a89 212
Kojto 91:031413cf7a89 213
Kojto 91:031413cf7a89 214 /* ================================================================================ */
Kojto 91:031413cf7a89 215 /* ================ MPU ================ */
Kojto 91:031413cf7a89 216 /* ================================================================================ */
Kojto 91:031413cf7a89 217
Kojto 91:031413cf7a89 218
Kojto 91:031413cf7a89 219 /**
Kojto 91:031413cf7a89 220 * @brief Memory Protection Unit. (MPU)
Kojto 91:031413cf7a89 221 */
Kojto 91:031413cf7a89 222
Kojto 91:031413cf7a89 223 typedef struct { /*!< MPU Structure */
Kojto 91:031413cf7a89 224 __I uint32_t RESERVED0[330];
Kojto 91:031413cf7a89 225 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
Kojto 91:031413cf7a89 226 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
Kojto 91:031413cf7a89 227 __I uint32_t RESERVED1[52];
Kojto 91:031413cf7a89 228 __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
Kojto 91:031413cf7a89 229 __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
Kojto 91:031413cf7a89 230 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
Kojto 91:031413cf7a89 231 } NRF_MPU_Type;
Kojto 91:031413cf7a89 232
Kojto 91:031413cf7a89 233
Kojto 91:031413cf7a89 234 /* ================================================================================ */
Kojto 91:031413cf7a89 235 /* ================ PU ================ */
Kojto 91:031413cf7a89 236 /* ================================================================================ */
Kojto 91:031413cf7a89 237
Kojto 91:031413cf7a89 238
Kojto 91:031413cf7a89 239 /**
Kojto 91:031413cf7a89 240 * @brief Patch unit. (PU)
Kojto 91:031413cf7a89 241 */
Kojto 91:031413cf7a89 242
Kojto 91:031413cf7a89 243 typedef struct { /*!< PU Structure */
Kojto 91:031413cf7a89 244 __I uint32_t RESERVED0[448];
Kojto 91:031413cf7a89 245 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
Kojto 91:031413cf7a89 246 __I uint32_t RESERVED1[24];
Kojto 91:031413cf7a89 247 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
Kojto 91:031413cf7a89 248 __I uint32_t RESERVED2[24];
Kojto 91:031413cf7a89 249 __IO uint32_t PATCHEN; /*!< Patch enable register. */
Kojto 91:031413cf7a89 250 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
Kojto 91:031413cf7a89 251 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
Kojto 91:031413cf7a89 252 } NRF_PU_Type;
Kojto 91:031413cf7a89 253
Kojto 91:031413cf7a89 254
Kojto 91:031413cf7a89 255 /* ================================================================================ */
Kojto 91:031413cf7a89 256 /* ================ AMLI ================ */
Kojto 91:031413cf7a89 257 /* ================================================================================ */
Kojto 91:031413cf7a89 258
Kojto 91:031413cf7a89 259
Kojto 91:031413cf7a89 260 /**
Kojto 91:031413cf7a89 261 * @brief AHB Multi-Layer Interface. (AMLI)
Kojto 91:031413cf7a89 262 */
Kojto 91:031413cf7a89 263
Kojto 91:031413cf7a89 264 typedef struct { /*!< AMLI Structure */
Kojto 91:031413cf7a89 265 __I uint32_t RESERVED0[896];
Kojto 91:031413cf7a89 266 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
Kojto 91:031413cf7a89 267 } NRF_AMLI_Type;
Kojto 91:031413cf7a89 268
Kojto 91:031413cf7a89 269
Kojto 91:031413cf7a89 270 /* ================================================================================ */
Kojto 91:031413cf7a89 271 /* ================ RADIO ================ */
Kojto 91:031413cf7a89 272 /* ================================================================================ */
Kojto 91:031413cf7a89 273
Kojto 91:031413cf7a89 274
Kojto 91:031413cf7a89 275 /**
Kojto 91:031413cf7a89 276 * @brief The radio. (RADIO)
Kojto 91:031413cf7a89 277 */
Kojto 91:031413cf7a89 278
Kojto 91:031413cf7a89 279 typedef struct { /*!< RADIO Structure */
Kojto 91:031413cf7a89 280 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
Kojto 91:031413cf7a89 281 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
Kojto 91:031413cf7a89 282 __O uint32_t TASKS_START; /*!< Start radio. */
Kojto 91:031413cf7a89 283 __O uint32_t TASKS_STOP; /*!< Stop radio. */
Kojto 91:031413cf7a89 284 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
Kojto 91:031413cf7a89 285 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
Kojto 91:031413cf7a89 286 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
Kojto 91:031413cf7a89 287 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
Kojto 91:031413cf7a89 288 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
Kojto 91:031413cf7a89 289 __I uint32_t RESERVED0[55];
Kojto 91:031413cf7a89 290 __IO uint32_t EVENTS_READY; /*!< Ready event. */
Kojto 91:031413cf7a89 291 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
Kojto 91:031413cf7a89 292 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
Kojto 91:031413cf7a89 293 __IO uint32_t EVENTS_END; /*!< End event. */
Kojto 91:031413cf7a89 294 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
Kojto 91:031413cf7a89 295 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
Kojto 91:031413cf7a89 296 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
Kojto 91:031413cf7a89 297 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
Kojto 91:031413cf7a89 298 sample is ready for readout at the RSSISAMPLE register. */
Kojto 91:031413cf7a89 299 __I uint32_t RESERVED1[2];
Kojto 91:031413cf7a89 300 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
Kojto 91:031413cf7a89 301 __I uint32_t RESERVED2[53];
Kojto 91:031413cf7a89 302 __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
Kojto 91:031413cf7a89 303 __I uint32_t RESERVED3[64];
Kojto 91:031413cf7a89 304 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 305 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 306 __I uint32_t RESERVED4[61];
Kojto 91:031413cf7a89 307 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
Kojto 91:031413cf7a89 308 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 309 __I uint32_t RXMATCH; /*!< Received address. */
Kojto 91:031413cf7a89 310 __I uint32_t RXCRC; /*!< Received CRC. */
Kojto 91:031413cf7a89 311 __IO uint32_t DAI; /*!< Device address match index. */
Kojto 91:031413cf7a89 312 __I uint32_t RESERVED6[60];
Kojto 91:031413cf7a89 313 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
Kojto 91:031413cf7a89 314 __IO uint32_t FREQUENCY; /*!< Frequency. */
Kojto 91:031413cf7a89 315 __IO uint32_t TXPOWER; /*!< Output power. */
Kojto 91:031413cf7a89 316 __IO uint32_t MODE; /*!< Data rate and modulation. */
Kojto 91:031413cf7a89 317 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
Kojto 91:031413cf7a89 318 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
Kojto 91:031413cf7a89 319 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
Kojto 91:031413cf7a89 320 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
Kojto 91:031413cf7a89 321 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
Kojto 91:031413cf7a89 322 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
Kojto 91:031413cf7a89 323 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
Kojto 91:031413cf7a89 324 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
Kojto 91:031413cf7a89 325 __IO uint32_t CRCCNF; /*!< CRC configuration. */
Kojto 91:031413cf7a89 326 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
Kojto 91:031413cf7a89 327 __IO uint32_t CRCINIT; /*!< CRC initial value. */
Kojto 91:031413cf7a89 328 __IO uint32_t TEST; /*!< Test features enable register. */
Kojto 91:031413cf7a89 329 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
Kojto 91:031413cf7a89 330 __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
Kojto 91:031413cf7a89 331 __I uint32_t RESERVED7;
Kojto 91:031413cf7a89 332 __I uint32_t STATE; /*!< Current radio state. */
Kojto 91:031413cf7a89 333 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
Kojto 91:031413cf7a89 334 __I uint32_t RESERVED8[2];
Kojto 91:031413cf7a89 335 __IO uint32_t BCC; /*!< Bit counter compare. */
Kojto 91:031413cf7a89 336 __I uint32_t RESERVED9[39];
Kojto 91:031413cf7a89 337 __IO uint32_t DAB[8]; /*!< Device address base segment. */
Kojto 91:031413cf7a89 338 __IO uint32_t DAP[8]; /*!< Device address prefix. */
Kojto 91:031413cf7a89 339 __IO uint32_t DACNF; /*!< Device address match configuration. */
Kojto 91:031413cf7a89 340 __I uint32_t RESERVED10[56];
Kojto 91:031413cf7a89 341 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
Kojto 91:031413cf7a89 342 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
Kojto 91:031413cf7a89 343 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
Kojto 91:031413cf7a89 344 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
Kojto 91:031413cf7a89 345 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
Kojto 91:031413cf7a89 346 __I uint32_t RESERVED11[561];
Kojto 91:031413cf7a89 347 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 348 } NRF_RADIO_Type;
Kojto 91:031413cf7a89 349
Kojto 91:031413cf7a89 350
Kojto 91:031413cf7a89 351 /* ================================================================================ */
Kojto 91:031413cf7a89 352 /* ================ UART ================ */
Kojto 91:031413cf7a89 353 /* ================================================================================ */
Kojto 91:031413cf7a89 354
Kojto 91:031413cf7a89 355
Kojto 91:031413cf7a89 356 /**
Kojto 91:031413cf7a89 357 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
Kojto 91:031413cf7a89 358 */
Kojto 91:031413cf7a89 359
Kojto 91:031413cf7a89 360 typedef struct { /*!< UART Structure */
Kojto 91:031413cf7a89 361 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
Kojto 91:031413cf7a89 362 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
Kojto 91:031413cf7a89 363 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
Kojto 91:031413cf7a89 364 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
Kojto 91:031413cf7a89 365 __I uint32_t RESERVED0[3];
Kojto 91:031413cf7a89 366 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
Kojto 91:031413cf7a89 367 __I uint32_t RESERVED1[56];
Kojto 91:031413cf7a89 368 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
Kojto 91:031413cf7a89 369 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
Kojto 91:031413cf7a89 370 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
Kojto 91:031413cf7a89 371 __I uint32_t RESERVED2[4];
Kojto 91:031413cf7a89 372 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
Kojto 91:031413cf7a89 373 __I uint32_t RESERVED3;
Kojto 91:031413cf7a89 374 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
Kojto 91:031413cf7a89 375 __I uint32_t RESERVED4[7];
Kojto 91:031413cf7a89 376 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
Kojto 91:031413cf7a89 377 __I uint32_t RESERVED5[46];
Kojto 91:031413cf7a89 378 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
Kojto 93:e188a91d3eaa 379 __I uint32_t RESERVED6[63];
Kojto 93:e188a91d3eaa 380 __IO uint32_t INTEN; /*!< Interrupt enable register. */
Kojto 91:031413cf7a89 381 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 382 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 383 __I uint32_t RESERVED7[93];
Kojto 91:031413cf7a89 384 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
Kojto 91:031413cf7a89 385 __I uint32_t RESERVED8[31];
Kojto 91:031413cf7a89 386 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
Kojto 91:031413cf7a89 387 __I uint32_t RESERVED9;
Kojto 91:031413cf7a89 388 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
Kojto 91:031413cf7a89 389 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
Kojto 91:031413cf7a89 390 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
Kojto 91:031413cf7a89 391 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
Kojto 91:031413cf7a89 392 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Kojto 91:031413cf7a89 393 Once read the character is consummed. If read when no character
Kojto 91:031413cf7a89 394 available, the UART will stop working. */
Kojto 91:031413cf7a89 395 __O uint32_t TXD; /*!< TXD register. */
Kojto 91:031413cf7a89 396 __I uint32_t RESERVED10;
Kojto 91:031413cf7a89 397 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
Kojto 91:031413cf7a89 398 __I uint32_t RESERVED11[17];
Kojto 91:031413cf7a89 399 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
Kojto 91:031413cf7a89 400 __I uint32_t RESERVED12[675];
Kojto 91:031413cf7a89 401 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 402 } NRF_UART_Type;
Kojto 91:031413cf7a89 403
Kojto 91:031413cf7a89 404
Kojto 91:031413cf7a89 405 /* ================================================================================ */
Kojto 91:031413cf7a89 406 /* ================ SPI ================ */
Kojto 91:031413cf7a89 407 /* ================================================================================ */
Kojto 91:031413cf7a89 408
Kojto 91:031413cf7a89 409
Kojto 91:031413cf7a89 410 /**
Kojto 91:031413cf7a89 411 * @brief SPI master 0. (SPI)
Kojto 91:031413cf7a89 412 */
Kojto 91:031413cf7a89 413
Kojto 91:031413cf7a89 414 typedef struct { /*!< SPI Structure */
Kojto 91:031413cf7a89 415 __I uint32_t RESERVED0[66];
Kojto 91:031413cf7a89 416 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
Kojto 91:031413cf7a89 417 __I uint32_t RESERVED1[126];
Kojto 91:031413cf7a89 418 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 419 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 420 __I uint32_t RESERVED2[125];
Kojto 91:031413cf7a89 421 __IO uint32_t ENABLE; /*!< Enable SPI. */
Kojto 91:031413cf7a89 422 __I uint32_t RESERVED3;
Kojto 91:031413cf7a89 423 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
Kojto 91:031413cf7a89 424 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
Kojto 91:031413cf7a89 425 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
Kojto 91:031413cf7a89 426 __I uint32_t RESERVED4;
Kojto 91:031413cf7a89 427 __IO uint32_t RXD; /*!< RX data. */
Kojto 91:031413cf7a89 428 __IO uint32_t TXD; /*!< TX data. */
Kojto 91:031413cf7a89 429 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 430 __IO uint32_t FREQUENCY; /*!< SPI frequency */
Kojto 91:031413cf7a89 431 __I uint32_t RESERVED6[11];
Kojto 91:031413cf7a89 432 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 433 __I uint32_t RESERVED7[681];
Kojto 91:031413cf7a89 434 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 435 } NRF_SPI_Type;
Kojto 91:031413cf7a89 436
Kojto 91:031413cf7a89 437
Kojto 91:031413cf7a89 438 /* ================================================================================ */
Kojto 91:031413cf7a89 439 /* ================ TWI ================ */
Kojto 91:031413cf7a89 440 /* ================================================================================ */
Kojto 91:031413cf7a89 441
Kojto 91:031413cf7a89 442
Kojto 91:031413cf7a89 443 /**
Kojto 91:031413cf7a89 444 * @brief Two-wire interface master 0. (TWI)
Kojto 91:031413cf7a89 445 */
Kojto 91:031413cf7a89 446
Kojto 91:031413cf7a89 447 typedef struct { /*!< TWI Structure */
Kojto 91:031413cf7a89 448 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
Kojto 91:031413cf7a89 449 __I uint32_t RESERVED0;
Kojto 91:031413cf7a89 450 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
Kojto 91:031413cf7a89 451 __I uint32_t RESERVED1[2];
Kojto 91:031413cf7a89 452 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
Kojto 91:031413cf7a89 453 __I uint32_t RESERVED2;
Kojto 91:031413cf7a89 454 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
Kojto 91:031413cf7a89 455 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
Kojto 91:031413cf7a89 456 __I uint32_t RESERVED3[56];
Kojto 91:031413cf7a89 457 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
Kojto 91:031413cf7a89 458 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
Kojto 91:031413cf7a89 459 __I uint32_t RESERVED4[4];
Kojto 91:031413cf7a89 460 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
Kojto 91:031413cf7a89 461 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 462 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
Kojto 91:031413cf7a89 463 __I uint32_t RESERVED6[4];
Kojto 91:031413cf7a89 464 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
Kojto 91:031413cf7a89 465 __I uint32_t RESERVED7[49];
Kojto 91:031413cf7a89 466 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
Kojto 91:031413cf7a89 467 __I uint32_t RESERVED8[64];
Kojto 91:031413cf7a89 468 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 469 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 470 __I uint32_t RESERVED9[110];
Kojto 91:031413cf7a89 471 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
Kojto 91:031413cf7a89 472 __I uint32_t RESERVED10[14];
Kojto 91:031413cf7a89 473 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
Kojto 91:031413cf7a89 474 __I uint32_t RESERVED11;
Kojto 91:031413cf7a89 475 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
Kojto 91:031413cf7a89 476 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
Kojto 91:031413cf7a89 477 __I uint32_t RESERVED12[2];
Kojto 91:031413cf7a89 478 __IO uint32_t RXD; /*!< RX data register. */
Kojto 91:031413cf7a89 479 __IO uint32_t TXD; /*!< TX data register. */
Kojto 91:031413cf7a89 480 __I uint32_t RESERVED13;
Kojto 91:031413cf7a89 481 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
Kojto 91:031413cf7a89 482 __I uint32_t RESERVED14[24];
Kojto 91:031413cf7a89 483 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
Kojto 91:031413cf7a89 484 __I uint32_t RESERVED15[668];
Kojto 91:031413cf7a89 485 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 486 } NRF_TWI_Type;
Kojto 91:031413cf7a89 487
Kojto 91:031413cf7a89 488
Kojto 91:031413cf7a89 489 /* ================================================================================ */
Kojto 91:031413cf7a89 490 /* ================ SPIS ================ */
Kojto 91:031413cf7a89 491 /* ================================================================================ */
Kojto 91:031413cf7a89 492
Kojto 91:031413cf7a89 493
Kojto 91:031413cf7a89 494 /**
Kojto 91:031413cf7a89 495 * @brief SPI slave 1. (SPIS)
Kojto 91:031413cf7a89 496 */
Kojto 91:031413cf7a89 497
Kojto 91:031413cf7a89 498 typedef struct { /*!< SPIS Structure */
Kojto 91:031413cf7a89 499 __I uint32_t RESERVED0[9];
Kojto 91:031413cf7a89 500 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
Kojto 91:031413cf7a89 501 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
Kojto 91:031413cf7a89 502 __I uint32_t RESERVED1[54];
Kojto 91:031413cf7a89 503 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
Kojto 91:031413cf7a89 504 __I uint32_t RESERVED2[8];
Kojto 91:031413cf7a89 505 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
Kojto 91:031413cf7a89 506 __I uint32_t RESERVED3[53];
Kojto 91:031413cf7a89 507 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
Kojto 91:031413cf7a89 508 __I uint32_t RESERVED4[64];
Kojto 91:031413cf7a89 509 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 510 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 511 __I uint32_t RESERVED5[61];
Kojto 91:031413cf7a89 512 __I uint32_t SEMSTAT; /*!< Semaphore status. */
Kojto 91:031413cf7a89 513 __I uint32_t RESERVED6[15];
Kojto 91:031413cf7a89 514 __IO uint32_t STATUS; /*!< Status from last transaction. */
Kojto 91:031413cf7a89 515 __I uint32_t RESERVED7[47];
Kojto 91:031413cf7a89 516 __IO uint32_t ENABLE; /*!< Enable SPIS. */
Kojto 91:031413cf7a89 517 __I uint32_t RESERVED8;
Kojto 91:031413cf7a89 518 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
Kojto 91:031413cf7a89 519 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
Kojto 91:031413cf7a89 520 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
Kojto 91:031413cf7a89 521 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
Kojto 91:031413cf7a89 522 __I uint32_t RESERVED9[7];
Kojto 91:031413cf7a89 523 __IO uint32_t RXDPTR; /*!< RX data pointer. */
Kojto 91:031413cf7a89 524 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
Kojto 91:031413cf7a89 525 __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
Kojto 91:031413cf7a89 526 __I uint32_t RESERVED10;
Kojto 91:031413cf7a89 527 __IO uint32_t TXDPTR; /*!< TX data pointer. */
Kojto 91:031413cf7a89 528 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
Kojto 91:031413cf7a89 529 __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
Kojto 91:031413cf7a89 530 __I uint32_t RESERVED11;
Kojto 91:031413cf7a89 531 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 532 __I uint32_t RESERVED12;
Kojto 91:031413cf7a89 533 __IO uint32_t DEF; /*!< Default character. */
Kojto 91:031413cf7a89 534 __I uint32_t RESERVED13[24];
Kojto 91:031413cf7a89 535 __IO uint32_t ORC; /*!< Over-read character. */
Kojto 91:031413cf7a89 536 __I uint32_t RESERVED14[654];
Kojto 91:031413cf7a89 537 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 538 } NRF_SPIS_Type;
Kojto 91:031413cf7a89 539
Kojto 91:031413cf7a89 540
Kojto 91:031413cf7a89 541 /* ================================================================================ */
Kojto 91:031413cf7a89 542 /* ================ GPIOTE ================ */
Kojto 91:031413cf7a89 543 /* ================================================================================ */
Kojto 91:031413cf7a89 544
Kojto 91:031413cf7a89 545
Kojto 91:031413cf7a89 546 /**
Kojto 91:031413cf7a89 547 * @brief GPIO tasks and events. (GPIOTE)
Kojto 91:031413cf7a89 548 */
Kojto 91:031413cf7a89 549
Kojto 91:031413cf7a89 550 typedef struct { /*!< GPIOTE Structure */
Kojto 91:031413cf7a89 551 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
Kojto 91:031413cf7a89 552 __I uint32_t RESERVED0[60];
Kojto 91:031413cf7a89 553 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
Kojto 91:031413cf7a89 554 __I uint32_t RESERVED1[27];
Kojto 91:031413cf7a89 555 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
Kojto 91:031413cf7a89 556 __I uint32_t RESERVED2[97];
Kojto 91:031413cf7a89 557 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 558 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 559 __I uint32_t RESERVED3[129];
Kojto 91:031413cf7a89 560 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
Kojto 91:031413cf7a89 561 __I uint32_t RESERVED4[695];
Kojto 91:031413cf7a89 562 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 563 } NRF_GPIOTE_Type;
Kojto 91:031413cf7a89 564
Kojto 91:031413cf7a89 565
Kojto 91:031413cf7a89 566 /* ================================================================================ */
Kojto 91:031413cf7a89 567 /* ================ ADC ================ */
Kojto 91:031413cf7a89 568 /* ================================================================================ */
Kojto 91:031413cf7a89 569
Kojto 91:031413cf7a89 570
Kojto 91:031413cf7a89 571 /**
Kojto 91:031413cf7a89 572 * @brief Analog to digital converter. (ADC)
Kojto 91:031413cf7a89 573 */
Kojto 91:031413cf7a89 574
Kojto 91:031413cf7a89 575 typedef struct { /*!< ADC Structure */
Kojto 91:031413cf7a89 576 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
Kojto 91:031413cf7a89 577 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
Kojto 91:031413cf7a89 578 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 579 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
Kojto 91:031413cf7a89 580 __I uint32_t RESERVED1[128];
Kojto 91:031413cf7a89 581 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 582 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 583 __I uint32_t RESERVED2[61];
Kojto 91:031413cf7a89 584 __I uint32_t BUSY; /*!< ADC busy register. */
Kojto 91:031413cf7a89 585 __I uint32_t RESERVED3[63];
Kojto 91:031413cf7a89 586 __IO uint32_t ENABLE; /*!< ADC enable. */
Kojto 91:031413cf7a89 587 __IO uint32_t CONFIG; /*!< ADC configuration register. */
Kojto 91:031413cf7a89 588 __I uint32_t RESULT; /*!< Result of ADC conversion. */
Kojto 91:031413cf7a89 589 __I uint32_t RESERVED4[700];
Kojto 91:031413cf7a89 590 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 591 } NRF_ADC_Type;
Kojto 91:031413cf7a89 592
Kojto 91:031413cf7a89 593
Kojto 91:031413cf7a89 594 /* ================================================================================ */
Kojto 91:031413cf7a89 595 /* ================ TIMER ================ */
Kojto 91:031413cf7a89 596 /* ================================================================================ */
Kojto 91:031413cf7a89 597
Kojto 91:031413cf7a89 598
Kojto 91:031413cf7a89 599 /**
Kojto 91:031413cf7a89 600 * @brief Timer 0. (TIMER)
Kojto 91:031413cf7a89 601 */
Kojto 91:031413cf7a89 602
Kojto 91:031413cf7a89 603 typedef struct { /*!< TIMER Structure */
Kojto 91:031413cf7a89 604 __O uint32_t TASKS_START; /*!< Start Timer. */
Kojto 91:031413cf7a89 605 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
Kojto 91:031413cf7a89 606 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
Kojto 91:031413cf7a89 607 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
Kojto 91:031413cf7a89 608 __I uint32_t RESERVED0[12];
Kojto 91:031413cf7a89 609 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
Kojto 91:031413cf7a89 610 __I uint32_t RESERVED1[60];
Kojto 91:031413cf7a89 611 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
Kojto 91:031413cf7a89 612 __I uint32_t RESERVED2[44];
Kojto 91:031413cf7a89 613 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
Kojto 91:031413cf7a89 614 __I uint32_t RESERVED3[64];
Kojto 91:031413cf7a89 615 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 616 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 617 __I uint32_t RESERVED4[126];
Kojto 91:031413cf7a89 618 __IO uint32_t MODE; /*!< Timer Mode selection. */
Kojto 91:031413cf7a89 619 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
Kojto 91:031413cf7a89 620 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 621 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
Kojto 91:031413cf7a89 622 clock frequency is divided by 2^SCALE. */
Kojto 91:031413cf7a89 623 __I uint32_t RESERVED6[11];
Kojto 91:031413cf7a89 624 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
Kojto 91:031413cf7a89 625 __I uint32_t RESERVED7[683];
Kojto 91:031413cf7a89 626 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 627 } NRF_TIMER_Type;
Kojto 91:031413cf7a89 628
Kojto 91:031413cf7a89 629
Kojto 91:031413cf7a89 630 /* ================================================================================ */
Kojto 91:031413cf7a89 631 /* ================ RTC ================ */
Kojto 91:031413cf7a89 632 /* ================================================================================ */
Kojto 91:031413cf7a89 633
Kojto 91:031413cf7a89 634
Kojto 91:031413cf7a89 635 /**
Kojto 91:031413cf7a89 636 * @brief Real time counter 0. (RTC)
Kojto 91:031413cf7a89 637 */
Kojto 91:031413cf7a89 638
Kojto 91:031413cf7a89 639 typedef struct { /*!< RTC Structure */
Kojto 91:031413cf7a89 640 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
Kojto 91:031413cf7a89 641 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
Kojto 91:031413cf7a89 642 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
Kojto 91:031413cf7a89 643 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
Kojto 91:031413cf7a89 644 __I uint32_t RESERVED0[60];
Kojto 91:031413cf7a89 645 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
Kojto 91:031413cf7a89 646 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
Kojto 91:031413cf7a89 647 __I uint32_t RESERVED1[14];
Kojto 91:031413cf7a89 648 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
Kojto 91:031413cf7a89 649 __I uint32_t RESERVED2[109];
Kojto 91:031413cf7a89 650 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 651 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 652 __I uint32_t RESERVED3[13];
Kojto 91:031413cf7a89 653 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
Kojto 91:031413cf7a89 654 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
Kojto 91:031413cf7a89 655 the value of EVTEN. */
Kojto 91:031413cf7a89 656 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
Kojto 91:031413cf7a89 657 gives the value of EVTEN. */
Kojto 91:031413cf7a89 658 __I uint32_t RESERVED4[110];
Kojto 91:031413cf7a89 659 __IO uint32_t COUNTER; /*!< Current COUNTER value. */
Kojto 91:031413cf7a89 660 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
Kojto 91:031413cf7a89 661 Must be written when RTC is STOPed. */
Kojto 91:031413cf7a89 662 __I uint32_t RESERVED5[13];
Kojto 91:031413cf7a89 663 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
Kojto 91:031413cf7a89 664 __I uint32_t RESERVED6[683];
Kojto 91:031413cf7a89 665 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 666 } NRF_RTC_Type;
Kojto 91:031413cf7a89 667
Kojto 91:031413cf7a89 668
Kojto 91:031413cf7a89 669 /* ================================================================================ */
Kojto 91:031413cf7a89 670 /* ================ TEMP ================ */
Kojto 91:031413cf7a89 671 /* ================================================================================ */
Kojto 91:031413cf7a89 672
Kojto 91:031413cf7a89 673
Kojto 91:031413cf7a89 674 /**
Kojto 91:031413cf7a89 675 * @brief Temperature Sensor. (TEMP)
Kojto 91:031413cf7a89 676 */
Kojto 91:031413cf7a89 677
Kojto 91:031413cf7a89 678 typedef struct { /*!< TEMP Structure */
Kojto 91:031413cf7a89 679 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
Kojto 91:031413cf7a89 680 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
Kojto 91:031413cf7a89 681 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 682 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
Kojto 91:031413cf7a89 683 __I uint32_t RESERVED1[128];
Kojto 91:031413cf7a89 684 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 685 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 686 __I uint32_t RESERVED2[127];
Kojto 91:031413cf7a89 687 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
Kojto 91:031413cf7a89 688 __I uint32_t RESERVED3[700];
Kojto 91:031413cf7a89 689 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 690 } NRF_TEMP_Type;
Kojto 91:031413cf7a89 691
Kojto 91:031413cf7a89 692
Kojto 91:031413cf7a89 693 /* ================================================================================ */
Kojto 91:031413cf7a89 694 /* ================ RNG ================ */
Kojto 91:031413cf7a89 695 /* ================================================================================ */
Kojto 91:031413cf7a89 696
Kojto 91:031413cf7a89 697
Kojto 91:031413cf7a89 698 /**
Kojto 91:031413cf7a89 699 * @brief Random Number Generator. (RNG)
Kojto 91:031413cf7a89 700 */
Kojto 91:031413cf7a89 701
Kojto 91:031413cf7a89 702 typedef struct { /*!< RNG Structure */
Kojto 91:031413cf7a89 703 __O uint32_t TASKS_START; /*!< Start the random number generator. */
Kojto 91:031413cf7a89 704 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
Kojto 91:031413cf7a89 705 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 706 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
Kojto 91:031413cf7a89 707 __I uint32_t RESERVED1[63];
Kojto 91:031413cf7a89 708 __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
Kojto 91:031413cf7a89 709 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 710 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
Kojto 91:031413cf7a89 711 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
Kojto 91:031413cf7a89 712 __I uint32_t RESERVED3[126];
Kojto 91:031413cf7a89 713 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 714 __I uint32_t VALUE; /*!< RNG random number. */
Kojto 91:031413cf7a89 715 __I uint32_t RESERVED4[700];
Kojto 91:031413cf7a89 716 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 717 } NRF_RNG_Type;
Kojto 91:031413cf7a89 718
Kojto 91:031413cf7a89 719
Kojto 91:031413cf7a89 720 /* ================================================================================ */
Kojto 91:031413cf7a89 721 /* ================ ECB ================ */
Kojto 91:031413cf7a89 722 /* ================================================================================ */
Kojto 91:031413cf7a89 723
Kojto 91:031413cf7a89 724
Kojto 91:031413cf7a89 725 /**
Kojto 91:031413cf7a89 726 * @brief AES ECB Mode Encryption. (ECB)
Kojto 91:031413cf7a89 727 */
Kojto 91:031413cf7a89 728
Kojto 91:031413cf7a89 729 typedef struct { /*!< ECB Structure */
Kojto 91:031413cf7a89 730 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
Kojto 91:031413cf7a89 731 will not initiate a new encryption and the ERRORECB event will
Kojto 91:031413cf7a89 732 be triggered. */
Kojto 91:031413cf7a89 733 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
Kojto 91:031413cf7a89 734 this will will trigger the ERRORECB event. */
Kojto 91:031413cf7a89 735 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 736 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
Kojto 91:031413cf7a89 737 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
Kojto 91:031413cf7a89 738 error. */
Kojto 91:031413cf7a89 739 __I uint32_t RESERVED1[127];
Kojto 91:031413cf7a89 740 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 741 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 742 __I uint32_t RESERVED2[126];
Kojto 91:031413cf7a89 743 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
Kojto 91:031413cf7a89 744 __I uint32_t RESERVED3[701];
Kojto 91:031413cf7a89 745 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 746 } NRF_ECB_Type;
Kojto 91:031413cf7a89 747
Kojto 91:031413cf7a89 748
Kojto 91:031413cf7a89 749 /* ================================================================================ */
Kojto 91:031413cf7a89 750 /* ================ AAR ================ */
Kojto 91:031413cf7a89 751 /* ================================================================================ */
Kojto 91:031413cf7a89 752
Kojto 91:031413cf7a89 753
Kojto 91:031413cf7a89 754 /**
Kojto 91:031413cf7a89 755 * @brief Accelerated Address Resolver. (AAR)
Kojto 91:031413cf7a89 756 */
Kojto 91:031413cf7a89 757
Kojto 91:031413cf7a89 758 typedef struct { /*!< AAR Structure */
Kojto 91:031413cf7a89 759 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
Kojto 91:031413cf7a89 760 data structure. */
Kojto 91:031413cf7a89 761 __I uint32_t RESERVED0;
Kojto 91:031413cf7a89 762 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
Kojto 91:031413cf7a89 763 __I uint32_t RESERVED1[61];
Kojto 91:031413cf7a89 764 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
Kojto 91:031413cf7a89 765 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
Kojto 91:031413cf7a89 766 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
Kojto 91:031413cf7a89 767 __I uint32_t RESERVED2[126];
Kojto 91:031413cf7a89 768 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 769 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 770 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 771 __I uint32_t STATUS; /*!< Resolution status. */
Kojto 91:031413cf7a89 772 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 773 __IO uint32_t ENABLE; /*!< Enable AAR. */
Kojto 91:031413cf7a89 774 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
Kojto 91:031413cf7a89 775 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
Kojto 91:031413cf7a89 776 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 777 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
Kojto 91:031413cf7a89 778 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
Kojto 91:031413cf7a89 779 resolution. A minimum of 3 bytes must be reserved. */
Kojto 91:031413cf7a89 780 __I uint32_t RESERVED6[697];
Kojto 91:031413cf7a89 781 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 782 } NRF_AAR_Type;
Kojto 91:031413cf7a89 783
Kojto 91:031413cf7a89 784
Kojto 91:031413cf7a89 785 /* ================================================================================ */
Kojto 91:031413cf7a89 786 /* ================ CCM ================ */
Kojto 91:031413cf7a89 787 /* ================================================================================ */
Kojto 91:031413cf7a89 788
Kojto 91:031413cf7a89 789
Kojto 91:031413cf7a89 790 /**
Kojto 91:031413cf7a89 791 * @brief AES CCM Mode Encryption. (CCM)
Kojto 91:031413cf7a89 792 */
Kojto 91:031413cf7a89 793
Kojto 91:031413cf7a89 794 typedef struct { /*!< CCM Structure */
Kojto 91:031413cf7a89 795 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
Kojto 91:031413cf7a89 796 itself when completed. */
Kojto 91:031413cf7a89 797 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
Kojto 91:031413cf7a89 798 completed. */
Kojto 91:031413cf7a89 799 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
Kojto 91:031413cf7a89 800 __I uint32_t RESERVED0[61];
Kojto 91:031413cf7a89 801 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
Kojto 91:031413cf7a89 802 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
Kojto 91:031413cf7a89 803 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
Kojto 91:031413cf7a89 804 __I uint32_t RESERVED1[61];
Kojto 91:031413cf7a89 805 __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
Kojto 91:031413cf7a89 806 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 807 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 808 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 809 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 810 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
Kojto 91:031413cf7a89 811 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 812 __IO uint32_t ENABLE; /*!< CCM enable. */
Kojto 91:031413cf7a89 813 __IO uint32_t MODE; /*!< Operation mode. */
Kojto 91:031413cf7a89 814 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
Kojto 91:031413cf7a89 815 __IO uint32_t INPTR; /*!< Pointer to input packet. */
Kojto 91:031413cf7a89 816 __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
Kojto 91:031413cf7a89 817 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
Kojto 91:031413cf7a89 818 resolution. A minimum of 43 bytes must be reserved. */
Kojto 91:031413cf7a89 819 __I uint32_t RESERVED5[697];
Kojto 91:031413cf7a89 820 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 821 } NRF_CCM_Type;
Kojto 91:031413cf7a89 822
Kojto 91:031413cf7a89 823
Kojto 91:031413cf7a89 824 /* ================================================================================ */
Kojto 91:031413cf7a89 825 /* ================ WDT ================ */
Kojto 91:031413cf7a89 826 /* ================================================================================ */
Kojto 91:031413cf7a89 827
Kojto 91:031413cf7a89 828
Kojto 91:031413cf7a89 829 /**
Kojto 91:031413cf7a89 830 * @brief Watchdog Timer. (WDT)
Kojto 91:031413cf7a89 831 */
Kojto 91:031413cf7a89 832
Kojto 91:031413cf7a89 833 typedef struct { /*!< WDT Structure */
Kojto 91:031413cf7a89 834 __O uint32_t TASKS_START; /*!< Start the watchdog. */
Kojto 91:031413cf7a89 835 __I uint32_t RESERVED0[63];
Kojto 91:031413cf7a89 836 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
Kojto 91:031413cf7a89 837 __I uint32_t RESERVED1[128];
Kojto 91:031413cf7a89 838 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 839 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 840 __I uint32_t RESERVED2[61];
Kojto 91:031413cf7a89 841 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
Kojto 91:031413cf7a89 842 __I uint32_t REQSTATUS; /*!< Request status. */
Kojto 91:031413cf7a89 843 __I uint32_t RESERVED3[63];
Kojto 91:031413cf7a89 844 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
Kojto 91:031413cf7a89 845 __IO uint32_t RREN; /*!< Reload request enable. */
Kojto 91:031413cf7a89 846 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 847 __I uint32_t RESERVED4[60];
Kojto 91:031413cf7a89 848 __O uint32_t RR[8]; /*!< Reload requests registers. */
Kojto 91:031413cf7a89 849 __I uint32_t RESERVED5[631];
Kojto 91:031413cf7a89 850 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 851 } NRF_WDT_Type;
Kojto 91:031413cf7a89 852
Kojto 91:031413cf7a89 853
Kojto 91:031413cf7a89 854 /* ================================================================================ */
Kojto 91:031413cf7a89 855 /* ================ QDEC ================ */
Kojto 91:031413cf7a89 856 /* ================================================================================ */
Kojto 91:031413cf7a89 857
Kojto 91:031413cf7a89 858
Kojto 91:031413cf7a89 859 /**
Kojto 91:031413cf7a89 860 * @brief Rotary decoder. (QDEC)
Kojto 91:031413cf7a89 861 */
Kojto 91:031413cf7a89 862
Kojto 91:031413cf7a89 863 typedef struct { /*!< QDEC Structure */
Kojto 91:031413cf7a89 864 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
Kojto 91:031413cf7a89 865 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
Kojto 91:031413cf7a89 866 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
Kojto 91:031413cf7a89 867 and clears the ACC registers. */
Kojto 91:031413cf7a89 868 __I uint32_t RESERVED0[61];
Kojto 91:031413cf7a89 869 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
Kojto 91:031413cf7a89 870 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
Kojto 91:031413cf7a89 871 ACC register different than zero. */
Kojto 91:031413cf7a89 872 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
Kojto 91:031413cf7a89 873 __I uint32_t RESERVED1[61];
Kojto 91:031413cf7a89 874 __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
Kojto 91:031413cf7a89 875 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 876 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 877 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 878 __I uint32_t RESERVED3[125];
Kojto 91:031413cf7a89 879 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
Kojto 91:031413cf7a89 880 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
Kojto 91:031413cf7a89 881 __IO uint32_t SAMPLEPER; /*!< Sample period. */
Kojto 91:031413cf7a89 882 __I int32_t SAMPLE; /*!< Motion sample value. */
Kojto 91:031413cf7a89 883 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
Kojto 91:031413cf7a89 884 __I int32_t ACC; /*!< Accumulated valid transitions register. */
Kojto 91:031413cf7a89 885 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
Kojto 91:031413cf7a89 886 task. */
Kojto 91:031413cf7a89 887 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
Kojto 91:031413cf7a89 888 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
Kojto 91:031413cf7a89 889 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
Kojto 91:031413cf7a89 890 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
Kojto 91:031413cf7a89 891 __I uint32_t RESERVED4[5];
Kojto 91:031413cf7a89 892 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
Kojto 91:031413cf7a89 893 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
Kojto 91:031413cf7a89 894 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
Kojto 91:031413cf7a89 895 task. */
Kojto 91:031413cf7a89 896 __I uint32_t RESERVED5[684];
Kojto 91:031413cf7a89 897 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 898 } NRF_QDEC_Type;
Kojto 91:031413cf7a89 899
Kojto 91:031413cf7a89 900
Kojto 91:031413cf7a89 901 /* ================================================================================ */
Kojto 91:031413cf7a89 902 /* ================ LPCOMP ================ */
Kojto 91:031413cf7a89 903 /* ================================================================================ */
Kojto 91:031413cf7a89 904
Kojto 91:031413cf7a89 905
Kojto 91:031413cf7a89 906 /**
Kojto 91:031413cf7a89 907 * @brief Wakeup Comparator. (LPCOMP)
Kojto 91:031413cf7a89 908 */
Kojto 91:031413cf7a89 909
Kojto 91:031413cf7a89 910 typedef struct { /*!< LPCOMP Structure */
Kojto 91:031413cf7a89 911 __O uint32_t TASKS_START; /*!< Start the comparator. */
Kojto 91:031413cf7a89 912 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
Kojto 91:031413cf7a89 913 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
Kojto 91:031413cf7a89 914 __I uint32_t RESERVED0[61];
Kojto 91:031413cf7a89 915 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
Kojto 91:031413cf7a89 916 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
Kojto 91:031413cf7a89 917 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
Kojto 91:031413cf7a89 918 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
Kojto 91:031413cf7a89 919 __I uint32_t RESERVED1[60];
Kojto 91:031413cf7a89 920 __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
Kojto 91:031413cf7a89 921 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 922 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 923 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 924 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 925 __I uint32_t RESULT; /*!< Result of last compare. */
Kojto 91:031413cf7a89 926 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 927 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
Kojto 91:031413cf7a89 928 __IO uint32_t PSEL; /*!< Input pin select. */
Kojto 91:031413cf7a89 929 __IO uint32_t REFSEL; /*!< Reference select. */
Kojto 91:031413cf7a89 930 __IO uint32_t EXTREFSEL; /*!< External reference select. */
Kojto 91:031413cf7a89 931 __I uint32_t RESERVED5[4];
Kojto 91:031413cf7a89 932 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
Kojto 91:031413cf7a89 933 __I uint32_t RESERVED6[694];
Kojto 91:031413cf7a89 934 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 935 } NRF_LPCOMP_Type;
Kojto 91:031413cf7a89 936
Kojto 91:031413cf7a89 937
Kojto 91:031413cf7a89 938 /* ================================================================================ */
Kojto 91:031413cf7a89 939 /* ================ COMP ================ */
Kojto 91:031413cf7a89 940 /* ================================================================================ */
Kojto 91:031413cf7a89 941
Kojto 91:031413cf7a89 942
Kojto 91:031413cf7a89 943 /**
Kojto 91:031413cf7a89 944 * @brief Comparator. (COMP)
Kojto 91:031413cf7a89 945 */
Kojto 91:031413cf7a89 946
Kojto 91:031413cf7a89 947 typedef struct { /*!< COMP Structure */
Kojto 91:031413cf7a89 948 __O uint32_t TASKS_START; /*!< Start the comparator. */
Kojto 91:031413cf7a89 949 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
Kojto 91:031413cf7a89 950 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
Kojto 91:031413cf7a89 951 __I uint32_t RESERVED0[61];
Kojto 91:031413cf7a89 952 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
Kojto 91:031413cf7a89 953 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
Kojto 91:031413cf7a89 954 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
Kojto 91:031413cf7a89 955 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
Kojto 91:031413cf7a89 956 __I uint32_t RESERVED1[60];
Kojto 91:031413cf7a89 957 __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
Kojto 91:031413cf7a89 958 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 959 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 960 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 961 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 962 __I uint32_t RESULT; /*!< Compare result. */
Kojto 91:031413cf7a89 963 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 964 __IO uint32_t ENABLE; /*!< Enable the COMP. */
Kojto 91:031413cf7a89 965 __IO uint32_t PSEL; /*!< Input pin select. */
Kojto 91:031413cf7a89 966 __IO uint32_t REFSEL; /*!< Reference select. */
Kojto 91:031413cf7a89 967 __IO uint32_t EXTREFSEL; /*!< External reference select. */
Kojto 91:031413cf7a89 968 __I uint32_t RESERVED5[8];
Kojto 91:031413cf7a89 969 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
Kojto 91:031413cf7a89 970 __IO uint32_t MODE; /*!< Mode configuration. */
Kojto 91:031413cf7a89 971 __I uint32_t RESERVED6[689];
Kojto 91:031413cf7a89 972 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 973 } NRF_COMP_Type;
Kojto 91:031413cf7a89 974
Kojto 91:031413cf7a89 975
Kojto 91:031413cf7a89 976 /* ================================================================================ */
Kojto 91:031413cf7a89 977 /* ================ SWI ================ */
Kojto 91:031413cf7a89 978 /* ================================================================================ */
Kojto 91:031413cf7a89 979
Kojto 91:031413cf7a89 980
Kojto 91:031413cf7a89 981 /**
Kojto 91:031413cf7a89 982 * @brief SW Interrupts. (SWI)
Kojto 91:031413cf7a89 983 */
Kojto 91:031413cf7a89 984
Kojto 91:031413cf7a89 985 typedef struct { /*!< SWI Structure */
Kojto 91:031413cf7a89 986 __I uint32_t UNUSED; /*!< Unused. */
Kojto 91:031413cf7a89 987 } NRF_SWI_Type;
Kojto 91:031413cf7a89 988
Kojto 91:031413cf7a89 989
Kojto 91:031413cf7a89 990 /* ================================================================================ */
Kojto 91:031413cf7a89 991 /* ================ NVMC ================ */
Kojto 91:031413cf7a89 992 /* ================================================================================ */
Kojto 91:031413cf7a89 993
Kojto 91:031413cf7a89 994
Kojto 91:031413cf7a89 995 /**
Kojto 91:031413cf7a89 996 * @brief Non Volatile Memory Controller. (NVMC)
Kojto 91:031413cf7a89 997 */
Kojto 91:031413cf7a89 998
Kojto 91:031413cf7a89 999 typedef struct { /*!< NVMC Structure */
Kojto 91:031413cf7a89 1000 __I uint32_t RESERVED0[256];
Kojto 91:031413cf7a89 1001 __I uint32_t READY; /*!< Ready flag. */
Kojto 91:031413cf7a89 1002 __I uint32_t RESERVED1[64];
Kojto 91:031413cf7a89 1003 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 1004 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
Kojto 91:031413cf7a89 1005 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
Kojto 91:031413cf7a89 1006 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
Kojto 91:031413cf7a89 1007 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
Kojto 91:031413cf7a89 1008 } NRF_NVMC_Type;
Kojto 91:031413cf7a89 1009
Kojto 91:031413cf7a89 1010
Kojto 91:031413cf7a89 1011 /* ================================================================================ */
Kojto 91:031413cf7a89 1012 /* ================ PPI ================ */
Kojto 91:031413cf7a89 1013 /* ================================================================================ */
Kojto 91:031413cf7a89 1014
Kojto 91:031413cf7a89 1015
Kojto 91:031413cf7a89 1016 /**
Kojto 91:031413cf7a89 1017 * @brief PPI controller. (PPI)
Kojto 91:031413cf7a89 1018 */
Kojto 91:031413cf7a89 1019
Kojto 91:031413cf7a89 1020 typedef struct { /*!< PPI Structure */
Kojto 91:031413cf7a89 1021 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
Kojto 91:031413cf7a89 1022 __I uint32_t RESERVED0[312];
Kojto 91:031413cf7a89 1023 __IO uint32_t CHEN; /*!< Channel enable. */
Kojto 91:031413cf7a89 1024 __IO uint32_t CHENSET; /*!< Channel enable set. */
Kojto 91:031413cf7a89 1025 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
Kojto 91:031413cf7a89 1026 __I uint32_t RESERVED1;
Kojto 91:031413cf7a89 1027 PPI_CH_Type CH[16]; /*!< PPI Channel. */
Kojto 91:031413cf7a89 1028 __I uint32_t RESERVED2[156];
Kojto 91:031413cf7a89 1029 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
Kojto 91:031413cf7a89 1030 } NRF_PPI_Type;
Kojto 91:031413cf7a89 1031
Kojto 91:031413cf7a89 1032
Kojto 91:031413cf7a89 1033 /* ================================================================================ */
Kojto 91:031413cf7a89 1034 /* ================ FICR ================ */
Kojto 91:031413cf7a89 1035 /* ================================================================================ */
Kojto 91:031413cf7a89 1036
Kojto 91:031413cf7a89 1037
Kojto 91:031413cf7a89 1038 /**
Kojto 91:031413cf7a89 1039 * @brief Factory Information Configuration. (FICR)
Kojto 91:031413cf7a89 1040 */
Kojto 91:031413cf7a89 1041
Kojto 91:031413cf7a89 1042 typedef struct { /*!< FICR Structure */
Kojto 91:031413cf7a89 1043 __I uint32_t RESERVED0[4];
Kojto 91:031413cf7a89 1044 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
Kojto 91:031413cf7a89 1045 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
Kojto 91:031413cf7a89 1046 __I uint32_t RESERVED1[4];
Kojto 91:031413cf7a89 1047 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
Kojto 91:031413cf7a89 1048 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
Kojto 91:031413cf7a89 1049 __I uint32_t RESERVED2;
Kojto 91:031413cf7a89 1050 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
Kojto 91:031413cf7a89 1051 __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
Kojto 91:031413cf7a89 1052 __I uint32_t RESERVED3[5];
Kojto 91:031413cf7a89 1053 __I uint32_t CONFIGID; /*!< Configuration identifier. */
Kojto 91:031413cf7a89 1054 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
Kojto 91:031413cf7a89 1055 __I uint32_t RESERVED4[6];
Kojto 91:031413cf7a89 1056 __I uint32_t ER[4]; /*!< Encryption root. */
Kojto 91:031413cf7a89 1057 __I uint32_t IR[4]; /*!< Identity root. */
Kojto 91:031413cf7a89 1058 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
Kojto 91:031413cf7a89 1059 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
Kojto 91:031413cf7a89 1060 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
Kojto 91:031413cf7a89 1061 __I uint32_t RESERVED5[15];
Kojto 91:031413cf7a89 1062 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
Kojto 91:031413cf7a89 1063 mode. */
Kojto 91:031413cf7a89 1064 } NRF_FICR_Type;
Kojto 91:031413cf7a89 1065
Kojto 91:031413cf7a89 1066
Kojto 91:031413cf7a89 1067 /* ================================================================================ */
Kojto 91:031413cf7a89 1068 /* ================ UICR ================ */
Kojto 91:031413cf7a89 1069 /* ================================================================================ */
Kojto 91:031413cf7a89 1070
Kojto 91:031413cf7a89 1071
Kojto 91:031413cf7a89 1072 /**
Kojto 91:031413cf7a89 1073 * @brief User Information Configuration. (UICR)
Kojto 91:031413cf7a89 1074 */
Kojto 91:031413cf7a89 1075
Kojto 91:031413cf7a89 1076 typedef struct { /*!< UICR Structure */
Kojto 91:031413cf7a89 1077 __IO uint32_t CLENR0; /*!< Length of code region 0. */
Kojto 91:031413cf7a89 1078 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
Kojto 91:031413cf7a89 1079 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
Kojto 91:031413cf7a89 1080 __I uint32_t RESERVED0;
Kojto 91:031413cf7a89 1081 __I uint32_t FWID; /*!< Firmware ID. */
Kojto 91:031413cf7a89 1082 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
Kojto 91:031413cf7a89 1083 } NRF_UICR_Type;
Kojto 91:031413cf7a89 1084
Kojto 91:031413cf7a89 1085
Kojto 91:031413cf7a89 1086 /* ================================================================================ */
Kojto 91:031413cf7a89 1087 /* ================ GPIO ================ */
Kojto 91:031413cf7a89 1088 /* ================================================================================ */
Kojto 91:031413cf7a89 1089
Kojto 91:031413cf7a89 1090
Kojto 91:031413cf7a89 1091 /**
Kojto 91:031413cf7a89 1092 * @brief General purpose input and output. (GPIO)
Kojto 91:031413cf7a89 1093 */
Kojto 91:031413cf7a89 1094
Kojto 91:031413cf7a89 1095 typedef struct { /*!< GPIO Structure */
Kojto 91:031413cf7a89 1096 __I uint32_t RESERVED0[321];
Kojto 91:031413cf7a89 1097 __IO uint32_t OUT; /*!< Write GPIO port. */
Kojto 91:031413cf7a89 1098 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
Kojto 91:031413cf7a89 1099 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
Kojto 91:031413cf7a89 1100 __I uint32_t IN; /*!< Read GPIO port. */
Kojto 91:031413cf7a89 1101 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
Kojto 91:031413cf7a89 1102 __IO uint32_t DIRSET; /*!< DIR set register. */
Kojto 91:031413cf7a89 1103 __IO uint32_t DIRCLR; /*!< DIR clear register. */
Kojto 91:031413cf7a89 1104 __I uint32_t RESERVED1[120];
Kojto 91:031413cf7a89 1105 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
Kojto 91:031413cf7a89 1106 } NRF_GPIO_Type;
Kojto 91:031413cf7a89 1107
Kojto 91:031413cf7a89 1108
Kojto 91:031413cf7a89 1109 /* -------------------- End of section using anonymous unions ------------------- */
Kojto 91:031413cf7a89 1110 #if defined(__CC_ARM)
Kojto 91:031413cf7a89 1111 #pragma pop
Kojto 91:031413cf7a89 1112 #elif defined(__ICCARM__)
Kojto 91:031413cf7a89 1113 /* leave anonymous unions enabled */
Kojto 91:031413cf7a89 1114 #elif defined(__GNUC__)
Kojto 91:031413cf7a89 1115 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 1116 #elif defined(__TMS470__)
Kojto 91:031413cf7a89 1117 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 1118 #elif defined(__TASKING__)
Kojto 91:031413cf7a89 1119 #pragma warning restore
Kojto 91:031413cf7a89 1120 #else
Kojto 91:031413cf7a89 1121 #warning Not supported compiler type
Kojto 91:031413cf7a89 1122 #endif
Kojto 91:031413cf7a89 1123
Kojto 91:031413cf7a89 1124
Kojto 91:031413cf7a89 1125
Kojto 91:031413cf7a89 1126
Kojto 91:031413cf7a89 1127 /* ================================================================================ */
Kojto 91:031413cf7a89 1128 /* ================ Peripheral memory map ================ */
Kojto 91:031413cf7a89 1129 /* ================================================================================ */
Kojto 91:031413cf7a89 1130
Kojto 91:031413cf7a89 1131 #define NRF_POWER_BASE 0x40000000UL
Kojto 91:031413cf7a89 1132 #define NRF_CLOCK_BASE 0x40000000UL
Kojto 91:031413cf7a89 1133 #define NRF_MPU_BASE 0x40000000UL
Kojto 91:031413cf7a89 1134 #define NRF_PU_BASE 0x40000000UL
Kojto 91:031413cf7a89 1135 #define NRF_AMLI_BASE 0x40000000UL
Kojto 91:031413cf7a89 1136 #define NRF_RADIO_BASE 0x40001000UL
Kojto 91:031413cf7a89 1137 #define NRF_UART0_BASE 0x40002000UL
Kojto 91:031413cf7a89 1138 #define NRF_SPI0_BASE 0x40003000UL
Kojto 91:031413cf7a89 1139 #define NRF_TWI0_BASE 0x40003000UL
Kojto 91:031413cf7a89 1140 #define NRF_SPI1_BASE 0x40004000UL
Kojto 91:031413cf7a89 1141 #define NRF_TWI1_BASE 0x40004000UL
Kojto 91:031413cf7a89 1142 #define NRF_SPIS1_BASE 0x40004000UL
Kojto 91:031413cf7a89 1143 #define NRF_GPIOTE_BASE 0x40006000UL
Kojto 91:031413cf7a89 1144 #define NRF_ADC_BASE 0x40007000UL
Kojto 91:031413cf7a89 1145 #define NRF_TIMER0_BASE 0x40008000UL
Kojto 91:031413cf7a89 1146 #define NRF_TIMER1_BASE 0x40009000UL
Kojto 91:031413cf7a89 1147 #define NRF_TIMER2_BASE 0x4000A000UL
Kojto 91:031413cf7a89 1148 #define NRF_RTC0_BASE 0x4000B000UL
Kojto 91:031413cf7a89 1149 #define NRF_TEMP_BASE 0x4000C000UL
Kojto 91:031413cf7a89 1150 #define NRF_RNG_BASE 0x4000D000UL
Kojto 91:031413cf7a89 1151 #define NRF_ECB_BASE 0x4000E000UL
Kojto 91:031413cf7a89 1152 #define NRF_AAR_BASE 0x4000F000UL
Kojto 91:031413cf7a89 1153 #define NRF_CCM_BASE 0x4000F000UL
Kojto 91:031413cf7a89 1154 #define NRF_WDT_BASE 0x40010000UL
Kojto 91:031413cf7a89 1155 #define NRF_RTC1_BASE 0x40011000UL
Kojto 91:031413cf7a89 1156 #define NRF_QDEC_BASE 0x40012000UL
Kojto 91:031413cf7a89 1157 #define NRF_LPCOMP_BASE 0x40013000UL
Kojto 91:031413cf7a89 1158 #define NRF_COMP_BASE 0x40013000UL
Kojto 91:031413cf7a89 1159 #define NRF_SWI_BASE 0x40014000UL
Kojto 91:031413cf7a89 1160 #define NRF_NVMC_BASE 0x4001E000UL
Kojto 91:031413cf7a89 1161 #define NRF_PPI_BASE 0x4001F000UL
Kojto 91:031413cf7a89 1162 #define NRF_FICR_BASE 0x10000000UL
Kojto 91:031413cf7a89 1163 #define NRF_UICR_BASE 0x10001000UL
Kojto 91:031413cf7a89 1164 #define NRF_GPIO_BASE 0x50000000UL
Kojto 91:031413cf7a89 1165
Kojto 91:031413cf7a89 1166
Kojto 91:031413cf7a89 1167 /* ================================================================================ */
Kojto 91:031413cf7a89 1168 /* ================ Peripheral declaration ================ */
Kojto 91:031413cf7a89 1169 /* ================================================================================ */
Kojto 91:031413cf7a89 1170
Kojto 91:031413cf7a89 1171 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
Kojto 91:031413cf7a89 1172 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
Kojto 91:031413cf7a89 1173 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
Kojto 91:031413cf7a89 1174 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
Kojto 91:031413cf7a89 1175 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
Kojto 91:031413cf7a89 1176 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
Kojto 91:031413cf7a89 1177 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
Kojto 91:031413cf7a89 1178 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
Kojto 91:031413cf7a89 1179 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
Kojto 91:031413cf7a89 1180 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
Kojto 91:031413cf7a89 1181 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
Kojto 91:031413cf7a89 1182 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Kojto 91:031413cf7a89 1183 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
Kojto 91:031413cf7a89 1184 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
Kojto 91:031413cf7a89 1185 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
Kojto 91:031413cf7a89 1186 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
Kojto 91:031413cf7a89 1187 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
Kojto 91:031413cf7a89 1188 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
Kojto 91:031413cf7a89 1189 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
Kojto 91:031413cf7a89 1190 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
Kojto 91:031413cf7a89 1191 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
Kojto 91:031413cf7a89 1192 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
Kojto 91:031413cf7a89 1193 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
Kojto 91:031413cf7a89 1194 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
Kojto 91:031413cf7a89 1195 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
Kojto 91:031413cf7a89 1196 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
Kojto 91:031413cf7a89 1197 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
Kojto 91:031413cf7a89 1198 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
Kojto 91:031413cf7a89 1199 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
Kojto 91:031413cf7a89 1200 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
Kojto 91:031413cf7a89 1201 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
Kojto 91:031413cf7a89 1202 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
Kojto 91:031413cf7a89 1203 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
Kojto 91:031413cf7a89 1204 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
Kojto 91:031413cf7a89 1205
Kojto 91:031413cf7a89 1206
Kojto 91:031413cf7a89 1207 /** @} */ /* End of group Device_Peripheral_Registers */
Kojto 91:031413cf7a89 1208 /** @} */ /* End of group nRF51 */
Kojto 91:031413cf7a89 1209 /** @} */ /* End of group Nordic Semiconductor */
Kojto 91:031413cf7a89 1210
Kojto 91:031413cf7a89 1211 #ifdef __cplusplus
Kojto 91:031413cf7a89 1212 }
Kojto 91:031413cf7a89 1213 #endif
Kojto 91:031413cf7a89 1214
Kojto 91:031413cf7a89 1215
Kojto 91:031413cf7a89 1216 #endif /* nRF51_H */