Filippo Casamassima / mbed

my fork

Dependents:   Nucleo_blueNRG

Fork of mbed by mbed official

TARGET_NUCLEO_L053R8/stm32l0xx_hal_spi.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:
filartrix
Date:
Wed Apr 08 14:12:53 2015 +0000
Revision:
97:4298809c7c9e
Parent:
96:487b796308b0 
First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_spi.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
Kojto 96:487b796308b0 5 * @version V1.2.0
Kojto 96:487b796308b0 6 * @date 06-February-2015
bogdanm 84:0b3ab51c8877 7 * @brief Header file of SPI HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
Kojto 96:487b796308b0 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_SPI_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_SPI_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
bogdanm 84:0b3ab51c8877 53 /** @addtogroup SPI
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 /* Exported types ------------------------------------------------------------*/
Kojto 96:487b796308b0 58 /** @defgroup SPI_Exported_Types SPI Exported Types
Kojto 96:487b796308b0 59 * @{
Kojto 96:487b796308b0 60 */
bogdanm 84:0b3ab51c8877 61
bogdanm 84:0b3ab51c8877 62 /**
bogdanm 84:0b3ab51c8877 63 * @brief SPI Configuration Structure definition
bogdanm 84:0b3ab51c8877 64 */
bogdanm 84:0b3ab51c8877 65 typedef struct
bogdanm 84:0b3ab51c8877 66 {
bogdanm 84:0b3ab51c8877 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
bogdanm 84:0b3ab51c8877 68 This parameter can be a value of @ref SPI_mode */
bogdanm 84:0b3ab51c8877 69
bogdanm 84:0b3ab51c8877 70 uint32_t Direction; /*!< Specifies the SPI Directional mode state.
bogdanm 84:0b3ab51c8877 71 This parameter can be a value of @ref SPI_Direction_mode */
bogdanm 84:0b3ab51c8877 72
bogdanm 84:0b3ab51c8877 73 uint32_t DataSize; /*!< Specifies the SPI data size.
bogdanm 84:0b3ab51c8877 74 This parameter can be a value of @ref SPI_data_size */
bogdanm 84:0b3ab51c8877 75
bogdanm 84:0b3ab51c8877 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
bogdanm 84:0b3ab51c8877 77 This parameter can be a value of @ref SPI_Clock_Polarity */
bogdanm 84:0b3ab51c8877 78
bogdanm 84:0b3ab51c8877 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
bogdanm 84:0b3ab51c8877 80 This parameter can be a value of @ref SPI_Clock_Phase */
bogdanm 84:0b3ab51c8877 81
bogdanm 84:0b3ab51c8877 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
bogdanm 84:0b3ab51c8877 83 hardware (NSS pin) or by software using the SSI bit.
bogdanm 84:0b3ab51c8877 84 This parameter can be a value of @ref SPI_Slave_Select_management */
bogdanm 84:0b3ab51c8877 85
bogdanm 84:0b3ab51c8877 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
bogdanm 84:0b3ab51c8877 87 used to configure the transmit and receive SCK clock.
bogdanm 84:0b3ab51c8877 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
bogdanm 84:0b3ab51c8877 89 @note The communication clock is derived from the master
bogdanm 84:0b3ab51c8877 90 clock. The slave clock does not need to be set */
bogdanm 84:0b3ab51c8877 91
bogdanm 84:0b3ab51c8877 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
bogdanm 84:0b3ab51c8877 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
bogdanm 84:0b3ab51c8877 94
bogdanm 84:0b3ab51c8877 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
bogdanm 84:0b3ab51c8877 96 This parameter can be a value of @ref SPI_TI_mode */
bogdanm 84:0b3ab51c8877 97
bogdanm 84:0b3ab51c8877 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
bogdanm 84:0b3ab51c8877 99 This parameter can be a value of @ref SPI_CRC_Calculation */
bogdanm 84:0b3ab51c8877 100
bogdanm 84:0b3ab51c8877 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
bogdanm 84:0b3ab51c8877 102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
bogdanm 84:0b3ab51c8877 103
bogdanm 84:0b3ab51c8877 104 }SPI_InitTypeDef;
bogdanm 84:0b3ab51c8877 105
bogdanm 84:0b3ab51c8877 106 /**
bogdanm 84:0b3ab51c8877 107 * @brief HAL SPI State structure definition
bogdanm 84:0b3ab51c8877 108 */
bogdanm 84:0b3ab51c8877 109 typedef enum
bogdanm 84:0b3ab51c8877 110 {
bogdanm 84:0b3ab51c8877 111 HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
bogdanm 84:0b3ab51c8877 112 HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
bogdanm 84:0b3ab51c8877 113 HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
bogdanm 84:0b3ab51c8877 114 HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 84:0b3ab51c8877 115 HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 84:0b3ab51c8877 116 HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
bogdanm 84:0b3ab51c8877 117 HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
bogdanm 84:0b3ab51c8877 118
bogdanm 84:0b3ab51c8877 119 }HAL_SPI_StateTypeDef;
bogdanm 84:0b3ab51c8877 120
bogdanm 84:0b3ab51c8877 121 /**
bogdanm 84:0b3ab51c8877 122 * @brief SPI handle Structure definition
bogdanm 84:0b3ab51c8877 123 */
bogdanm 84:0b3ab51c8877 124 typedef struct __SPI_HandleTypeDef
bogdanm 84:0b3ab51c8877 125 {
Kojto 96:487b796308b0 126 SPI_TypeDef *Instance; /*!< SPI registers base address */
bogdanm 84:0b3ab51c8877 127
Kojto 96:487b796308b0 128 SPI_InitTypeDef Init; /*!< SPI communication parameters */
bogdanm 84:0b3ab51c8877 129
Kojto 96:487b796308b0 130 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
bogdanm 84:0b3ab51c8877 131
Kojto 96:487b796308b0 132 uint16_t TxXferSize; /*!< SPI Tx transfer size */
bogdanm 84:0b3ab51c8877 133
Kojto 96:487b796308b0 134 uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
bogdanm 84:0b3ab51c8877 135
Kojto 96:487b796308b0 136 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
bogdanm 84:0b3ab51c8877 137
Kojto 96:487b796308b0 138 uint16_t RxXferSize; /*!< SPI Rx transfer size */
bogdanm 84:0b3ab51c8877 139
Kojto 96:487b796308b0 140 uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
bogdanm 84:0b3ab51c8877 141
Kojto 96:487b796308b0 142 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */
bogdanm 84:0b3ab51c8877 143
Kojto 96:487b796308b0 144 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */
bogdanm 84:0b3ab51c8877 145
Kojto 96:487b796308b0 146 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */
bogdanm 84:0b3ab51c8877 147
Kojto 96:487b796308b0 148 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */
bogdanm 84:0b3ab51c8877 149
Kojto 96:487b796308b0 150 HAL_LockTypeDef Lock; /*!< SPI locking object */
bogdanm 84:0b3ab51c8877 151
Kojto 96:487b796308b0 152 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
bogdanm 84:0b3ab51c8877 153
Kojto 96:487b796308b0 154 __IO uint32_t ErrorCode; /*!< SPI Error code */
bogdanm 84:0b3ab51c8877 155
bogdanm 84:0b3ab51c8877 156 }SPI_HandleTypeDef;
Kojto 96:487b796308b0 157 /**
Kojto 96:487b796308b0 158 * @}
Kojto 96:487b796308b0 159 */
Kojto 96:487b796308b0 160
bogdanm 84:0b3ab51c8877 161
bogdanm 84:0b3ab51c8877 162 /* Exported constants --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 163
Kojto 96:487b796308b0 164 /** @defgroup SPI_Exported_Constants SPI Exported Constants
bogdanm 84:0b3ab51c8877 165 * @{
bogdanm 84:0b3ab51c8877 166 */
bogdanm 84:0b3ab51c8877 167
Kojto 96:487b796308b0 168 /**
Kojto 96:487b796308b0 169 * @defgroup SPI_ErrorCode SPI Error Code
Kojto 96:487b796308b0 170 * @{
Kojto 96:487b796308b0 171 */
Kojto 96:487b796308b0 172 #define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */
Kojto 96:487b796308b0 173 #define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */
Kojto 96:487b796308b0 174 #define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */
Kojto 96:487b796308b0 175 #define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */
Kojto 96:487b796308b0 176 #define HAL_SPI_ERROR_FRE ((uint32_t)0x08) /*!< FRE error */
Kojto 96:487b796308b0 177 #define HAL_SPI_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */
Kojto 96:487b796308b0 178 #define HAL_SPI_ERROR_FLAG ((uint32_t)0x20) /*!< Flag: RXNE,TXE, BSY */
Kojto 96:487b796308b0 179 /**
Kojto 96:487b796308b0 180 * @}
Kojto 96:487b796308b0 181 */
Kojto 96:487b796308b0 182
Kojto 96:487b796308b0 183 /** @defgroup SPI_mode SPI mode
bogdanm 84:0b3ab51c8877 184 * @{
bogdanm 84:0b3ab51c8877 185 */
bogdanm 84:0b3ab51c8877 186 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 187 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
bogdanm 84:0b3ab51c8877 188
bogdanm 84:0b3ab51c8877 189 /**
bogdanm 84:0b3ab51c8877 190 * @}
bogdanm 84:0b3ab51c8877 191 */
bogdanm 84:0b3ab51c8877 192
Kojto 96:487b796308b0 193 /** @defgroup SPI_Direction_mode SPI Direction mode
bogdanm 84:0b3ab51c8877 194 * @{
bogdanm 84:0b3ab51c8877 195 */
Kojto 96:487b796308b0 196 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
Kojto 96:487b796308b0 197 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
Kojto 96:487b796308b0 198 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
bogdanm 84:0b3ab51c8877 199
bogdanm 84:0b3ab51c8877 200 /**
bogdanm 84:0b3ab51c8877 201 * @}
bogdanm 84:0b3ab51c8877 202 */
bogdanm 84:0b3ab51c8877 203
Kojto 96:487b796308b0 204 /** @defgroup SPI_data_size SPI data size
bogdanm 84:0b3ab51c8877 205 * @{
bogdanm 84:0b3ab51c8877 206 */
bogdanm 84:0b3ab51c8877 207 #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 208 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
bogdanm 84:0b3ab51c8877 209
bogdanm 84:0b3ab51c8877 210 /**
bogdanm 84:0b3ab51c8877 211 * @}
bogdanm 84:0b3ab51c8877 212 */
bogdanm 84:0b3ab51c8877 213
Kojto 96:487b796308b0 214 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
bogdanm 84:0b3ab51c8877 215 * @{
bogdanm 84:0b3ab51c8877 216 */
bogdanm 84:0b3ab51c8877 217 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 218 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
bogdanm 84:0b3ab51c8877 219
bogdanm 84:0b3ab51c8877 220 /**
bogdanm 84:0b3ab51c8877 221 * @}
bogdanm 84:0b3ab51c8877 222 */
bogdanm 84:0b3ab51c8877 223
Kojto 96:487b796308b0 224 /** @defgroup SPI_Clock_Phase SPI Clock Phase
bogdanm 84:0b3ab51c8877 225 * @{
bogdanm 84:0b3ab51c8877 226 */
bogdanm 84:0b3ab51c8877 227 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 228 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
bogdanm 84:0b3ab51c8877 229
bogdanm 84:0b3ab51c8877 230 /**
bogdanm 84:0b3ab51c8877 231 * @}
bogdanm 84:0b3ab51c8877 232 */
bogdanm 84:0b3ab51c8877 233
Kojto 96:487b796308b0 234 /** @defgroup SPI_Slave_Select_management SPI Slave Select management
bogdanm 84:0b3ab51c8877 235 * @{
bogdanm 84:0b3ab51c8877 236 */
bogdanm 84:0b3ab51c8877 237 #define SPI_NSS_SOFT SPI_CR1_SSM
bogdanm 84:0b3ab51c8877 238 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
Kojto 96:487b796308b0 239 #define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))
bogdanm 84:0b3ab51c8877 240
bogdanm 84:0b3ab51c8877 241 /**
bogdanm 84:0b3ab51c8877 242 * @}
bogdanm 84:0b3ab51c8877 243 */
bogdanm 84:0b3ab51c8877 244
Kojto 96:487b796308b0 245 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
bogdanm 84:0b3ab51c8877 246 * @{
bogdanm 84:0b3ab51c8877 247 */
bogdanm 84:0b3ab51c8877 248 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
Kojto 96:487b796308b0 249 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0)
Kojto 96:487b796308b0 250 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1)
Kojto 96:487b796308b0 251 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0)
Kojto 96:487b796308b0 252 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2)
Kojto 96:487b796308b0 253 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0)
Kojto 96:487b796308b0 254 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1)
Kojto 96:487b796308b0 255 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
bogdanm 84:0b3ab51c8877 256
bogdanm 84:0b3ab51c8877 257 /**
bogdanm 84:0b3ab51c8877 258 * @}
bogdanm 84:0b3ab51c8877 259 */
bogdanm 84:0b3ab51c8877 260
Kojto 96:487b796308b0 261 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
bogdanm 84:0b3ab51c8877 262 * @{
bogdanm 84:0b3ab51c8877 263 */
bogdanm 84:0b3ab51c8877 264 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 265 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
bogdanm 84:0b3ab51c8877 266
bogdanm 84:0b3ab51c8877 267 /**
bogdanm 84:0b3ab51c8877 268 * @}
bogdanm 84:0b3ab51c8877 269 */
bogdanm 84:0b3ab51c8877 270
Kojto 96:487b796308b0 271 /** @defgroup SPI_TI_mode SPI TI mode
bogdanm 84:0b3ab51c8877 272 * @{
bogdanm 84:0b3ab51c8877 273 */
Kojto 96:487b796308b0 274 #define SPI_TIMODE_DISABLE ((uint32_t)0x00000000)
Kojto 96:487b796308b0 275 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
bogdanm 84:0b3ab51c8877 276
bogdanm 84:0b3ab51c8877 277 /**
bogdanm 84:0b3ab51c8877 278 * @}
bogdanm 84:0b3ab51c8877 279 */
bogdanm 84:0b3ab51c8877 280
Kojto 96:487b796308b0 281 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
bogdanm 84:0b3ab51c8877 282 * @{
bogdanm 84:0b3ab51c8877 283 */
Kojto 96:487b796308b0 284 #define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000)
Kojto 96:487b796308b0 285 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
bogdanm 84:0b3ab51c8877 286
bogdanm 84:0b3ab51c8877 287 /**
bogdanm 84:0b3ab51c8877 288 * @}
bogdanm 84:0b3ab51c8877 289 */
bogdanm 84:0b3ab51c8877 290
Kojto 96:487b796308b0 291 /** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
bogdanm 84:0b3ab51c8877 292 * @{
bogdanm 84:0b3ab51c8877 293 */
bogdanm 84:0b3ab51c8877 294 #define SPI_IT_TXE SPI_CR2_TXEIE
bogdanm 84:0b3ab51c8877 295 #define SPI_IT_RXNE SPI_CR2_RXNEIE
bogdanm 84:0b3ab51c8877 296 #define SPI_IT_ERR SPI_CR2_ERRIE
bogdanm 84:0b3ab51c8877 297 /**
bogdanm 84:0b3ab51c8877 298 * @}
bogdanm 84:0b3ab51c8877 299 */
bogdanm 84:0b3ab51c8877 300
Kojto 96:487b796308b0 301 /** @defgroup SPI_Flag_definition SPI Flag definition
bogdanm 84:0b3ab51c8877 302 * @{
bogdanm 84:0b3ab51c8877 303 */
bogdanm 84:0b3ab51c8877 304 #define SPI_FLAG_RXNE SPI_SR_RXNE
bogdanm 84:0b3ab51c8877 305 #define SPI_FLAG_TXE SPI_SR_TXE
bogdanm 84:0b3ab51c8877 306 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
bogdanm 84:0b3ab51c8877 307 #define SPI_FLAG_MODF SPI_SR_MODF
bogdanm 84:0b3ab51c8877 308 #define SPI_FLAG_OVR SPI_SR_OVR
bogdanm 84:0b3ab51c8877 309 #define SPI_FLAG_BSY SPI_SR_BSY
bogdanm 84:0b3ab51c8877 310 #define SPI_FLAG_FRE SPI_SR_FRE
bogdanm 84:0b3ab51c8877 311
bogdanm 84:0b3ab51c8877 312 /**
bogdanm 84:0b3ab51c8877 313 * @}
bogdanm 84:0b3ab51c8877 314 */
bogdanm 84:0b3ab51c8877 315
bogdanm 84:0b3ab51c8877 316 /**
bogdanm 84:0b3ab51c8877 317 * @}
bogdanm 84:0b3ab51c8877 318 */
bogdanm 84:0b3ab51c8877 319
Kojto 96:487b796308b0 320
bogdanm 84:0b3ab51c8877 321 /* Exported macro ------------------------------------------------------------*/
Kojto 96:487b796308b0 322 /** @defgroup SPI_Exported_Macros SPI Exported Macros
Kojto 96:487b796308b0 323 * @{
Kojto 96:487b796308b0 324 */
bogdanm 84:0b3ab51c8877 325
bogdanm 84:0b3ab51c8877 326 /** @brief Reset SPI handle state
bogdanm 84:0b3ab51c8877 327 * @param __HANDLE__: specifies the SPI handle.
Kojto 96:487b796308b0 328 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 329 * @retval None
bogdanm 84:0b3ab51c8877 330 */
bogdanm 84:0b3ab51c8877 331 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
bogdanm 84:0b3ab51c8877 332
Kojto 96:487b796308b0 333 /** @brief Enable the specified SPI interrupts.
bogdanm 84:0b3ab51c8877 334 * @param __HANDLE__: specifies the SPI handle.
Kojto 96:487b796308b0 335 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
Kojto 96:487b796308b0 336 * @param __INTERRUPT__: specifies the interrupt source to enable.
bogdanm 84:0b3ab51c8877 337 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 338 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 84:0b3ab51c8877 339 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 84:0b3ab51c8877 340 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 84:0b3ab51c8877 341 * @retval None
bogdanm 84:0b3ab51c8877 342 */
Kojto 96:487b796308b0 343 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
Kojto 96:487b796308b0 344
Kojto 96:487b796308b0 345 /** @brief Disable the specified SPI interrupts.
Kojto 96:487b796308b0 346 * @param __HANDLE__: specifies the SPI handle.
Kojto 96:487b796308b0 347 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
Kojto 96:487b796308b0 348 * @param __INTERRUPT__: specifies the interrupt source to disable.
Kojto 96:487b796308b0 349 * This parameter can be one of the following values:
Kojto 96:487b796308b0 350 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
Kojto 96:487b796308b0 351 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
Kojto 96:487b796308b0 352 * @arg SPI_IT_ERR: Error interrupt enable
Kojto 96:487b796308b0 353 * @retval None
Kojto 96:487b796308b0 354 */
Kojto 96:487b796308b0 355 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 356
bogdanm 84:0b3ab51c8877 357 /** @brief Check if the specified SPI interrupt source is enabled or disabled.
bogdanm 84:0b3ab51c8877 358 * @param __HANDLE__: specifies the SPI handle.
Kojto 96:487b796308b0 359 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 360 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
bogdanm 84:0b3ab51c8877 361 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 362 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 84:0b3ab51c8877 363 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 84:0b3ab51c8877 364 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 84:0b3ab51c8877 365 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 366 */
bogdanm 84:0b3ab51c8877 367 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 84:0b3ab51c8877 368
bogdanm 84:0b3ab51c8877 369 /** @brief Check whether the specified SPI flag is set or not.
bogdanm 84:0b3ab51c8877 370 * @param __HANDLE__: specifies the SPI handle.
Kojto 96:487b796308b0 371 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 372 * @param __FLAG__: specifies the flag to check.
bogdanm 84:0b3ab51c8877 373 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 374 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
bogdanm 84:0b3ab51c8877 375 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
bogdanm 84:0b3ab51c8877 376 * @arg SPI_FLAG_CRCERR: CRC error flag
bogdanm 84:0b3ab51c8877 377 * @arg SPI_FLAG_MODF: Mode fault flag
bogdanm 84:0b3ab51c8877 378 * @arg SPI_FLAG_OVR: Overrun flag
bogdanm 84:0b3ab51c8877 379 * @arg SPI_FLAG_BSY: Busy flag
bogdanm 84:0b3ab51c8877 380 * @arg SPI_FLAG_FRE: Frame format error flag
bogdanm 84:0b3ab51c8877 381 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 382 */
bogdanm 84:0b3ab51c8877 383 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 84:0b3ab51c8877 384
bogdanm 84:0b3ab51c8877 385 /** @brief Clear the SPI CRCERR pending flag.
bogdanm 84:0b3ab51c8877 386 * @param __HANDLE__: specifies the SPI handle.
Kojto 96:487b796308b0 387 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 388 * @retval None
bogdanm 84:0b3ab51c8877 389 */
Kojto 96:487b796308b0 390 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
bogdanm 84:0b3ab51c8877 391
bogdanm 84:0b3ab51c8877 392 /** @brief Clear the SPI MODF pending flag.
bogdanm 84:0b3ab51c8877 393 * @param __HANDLE__: specifies the SPI handle.
Kojto 96:487b796308b0 394 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 395 * @retval None
Kojto 96:487b796308b0 396 */
Kojto 96:487b796308b0 397 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
Kojto 96:487b796308b0 398 do{ \
Kojto 96:487b796308b0 399 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 400 tmpreg = (__HANDLE__)->Instance->SR; \
Kojto 96:487b796308b0 401 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
Kojto 96:487b796308b0 402 UNUSED(tmpreg); \
Kojto 96:487b796308b0 403 } while(0)
bogdanm 84:0b3ab51c8877 404
bogdanm 84:0b3ab51c8877 405 /** @brief Clear the SPI OVR pending flag.
bogdanm 84:0b3ab51c8877 406 * @param __HANDLE__: specifies the SPI handle.
Kojto 96:487b796308b0 407 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 408 * @retval None
bogdanm 84:0b3ab51c8877 409 */
Kojto 96:487b796308b0 410 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
Kojto 96:487b796308b0 411 do{ \
Kojto 96:487b796308b0 412 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 413 tmpreg = (__HANDLE__)->Instance->DR; \
Kojto 96:487b796308b0 414 tmpreg = (__HANDLE__)->Instance->SR; \
Kojto 96:487b796308b0 415 UNUSED(tmpreg); \
Kojto 96:487b796308b0 416 } while(0)
bogdanm 84:0b3ab51c8877 417
bogdanm 84:0b3ab51c8877 418 /** @brief Clear the SPI FRE pending flag.
bogdanm 84:0b3ab51c8877 419 * @param __HANDLE__: specifies the SPI handle.
Kojto 96:487b796308b0 420 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
Kojto 96:487b796308b0 421 * @retval None
Kojto 96:487b796308b0 422 */
Kojto 96:487b796308b0 423 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
Kojto 96:487b796308b0 424 do{ \
Kojto 96:487b796308b0 425 __IO uint32_t tmpreg; \
Kojto 96:487b796308b0 426 tmpreg = (__HANDLE__)->Instance->SR; \
Kojto 96:487b796308b0 427 UNUSED(tmpreg); \
Kojto 96:487b796308b0 428 } while(0)
Kojto 96:487b796308b0 429
Kojto 96:487b796308b0 430 /** @brief Enables the SPI.
Kojto 96:487b796308b0 431 * @param __HANDLE__: specifies the SPI Handle.
Kojto 96:487b796308b0 432 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
Kojto 96:487b796308b0 433 * @retval None
Kojto 96:487b796308b0 434 */
Kojto 96:487b796308b0 435 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Kojto 96:487b796308b0 436
Kojto 96:487b796308b0 437 /** @brief Disables the SPI.
Kojto 96:487b796308b0 438 * @param __HANDLE__: specifies the SPI Handle.
Kojto 96:487b796308b0 439 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
Kojto 96:487b796308b0 440 * @retval None
Kojto 96:487b796308b0 441 */
Kojto 96:487b796308b0 442 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
Kojto 96:487b796308b0 443 /**
Kojto 96:487b796308b0 444 * @}
Kojto 96:487b796308b0 445 */
Kojto 96:487b796308b0 446
Kojto 96:487b796308b0 447
Kojto 96:487b796308b0 448 /* Private macros -----------------------------------------------------------*/
Kojto 96:487b796308b0 449 /** @defgroup SPI_Private_Macros SPI Private Macros
Kojto 96:487b796308b0 450 * @{
Kojto 96:487b796308b0 451 */
Kojto 96:487b796308b0 452
Kojto 96:487b796308b0 453 /** @brief Checks if SPI Mode parameter is in allowed range.
Kojto 96:487b796308b0 454 * @param __MODE__: specifies the SPI Mode.
Kojto 96:487b796308b0 455 * This parameter can be a value of @ref SPI_mode
Kojto 96:487b796308b0 456 * @retval None
Kojto 96:487b796308b0 457 */
Kojto 96:487b796308b0 458 #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER))
Kojto 96:487b796308b0 459
Kojto 96:487b796308b0 460 /** @brief Checks if SPI Direction Mode parameter is in allowed range.
Kojto 96:487b796308b0 461 * @param __MODE__: specifies the SPI Direction Mode.
Kojto 96:487b796308b0 462 * This parameter can be a value of @ref SPI_Direction_mode
Kojto 96:487b796308b0 463 * @retval None
Kojto 96:487b796308b0 464 */
Kojto 96:487b796308b0 465 #define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
Kojto 96:487b796308b0 466 ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
Kojto 96:487b796308b0 467 ((__MODE__) == SPI_DIRECTION_1LINE))
Kojto 96:487b796308b0 468
Kojto 96:487b796308b0 469 /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
Kojto 96:487b796308b0 470 * @param __MODE__: specifies the SPI Direction Mode.
Kojto 96:487b796308b0 471 * @retval None
Kojto 96:487b796308b0 472 */
Kojto 96:487b796308b0 473 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
Kojto 96:487b796308b0 474 ((__MODE__) == SPI_DIRECTION_1LINE))
Kojto 96:487b796308b0 475
Kojto 96:487b796308b0 476 /** @brief Checks if SPI Direction Mode parameter is 2 lines.
Kojto 96:487b796308b0 477 * @param __MODE__: specifies the SPI Direction Mode.
Kojto 96:487b796308b0 478 * @retval None
Kojto 96:487b796308b0 479 */
Kojto 96:487b796308b0 480 #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
Kojto 96:487b796308b0 481
Kojto 96:487b796308b0 482 /** @brief Checks if SPI Data Size parameter is in allowed range.
Kojto 96:487b796308b0 483 * @param __DATASIZE__: specifies the SPI Data Size.
Kojto 96:487b796308b0 484 * This parameter can be a value of @ref SPI_data_size
Kojto 96:487b796308b0 485 * @retval None
Kojto 96:487b796308b0 486 */
Kojto 96:487b796308b0 487 #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
Kojto 96:487b796308b0 488 ((__DATASIZE__) == SPI_DATASIZE_8BIT))
Kojto 96:487b796308b0 489
Kojto 96:487b796308b0 490 /** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
Kojto 96:487b796308b0 491 * @param __CPOL__: specifies the SPI serial clock steady state.
Kojto 96:487b796308b0 492 * This parameter can be a value of @ref SPI_Clock_Polarity
Kojto 96:487b796308b0 493 * @retval None
Kojto 96:487b796308b0 494 */
Kojto 96:487b796308b0 495 #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
Kojto 96:487b796308b0 496 ((__CPOL__) == SPI_POLARITY_HIGH))
Kojto 96:487b796308b0 497
Kojto 96:487b796308b0 498 /** @brief Checks if SPI Clock Phase parameter is in allowed range.
Kojto 96:487b796308b0 499 * @param __CPHA__: specifies the SPI Clock Phase.
Kojto 96:487b796308b0 500 * This parameter can be a value of @ref SPI_Clock_Phase
bogdanm 84:0b3ab51c8877 501 * @retval None
bogdanm 84:0b3ab51c8877 502 */
Kojto 96:487b796308b0 503 #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
Kojto 96:487b796308b0 504 ((__CPHA__) == SPI_PHASE_2EDGE))
Kojto 96:487b796308b0 505
Kojto 96:487b796308b0 506 /** @brief Checks if SPI Slave select parameter is in allowed range.
Kojto 96:487b796308b0 507 * @param __NSS__: specifies the SPI Slave Slelect management parameter.
Kojto 96:487b796308b0 508 * This parameter can be a value of @ref SPI_Slave_Select_management
Kojto 96:487b796308b0 509 * @retval None
Kojto 96:487b796308b0 510 */
Kojto 96:487b796308b0 511 #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
Kojto 96:487b796308b0 512 ((__NSS__) == SPI_NSS_HARD_INPUT) || \
Kojto 96:487b796308b0 513 ((__NSS__) == SPI_NSS_HARD_OUTPUT))
bogdanm 84:0b3ab51c8877 514
Kojto 96:487b796308b0 515 /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
Kojto 96:487b796308b0 516 * @param __PRESCALER__: specifies the SPI Baudrate prescaler.
Kojto 96:487b796308b0 517 * This parameter can be a value of @ref SPI_BaudRate_Prescaler
Kojto 96:487b796308b0 518 * @retval None
Kojto 96:487b796308b0 519 */
Kojto 96:487b796308b0 520 #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
Kojto 96:487b796308b0 521 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
Kojto 96:487b796308b0 522 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
Kojto 96:487b796308b0 523 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
Kojto 96:487b796308b0 524 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
Kojto 96:487b796308b0 525 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
Kojto 96:487b796308b0 526 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
Kojto 96:487b796308b0 527 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
bogdanm 84:0b3ab51c8877 528
Kojto 96:487b796308b0 529 /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
Kojto 96:487b796308b0 530 * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
Kojto 96:487b796308b0 531 * This parameter can be a value of @ref SPI_MSB_LSB_transmission
Kojto 96:487b796308b0 532 * @retval None
Kojto 96:487b796308b0 533 */
Kojto 96:487b796308b0 534 #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
Kojto 96:487b796308b0 535 ((__BIT__) == SPI_FIRSTBIT_LSB))
bogdanm 84:0b3ab51c8877 536
Kojto 96:487b796308b0 537 /** @brief Checks if SPI TI mode parameter is in allowed range.
Kojto 96:487b796308b0 538 * @param __MODE__: specifies the SPI TI mode.
Kojto 96:487b796308b0 539 * This parameter can be a value of @ref SPI_TI_mode
Kojto 96:487b796308b0 540 * @retval None
Kojto 96:487b796308b0 541 */
Kojto 96:487b796308b0 542 #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
Kojto 96:487b796308b0 543 ((__MODE__) == SPI_TIMODE_ENABLE))
Kojto 96:487b796308b0 544 /** @brief Checks if SPI CRC calculation enabled state is in allowed range.
Kojto 96:487b796308b0 545 * @param __CALCULATION__: specifies the SPI CRC calculation enable state.
Kojto 96:487b796308b0 546 * This parameter can be a value of @ref SPI_CRC_Calculation
Kojto 96:487b796308b0 547 * @retval None
Kojto 96:487b796308b0 548 */
Kojto 96:487b796308b0 549 #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
Kojto 96:487b796308b0 550 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
bogdanm 84:0b3ab51c8877 551
Kojto 96:487b796308b0 552 /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
Kojto 96:487b796308b0 553 * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation.
Kojto 96:487b796308b0 554 * This parameter must be a number between Min_Data = 0 and Max_Data = 65535
Kojto 96:487b796308b0 555 * @retval None
Kojto 96:487b796308b0 556 */
Kojto 96:487b796308b0 557 #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF))
Kojto 96:487b796308b0 558 /** @brief Sets the SPI transmit-only mode.
Kojto 96:487b796308b0 559 * @param __HANDLE__: specifies the SPI Handle.
Kojto 96:487b796308b0 560 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
Kojto 96:487b796308b0 561 * @retval None
Kojto 96:487b796308b0 562 */
Kojto 96:487b796308b0 563 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
bogdanm 84:0b3ab51c8877 564
Kojto 96:487b796308b0 565 /** @brief Sets the SPI receive-only mode.
Kojto 96:487b796308b0 566 * @param __HANDLE__: specifies the SPI Handle.
Kojto 96:487b796308b0 567 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
Kojto 96:487b796308b0 568 * @retval None
Kojto 96:487b796308b0 569 */
Kojto 96:487b796308b0 570 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
Kojto 96:487b796308b0 571
Kojto 96:487b796308b0 572 /** @brief Resets the CRC calculation of the SPI.
Kojto 96:487b796308b0 573 * @param __HANDLE__: specifies the SPI Handle.
Kojto 96:487b796308b0 574 * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral.
Kojto 96:487b796308b0 575 * @retval None
Kojto 96:487b796308b0 576 */
Kojto 96:487b796308b0 577 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
Kojto 96:487b796308b0 578 SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0)
Kojto 96:487b796308b0 579 /**
Kojto 96:487b796308b0 580 * @}
Kojto 96:487b796308b0 581 */
bogdanm 84:0b3ab51c8877 582
bogdanm 84:0b3ab51c8877 583 /* Exported functions --------------------------------------------------------*/
Kojto 96:487b796308b0 584 /** @addtogroup SPI_Exported_Functions
Kojto 96:487b796308b0 585 * @{
Kojto 96:487b796308b0 586 */
bogdanm 84:0b3ab51c8877 587
bogdanm 84:0b3ab51c8877 588 /* Initialization/de-initialization functions **********************************/
Kojto 96:487b796308b0 589 /** @addtogroup SPI_Exported_Functions_Group1
Kojto 96:487b796308b0 590 * @{
Kojto 96:487b796308b0 591 */
bogdanm 84:0b3ab51c8877 592 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 593 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 594 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 595 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
Kojto 96:487b796308b0 596 /**
Kojto 96:487b796308b0 597 * @}
Kojto 96:487b796308b0 598 */
bogdanm 84:0b3ab51c8877 599
bogdanm 84:0b3ab51c8877 600 /* I/O operation functions *****************************************************/
Kojto 96:487b796308b0 601 /** @addtogroup SPI_Exported_Functions_Group2
Kojto 96:487b796308b0 602 * @{
Kojto 96:487b796308b0 603 */
bogdanm 84:0b3ab51c8877 604 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 605 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 606 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 607 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 608 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 609 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm 84:0b3ab51c8877 610 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 611 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 612 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm 92:4fc01daae5a5 613 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 614 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 615 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 616
bogdanm 84:0b3ab51c8877 617 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 618 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 619 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 620 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 621 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 622 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 623 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 624 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
Kojto 96:487b796308b0 625 /**
Kojto 96:487b796308b0 626 * @}
Kojto 96:487b796308b0 627 */
Kojto 96:487b796308b0 628
bogdanm 84:0b3ab51c8877 629
bogdanm 84:0b3ab51c8877 630 /* Peripheral State and Control functions **************************************/
Kojto 96:487b796308b0 631 /** @addtogroup SPI_Exported_Functions_Group3
Kojto 96:487b796308b0 632 * @{
Kojto 96:487b796308b0 633 */
bogdanm 84:0b3ab51c8877 634 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
Kojto 96:487b796308b0 635 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
Kojto 96:487b796308b0 636
Kojto 96:487b796308b0 637 /**
Kojto 96:487b796308b0 638 * @}
Kojto 96:487b796308b0 639 */
Kojto 96:487b796308b0 640
Kojto 96:487b796308b0 641 /**
Kojto 96:487b796308b0 642 * @}
Kojto 96:487b796308b0 643 */
Kojto 96:487b796308b0 644
bogdanm 84:0b3ab51c8877 645
bogdanm 84:0b3ab51c8877 646 /**
bogdanm 84:0b3ab51c8877 647 * @}
bogdanm 84:0b3ab51c8877 648 */
bogdanm 84:0b3ab51c8877 649
bogdanm 84:0b3ab51c8877 650 /**
bogdanm 84:0b3ab51c8877 651 * @}
bogdanm 84:0b3ab51c8877 652 */
bogdanm 84:0b3ab51c8877 653
bogdanm 84:0b3ab51c8877 654 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 655 }
bogdanm 84:0b3ab51c8877 656 #endif
bogdanm 84:0b3ab51c8877 657
bogdanm 84:0b3ab51c8877 658 #endif /* __STM32L0xx_HAL_SPI_H */
bogdanm 84:0b3ab51c8877 659
bogdanm 84:0b3ab51c8877 660 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 96:487b796308b0 661