Filippo Casamassima / mbed

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TARGET_NUCLEO_L053R8/stm32l0xx_hal_spi.h@84:0b3ab51c8877, 2014-05-19 (annotated)

Committer:
bogdanm
Date:
Mon May 19 18:14:09 2014 +0100
Revision:
84:0b3ab51c8877
Child:
92:4fc01daae5a5
Release 84 of the mbed library



Main changes:



- added LPC11U68 to the official build

- Bug fixes and new features for ST Nucleo boards

- I2C fixes for Freescale targets

- Added nRF51822 exporters

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_spi.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
bogdanm 84:0b3ab51c8877 5 * @version V1.0.0
bogdanm 84:0b3ab51c8877 6 * @date 22-April-2014
bogdanm 84:0b3ab51c8877 7 * @brief Header file of SPI HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
bogdanm 84:0b3ab51c8877 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_SPI_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_SPI_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
bogdanm 84:0b3ab51c8877 53 /** @addtogroup SPI
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 /* Exported types ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 58
bogdanm 84:0b3ab51c8877 59 /**
bogdanm 84:0b3ab51c8877 60 * @brief SPI Configuration Structure definition
bogdanm 84:0b3ab51c8877 61 */
bogdanm 84:0b3ab51c8877 62 typedef struct
bogdanm 84:0b3ab51c8877 63 {
bogdanm 84:0b3ab51c8877 64 uint32_t Mode; /*!< Specifies the SPI operating mode.
bogdanm 84:0b3ab51c8877 65 This parameter can be a value of @ref SPI_mode */
bogdanm 84:0b3ab51c8877 66
bogdanm 84:0b3ab51c8877 67 uint32_t Direction; /*!< Specifies the SPI Directional mode state.
bogdanm 84:0b3ab51c8877 68 This parameter can be a value of @ref SPI_Direction_mode */
bogdanm 84:0b3ab51c8877 69
bogdanm 84:0b3ab51c8877 70 uint32_t DataSize; /*!< Specifies the SPI data size.
bogdanm 84:0b3ab51c8877 71 This parameter can be a value of @ref SPI_data_size */
bogdanm 84:0b3ab51c8877 72
bogdanm 84:0b3ab51c8877 73 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
bogdanm 84:0b3ab51c8877 74 This parameter can be a value of @ref SPI_Clock_Polarity */
bogdanm 84:0b3ab51c8877 75
bogdanm 84:0b3ab51c8877 76 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
bogdanm 84:0b3ab51c8877 77 This parameter can be a value of @ref SPI_Clock_Phase */
bogdanm 84:0b3ab51c8877 78
bogdanm 84:0b3ab51c8877 79 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
bogdanm 84:0b3ab51c8877 80 hardware (NSS pin) or by software using the SSI bit.
bogdanm 84:0b3ab51c8877 81 This parameter can be a value of @ref SPI_Slave_Select_management */
bogdanm 84:0b3ab51c8877 82
bogdanm 84:0b3ab51c8877 83 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
bogdanm 84:0b3ab51c8877 84 used to configure the transmit and receive SCK clock.
bogdanm 84:0b3ab51c8877 85 This parameter can be a value of @ref SPI_BaudRate_Prescaler
bogdanm 84:0b3ab51c8877 86 @note The communication clock is derived from the master
bogdanm 84:0b3ab51c8877 87 clock. The slave clock does not need to be set */
bogdanm 84:0b3ab51c8877 88
bogdanm 84:0b3ab51c8877 89 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
bogdanm 84:0b3ab51c8877 90 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
bogdanm 84:0b3ab51c8877 91
bogdanm 84:0b3ab51c8877 92 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
bogdanm 84:0b3ab51c8877 93 This parameter can be a value of @ref SPI_TI_mode */
bogdanm 84:0b3ab51c8877 94
bogdanm 84:0b3ab51c8877 95 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
bogdanm 84:0b3ab51c8877 96 This parameter can be a value of @ref SPI_CRC_Calculation */
bogdanm 84:0b3ab51c8877 97
bogdanm 84:0b3ab51c8877 98 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
bogdanm 84:0b3ab51c8877 99 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
bogdanm 84:0b3ab51c8877 100
bogdanm 84:0b3ab51c8877 101 }SPI_InitTypeDef;
bogdanm 84:0b3ab51c8877 102
bogdanm 84:0b3ab51c8877 103 /**
bogdanm 84:0b3ab51c8877 104 * @brief HAL SPI State structure definition
bogdanm 84:0b3ab51c8877 105 */
bogdanm 84:0b3ab51c8877 106 typedef enum
bogdanm 84:0b3ab51c8877 107 {
bogdanm 84:0b3ab51c8877 108 HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
bogdanm 84:0b3ab51c8877 109 HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
bogdanm 84:0b3ab51c8877 110 HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
bogdanm 84:0b3ab51c8877 111 HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 84:0b3ab51c8877 112 HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 84:0b3ab51c8877 113 HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
bogdanm 84:0b3ab51c8877 114 HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
bogdanm 84:0b3ab51c8877 115
bogdanm 84:0b3ab51c8877 116 }HAL_SPI_StateTypeDef;
bogdanm 84:0b3ab51c8877 117
bogdanm 84:0b3ab51c8877 118 /**
bogdanm 84:0b3ab51c8877 119 * @brief HAL SPI Error Code structure definition
bogdanm 84:0b3ab51c8877 120 */
bogdanm 84:0b3ab51c8877 121 typedef enum
bogdanm 84:0b3ab51c8877 122 {
bogdanm 84:0b3ab51c8877 123 HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
bogdanm 84:0b3ab51c8877 124 HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
bogdanm 84:0b3ab51c8877 125 HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
bogdanm 84:0b3ab51c8877 126 HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
bogdanm 84:0b3ab51c8877 127 HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
bogdanm 84:0b3ab51c8877 128 HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
bogdanm 84:0b3ab51c8877 129 HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */
bogdanm 84:0b3ab51c8877 130
bogdanm 84:0b3ab51c8877 131 }HAL_SPI_ErrorTypeDef;
bogdanm 84:0b3ab51c8877 132
bogdanm 84:0b3ab51c8877 133 /**
bogdanm 84:0b3ab51c8877 134 * @brief SPI handle Structure definition
bogdanm 84:0b3ab51c8877 135 */
bogdanm 84:0b3ab51c8877 136 typedef struct __SPI_HandleTypeDef
bogdanm 84:0b3ab51c8877 137 {
bogdanm 84:0b3ab51c8877 138 SPI_TypeDef *Instance; /* SPI registers base address */
bogdanm 84:0b3ab51c8877 139
bogdanm 84:0b3ab51c8877 140 SPI_InitTypeDef Init; /* SPI communication parameters */
bogdanm 84:0b3ab51c8877 141
bogdanm 84:0b3ab51c8877 142 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
bogdanm 84:0b3ab51c8877 143
bogdanm 84:0b3ab51c8877 144 uint16_t TxXferSize; /* SPI Tx transfer size */
bogdanm 84:0b3ab51c8877 145
bogdanm 84:0b3ab51c8877 146 uint16_t TxXferCount; /* SPI Tx Transfer Counter */
bogdanm 84:0b3ab51c8877 147
bogdanm 84:0b3ab51c8877 148 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
bogdanm 84:0b3ab51c8877 149
bogdanm 84:0b3ab51c8877 150 uint16_t RxXferSize; /* SPI Rx transfer size */
bogdanm 84:0b3ab51c8877 151
bogdanm 84:0b3ab51c8877 152 uint16_t RxXferCount; /* SPI Rx Transfer Counter */
bogdanm 84:0b3ab51c8877 153
bogdanm 84:0b3ab51c8877 154 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
bogdanm 84:0b3ab51c8877 155
bogdanm 84:0b3ab51c8877 156 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
bogdanm 84:0b3ab51c8877 157
bogdanm 84:0b3ab51c8877 158 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
bogdanm 84:0b3ab51c8877 159
bogdanm 84:0b3ab51c8877 160 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
bogdanm 84:0b3ab51c8877 161
bogdanm 84:0b3ab51c8877 162 HAL_LockTypeDef Lock; /* SPI locking object */
bogdanm 84:0b3ab51c8877 163
bogdanm 84:0b3ab51c8877 164 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
bogdanm 84:0b3ab51c8877 165
bogdanm 84:0b3ab51c8877 166 __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
bogdanm 84:0b3ab51c8877 167
bogdanm 84:0b3ab51c8877 168 }SPI_HandleTypeDef;
bogdanm 84:0b3ab51c8877 169
bogdanm 84:0b3ab51c8877 170 /* Exported constants --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 171
bogdanm 84:0b3ab51c8877 172 /** @defgroup SPI_Exported_Constants
bogdanm 84:0b3ab51c8877 173 * @{
bogdanm 84:0b3ab51c8877 174 */
bogdanm 84:0b3ab51c8877 175
bogdanm 84:0b3ab51c8877 176 /** @defgroup SPI_mode
bogdanm 84:0b3ab51c8877 177 * @{
bogdanm 84:0b3ab51c8877 178 */
bogdanm 84:0b3ab51c8877 179 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 180 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
bogdanm 84:0b3ab51c8877 181
bogdanm 84:0b3ab51c8877 182 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
bogdanm 84:0b3ab51c8877 183 ((MODE) == SPI_MODE_MASTER))
bogdanm 84:0b3ab51c8877 184 /**
bogdanm 84:0b3ab51c8877 185 * @}
bogdanm 84:0b3ab51c8877 186 */
bogdanm 84:0b3ab51c8877 187
bogdanm 84:0b3ab51c8877 188 /** @defgroup SPI_Direction_mode
bogdanm 84:0b3ab51c8877 189 * @{
bogdanm 84:0b3ab51c8877 190 */
bogdanm 84:0b3ab51c8877 191 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 192 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
bogdanm 84:0b3ab51c8877 193 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
bogdanm 84:0b3ab51c8877 194
bogdanm 84:0b3ab51c8877 195 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
bogdanm 84:0b3ab51c8877 196 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
bogdanm 84:0b3ab51c8877 197 ((MODE) == SPI_DIRECTION_1LINE))
bogdanm 84:0b3ab51c8877 198
bogdanm 84:0b3ab51c8877 199 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
bogdanm 84:0b3ab51c8877 200 ((MODE) == SPI_DIRECTION_1LINE))
bogdanm 84:0b3ab51c8877 201
bogdanm 84:0b3ab51c8877 202 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
bogdanm 84:0b3ab51c8877 203
bogdanm 84:0b3ab51c8877 204 /**
bogdanm 84:0b3ab51c8877 205 * @}
bogdanm 84:0b3ab51c8877 206 */
bogdanm 84:0b3ab51c8877 207
bogdanm 84:0b3ab51c8877 208 /** @defgroup SPI_data_size
bogdanm 84:0b3ab51c8877 209 * @{
bogdanm 84:0b3ab51c8877 210 */
bogdanm 84:0b3ab51c8877 211 #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 212 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
bogdanm 84:0b3ab51c8877 213
bogdanm 84:0b3ab51c8877 214 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
bogdanm 84:0b3ab51c8877 215 ((DATASIZE) == SPI_DATASIZE_8BIT))
bogdanm 84:0b3ab51c8877 216 /**
bogdanm 84:0b3ab51c8877 217 * @}
bogdanm 84:0b3ab51c8877 218 */
bogdanm 84:0b3ab51c8877 219
bogdanm 84:0b3ab51c8877 220 /** @defgroup SPI_Clock_Polarity
bogdanm 84:0b3ab51c8877 221 * @{
bogdanm 84:0b3ab51c8877 222 */
bogdanm 84:0b3ab51c8877 223 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 224 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
bogdanm 84:0b3ab51c8877 225
bogdanm 84:0b3ab51c8877 226 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
bogdanm 84:0b3ab51c8877 227 ((CPOL) == SPI_POLARITY_HIGH))
bogdanm 84:0b3ab51c8877 228 /**
bogdanm 84:0b3ab51c8877 229 * @}
bogdanm 84:0b3ab51c8877 230 */
bogdanm 84:0b3ab51c8877 231
bogdanm 84:0b3ab51c8877 232 /** @defgroup SPI_Clock_Phase
bogdanm 84:0b3ab51c8877 233 * @{
bogdanm 84:0b3ab51c8877 234 */
bogdanm 84:0b3ab51c8877 235 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 236 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
bogdanm 84:0b3ab51c8877 237
bogdanm 84:0b3ab51c8877 238 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
bogdanm 84:0b3ab51c8877 239 ((CPHA) == SPI_PHASE_2EDGE))
bogdanm 84:0b3ab51c8877 240 /**
bogdanm 84:0b3ab51c8877 241 * @}
bogdanm 84:0b3ab51c8877 242 */
bogdanm 84:0b3ab51c8877 243
bogdanm 84:0b3ab51c8877 244 /** @defgroup SPI_Slave_Select_management
bogdanm 84:0b3ab51c8877 245 * @{
bogdanm 84:0b3ab51c8877 246 */
bogdanm 84:0b3ab51c8877 247 #define SPI_NSS_SOFT SPI_CR1_SSM
bogdanm 84:0b3ab51c8877 248 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 249 #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
bogdanm 84:0b3ab51c8877 250
bogdanm 84:0b3ab51c8877 251 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
bogdanm 84:0b3ab51c8877 252 ((NSS) == SPI_NSS_HARD_INPUT) || \
bogdanm 84:0b3ab51c8877 253 ((NSS) == SPI_NSS_HARD_OUTPUT))
bogdanm 84:0b3ab51c8877 254 /**
bogdanm 84:0b3ab51c8877 255 * @}
bogdanm 84:0b3ab51c8877 256 */
bogdanm 84:0b3ab51c8877 257
bogdanm 84:0b3ab51c8877 258 /** @defgroup SPI_BaudRate_Prescaler
bogdanm 84:0b3ab51c8877 259 * @{
bogdanm 84:0b3ab51c8877 260 */
bogdanm 84:0b3ab51c8877 261 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 262 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
bogdanm 84:0b3ab51c8877 263 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
bogdanm 84:0b3ab51c8877 264 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
bogdanm 84:0b3ab51c8877 265 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
bogdanm 84:0b3ab51c8877 266 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
bogdanm 84:0b3ab51c8877 267 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
bogdanm 84:0b3ab51c8877 268 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
bogdanm 84:0b3ab51c8877 269
bogdanm 84:0b3ab51c8877 270 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
bogdanm 84:0b3ab51c8877 271 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
bogdanm 84:0b3ab51c8877 272 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
bogdanm 84:0b3ab51c8877 273 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
bogdanm 84:0b3ab51c8877 274 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
bogdanm 84:0b3ab51c8877 275 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
bogdanm 84:0b3ab51c8877 276 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
bogdanm 84:0b3ab51c8877 277 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
bogdanm 84:0b3ab51c8877 278 /**
bogdanm 84:0b3ab51c8877 279 * @}
bogdanm 84:0b3ab51c8877 280 */
bogdanm 84:0b3ab51c8877 281
bogdanm 84:0b3ab51c8877 282 /** @defgroup SPI_MSB_LSB_transmission
bogdanm 84:0b3ab51c8877 283 * @{
bogdanm 84:0b3ab51c8877 284 */
bogdanm 84:0b3ab51c8877 285 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 286 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
bogdanm 84:0b3ab51c8877 287
bogdanm 84:0b3ab51c8877 288 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
bogdanm 84:0b3ab51c8877 289 ((BIT) == SPI_FIRSTBIT_LSB))
bogdanm 84:0b3ab51c8877 290 /**
bogdanm 84:0b3ab51c8877 291 * @}
bogdanm 84:0b3ab51c8877 292 */
bogdanm 84:0b3ab51c8877 293
bogdanm 84:0b3ab51c8877 294 /** @defgroup SPI_TI_mode
bogdanm 84:0b3ab51c8877 295 * @{
bogdanm 84:0b3ab51c8877 296 */
bogdanm 84:0b3ab51c8877 297 #define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 298 #define SPI_TIMODE_ENABLED SPI_CR2_FRF
bogdanm 84:0b3ab51c8877 299
bogdanm 84:0b3ab51c8877 300 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
bogdanm 84:0b3ab51c8877 301 ((MODE) == SPI_TIMODE_ENABLED))
bogdanm 84:0b3ab51c8877 302 /**
bogdanm 84:0b3ab51c8877 303 * @}
bogdanm 84:0b3ab51c8877 304 */
bogdanm 84:0b3ab51c8877 305
bogdanm 84:0b3ab51c8877 306 /** @defgroup SPI_CRC_Calculation
bogdanm 84:0b3ab51c8877 307 * @{
bogdanm 84:0b3ab51c8877 308 */
bogdanm 84:0b3ab51c8877 309 #define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
bogdanm 84:0b3ab51c8877 310 #define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
bogdanm 84:0b3ab51c8877 311
bogdanm 84:0b3ab51c8877 312 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
bogdanm 84:0b3ab51c8877 313 ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
bogdanm 84:0b3ab51c8877 314 /**
bogdanm 84:0b3ab51c8877 315 * @}
bogdanm 84:0b3ab51c8877 316 */
bogdanm 84:0b3ab51c8877 317
bogdanm 84:0b3ab51c8877 318 /** @defgroup SPI_Interrupt_configuration_definition
bogdanm 84:0b3ab51c8877 319 * @{
bogdanm 84:0b3ab51c8877 320 */
bogdanm 84:0b3ab51c8877 321 #define SPI_IT_TXE SPI_CR2_TXEIE
bogdanm 84:0b3ab51c8877 322 #define SPI_IT_RXNE SPI_CR2_RXNEIE
bogdanm 84:0b3ab51c8877 323 #define SPI_IT_ERR SPI_CR2_ERRIE
bogdanm 84:0b3ab51c8877 324 /**
bogdanm 84:0b3ab51c8877 325 * @}
bogdanm 84:0b3ab51c8877 326 */
bogdanm 84:0b3ab51c8877 327
bogdanm 84:0b3ab51c8877 328 /** @defgroup SPI_Flag_definition
bogdanm 84:0b3ab51c8877 329 * @{
bogdanm 84:0b3ab51c8877 330 */
bogdanm 84:0b3ab51c8877 331 #define SPI_FLAG_RXNE SPI_SR_RXNE
bogdanm 84:0b3ab51c8877 332 #define SPI_FLAG_TXE SPI_SR_TXE
bogdanm 84:0b3ab51c8877 333 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
bogdanm 84:0b3ab51c8877 334 #define SPI_FLAG_MODF SPI_SR_MODF
bogdanm 84:0b3ab51c8877 335 #define SPI_FLAG_OVR SPI_SR_OVR
bogdanm 84:0b3ab51c8877 336 #define SPI_FLAG_BSY SPI_SR_BSY
bogdanm 84:0b3ab51c8877 337 #define SPI_FLAG_FRE SPI_SR_FRE
bogdanm 84:0b3ab51c8877 338
bogdanm 84:0b3ab51c8877 339 /**
bogdanm 84:0b3ab51c8877 340 * @}
bogdanm 84:0b3ab51c8877 341 */
bogdanm 84:0b3ab51c8877 342
bogdanm 84:0b3ab51c8877 343 /**
bogdanm 84:0b3ab51c8877 344 * @}
bogdanm 84:0b3ab51c8877 345 */
bogdanm 84:0b3ab51c8877 346
bogdanm 84:0b3ab51c8877 347 /* Exported macro ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 348
bogdanm 84:0b3ab51c8877 349 /** @brief Reset SPI handle state
bogdanm 84:0b3ab51c8877 350 * @param __HANDLE__: specifies the SPI handle.
bogdanm 84:0b3ab51c8877 351 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 352 * @retval None
bogdanm 84:0b3ab51c8877 353 */
bogdanm 84:0b3ab51c8877 354 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
bogdanm 84:0b3ab51c8877 355
bogdanm 84:0b3ab51c8877 356 /** @brief Enable or disable the specified SPI interrupts.
bogdanm 84:0b3ab51c8877 357 * @param __HANDLE__: specifies the SPI handle.
bogdanm 84:0b3ab51c8877 358 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 359 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 84:0b3ab51c8877 360 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 361 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 84:0b3ab51c8877 362 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 84:0b3ab51c8877 363 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 84:0b3ab51c8877 364 * @retval None
bogdanm 84:0b3ab51c8877 365 */
bogdanm 84:0b3ab51c8877 366 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
bogdanm 84:0b3ab51c8877 367 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
bogdanm 84:0b3ab51c8877 368
bogdanm 84:0b3ab51c8877 369 /** @brief Check if the specified SPI interrupt source is enabled or disabled.
bogdanm 84:0b3ab51c8877 370 * @param __HANDLE__: specifies the SPI handle.
bogdanm 84:0b3ab51c8877 371 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 372 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
bogdanm 84:0b3ab51c8877 373 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 374 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 84:0b3ab51c8877 375 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 84:0b3ab51c8877 376 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 84:0b3ab51c8877 377 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 378 */
bogdanm 84:0b3ab51c8877 379 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 84:0b3ab51c8877 380
bogdanm 84:0b3ab51c8877 381 /** @brief Check whether the specified SPI flag is set or not.
bogdanm 84:0b3ab51c8877 382 * @param __HANDLE__: specifies the SPI handle.
bogdanm 84:0b3ab51c8877 383 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 384 * @param __FLAG__: specifies the flag to check.
bogdanm 84:0b3ab51c8877 385 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 386 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
bogdanm 84:0b3ab51c8877 387 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
bogdanm 84:0b3ab51c8877 388 * @arg SPI_FLAG_CRCERR: CRC error flag
bogdanm 84:0b3ab51c8877 389 * @arg SPI_FLAG_MODF: Mode fault flag
bogdanm 84:0b3ab51c8877 390 * @arg SPI_FLAG_OVR: Overrun flag
bogdanm 84:0b3ab51c8877 391 * @arg SPI_FLAG_BSY: Busy flag
bogdanm 84:0b3ab51c8877 392 * @arg SPI_FLAG_FRE: Frame format error flag
bogdanm 84:0b3ab51c8877 393 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 84:0b3ab51c8877 394 */
bogdanm 84:0b3ab51c8877 395 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 84:0b3ab51c8877 396
bogdanm 84:0b3ab51c8877 397 /** @brief Clear the SPI CRCERR pending flag.
bogdanm 84:0b3ab51c8877 398 * @param __HANDLE__: specifies the SPI handle.
bogdanm 84:0b3ab51c8877 399 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 400 * @retval None
bogdanm 84:0b3ab51c8877 401 */
bogdanm 84:0b3ab51c8877 402 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= (uint32_t)~((uint32_t)SPI_FLAG_CRCERR))
bogdanm 84:0b3ab51c8877 403
bogdanm 84:0b3ab51c8877 404 /** @brief Clear the SPI MODF pending flag.
bogdanm 84:0b3ab51c8877 405 * @param __HANDLE__: specifies the SPI handle.
bogdanm 84:0b3ab51c8877 406 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 407 * @retval None
bogdanm 84:0b3ab51c8877 408 */
bogdanm 84:0b3ab51c8877 409 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
bogdanm 84:0b3ab51c8877 410 (__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_SPE);}while(0)
bogdanm 84:0b3ab51c8877 411
bogdanm 84:0b3ab51c8877 412 /** @brief Clear the SPI OVR pending flag.
bogdanm 84:0b3ab51c8877 413 * @param __HANDLE__: specifies the SPI handle.
bogdanm 84:0b3ab51c8877 414 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 415 * @retval None
bogdanm 84:0b3ab51c8877 416 */
bogdanm 84:0b3ab51c8877 417 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
bogdanm 84:0b3ab51c8877 418 (__HANDLE__)->Instance->SR;}while(0)
bogdanm 84:0b3ab51c8877 419
bogdanm 84:0b3ab51c8877 420 /** @brief Clear the SPI FRE pending flag.
bogdanm 84:0b3ab51c8877 421 * @param __HANDLE__: specifies the SPI handle.
bogdanm 84:0b3ab51c8877 422 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 84:0b3ab51c8877 423 * @retval None
bogdanm 84:0b3ab51c8877 424 */
bogdanm 84:0b3ab51c8877 425 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
bogdanm 84:0b3ab51c8877 426
bogdanm 84:0b3ab51c8877 427 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
bogdanm 84:0b3ab51c8877 428 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_SPE))
bogdanm 84:0b3ab51c8877 429
bogdanm 84:0b3ab51c8877 430 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
bogdanm 84:0b3ab51c8877 431
bogdanm 84:0b3ab51c8877 432 #define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
bogdanm 84:0b3ab51c8877 433
bogdanm 84:0b3ab51c8877 434 #define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_BIDIOE))
bogdanm 84:0b3ab51c8877 435
bogdanm 84:0b3ab51c8877 436 #define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_CRCEN);\
bogdanm 84:0b3ab51c8877 437 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
bogdanm 84:0b3ab51c8877 438
bogdanm 84:0b3ab51c8877 439 /* Exported functions --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 440
bogdanm 84:0b3ab51c8877 441 /* Initialization/de-initialization functions **********************************/
bogdanm 84:0b3ab51c8877 442 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 443 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 444 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 445 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 446
bogdanm 84:0b3ab51c8877 447 /* I/O operation functions *****************************************************/
bogdanm 84:0b3ab51c8877 448 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 449 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 450 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
bogdanm 84:0b3ab51c8877 451 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 452 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 453 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm 84:0b3ab51c8877 454 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 455 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 84:0b3ab51c8877 456 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm 84:0b3ab51c8877 457 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 458 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 459 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 460 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 461 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 462
bogdanm 84:0b3ab51c8877 463 /* Peripheral State and Control functions **************************************/
bogdanm 84:0b3ab51c8877 464 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 465 HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
bogdanm 84:0b3ab51c8877 466
bogdanm 84:0b3ab51c8877 467 /**
bogdanm 84:0b3ab51c8877 468 * @}
bogdanm 84:0b3ab51c8877 469 */
bogdanm 84:0b3ab51c8877 470
bogdanm 84:0b3ab51c8877 471 /**
bogdanm 84:0b3ab51c8877 472 * @}
bogdanm 84:0b3ab51c8877 473 */
bogdanm 84:0b3ab51c8877 474
bogdanm 84:0b3ab51c8877 475 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 476 }
bogdanm 84:0b3ab51c8877 477 #endif
bogdanm 84:0b3ab51c8877 478
bogdanm 84:0b3ab51c8877 479 #endif /* __STM32L0xx_HAL_SPI_H */
bogdanm 84:0b3ab51c8877 480
bogdanm 84:0b3ab51c8877 481 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/