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TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:: emilmont
Date:: Fri Feb 14 14:36:43 2014 +0000
Revision:: 77:869cf507173a
Child:: 81:7d30d6019079

Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_hal_dma2d.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
emilmont	77:869cf507173a	5	* @version V1.0.0RC2
emilmont	77:869cf507173a	6	* @date 04-February-2014
emilmont	77:869cf507173a	7	* @brief Header file of DMA2D HAL module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
emilmont	77:869cf507173a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_HAL_DMA2D_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_HAL_DMA2D_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	#if defined(STM32F429xx) \|\| defined(STM32F439xx)
emilmont	77:869cf507173a	47	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	48	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	49
emilmont	77:869cf507173a	50	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	51	* @{
emilmont	77:869cf507173a	52	*/
emilmont	77:869cf507173a	53
emilmont	77:869cf507173a	54	/** @addtogroup DMA2D
emilmont	77:869cf507173a	55	* @{
emilmont	77:869cf507173a	56	*/
emilmont	77:869cf507173a	57
emilmont	77:869cf507173a	58	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	59
emilmont	77:869cf507173a	60	#define MAX_DMA2D_LAYER 2
emilmont	77:869cf507173a	61
emilmont	77:869cf507173a	62	/**
emilmont	77:869cf507173a	63	* @brief DMA2D color Structure definition
emilmont	77:869cf507173a	64	*/
emilmont	77:869cf507173a	65	typedef struct
emilmont	77:869cf507173a	66	{
emilmont	77:869cf507173a	67	uint32_t Blue; /*!< Configures the blue value.
emilmont	77:869cf507173a	68	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
emilmont	77:869cf507173a	69
emilmont	77:869cf507173a	70	uint32_t Green; /*!< Configures the green value.
emilmont	77:869cf507173a	71	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
emilmont	77:869cf507173a	72
emilmont	77:869cf507173a	73	uint32_t Red; /*!< Configures the red value.
emilmont	77:869cf507173a	74	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
emilmont	77:869cf507173a	75	} DMA2D_ColorTypeDef;
emilmont	77:869cf507173a	76
emilmont	77:869cf507173a	77	/**
emilmont	77:869cf507173a	78	* @brief DMA2D CLUT Structure definition
emilmont	77:869cf507173a	79	*/
emilmont	77:869cf507173a	80	typedef struct
emilmont	77:869cf507173a	81	{
emilmont	77:869cf507173a	82	uint32_t pCLUT; /!< Configures the DMA2D CLUT memory address. */
emilmont	77:869cf507173a	83
emilmont	77:869cf507173a	84	uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
emilmont	77:869cf507173a	85	This parameter can be one value of @ref DMA2D_CLUT_CM */
emilmont	77:869cf507173a	86
emilmont	77:869cf507173a	87	uint32_t Size; /*!< configures the DMA2D CLUT size.
emilmont	77:869cf507173a	88	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
emilmont	77:869cf507173a	89	} DMA2D_CLUTCfgTypeDef;
emilmont	77:869cf507173a	90
emilmont	77:869cf507173a	91	/**
emilmont	77:869cf507173a	92	* @brief DMA2D Init structure definition
emilmont	77:869cf507173a	93	*/
emilmont	77:869cf507173a	94	typedef struct
emilmont	77:869cf507173a	95	{
emilmont	77:869cf507173a	96	uint32_t Mode; /*!< configures the DMA2D transfer mode.
emilmont	77:869cf507173a	97	This parameter can be one value of @ref DMA2D_Mode */
emilmont	77:869cf507173a	98
emilmont	77:869cf507173a	99	uint32_t ColorMode; /*!< configures the color format of the output image.
emilmont	77:869cf507173a	100	This parameter can be one value of @ref DMA2D_Color_Mode */
emilmont	77:869cf507173a	101
emilmont	77:869cf507173a	102	uint32_t OutputOffset; /*!< Specifies the Offset value.
emilmont	77:869cf507173a	103	This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
emilmont	77:869cf507173a	104
emilmont	77:869cf507173a	105	} DMA2D_InitTypeDef;
emilmont	77:869cf507173a	106
emilmont	77:869cf507173a	107	/**
emilmont	77:869cf507173a	108	* @brief DMA2D Layer structure definition
emilmont	77:869cf507173a	109	*/
emilmont	77:869cf507173a	110	typedef struct
emilmont	77:869cf507173a	111	{
emilmont	77:869cf507173a	112
emilmont	77:869cf507173a	113
emilmont	77:869cf507173a	114	uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
emilmont	77:869cf507173a	115	This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
emilmont	77:869cf507173a	116
emilmont	77:869cf507173a	117	uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
emilmont	77:869cf507173a	118	This parameter can be one value of @ref DMA2D_Input_Color_Mode */
emilmont	77:869cf507173a	119
emilmont	77:869cf507173a	120	uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
emilmont	77:869cf507173a	121	This parameter can be one value of @ref DMA2D_ALPHA_MODE */
emilmont	77:869cf507173a	122
emilmont	77:869cf507173a	123	uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value
emilmont	77:869cf507173a	124	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
emilmont	77:869cf507173a	125
emilmont	77:869cf507173a	126	} DMA2D_LayerCfgTypeDef;
emilmont	77:869cf507173a	127
emilmont	77:869cf507173a	128	/**
emilmont	77:869cf507173a	129	* @brief HAL DMA2D State structures definition
emilmont	77:869cf507173a	130	*/
emilmont	77:869cf507173a	131	typedef enum
emilmont	77:869cf507173a	132	{
emilmont	77:869cf507173a	133	HAL_DMA2D_STATE_RESET = 0x00, /!< DMA2D not yet initialized or disabled /
emilmont	77:869cf507173a	134	HAL_DMA2D_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
emilmont	77:869cf507173a	135	HAL_DMA2D_STATE_BUSY = 0x02, /!< an internal process is ongoing /
emilmont	77:869cf507173a	136	HAL_DMA2D_STATE_TIMEOUT = 0x03, /!< Timeout state /
emilmont	77:869cf507173a	137	HAL_DMA2D_STATE_ERROR = 0x04, /!< DMA2D state error /
emilmont	77:869cf507173a	138	HAL_DMA2D_STATE_SUSPEND = 0x05 /!< DMA2D process is suspended /
emilmont	77:869cf507173a	139
emilmont	77:869cf507173a	140	}HAL_DMA2D_StateTypeDef;
emilmont	77:869cf507173a	141
emilmont	77:869cf507173a	142	/**
emilmont	77:869cf507173a	143	* @brief DMA2D handle Structure definition
emilmont	77:869cf507173a	144	*/
emilmont	77:869cf507173a	145	typedef struct __DMA2D_HandleTypeDef
emilmont	77:869cf507173a	146	{
emilmont	77:869cf507173a	147	DMA2D_TypeDef Instance; /!< DMA2D Register base address */
emilmont	77:869cf507173a	148
emilmont	77:869cf507173a	149	DMA2D_InitTypeDef Init; /!< DMA2D communication parameters /
emilmont	77:869cf507173a	150
emilmont	77:869cf507173a	151	void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /!< DMA2D transfer complete callback /
emilmont	77:869cf507173a	152
emilmont	77:869cf507173a	153	void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /!< DMA2D transfer error callback /
emilmont	77:869cf507173a	154
emilmont	77:869cf507173a	155	DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /!< DMA2D Layers parameters /
emilmont	77:869cf507173a	156
emilmont	77:869cf507173a	157	HAL_LockTypeDef Lock; /!< DMA2D Lock /
emilmont	77:869cf507173a	158
emilmont	77:869cf507173a	159	__IO HAL_DMA2D_StateTypeDef State; /!< DMA2D transfer state /
emilmont	77:869cf507173a	160
emilmont	77:869cf507173a	161	__IO uint32_t ErrorCode; /!< DMA2D Error code /
emilmont	77:869cf507173a	162
emilmont	77:869cf507173a	163	} DMA2D_HandleTypeDef;
emilmont	77:869cf507173a	164
emilmont	77:869cf507173a	165
emilmont	77:869cf507173a	166	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	167
emilmont	77:869cf507173a	168	/** @defgroup DMA2D_Exported_Constants
emilmont	77:869cf507173a	169	* @{
emilmont	77:869cf507173a	170	*/
emilmont	77:869cf507173a	171
emilmont	77:869cf507173a	172	/** @defgroup DMA2D_Layer
emilmont	77:869cf507173a	173	* @{
emilmont	77:869cf507173a	174	*/
emilmont	77:869cf507173a	175	#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
emilmont	77:869cf507173a	176	/**
emilmont	77:869cf507173a	177	* @}
emilmont	77:869cf507173a	178	*/
emilmont	77:869cf507173a	179
emilmont	77:869cf507173a	180	/** @defgroup DMA2D_Error_Code
emilmont	77:869cf507173a	181	* @{
emilmont	77:869cf507173a	182	*/
emilmont	77:869cf507173a	183	#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /!< No error /
emilmont	77:869cf507173a	184	#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /!< Transfer error /
emilmont	77:869cf507173a	185	#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /!< Configuration error /
emilmont	77:869cf507173a	186	#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /!< Timeout error /
emilmont	77:869cf507173a	187	/**
emilmont	77:869cf507173a	188	* @}
emilmont	77:869cf507173a	189	*/
emilmont	77:869cf507173a	190
emilmont	77:869cf507173a	191	/** @defgroup DMA2D_Mode
emilmont	77:869cf507173a	192	* @{
emilmont	77:869cf507173a	193	*/
emilmont	77:869cf507173a	194	#define DMA2D_M2M ((uint32_t)0x00000000) /!< DMA2D memory to memory transfer mode /
emilmont	77:869cf507173a	195	#define DMA2D_M2M_PFC ((uint32_t)0x00010000) /!< DMA2D memory to memory with pixel format conversion transfer mode /
emilmont	77:869cf507173a	196	#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /!< DMA2D memory to memory with blending transfer mode /
emilmont	77:869cf507173a	197	#define DMA2D_R2M ((uint32_t)0x00030000) /!< DMA2D register to memory transfer mode /
emilmont	77:869cf507173a	198
emilmont	77:869cf507173a	199	#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) \|\| ((MODE) == DMA2D_M2M_PFC) \|\| \
emilmont	77:869cf507173a	200	((MODE) == DMA2D_M2M_BLEND) \|\| ((MODE) == DMA2D_R2M))
emilmont	77:869cf507173a	201	/**
emilmont	77:869cf507173a	202	* @}
emilmont	77:869cf507173a	203	*/
emilmont	77:869cf507173a	204
emilmont	77:869cf507173a	205	/** @defgroup DMA2D_Color_Mode
emilmont	77:869cf507173a	206	* @{
emilmont	77:869cf507173a	207	*/
emilmont	77:869cf507173a	208	#define DMA2D_ARGB8888 ((uint32_t)0x00000000) /!< ARGB8888 DMA2D color mode /
emilmont	77:869cf507173a	209	#define DMA2D_RGB888 ((uint32_t)0x00000001) /!< RGB888 DMA2D color mode /
emilmont	77:869cf507173a	210	#define DMA2D_RGB565 ((uint32_t)0x00000002) /!< RGB565 DMA2D color mode /
emilmont	77:869cf507173a	211	#define DMA2D_ARGB1555 ((uint32_t)0x00000003) /!< ARGB1555 DMA2D color mode /
emilmont	77:869cf507173a	212	#define DMA2D_ARGB4444 ((uint32_t)0x00000004) /!< ARGB4444 DMA2D color mode /
emilmont	77:869cf507173a	213
emilmont	77:869cf507173a	214	#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) \|\| ((MODE_ARGB) == DMA2D_RGB888) \|\| \
emilmont	77:869cf507173a	215	((MODE_ARGB) == DMA2D_RGB565) \|\| ((MODE_ARGB) == DMA2D_ARGB1555) \|\| \
emilmont	77:869cf507173a	216	((MODE_ARGB) == DMA2D_ARGB4444))
emilmont	77:869cf507173a	217	/**
emilmont	77:869cf507173a	218	* @}
emilmont	77:869cf507173a	219	*/
emilmont	77:869cf507173a	220
emilmont	77:869cf507173a	221	/** @defgroup DMA2D_COLOR_VALUE
emilmont	77:869cf507173a	222	* @{
emilmont	77:869cf507173a	223	*/
emilmont	77:869cf507173a	224
emilmont	77:869cf507173a	225	#define COLOR_VALUE ((uint32_t)0x000000FF) /!< color value mask /
emilmont	77:869cf507173a	226
emilmont	77:869cf507173a	227	#define IS_DMA2D_ALPHA_VALUE(ALPHA_VALUE) ((ALPHA_VALUE) <= COLOR_VALUE)
emilmont	77:869cf507173a	228	#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
emilmont	77:869cf507173a	229	/**
emilmont	77:869cf507173a	230	* @}
emilmont	77:869cf507173a	231	*/
emilmont	77:869cf507173a	232
emilmont	77:869cf507173a	233	/** @defgroup DMA2D_SIZE
emilmont	77:869cf507173a	234	* @{
emilmont	77:869cf507173a	235	*/
emilmont	77:869cf507173a	236	#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /!< DMA2D pixel per line /
emilmont	77:869cf507173a	237	#define DMA2D_LINE DMA2D_NLR_NL /!< DMA2D number of line /
emilmont	77:869cf507173a	238
emilmont	77:869cf507173a	239	#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
emilmont	77:869cf507173a	240	#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
emilmont	77:869cf507173a	241	/**
emilmont	77:869cf507173a	242	* @}
emilmont	77:869cf507173a	243	*/
emilmont	77:869cf507173a	244
emilmont	77:869cf507173a	245	/** @defgroup DMA2D_OFFSET
emilmont	77:869cf507173a	246	* @{
emilmont	77:869cf507173a	247	*/
emilmont	77:869cf507173a	248	#define DMA2D_OFFSET DMA2D_FGOR_LO /!< Line Offset /
emilmont	77:869cf507173a	249
emilmont	77:869cf507173a	250	#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
emilmont	77:869cf507173a	251	/**
emilmont	77:869cf507173a	252	* @}
emilmont	77:869cf507173a	253	*/
emilmont	77:869cf507173a	254
emilmont	77:869cf507173a	255	/** @defgroup DMA2D_Input_Color_Mode
emilmont	77:869cf507173a	256	* @{
emilmont	77:869cf507173a	257	*/
emilmont	77:869cf507173a	258	#define CM_ARGB8888 ((uint32_t)0x00000000) /!< ARGB8888 color mode /
emilmont	77:869cf507173a	259	#define CM_RGB888 ((uint32_t)0x00000001) /!< RGB888 color mode /
emilmont	77:869cf507173a	260	#define CM_RGB565 ((uint32_t)0x00000002) /!< RGB565 color mode /
emilmont	77:869cf507173a	261	#define CM_ARGB1555 ((uint32_t)0x00000003) /!< ARGB1555 color mode /
emilmont	77:869cf507173a	262	#define CM_ARGB4444 ((uint32_t)0x00000004) /!< ARGB4444 color mode /
emilmont	77:869cf507173a	263	#define CM_L8 ((uint32_t)0x00000005) /!< L8 color mode /
emilmont	77:869cf507173a	264	#define CM_AL44 ((uint32_t)0x00000006) /!< AL44 color mode /
emilmont	77:869cf507173a	265	#define CM_AL88 ((uint32_t)0x00000007) /!< AL88 color mode /
emilmont	77:869cf507173a	266	#define CM_L4 ((uint32_t)0x00000008) /!< L4 color mode /
emilmont	77:869cf507173a	267	#define CM_A8 ((uint32_t)0x00000009) /!< A8 color mode /
emilmont	77:869cf507173a	268	#define CM_A4 ((uint32_t)0x0000000A) /!< A4 color mode /
emilmont	77:869cf507173a	269
emilmont	77:869cf507173a	270	#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) \|\| ((INPUT_CM) == CM_RGB888) \|\| \
emilmont	77:869cf507173a	271	((INPUT_CM) == CM_RGB565) \|\| ((INPUT_CM) == CM_ARGB1555) \|\| \
emilmont	77:869cf507173a	272	((INPUT_CM) == CM_ARGB4444) \|\| ((INPUT_CM) == CM_L8) \|\| \
emilmont	77:869cf507173a	273	((INPUT_CM) == CM_AL44) \|\| ((INPUT_CM) == CM_AL88) \|\| \
emilmont	77:869cf507173a	274	((INPUT_CM) == CM_L4) \|\| ((INPUT_CM) == CM_A8) \|\| \
emilmont	77:869cf507173a	275	((INPUT_CM) == CM_A4))
emilmont	77:869cf507173a	276	/**
emilmont	77:869cf507173a	277	* @}
emilmont	77:869cf507173a	278	*/
emilmont	77:869cf507173a	279
emilmont	77:869cf507173a	280	/** @defgroup DMA2D_ALPHA_MODE
emilmont	77:869cf507173a	281	* @{
emilmont	77:869cf507173a	282	*/
emilmont	77:869cf507173a	283	#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /!< No modification of the alpha channel value /
emilmont	77:869cf507173a	284	#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /!< Replace original alpha channel value by programmed alpha value /
emilmont	77:869cf507173a	285	#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
emilmont	77:869cf507173a	286	with original alpha channel value */
emilmont	77:869cf507173a	287
emilmont	77:869cf507173a	288	#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) \|\| \
emilmont	77:869cf507173a	289	((AlphaMode) == DMA2D_REPLACE_ALPHA) \|\| \
emilmont	77:869cf507173a	290	((AlphaMode) == DMA2D_COMBINE_ALPHA))
emilmont	77:869cf507173a	291	/**
emilmont	77:869cf507173a	292	* @}
emilmont	77:869cf507173a	293	*/
emilmont	77:869cf507173a	294
emilmont	77:869cf507173a	295	/** @defgroup DMA2D_CLUT_CM
emilmont	77:869cf507173a	296	* @{
emilmont	77:869cf507173a	297	*/
emilmont	77:869cf507173a	298	#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /!< ARGB8888 DMA2D C-LUT color mode /
emilmont	77:869cf507173a	299	#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /!< RGB888 DMA2D C-LUT color mode /
emilmont	77:869cf507173a	300
emilmont	77:869cf507173a	301	#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) \|\| ((CLUT_CM) == DMA2D_CCM_RGB888))
emilmont	77:869cf507173a	302	/**
emilmont	77:869cf507173a	303	* @}
emilmont	77:869cf507173a	304	*/
emilmont	77:869cf507173a	305
emilmont	77:869cf507173a	306	/** @defgroup DMA2D_CLUT_SIZE
emilmont	77:869cf507173a	307	* @{
emilmont	77:869cf507173a	308	*/
emilmont	77:869cf507173a	309	#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /!< DMA2D C-LUT size /
emilmont	77:869cf507173a	310
emilmont	77:869cf507173a	311	#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
emilmont	77:869cf507173a	312	/**
emilmont	77:869cf507173a	313	* @}
emilmont	77:869cf507173a	314	*/
emilmont	77:869cf507173a	315
emilmont	77:869cf507173a	316	/** @defgroup DMA2D_DeadTime
emilmont	77:869cf507173a	317	* @{
emilmont	77:869cf507173a	318	*/
emilmont	77:869cf507173a	319	#define LINE_WATERMARK DMA2D_LWR_LW
emilmont	77:869cf507173a	320
emilmont	77:869cf507173a	321	#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
emilmont	77:869cf507173a	322	/**
emilmont	77:869cf507173a	323	* @}
emilmont	77:869cf507173a	324	*/
emilmont	77:869cf507173a	325
emilmont	77:869cf507173a	326	/** @defgroup DMA2D_Interrupts
emilmont	77:869cf507173a	327	* @{
emilmont	77:869cf507173a	328	*/
emilmont	77:869cf507173a	329	#define DMA2D_IT_CE DMA2D_CR_CEIE /!< Configuration Error Interrupt /
emilmont	77:869cf507173a	330	#define DMA2D_IT_CTC DMA2D_CR_CTCIE /!< C-LUT Transfer Complete Interrupt /
emilmont	77:869cf507173a	331	#define DMA2D_IT_CAE DMA2D_CR_CAEIE /!< C-LUT Access Error Interrupt /
emilmont	77:869cf507173a	332	#define DMA2D_IT_TW DMA2D_CR_TWIE /!< Transfer Watermark Interrupt /
emilmont	77:869cf507173a	333	#define DMA2D_IT_TC DMA2D_CR_TCIE /!< Transfer Complete Interrupt /
emilmont	77:869cf507173a	334	#define DMA2D_IT_TE DMA2D_CR_TEIE /!< Transfer Error Interrupt /
emilmont	77:869cf507173a	335
emilmont	77:869cf507173a	336	#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) \|\| ((IT) == DMA2D_IT_CAE) \|\| \
emilmont	77:869cf507173a	337	((IT) == DMA2D_IT_TW) \|\| ((IT) == DMA2D_IT_TC) \|\| \
emilmont	77:869cf507173a	338	((IT) == DMA2D_IT_TE) \|\| ((IT) == DMA2D_IT_CE))
emilmont	77:869cf507173a	339	/**
emilmont	77:869cf507173a	340	* @}
emilmont	77:869cf507173a	341	*/
emilmont	77:869cf507173a	342
emilmont	77:869cf507173a	343	/** @defgroup DMA2D_Flag
emilmont	77:869cf507173a	344	* @{
emilmont	77:869cf507173a	345	*/
emilmont	77:869cf507173a	346	#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /!< Configuration Error Interrupt Flag /
emilmont	77:869cf507173a	347	#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /!< C-LUT Transfer Complete Interrupt Flag /
emilmont	77:869cf507173a	348	#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /!< C-LUT Access Error Interrupt Flag /
emilmont	77:869cf507173a	349	#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /!< Transfer Watermark Interrupt Flag /
emilmont	77:869cf507173a	350	#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /!< Transfer Complete Interrupt Flag /
emilmont	77:869cf507173a	351	#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /!< Transfer Error Interrupt Flag /
emilmont	77:869cf507173a	352
emilmont	77:869cf507173a	353	#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) \|\| ((FLAG) == DMA2D_FLAG_CAE) \|\| \
emilmont	77:869cf507173a	354	((FLAG) == DMA2D_FLAG_TW) \|\| ((FLAG) == DMA2D_FLAG_TC) \|\| \
emilmont	77:869cf507173a	355	((FLAG) == DMA2D_FLAG_TE) \|\| ((FLAG) == DMA2D_FLAG_CE))
emilmont	77:869cf507173a	356	/**
emilmont	77:869cf507173a	357	* @}
emilmont	77:869cf507173a	358	*/
emilmont	77:869cf507173a	359
emilmont	77:869cf507173a	360	/**
emilmont	77:869cf507173a	361	* @}
emilmont	77:869cf507173a	362	*/
emilmont	77:869cf507173a	363	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	364	/**
emilmont	77:869cf507173a	365	* @brief Enable the DMA2D.
emilmont	77:869cf507173a	366	* @param __HANDLE__: DMA2D handle
emilmont	77:869cf507173a	367	* @retval None.
emilmont	77:869cf507173a	368	*/
emilmont	77:869cf507173a	369	#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= DMA2D_CR_START)
emilmont	77:869cf507173a	370
emilmont	77:869cf507173a	371	/**
emilmont	77:869cf507173a	372	* @brief Disable the DMA2D.
emilmont	77:869cf507173a	373	* @param __HANDLE__: DMA2D handle
emilmont	77:869cf507173a	374	* @retval None.
emilmont	77:869cf507173a	375	*/
emilmont	77:869cf507173a	376	#define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
emilmont	77:869cf507173a	377
emilmont	77:869cf507173a	378	/* Interrupt & Flag management */
emilmont	77:869cf507173a	379	/**
emilmont	77:869cf507173a	380	* @brief Get the DMA2D pending flags.
emilmont	77:869cf507173a	381	* @param __HANDLE__: DMA2D handle
emilmont	77:869cf507173a	382	* @param __FLAG__: Get the specified flag.
emilmont	77:869cf507173a	383	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	384	* @arg DMA2D_FLAG_CE: Configuration error flag
emilmont	77:869cf507173a	385	* @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
emilmont	77:869cf507173a	386	* @arg DMA2D_FLAG_CAE: C-LUT access error flag
emilmont	77:869cf507173a	387	* @arg DMA2D_FLAG_TW: Transfer Watermark flag
emilmont	77:869cf507173a	388	* @arg DMA2D_FLAG_TC: Transfer complete flag
emilmont	77:869cf507173a	389	* @arg DMA2D_FLAG_TE: Transfer error flag
emilmont	77:869cf507173a	390	* @retval The state of FLAG.
emilmont	77:869cf507173a	391	*/
emilmont	77:869cf507173a	392	#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
emilmont	77:869cf507173a	393
emilmont	77:869cf507173a	394	/**
emilmont	77:869cf507173a	395	* @brief Clears the DMA2D pending flags.
emilmont	77:869cf507173a	396	* @param __HANDLE__: DMA2D handle
emilmont	77:869cf507173a	397	* @param __FLAG__: specifies the flag to clear.
emilmont	77:869cf507173a	398	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	399	* @arg DMA2D_FLAG_CE: Configuration error flag
emilmont	77:869cf507173a	400	* @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
emilmont	77:869cf507173a	401	* @arg DMA2D_FLAG_CAE: C-LUT access error flag
emilmont	77:869cf507173a	402	* @arg DMA2D_FLAG_TW: Transfer Watermark flag
emilmont	77:869cf507173a	403	* @arg DMA2D_FLAG_TC: Transfer complete flag
emilmont	77:869cf507173a	404	* @arg DMA2D_FLAG_TE: Transfer error flag
emilmont	77:869cf507173a	405	* @retval None
emilmont	77:869cf507173a	406	*/
emilmont	77:869cf507173a	407	#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR \|= (__FLAG__))
emilmont	77:869cf507173a	408
emilmont	77:869cf507173a	409	/**
emilmont	77:869cf507173a	410	* @brief Enables the specified DMA2D interrupts.
emilmont	77:869cf507173a	411	* @param __HANDLE__: DMA2D handle
emilmont	77:869cf507173a	412	* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
emilmont	77:869cf507173a	413	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	414	* @arg DMA2D_IT_CE: Configuration error interrupt mask
emilmont	77:869cf507173a	415	* @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
emilmont	77:869cf507173a	416	* @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
emilmont	77:869cf507173a	417	* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
emilmont	77:869cf507173a	418	* @arg DMA2D_IT_TC: Transfer complete interrupt mask
emilmont	77:869cf507173a	419	* @arg DMA2D_IT_TE: Transfer error interrupt mask
emilmont	77:869cf507173a	420	* @retval None
emilmont	77:869cf507173a	421	*/
emilmont	77:869cf507173a	422	#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR \|= (__INTERRUPT__))
emilmont	77:869cf507173a	423
emilmont	77:869cf507173a	424	/**
emilmont	77:869cf507173a	425	* @brief Disables the specified DMA2D interrupts.
emilmont	77:869cf507173a	426	* @param __HANDLE__: DMA2D handle
emilmont	77:869cf507173a	427	* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
emilmont	77:869cf507173a	428	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	429	* @arg DMA2D_IT_CE: Configuration error interrupt mask
emilmont	77:869cf507173a	430	* @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
emilmont	77:869cf507173a	431	* @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
emilmont	77:869cf507173a	432	* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
emilmont	77:869cf507173a	433	* @arg DMA2D_IT_TC: Transfer complete interrupt mask
emilmont	77:869cf507173a	434	* @arg DMA2D_IT_TE: Transfer error interrupt mask
emilmont	77:869cf507173a	435	* @retval None
emilmont	77:869cf507173a	436	*/
emilmont	77:869cf507173a	437	#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	438
emilmont	77:869cf507173a	439	/**
emilmont	77:869cf507173a	440	* @brief Checks whether the specified DMA2D interrupt has occurred or not.
emilmont	77:869cf507173a	441	* @param __HANDLE__: DMA2D handle
emilmont	77:869cf507173a	442	* @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
emilmont	77:869cf507173a	443	* This parameter can be one of the following values:
emilmont	77:869cf507173a	444	* @arg DMA2D_IT_CE: Configuration error interrupt mask
emilmont	77:869cf507173a	445	* @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
emilmont	77:869cf507173a	446	* @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
emilmont	77:869cf507173a	447	* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
emilmont	77:869cf507173a	448	* @arg DMA2D_IT_TC: Transfer complete interrupt mask
emilmont	77:869cf507173a	449	* @arg DMA2D_IT_TE: Transfer error interrupt mask
emilmont	77:869cf507173a	450	* @retval The state of INTERRUPT.
emilmont	77:869cf507173a	451	*/
emilmont	77:869cf507173a	452	#define __HAL_DMA2D_IT_STATUS(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
emilmont	77:869cf507173a	453
emilmont	77:869cf507173a	454	/* Exported functions --------------------------------------------------------*/
emilmont	77:869cf507173a	455
emilmont	77:869cf507173a	456	/* Initialization and de-initialization functions *******************************/
emilmont	77:869cf507173a	457	HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
emilmont	77:869cf507173a	458	HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
emilmont	77:869cf507173a	459	__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
emilmont	77:869cf507173a	460	__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
emilmont	77:869cf507173a	461
emilmont	77:869cf507173a	462	/* IO operation functions *******************************************************/
emilmont	77:869cf507173a	463	HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
emilmont	77:869cf507173a	464	HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
emilmont	77:869cf507173a	465	HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
emilmont	77:869cf507173a	466	HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
emilmont	77:869cf507173a	467	HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
emilmont	77:869cf507173a	468	HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
emilmont	77:869cf507173a	469	HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
emilmont	77:869cf507173a	470	HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
emilmont	77:869cf507173a	471	void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
emilmont	77:869cf507173a	472
emilmont	77:869cf507173a	473	/* Peripheral Control functions *************************************************/
emilmont	77:869cf507173a	474	HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
emilmont	77:869cf507173a	475	HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
emilmont	77:869cf507173a	476	HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
emilmont	77:869cf507173a	477	HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
emilmont	77:869cf507173a	478	HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
emilmont	77:869cf507173a	479
emilmont	77:869cf507173a	480	/* Peripheral State functions ***************************************************/
emilmont	77:869cf507173a	481	HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
emilmont	77:869cf507173a	482	uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
emilmont	77:869cf507173a	483
emilmont	77:869cf507173a	484	#endif /* STM32F429xx \|\| STM32F439xx */
emilmont	77:869cf507173a	485
emilmont	77:869cf507173a	486	/**
emilmont	77:869cf507173a	487	* @}
emilmont	77:869cf507173a	488	*/
emilmont	77:869cf507173a	489
emilmont	77:869cf507173a	490	/**
emilmont	77:869cf507173a	491	* @}
emilmont	77:869cf507173a	492	*/
emilmont	77:869cf507173a	493
emilmont	77:869cf507173a	494	#ifdef __cplusplus
emilmont	77:869cf507173a	495	}
emilmont	77:869cf507173a	496	#endif
emilmont	77:869cf507173a	497
emilmont	77:869cf507173a	498	#endif /* __STM32F4xx_HAL_DMA2D_H */
emilmont	77:869cf507173a	499
emilmont	77:869cf507173a	500
emilmont	77:869cf507173a	501	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Dec 2014
Imports:	4
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The code in this repository is Apache licensed.

TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.h@77:869cf507173a, 2014-02-14 (annotated)

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