frederic blanc / ADC128D818

12-Bit, 8-Channel, ADC System Monitor w/ Temp Sensor, Internal/External Reference, & I2C Interface

Dependents:   ADC128D818_HelloWorld

ADC128D818.h@3:816284ff2a09, 2013-09-06 (annotated)

Committer:
fblanc
Date:
Fri Sep 06 07:19:25 2013 +0000
Revision:
3:816284ff2a09
Parent:
2:f9a0518b352a 
doc classes

Who changed what in which revision?

UserRevisionLine numberNew contents of line
fblanc 1:5f9dbbbc34c5 1 /**
fblanc 1:5f9dbbbc34c5 2 * @brief ADC128D818 12-Bit, 8-Channel, ADC System Monitor w/ Temp Sensor, Internal/External Reference, & I2C Interfac
fblanc 1:5f9dbbbc34c5 3 * http://www.ti.com/product/adc128d818/
fblanc 1:5f9dbbbc34c5 4 * @date 02/09/2013
fblanc 1:5f9dbbbc34c5 5 * @author F.BLANC LAAS-CNRS
fblanc 1:5f9dbbbc34c5 6 * http://homepages.laas.fr/fblanc/
fblanc 1:5f9dbbbc34c5 7 */
fblanc 0:9cc68ef524da 8
fblanc 0:9cc68ef524da 9 #ifndef ADC128D818_H
fblanc 0:9cc68ef524da 10
fblanc 0:9cc68ef524da 11 #define ADC128D818_H
fblanc 0:9cc68ef524da 12
fblanc 0:9cc68ef524da 13 #include "mbed.h"
fblanc 0:9cc68ef524da 14
fblanc 0:9cc68ef524da 15
fblanc 0:9cc68ef524da 16 //Library for the ADC128D818 12 BIT ADC.
fblanc 0:9cc68ef524da 17 enum ADC_MODE {
fblanc 2:f9a0518b352a 18 ADC_MODE_0 = 0x00,
fblanc 2:f9a0518b352a 19 ADC_MODE_1 = 0x01,
fblanc 2:f9a0518b352a 20 ADC_MODE_2 = 0x02,
fblanc 2:f9a0518b352a 21 ADC_MODE_3 = 0x03
fblanc 2:f9a0518b352a 22 };
fblanc 2:f9a0518b352a 23 enum ADC_ADDRESS {
fblanc 2:f9a0518b352a 24 ADC_ADDRESS_LOW_LOW = 0x1D,
fblanc 2:f9a0518b352a 25 ADC_ADDRESS_LOW_MID = 0x1E,
fblanc 2:f9a0518b352a 26 ADC_ADDRESS_LOW_HIGH = 0x1F,
fblanc 2:f9a0518b352a 27 ADC_ADDRESS_MID_LOW = 0x2D,
fblanc 2:f9a0518b352a 28 ADC_ADDRESS_MID_MID = 0x2E,
fblanc 2:f9a0518b352a 29 ADC_ADDRESS_MID_HIGH = 0x2F,
fblanc 2:f9a0518b352a 30 ADC_ADDRESS_HIGH_LOW = 0x35,
fblanc 2:f9a0518b352a 31 ADC_ADDRESS_HIGH_MID = 0x36,
fblanc 2:f9a0518b352a 32 ADC_ADDRESS_HIGH_HIGH = 0x37
fblanc 2:f9a0518b352a 33 };
fblanc 2:f9a0518b352a 34 enum ADC_VREF {
fblanc 2:f9a0518b352a 35 ADC_VREF_INT = 0x00,
fblanc 2:f9a0518b352a 36 ADC_VREF_EXT = 0x01
fblanc 2:f9a0518b352a 37 };
fblanc 2:f9a0518b352a 38 enum ADC_RATE {
fblanc 2:f9a0518b352a 39 ADC_RATE_LOW_POWER = 0x00,
fblanc 2:f9a0518b352a 40 ADC_RATE_CONTINUOUS = 0x01
fblanc 2:f9a0518b352a 41 };
fblanc 2:f9a0518b352a 42 enum ADC_LIMIT {
fblanc 2:f9a0518b352a 43 ADC_LIMIT_HIGH = 0x00,
fblanc 2:f9a0518b352a 44 ADC_LIMIT_LOW = 0x01
fblanc 2:f9a0518b352a 45 };
fblanc 2:f9a0518b352a 46 enum ADC_CHANNEL {
fblanc 2:f9a0518b352a 47 ADC_CHANNEL_IN0 = 0x00,
fblanc 2:f9a0518b352a 48 ADC_CHANNEL_IN1 = 0x01,
fblanc 2:f9a0518b352a 49 ADC_CHANNEL_IN2 = 0x02,
fblanc 2:f9a0518b352a 50 ADC_CHANNEL_IN3 = 0x03,
fblanc 2:f9a0518b352a 51 ADC_CHANNEL_IN4 = 0x04,
fblanc 2:f9a0518b352a 52 ADC_CHANNEL_IN5 = 0x05,
fblanc 2:f9a0518b352a 53 ADC_CHANNEL_IN6 = 0x06,
fblanc 2:f9a0518b352a 54 ADC_CHANNEL_IN7 = 0x07,
fblanc 2:f9a0518b352a 55 ADC_CHANNEL_TEMP = 0x07
fblanc 2:f9a0518b352a 56 };
fblanc 2:f9a0518b352a 57 enum ADC_INT {
fblanc 2:f9a0518b352a 58
fblanc 2:f9a0518b352a 59 ADC_INT_IN0 = (char)~(0x01 <<0),
fblanc 2:f9a0518b352a 60 ADC_INT_IN1 = (char)~(0x01 <<1),
fblanc 2:f9a0518b352a 61 ADC_INT_IN2 = (char)~(0x01 <<2),
fblanc 2:f9a0518b352a 62 ADC_INT_IN3 = (char)~(0x01 <<3),
fblanc 2:f9a0518b352a 63 ADC_INT_IN4 = (char)~(0x01 <<4),
fblanc 2:f9a0518b352a 64 ADC_INT_IN5 = (char)~(0x01 <<5),
fblanc 2:f9a0518b352a 65 ADC_INT_IN6 = (char)~(0x01 <<6),
fblanc 2:f9a0518b352a 66 ADC_INT_IN7 = (char)~(0x01 <<7),
fblanc 2:f9a0518b352a 67 ADC_INT_TEMP = (char)~(0x01 <<7),
fblanc 2:f9a0518b352a 68 ADC_INT_ALL = 0x00
fblanc 2:f9a0518b352a 69 };
fblanc 2:f9a0518b352a 70 enum ADC_ENABLE {
fblanc 2:f9a0518b352a 71
fblanc 2:f9a0518b352a 72 ADC_ENABLE_IN0 = (char)~(0x01 <<0),
fblanc 2:f9a0518b352a 73 ADC_ENABLE_IN1 = (char)~(0x01 <<1),
fblanc 2:f9a0518b352a 74 ADC_ENABLE_IN2 = (char)~(0x01 <<2),
fblanc 2:f9a0518b352a 75 ADC_ENABLE_IN3 = (char)~(0x01 <<3),
fblanc 2:f9a0518b352a 76 ADC_ENABLE_IN4 = (char)~(0x01 <<4),
fblanc 2:f9a0518b352a 77 ADC_ENABLE_IN5 = (char)~(0x01 <<5),
fblanc 2:f9a0518b352a 78 ADC_ENABLE_IN6 = (char)~(0x01 <<6),
fblanc 2:f9a0518b352a 79 ADC_ENABLE_IN7 = (char)~(0x01 <<7),
fblanc 2:f9a0518b352a 80 ADC_ENABLE_TEMP = ~(0x01 <<7),
fblanc 2:f9a0518b352a 81 ADC_ENABLE_ALL = 0x00
fblanc 2:f9a0518b352a 82 };
fblanc 2:f9a0518b352a 83 enum ADC_REG {
fblanc 2:f9a0518b352a 84 ADC_REG_Configuration_Register = 0x00,
fblanc 2:f9a0518b352a 85 ADC_REG_Interrupt_Status_Register = 0x01,
fblanc 2:f9a0518b352a 86 ADC_REG_Interrupt_Mask_Register = 0x03,
fblanc 2:f9a0518b352a 87 ADC_REG_Conversion_Rate_Register = 0x07,
fblanc 2:f9a0518b352a 88 ADC_REG_Channel_Disable_Register = 0x08,
fblanc 2:f9a0518b352a 89 ADC_REG_One_Shot_Register = 0x09,
fblanc 2:f9a0518b352a 90 ADC_REG_Deep_Shutdown_Register = 0x0A,
fblanc 2:f9a0518b352a 91 ADC_REG_Advanced_Configuration_Register = 0x0B,
fblanc 2:f9a0518b352a 92 ADC_REG_Busy_Status_Register = 0x0C,
fblanc 2:f9a0518b352a 93 ADC_REG_Channel_Readings_Registers = 0x20,
fblanc 2:f9a0518b352a 94 ADC_REG_Limit_Registers = 0x2A,
fblanc 2:f9a0518b352a 95 ADC_REG_Manufacturer_ID_Register = 0x3E,
fblanc 2:f9a0518b352a 96 ADC_REG_Revision_ID_Register = 0x3F
fblanc 2:f9a0518b352a 97 };
fblanc 3:816284ff2a09 98 /** ADC128D818 class.
fblanc 3:816284ff2a09 99 * Used for controlling a ADC128D818 adc connected via I2C.
fblanc 3:816284ff2a09 100 *
fblanc 3:816284ff2a09 101 * Example:
fblanc 3:816284ff2a09 102 * @code
fblanc 3:816284ff2a09 103 * #include "mbed.h"
fblanc 3:816284ff2a09 104 * #include "ADC128D818.h"
fblanc 3:816284ff2a09 105 * Serial pc(USBTX, USBRX);
fblanc 3:816284ff2a09 106 * ADC128D818 adc(p9,p10,p26);
fblanc 3:816284ff2a09 107 * AnalogOut dac(p18);
fblanc 3:816284ff2a09 108 * int main()
fblanc 3:816284ff2a09 109 * {
fblanc 3:816284ff2a09 110 * dac=0.5;
fblanc 3:816284ff2a09 111 * printf("helloword_ADC128D818\r\n");
fblanc 3:816284ff2a09 112 * wait_ms(100);
fblanc 3:816284ff2a09 113 * int err=adc.init(ADC_ADDRESS_LOW_LOW, ADC_MODE_0, ADC_VREF_INT, ADC_RATE_CONTINUOUS, ADC_ENABLE_TEMP & ADC_ENABLE_IN1, ADC_INT_TEMP);
fblanc 3:816284ff2a09 114 * switch (err) {
fblanc 3:816284ff2a09 115 * case -1:
fblanc 3:816284ff2a09 116 * printf("No Device\r\n");
fblanc 3:816284ff2a09 117 * break;
fblanc 3:816284ff2a09 118 * case -2:
fblanc 3:816284ff2a09 119 * printf("Busy\r\n");
fblanc 3:816284ff2a09 120 * break;
fblanc 3:816284ff2a09 121 * }
fblanc 3:816284ff2a09 122 * adc.init_limit(ADC_CHANNEL_IN0, 0x80, ADC_LIMIT_HIGH);
fblanc 3:816284ff2a09 123 * adc.init_limit(ADC_CHANNEL_IN1, 0xA6, ADC_LIMIT_HIGH);
fblanc 3:816284ff2a09 124 * adc.init_limit(ADC_CHANNEL_IN2, 0x80, ADC_LIMIT_HIGH);
fblanc 3:816284ff2a09 125 * adc.init_limit(ADC_CHANNEL_IN3, 0x80, ADC_LIMIT_HIGH);
fblanc 3:816284ff2a09 126 * adc.init_limit(ADC_CHANNEL_IN4, 0x80, ADC_LIMIT_HIGH);
fblanc 3:816284ff2a09 127 * adc.init_limit(ADC_CHANNEL_IN5, 0x80, ADC_LIMIT_HIGH);
fblanc 3:816284ff2a09 128 * adc.init_limit(ADC_CHANNEL_IN6, 0x80, ADC_LIMIT_HIGH);
fblanc 3:816284ff2a09 129 * adc.init_limit(ADC_CHANNEL_TEMP, 30, ADC_LIMIT_HIGH);
fblanc 3:816284ff2a09 130 * adc.init_limit(ADC_CHANNEL_TEMP, 29, ADC_LIMIT_LOW);
fblanc 3:816284ff2a09 131 * char reg;
fblanc 3:816284ff2a09 132 * reg=ADC_REG_Advanced_Configuration_Register;
fblanc 3:816284ff2a09 133 * printf("reg %02X=%02X\r\n",reg,adc.read_register(reg));
fblanc 3:816284ff2a09 134 * printf("reg %02X=%02X\r\n",0x2C,adc.read_channel(0x0C));
fblanc 3:816284ff2a09 135 * adc.start();
fblanc 3:816284ff2a09 136 * for(int i=0; i<1000; ++i) {
fblanc 3:816284ff2a09 137 * wait(1);
fblanc 3:816284ff2a09 138 * printf("ch0:%d : %d\r\n",i,adc.read_channel(ADC_CHANNEL_IN0));
fblanc 3:816284ff2a09 139 * for( char c=1; c<7 ;++c)
fblanc 3:816284ff2a09 140 * printf("ch%d:%d : %04X\r\n",c,i,adc.read_channel(c));
fblanc 3:816284ff2a09 141 *
fblanc 3:816284ff2a09 142 * printf("temp:%d : %f\r\n",i,(adc.read_channel(ADC_CHANNEL_TEMP)>>7)/2.0);
fblanc 3:816284ff2a09 143 * reg=0x01;
fblanc 3:816284ff2a09 144 * printf("reg %02X=%02X\r\n",reg,adc.read_register(reg));
fblanc 3:816284ff2a09 145 * }
fblanc 3:816284ff2a09 146 * }
fblanc 3:816284ff2a09 147 * @endcode
fblanc 3:816284ff2a09 148 */
fblanc 0:9cc68ef524da 149 class ADC128D818
fblanc 0:9cc68ef524da 150 {
fblanc 2:f9a0518b352a 151 protected:
fblanc 2:f9a0518b352a 152
fblanc 2:f9a0518b352a 153
fblanc 2:f9a0518b352a 154 enum Configuration_Register {
fblanc 0:9cc68ef524da 155 Configuration_Register_Start = 1<<0,
fblanc 0:9cc68ef524da 156 Configuration_Register_INT_Enable = 1<<1,
fblanc 0:9cc68ef524da 157 Configuration_Register_INT_Clear = 1<<3,
fblanc 0:9cc68ef524da 158 Configuration_Register_Initialization = 1<<7
fblanc 0:9cc68ef524da 159 };
fblanc 2:f9a0518b352a 160
fblanc 0:9cc68ef524da 161 enum Busy_Status_Register {
fblanc 0:9cc68ef524da 162 Busy_Status_Register_Busy = 1<<0,
fblanc 0:9cc68ef524da 163 Busy_Status_Register_Not_Ready = 1<<1
fblanc 0:9cc68ef524da 164 };
fblanc 2:f9a0518b352a 165
fblanc 0:9cc68ef524da 166 enum Advanced_Configuration_Register {
fblanc 0:9cc68ef524da 167 Advanced_Configuration_Register_External_Reference_Enable = 1<<0,
fblanc 0:9cc68ef524da 168 Advanced_Configuration_Register_Mode_Select_0 = 1<<1,
fblanc 0:9cc68ef524da 169 Advanced_Configuration_Register_Mode_Select_1 = 1<<2
fblanc 0:9cc68ef524da 170 };
fblanc 2:f9a0518b352a 171
fblanc 0:9cc68ef524da 172 enum Conversion_Rate_Register {
fblanc 0:9cc68ef524da 173 Conversion_Rate_Register_Rate_Register = 1<<0
fblanc 0:9cc68ef524da 174 };
fblanc 2:f9a0518b352a 175
fblanc 2:f9a0518b352a 176
fblanc 0:9cc68ef524da 177 private:
fblanc 0:9cc68ef524da 178 I2C _i2c;
fblanc 0:9cc68ef524da 179 char _data[2];
fblanc 0:9cc68ef524da 180 char _address;
fblanc 0:9cc68ef524da 181 char _mode;
fblanc 2:f9a0518b352a 182
fblanc 0:9cc68ef524da 183 public:
fblanc 2:f9a0518b352a 184 /**
fblanc 2:f9a0518b352a 185 * @brief Constructor.
fblanc 2:f9a0518b352a 186 *
fblanc 2:f9a0518b352a 187 * @param sda I2C
fblanc 2:f9a0518b352a 188 * @param scl I2C
fblanc 2:f9a0518b352a 189 * @param adc_int
fblanc 2:f9a0518b352a 190 */
fblanc 0:9cc68ef524da 191 ADC128D818(PinName sda, PinName scl, PinName adc_int );
fblanc 2:f9a0518b352a 192 /**
fblanc 2:f9a0518b352a 193 * @brief Destructor.
fblanc 2:f9a0518b352a 194 */
fblanc 0:9cc68ef524da 195 ~ADC128D818();
fblanc 0:9cc68ef524da 196
fblanc 0:9cc68ef524da 197 InterruptIn _Adc_Int;
fblanc 2:f9a0518b352a 198 /**
fblanc 2:f9a0518b352a 199 * @brief read_channel
fblanc 2:f9a0518b352a 200 * @param channel
fblanc 2:f9a0518b352a 201 * @return u32_data
fblanc 2:f9a0518b352a 202 * @date 02/09/2013
fblanc 2:f9a0518b352a 203 */
fblanc 0:9cc68ef524da 204 int read_channel(char channel);
fblanc 2:f9a0518b352a 205 /**
fblanc 2:f9a0518b352a 206 * @brief read_register
fblanc 2:f9a0518b352a 207 * @param Register
fblanc 2:f9a0518b352a 208 * @return u8_data
fblanc 2:f9a0518b352a 209 * @date 02/09/2013
fblanc 2:f9a0518b352a 210 */
fblanc 0:9cc68ef524da 211 char read_register(char Register);
fblanc 2:f9a0518b352a 212 /**
fblanc 2:f9a0518b352a 213 * @brief init
fblanc 2:f9a0518b352a 214 *
fblanc 2:f9a0518b352a 215 * @param address I2C (7bits)
fblanc 2:f9a0518b352a 216 ADC_ADDRESS_LOW_LOW
fblanc 2:f9a0518b352a 217 ADC_ADDRESS_LOW_MID
fblanc 2:f9a0518b352a 218 ADC_ADDRESS_LOW_HIGH
fblanc 2:f9a0518b352a 219 ADC_ADDRESS_MID_LOW
fblanc 2:f9a0518b352a 220 ADC_ADDRESS_MID_MID
fblanc 2:f9a0518b352a 221 ADC_ADDRESS_MID_HIGH
fblanc 2:f9a0518b352a 222 ADC_ADDRESS_HIGH_LOW
fblanc 2:f9a0518b352a 223 ADC_ADDRESS_HIGH_MID
fblanc 2:f9a0518b352a 224 ADC_ADDRESS_HIGH_HIGH
fblanc 2:f9a0518b352a 225 * @param mode :
fblanc 2:f9a0518b352a 226 ADC_MODE_0
fblanc 2:f9a0518b352a 227 ADC_MODE_1
fblanc 2:f9a0518b352a 228 ADC_MODE_2
fblanc 2:f9a0518b352a 229 ADC_MODE_3
fblanc 2:f9a0518b352a 230 * @param vref
fblanc 2:f9a0518b352a 231 ADC_VREF_INT
fblanc 2:f9a0518b352a 232 ADC_VREF_EXT
fblanc 2:f9a0518b352a 233 * @param rate
fblanc 2:f9a0518b352a 234 ADC_RATE_LOW_POWER
fblanc 2:f9a0518b352a 235 ADC_RATE_CONTINUOUS
fblanc 2:f9a0518b352a 236 * @param mask_channel
fblanc 2:f9a0518b352a 237 * @param mask_int
fblanc 2:f9a0518b352a 238 * @return error 0 OK, -1 NO DEVICE, -2 ADC is BUSY
fblanc 2:f9a0518b352a 239 * @date 02/09/2013
fblanc 2:f9a0518b352a 240 */
fblanc 0:9cc68ef524da 241 int init(char address, char mode, char vref, char rate, char mask_channel, char mask_int);
fblanc 2:f9a0518b352a 242 /**
fblanc 2:f9a0518b352a 243 * @brief init_limit
fblanc 2:f9a0518b352a 244 *
fblanc 2:f9a0518b352a 245 * @param limit
fblanc 2:f9a0518b352a 246 * @param high_low
fblanc 2:f9a0518b352a 247 ADC_LIMIT_HIGH
fblanc 2:f9a0518b352a 248 ADC_LIMIT_LOW
fblanc 2:f9a0518b352a 249 * @return error 0 OK
fblanc 2:f9a0518b352a 250 * @date 02/09/2013
fblanc 2:f9a0518b352a 251 */
fblanc 1:5f9dbbbc34c5 252 int init_limit(char channel, char limit, char high_low);
fblanc 2:f9a0518b352a 253 /**
fblanc 2:f9a0518b352a 254 * @brief start
fblanc 2:f9a0518b352a 255 * @date 02/09/2013
fblanc 2:f9a0518b352a 256 */
fblanc 0:9cc68ef524da 257 void start();
fblanc 2:f9a0518b352a 258 /**
fblanc 2:f9a0518b352a 259 * @brief stop
fblanc 2:f9a0518b352a 260 * @date 02/09/2013
fblanc 2:f9a0518b352a 261 */
fblanc 0:9cc68ef524da 262 void stop();
fblanc 0:9cc68ef524da 263 };
fblanc 0:9cc68ef524da 264
fblanc 0:9cc68ef524da 265 #endif
fblanc 0:9cc68ef524da 266