Fahad Mirza / MODSERIAL

MODSERIAL with support for more devices

Fork of MODSERIAL by Erik -

MACROS.h@27:9c93ce7cb9d8, 2013-07-11 (annotated)

Committer:
Sissors
Date:
Thu Jul 11 13:34:53 2013 +0000
Revision:
27:9c93ce7cb9d8
Parent:
20:59c74aaedda2
Child:
28:76793a84f9e5
v0.1 for KL25 support

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Who changed what in which revision?

UserRevisionLine numberNew contents of line
AjK 12:8c7394e2ae7f 1 /*
AjK 12:8c7394e2ae7f 2 Copyright (c) 2010 Andy Kirkham
AjK 12:8c7394e2ae7f 3
AjK 12:8c7394e2ae7f 4 Permission is hereby granted, free of charge, to any person obtaining a copy
AjK 12:8c7394e2ae7f 5 of this software and associated documentation files (the "Software"), to deal
AjK 12:8c7394e2ae7f 6 in the Software without restriction, including without limitation the rights
AjK 12:8c7394e2ae7f 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
AjK 12:8c7394e2ae7f 8 copies of the Software, and to permit persons to whom the Software is
AjK 12:8c7394e2ae7f 9 furnished to do so, subject to the following conditions:
AjK 12:8c7394e2ae7f 10
AjK 12:8c7394e2ae7f 11 The above copyright notice and this permission notice shall be included in
AjK 12:8c7394e2ae7f 12 all copies or substantial portions of the Software.
AjK 12:8c7394e2ae7f 13
AjK 12:8c7394e2ae7f 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
AjK 12:8c7394e2ae7f 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
AjK 12:8c7394e2ae7f 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AjK 12:8c7394e2ae7f 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
AjK 12:8c7394e2ae7f 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
AjK 12:8c7394e2ae7f 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
AjK 12:8c7394e2ae7f 20 THE SOFTWARE.
AjK 12:8c7394e2ae7f 21 */
AjK 12:8c7394e2ae7f 22
AjK 12:8c7394e2ae7f 23 #ifndef MODSERIAL_MACROS_H
AjK 12:8c7394e2ae7f 24 #define MODSERIAL_MACROS_H
AjK 12:8c7394e2ae7f 25
AjK 12:8c7394e2ae7f 26
AjK 12:8c7394e2ae7f 27 #define MODSERIAL_TX_BUFFER_EMPTY (buffer_count[TxIrq]==0)
AjK 12:8c7394e2ae7f 28 #define MODSERIAL_RX_BUFFER_EMPTY (buffer_count[RxIrq]==0)
AjK 12:8c7394e2ae7f 29 #define MODSERIAL_TX_BUFFER_FULL (buffer_count[TxIrq]==buffer_size[TxIrq])
AjK 12:8c7394e2ae7f 30 #define MODSERIAL_RX_BUFFER_FULL (buffer_count[RxIrq]==buffer_size[RxIrq])
AjK 12:8c7394e2ae7f 31
Sissors 27:9c93ce7cb9d8 32
Sissors 27:9c93ce7cb9d8 33 #ifdef TARGET_LPC1768
Sissors 27:9c93ce7cb9d8 34
Sissors 27:9c93ce7cb9d8 35 #define MODSERIAL_IRQ_REG ((LPC_UART_TypeDef*)_base)->IER
Sissors 27:9c93ce7cb9d8 36 #define DISABLE_TX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << 1)
Sissors 27:9c93ce7cb9d8 37 #define DISABLE_RX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << 0)
Sissors 27:9c93ce7cb9d8 38 #define ENABLE_TX_IRQ MODSERIAL_IRQ_REG |= (1UL << 1)
Sissors 27:9c93ce7cb9d8 39 #define ENABLE_RX_IRQ MODSERIAL_IRQ_REG |= (1UL << 0)
Sissors 27:9c93ce7cb9d8 40
Sissors 27:9c93ce7cb9d8 41 #define RESET_TX_FIFO ((LPC_UART_TypeDef*)_base)->FCR |= (1UL<<2)
Sissors 27:9c93ce7cb9d8 42 #define RESET_RX_FIFO ((LPC_UART_TypeDef*)_base)->FCR |= (1UL<<1)
Sissors 27:9c93ce7cb9d8 43 #define ENABLE_FIFO ((LPC_UART_TypeDef*)_base)->FCR = (1UL<<0) + (1UL<<1) + (1UL<<2)
Sissors 27:9c93ce7cb9d8 44
Sissors 27:9c93ce7cb9d8 45 #define MODSERIAL_READ_REG ((LPC_UART_TypeDef*)_base)->RBR
Sissors 27:9c93ce7cb9d8 46 #define MODSERIAL_WRITE_REG ((LPC_UART_TypeDef*)_base)->THR
Sissors 27:9c93ce7cb9d8 47 #define MODSERIAL_READABLE ((((LPC_UART_TypeDef*)_base)->LSR & (1UL<<0)) != 0)
Sissors 27:9c93ce7cb9d8 48 #define MODSERIAL_WRITABLE ((((LPC_UART_TypeDef*)_base)->LSR & (1UL<<5)) != 0)
Sissors 27:9c93ce7cb9d8 49
AjK 12:8c7394e2ae7f 50
AjK 12:8c7394e2ae7f 51 #endif
Sissors 27:9c93ce7cb9d8 52
Sissors 27:9c93ce7cb9d8 53 #ifdef TARGET_LPC11U24
Sissors 27:9c93ce7cb9d8 54
Sissors 27:9c93ce7cb9d8 55 #define MODSERIAL_IRQ_REG ((LPC_UART_TypeDef*)_base)->IER
Sissors 27:9c93ce7cb9d8 56 #define DISABLE_TX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << 1)
Sissors 27:9c93ce7cb9d8 57 #define DISABLE_RX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << 0)
Sissors 27:9c93ce7cb9d8 58 #define ENABLE_TX_IRQ MODSERIAL_IRQ_REG |= (1UL << 1)
Sissors 27:9c93ce7cb9d8 59 #define ENABLE_RX_IRQ MODSERIAL_IRQ_REG |= (1UL << 0)
Sissors 27:9c93ce7cb9d8 60
Sissors 27:9c93ce7cb9d8 61 #define RESET_TX_FIFO ((LPC_UART_TypeDef*)_base)->FCR |= (1UL<<2)
Sissors 27:9c93ce7cb9d8 62 #define RESET_RX_FIFO ((LPC_UART_TypeDef*)_base)->FCR |= (1UL<<1)
Sissors 27:9c93ce7cb9d8 63 #define ENABLE_FIFO ((LPC_UART_TypeDef*)_base)->FCR = (1UL<<0) + (1UL<<1) + (1UL<<2)
Sissors 27:9c93ce7cb9d8 64
Sissors 27:9c93ce7cb9d8 65 #define MODSERIAL_READ_REG ((LPC_UART_TypeDef*)_base)->RBR
Sissors 27:9c93ce7cb9d8 66 #define MODSERIAL_WRITE_REG ((LPC_UART_TypeDef*)_base)->THR
Sissors 27:9c93ce7cb9d8 67 #define MODSERIAL_READABLE ((((LPC_UART_TypeDef*)_base)->LSR & (1UL<<0)) != 0)
Sissors 27:9c93ce7cb9d8 68 #define MODSERIAL_WRITABLE ((((LPC_UART_TypeDef*)_base)->LSR & (1UL<<5)) != 0)
Sissors 27:9c93ce7cb9d8 69
Sissors 27:9c93ce7cb9d8 70 #endif
Sissors 27:9c93ce7cb9d8 71
Sissors 27:9c93ce7cb9d8 72 #ifdef TARGET_KL25Z
Sissors 27:9c93ce7cb9d8 73
Sissors 27:9c93ce7cb9d8 74 #define MODSERIAL_IRQ_REG ((UART_Type*)_base)->C2
Sissors 27:9c93ce7cb9d8 75 #define DISABLE_TX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << UART_C2_TIE_SHIFT)
Sissors 27:9c93ce7cb9d8 76 #define DISABLE_RX_IRQ MODSERIAL_IRQ_REG &= ~(1UL << UART_C2_RIE_SHIFT)
Sissors 27:9c93ce7cb9d8 77 #define ENABLE_TX_IRQ MODSERIAL_IRQ_REG |= (1UL << UART_C2_TIE_SHIFT)
Sissors 27:9c93ce7cb9d8 78 #define ENABLE_RX_IRQ MODSERIAL_IRQ_REG |= (1UL << UART_C2_RIE_SHIFT)
Sissors 27:9c93ce7cb9d8 79
Sissors 27:9c93ce7cb9d8 80 #define RESET_TX_FIFO while(0 == 1)
Sissors 27:9c93ce7cb9d8 81 #define RESET_RX_FIFO while(0 == 1)
Sissors 27:9c93ce7cb9d8 82 #define ENABLE_FIFO while(0 == 1)
Sissors 27:9c93ce7cb9d8 83
Sissors 27:9c93ce7cb9d8 84 #define MODSERIAL_READ_REG ((UART_Type*)_base)->D
Sissors 27:9c93ce7cb9d8 85 #define MODSERIAL_WRITE_REG ((UART_Type*)_base)->D
Sissors 27:9c93ce7cb9d8 86 #define MODSERIAL_READABLE ((((UART_Type*)_base)->S1 & (1UL<<5)) != 0)
Sissors 27:9c93ce7cb9d8 87 #define MODSERIAL_WRITABLE ((((UART_Type*)_base)->S1 & (1UL<<7)) != 0)
Sissors 27:9c93ce7cb9d8 88
Sissors 27:9c93ce7cb9d8 89 #endif
Sissors 27:9c93ce7cb9d8 90
Sissors 27:9c93ce7cb9d8 91 #endif