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TARGET_NUCLEO_F030R8/stm32f0xx_pwr.h@86:4f9a848d74c7, 2014-06-25 (annotated)

Committer:
erezi
Date:
Wed Jun 25 06:08:49 2014 +0000
Revision:
86:4f9a848d74c7
Parent:
81:7d30d6019079 
version_2.0

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emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f0xx_pwr.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.3.0
emilmont 77:869cf507173a 6 * @date 16-January-2014
emilmont 77:869cf507173a 7 * @brief This file contains all the functions prototypes for the PWR firmware
emilmont 77:869cf507173a 8 * library.
emilmont 77:869cf507173a 9 ******************************************************************************
emilmont 77:869cf507173a 10 * @attention
emilmont 77:869cf507173a 11 *
bogdanm 81:7d30d6019079 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 13 *
bogdanm 81:7d30d6019079 14 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 81:7d30d6019079 15 * are permitted provided that the following conditions are met:
bogdanm 81:7d30d6019079 16 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 81:7d30d6019079 17 * this list of conditions and the following disclaimer.
bogdanm 81:7d30d6019079 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 81:7d30d6019079 19 * this list of conditions and the following disclaimer in the documentation
bogdanm 81:7d30d6019079 20 * and/or other materials provided with the distribution.
bogdanm 81:7d30d6019079 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 81:7d30d6019079 22 * may be used to endorse or promote products derived from this software
bogdanm 81:7d30d6019079 23 * without specific prior written permission.
emilmont 77:869cf507173a 24 *
bogdanm 81:7d30d6019079 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 81:7d30d6019079 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 81:7d30d6019079 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 81:7d30d6019079 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 81:7d30d6019079 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 81:7d30d6019079 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 81:7d30d6019079 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 81:7d30d6019079 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 81:7d30d6019079 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 81:7d30d6019079 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 35 *
emilmont 77:869cf507173a 36 ******************************************************************************
emilmont 77:869cf507173a 37 */
emilmont 77:869cf507173a 38
emilmont 77:869cf507173a 39 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 40 #ifndef __STM32F0XX_PWR_H
emilmont 77:869cf507173a 41 #define __STM32F0XX_PWR_H
emilmont 77:869cf507173a 42
emilmont 77:869cf507173a 43 #ifdef __cplusplus
emilmont 77:869cf507173a 44 extern "C" {
emilmont 77:869cf507173a 45 #endif
emilmont 77:869cf507173a 46
emilmont 77:869cf507173a 47 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 48 #include "stm32f0xx.h"
emilmont 77:869cf507173a 49
emilmont 77:869cf507173a 50 /** @addtogroup STM32F0xx_StdPeriph_Driver
emilmont 77:869cf507173a 51 * @{
emilmont 77:869cf507173a 52 */
emilmont 77:869cf507173a 53
emilmont 77:869cf507173a 54 /** @addtogroup PWR
emilmont 77:869cf507173a 55 * @{
emilmont 77:869cf507173a 56 */
emilmont 77:869cf507173a 57
emilmont 77:869cf507173a 58 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 59
emilmont 77:869cf507173a 60 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 61
emilmont 77:869cf507173a 62 /** @defgroup PWR_Exported_Constants
emilmont 77:869cf507173a 63 * @{
emilmont 77:869cf507173a 64 */
emilmont 77:869cf507173a 65
emilmont 77:869cf507173a 66 /** @defgroup PWR_PVD_detection_level
emilmont 77:869cf507173a 67 * @brief This parameters are only applicable for STM32F051 and STM32F072 devices
emilmont 77:869cf507173a 68 * @{
emilmont 77:869cf507173a 69 */
emilmont 77:869cf507173a 70
emilmont 77:869cf507173a 71 #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
emilmont 77:869cf507173a 72 #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
emilmont 77:869cf507173a 73 #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
emilmont 77:869cf507173a 74 #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
emilmont 77:869cf507173a 75 #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
emilmont 77:869cf507173a 76 #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
emilmont 77:869cf507173a 77 #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
emilmont 77:869cf507173a 78 #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
emilmont 77:869cf507173a 79
emilmont 77:869cf507173a 80 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
emilmont 77:869cf507173a 81 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
emilmont 77:869cf507173a 82 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
emilmont 77:869cf507173a 83 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
emilmont 77:869cf507173a 84 /**
emilmont 77:869cf507173a 85 * @}
emilmont 77:869cf507173a 86 */
emilmont 77:869cf507173a 87
emilmont 77:869cf507173a 88 /** @defgroup PWR_WakeUp_Pins
emilmont 77:869cf507173a 89 * @{
emilmont 77:869cf507173a 90 */
emilmont 77:869cf507173a 91
emilmont 77:869cf507173a 92 #define PWR_WakeUpPin_1 PWR_CSR_EWUP1
emilmont 77:869cf507173a 93 #define PWR_WakeUpPin_2 PWR_CSR_EWUP2
emilmont 77:869cf507173a 94 #define PWR_WakeUpPin_3 PWR_CSR_EWUP3 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 95 #define PWR_WakeUpPin_4 PWR_CSR_EWUP4 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 96 #define PWR_WakeUpPin_5 PWR_CSR_EWUP5 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 97 #define PWR_WakeUpPin_6 PWR_CSR_EWUP6 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 98 #define PWR_WakeUpPin_7 PWR_CSR_EWUP7 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 99 #define PWR_WakeUpPin_8 PWR_CSR_EWUP8 /*!< only applicable for STM32F072 devices */
emilmont 77:869cf507173a 100 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \
emilmont 77:869cf507173a 101 ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \
emilmont 77:869cf507173a 102 ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \
emilmont 77:869cf507173a 103 ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8))
emilmont 77:869cf507173a 104 /**
emilmont 77:869cf507173a 105 * @}
emilmont 77:869cf507173a 106 */
emilmont 77:869cf507173a 107
emilmont 77:869cf507173a 108
emilmont 77:869cf507173a 109 /** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
emilmont 77:869cf507173a 110 * @{
emilmont 77:869cf507173a 111 */
emilmont 77:869cf507173a 112
emilmont 77:869cf507173a 113 #define PWR_Regulator_ON ((uint32_t)0x00000000)
emilmont 77:869cf507173a 114 #define PWR_Regulator_LowPower PWR_CR_LPSDSR
emilmont 77:869cf507173a 115 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
emilmont 77:869cf507173a 116 ((REGULATOR) == PWR_Regulator_LowPower))
emilmont 77:869cf507173a 117 /**
emilmont 77:869cf507173a 118 * @}
emilmont 77:869cf507173a 119 */
emilmont 77:869cf507173a 120
emilmont 77:869cf507173a 121 /** @defgroup PWR_SLEEP_mode_entry
emilmont 77:869cf507173a 122 * @{
emilmont 77:869cf507173a 123 */
emilmont 77:869cf507173a 124
emilmont 77:869cf507173a 125 #define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
emilmont 77:869cf507173a 126 #define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
emilmont 77:869cf507173a 127 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
emilmont 77:869cf507173a 128
emilmont 77:869cf507173a 129 /**
emilmont 77:869cf507173a 130 * @}
emilmont 77:869cf507173a 131 */
emilmont 77:869cf507173a 132
emilmont 77:869cf507173a 133 /** @defgroup PWR_STOP_mode_entry
emilmont 77:869cf507173a 134 * @{
emilmont 77:869cf507173a 135 */
emilmont 77:869cf507173a 136
emilmont 77:869cf507173a 137 #define PWR_STOPEntry_WFI ((uint8_t)0x01)
emilmont 77:869cf507173a 138 #define PWR_STOPEntry_WFE ((uint8_t)0x02)
emilmont 77:869cf507173a 139 #define PWR_STOPEntry_SLEEPONEXIT ((uint8_t)0x03)
emilmont 77:869cf507173a 140 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\
emilmont 77:869cf507173a 141 ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT))
emilmont 77:869cf507173a 142
emilmont 77:869cf507173a 143 /**
emilmont 77:869cf507173a 144 * @}
emilmont 77:869cf507173a 145 */
emilmont 77:869cf507173a 146
emilmont 77:869cf507173a 147 /** @defgroup PWR_Flag
emilmont 77:869cf507173a 148 * @{
emilmont 77:869cf507173a 149 */
emilmont 77:869cf507173a 150
emilmont 77:869cf507173a 151 #define PWR_FLAG_WU PWR_CSR_WUF
emilmont 77:869cf507173a 152 #define PWR_FLAG_SB PWR_CSR_SBF
emilmont 77:869cf507173a 153 #define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Not applicable for STM32F030 devices */
emilmont 77:869cf507173a 154 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
emilmont 77:869cf507173a 155
emilmont 77:869cf507173a 156 #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
emilmont 77:869cf507173a 157 ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
emilmont 77:869cf507173a 158
emilmont 77:869cf507173a 159 #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
emilmont 77:869cf507173a 160 /**
emilmont 77:869cf507173a 161 * @}
emilmont 77:869cf507173a 162 */
emilmont 77:869cf507173a 163
emilmont 77:869cf507173a 164 /**
emilmont 77:869cf507173a 165 * @}
emilmont 77:869cf507173a 166 */
emilmont 77:869cf507173a 167
emilmont 77:869cf507173a 168 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 169 /* Exported functions ------------------------------------------------------- */
emilmont 77:869cf507173a 170
emilmont 77:869cf507173a 171 /* Function used to set the PWR configuration to the default reset state ******/
emilmont 77:869cf507173a 172 void PWR_DeInit(void);
emilmont 77:869cf507173a 173
emilmont 77:869cf507173a 174 /* Backup Domain Access function **********************************************/
emilmont 77:869cf507173a 175 void PWR_BackupAccessCmd(FunctionalState NewState);
emilmont 77:869cf507173a 176
emilmont 77:869cf507173a 177 /* PVD configuration functions ************************************************/
emilmont 77:869cf507173a 178 void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); /*!< only applicable for STM32F051 and STM32F072 devices */
emilmont 77:869cf507173a 179 void PWR_PVDCmd(FunctionalState NewState); /*!< only applicable for STM32F051 and STM32F072 devices */
emilmont 77:869cf507173a 180
emilmont 77:869cf507173a 181 /* WakeUp pins configuration functions ****************************************/
emilmont 77:869cf507173a 182 void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
emilmont 77:869cf507173a 183
emilmont 77:869cf507173a 184 /* Low Power modes configuration functions ************************************/
emilmont 77:869cf507173a 185 void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
emilmont 77:869cf507173a 186 void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
emilmont 77:869cf507173a 187 void PWR_EnterSTANDBYMode(void);
emilmont 77:869cf507173a 188
emilmont 77:869cf507173a 189 /* Flags management functions *************************************************/
emilmont 77:869cf507173a 190 FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
emilmont 77:869cf507173a 191 void PWR_ClearFlag(uint32_t PWR_FLAG);
emilmont 77:869cf507173a 192
emilmont 77:869cf507173a 193 #ifdef __cplusplus
emilmont 77:869cf507173a 194 }
emilmont 77:869cf507173a 195 #endif
emilmont 77:869cf507173a 196
emilmont 77:869cf507173a 197 #endif /* __STM32F0XX_PWR_H */
emilmont 77:869cf507173a 198
emilmont 77:869cf507173a 199 /**
emilmont 77:869cf507173a 200 * @}
emilmont 77:869cf507173a 201 */
emilmont 77:869cf507173a 202
emilmont 77:869cf507173a 203 /**
emilmont 77:869cf507173a 204 * @}
emilmont 77:869cf507173a 205 */
emilmont 77:869cf507173a 206
emilmont 77:869cf507173a 207 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/