Emilio Monti / mbed-KL25Z

mbed libraries for KL25Z

Dependents:   FRDM_RGBLED

KL25Z/core_cmFunc.h@9:663789d7729f, 2013-02-18 (annotated)

Committer:
emilmont
Date:
Mon Feb 18 09:41:56 2013 +0000
Revision:
9:663789d7729f
Parent:
2:e9a661555b58 
Update mbed-KL25Z to latest build

Who changed what in which revision?

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emilmont 2:e9a661555b58 1 /**************************************************************************//**
emilmont 2:e9a661555b58 2 * @file core_cmFunc.h
emilmont 2:e9a661555b58 3 * @brief CMSIS Cortex-M Core Function Access Header File
emilmont 2:e9a661555b58 4 * @version V3.02
emilmont 2:e9a661555b58 5 * @date 24. May 2012
emilmont 2:e9a661555b58 6 *
emilmont 2:e9a661555b58 7 * @note
emilmont 2:e9a661555b58 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 2:e9a661555b58 9 *
emilmont 2:e9a661555b58 10 * @par
emilmont 2:e9a661555b58 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emilmont 2:e9a661555b58 12 * processor based microcontrollers. This file can be freely distributed
emilmont 2:e9a661555b58 13 * within development tools that are supporting such ARM based processors.
emilmont 2:e9a661555b58 14 *
emilmont 2:e9a661555b58 15 * @par
emilmont 2:e9a661555b58 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 2:e9a661555b58 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 2:e9a661555b58 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 2:e9a661555b58 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 2:e9a661555b58 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 2:e9a661555b58 21 *
emilmont 2:e9a661555b58 22 ******************************************************************************/
emilmont 2:e9a661555b58 23
emilmont 2:e9a661555b58 24 #ifndef __CORE_CMFUNC_H
emilmont 2:e9a661555b58 25 #define __CORE_CMFUNC_H
emilmont 2:e9a661555b58 26
emilmont 2:e9a661555b58 27
emilmont 2:e9a661555b58 28 /* ########################### Core Function Access ########################### */
emilmont 2:e9a661555b58 29 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 2:e9a661555b58 30 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
emilmont 2:e9a661555b58 31 @{
emilmont 2:e9a661555b58 32 */
emilmont 2:e9a661555b58 33
emilmont 2:e9a661555b58 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 2:e9a661555b58 35 /* ARM armcc specific functions */
emilmont 2:e9a661555b58 36
emilmont 2:e9a661555b58 37 #if (__ARMCC_VERSION < 400677)
emilmont 2:e9a661555b58 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 2:e9a661555b58 39 #endif
emilmont 2:e9a661555b58 40
emilmont 2:e9a661555b58 41 /* intrinsic void __enable_irq(); */
emilmont 2:e9a661555b58 42 /* intrinsic void __disable_irq(); */
emilmont 2:e9a661555b58 43
emilmont 2:e9a661555b58 44 /** \brief Get Control Register
emilmont 2:e9a661555b58 45
emilmont 2:e9a661555b58 46 This function returns the content of the Control Register.
emilmont 2:e9a661555b58 47
emilmont 2:e9a661555b58 48 \return Control Register value
emilmont 2:e9a661555b58 49 */
emilmont 2:e9a661555b58 50 __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 2:e9a661555b58 51 {
emilmont 2:e9a661555b58 52 register uint32_t __regControl __ASM("control");
emilmont 2:e9a661555b58 53 return(__regControl);
emilmont 2:e9a661555b58 54 }
emilmont 2:e9a661555b58 55
emilmont 2:e9a661555b58 56
emilmont 2:e9a661555b58 57 /** \brief Set Control Register
emilmont 2:e9a661555b58 58
emilmont 2:e9a661555b58 59 This function writes the given value to the Control Register.
emilmont 2:e9a661555b58 60
emilmont 2:e9a661555b58 61 \param [in] control Control Register value to set
emilmont 2:e9a661555b58 62 */
emilmont 2:e9a661555b58 63 __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 2:e9a661555b58 64 {
emilmont 2:e9a661555b58 65 register uint32_t __regControl __ASM("control");
emilmont 2:e9a661555b58 66 __regControl = control;
emilmont 2:e9a661555b58 67 }
emilmont 2:e9a661555b58 68
emilmont 2:e9a661555b58 69
emilmont 2:e9a661555b58 70 /** \brief Get IPSR Register
emilmont 2:e9a661555b58 71
emilmont 2:e9a661555b58 72 This function returns the content of the IPSR Register.
emilmont 2:e9a661555b58 73
emilmont 2:e9a661555b58 74 \return IPSR Register value
emilmont 2:e9a661555b58 75 */
emilmont 2:e9a661555b58 76 __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 2:e9a661555b58 77 {
emilmont 2:e9a661555b58 78 register uint32_t __regIPSR __ASM("ipsr");
emilmont 2:e9a661555b58 79 return(__regIPSR);
emilmont 2:e9a661555b58 80 }
emilmont 2:e9a661555b58 81
emilmont 2:e9a661555b58 82
emilmont 2:e9a661555b58 83 /** \brief Get APSR Register
emilmont 2:e9a661555b58 84
emilmont 2:e9a661555b58 85 This function returns the content of the APSR Register.
emilmont 2:e9a661555b58 86
emilmont 2:e9a661555b58 87 \return APSR Register value
emilmont 2:e9a661555b58 88 */
emilmont 2:e9a661555b58 89 __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 2:e9a661555b58 90 {
emilmont 2:e9a661555b58 91 register uint32_t __regAPSR __ASM("apsr");
emilmont 2:e9a661555b58 92 return(__regAPSR);
emilmont 2:e9a661555b58 93 }
emilmont 2:e9a661555b58 94
emilmont 2:e9a661555b58 95
emilmont 2:e9a661555b58 96 /** \brief Get xPSR Register
emilmont 2:e9a661555b58 97
emilmont 2:e9a661555b58 98 This function returns the content of the xPSR Register.
emilmont 2:e9a661555b58 99
emilmont 2:e9a661555b58 100 \return xPSR Register value
emilmont 2:e9a661555b58 101 */
emilmont 2:e9a661555b58 102 __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 2:e9a661555b58 103 {
emilmont 2:e9a661555b58 104 register uint32_t __regXPSR __ASM("xpsr");
emilmont 2:e9a661555b58 105 return(__regXPSR);
emilmont 2:e9a661555b58 106 }
emilmont 2:e9a661555b58 107
emilmont 2:e9a661555b58 108
emilmont 2:e9a661555b58 109 /** \brief Get Process Stack Pointer
emilmont 2:e9a661555b58 110
emilmont 2:e9a661555b58 111 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 2:e9a661555b58 112
emilmont 2:e9a661555b58 113 \return PSP Register value
emilmont 2:e9a661555b58 114 */
emilmont 2:e9a661555b58 115 __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 2:e9a661555b58 116 {
emilmont 2:e9a661555b58 117 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 2:e9a661555b58 118 return(__regProcessStackPointer);
emilmont 2:e9a661555b58 119 }
emilmont 2:e9a661555b58 120
emilmont 2:e9a661555b58 121
emilmont 2:e9a661555b58 122 /** \brief Set Process Stack Pointer
emilmont 2:e9a661555b58 123
emilmont 2:e9a661555b58 124 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 2:e9a661555b58 125
emilmont 2:e9a661555b58 126 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 2:e9a661555b58 127 */
emilmont 2:e9a661555b58 128 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 2:e9a661555b58 129 {
emilmont 2:e9a661555b58 130 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 2:e9a661555b58 131 __regProcessStackPointer = topOfProcStack;
emilmont 2:e9a661555b58 132 }
emilmont 2:e9a661555b58 133
emilmont 2:e9a661555b58 134
emilmont 2:e9a661555b58 135 /** \brief Get Main Stack Pointer
emilmont 2:e9a661555b58 136
emilmont 2:e9a661555b58 137 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 2:e9a661555b58 138
emilmont 2:e9a661555b58 139 \return MSP Register value
emilmont 2:e9a661555b58 140 */
emilmont 2:e9a661555b58 141 __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 2:e9a661555b58 142 {
emilmont 2:e9a661555b58 143 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 2:e9a661555b58 144 return(__regMainStackPointer);
emilmont 2:e9a661555b58 145 }
emilmont 2:e9a661555b58 146
emilmont 2:e9a661555b58 147
emilmont 2:e9a661555b58 148 /** \brief Set Main Stack Pointer
emilmont 2:e9a661555b58 149
emilmont 2:e9a661555b58 150 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 2:e9a661555b58 151
emilmont 2:e9a661555b58 152 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 2:e9a661555b58 153 */
emilmont 2:e9a661555b58 154 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 2:e9a661555b58 155 {
emilmont 2:e9a661555b58 156 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 2:e9a661555b58 157 __regMainStackPointer = topOfMainStack;
emilmont 2:e9a661555b58 158 }
emilmont 2:e9a661555b58 159
emilmont 2:e9a661555b58 160
emilmont 2:e9a661555b58 161 /** \brief Get Priority Mask
emilmont 2:e9a661555b58 162
emilmont 2:e9a661555b58 163 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 2:e9a661555b58 164
emilmont 2:e9a661555b58 165 \return Priority Mask value
emilmont 2:e9a661555b58 166 */
emilmont 2:e9a661555b58 167 __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 2:e9a661555b58 168 {
emilmont 2:e9a661555b58 169 register uint32_t __regPriMask __ASM("primask");
emilmont 2:e9a661555b58 170 return(__regPriMask);
emilmont 2:e9a661555b58 171 }
emilmont 2:e9a661555b58 172
emilmont 2:e9a661555b58 173
emilmont 2:e9a661555b58 174 /** \brief Set Priority Mask
emilmont 2:e9a661555b58 175
emilmont 2:e9a661555b58 176 This function assigns the given value to the Priority Mask Register.
emilmont 2:e9a661555b58 177
emilmont 2:e9a661555b58 178 \param [in] priMask Priority Mask
emilmont 2:e9a661555b58 179 */
emilmont 2:e9a661555b58 180 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 2:e9a661555b58 181 {
emilmont 2:e9a661555b58 182 register uint32_t __regPriMask __ASM("primask");
emilmont 2:e9a661555b58 183 __regPriMask = (priMask);
emilmont 2:e9a661555b58 184 }
emilmont 2:e9a661555b58 185
emilmont 2:e9a661555b58 186
emilmont 2:e9a661555b58 187 #if (__CORTEX_M >= 0x03)
emilmont 2:e9a661555b58 188
emilmont 2:e9a661555b58 189 /** \brief Enable FIQ
emilmont 2:e9a661555b58 190
emilmont 2:e9a661555b58 191 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 2:e9a661555b58 192 Can only be executed in Privileged modes.
emilmont 2:e9a661555b58 193 */
emilmont 2:e9a661555b58 194 #define __enable_fault_irq __enable_fiq
emilmont 2:e9a661555b58 195
emilmont 2:e9a661555b58 196
emilmont 2:e9a661555b58 197 /** \brief Disable FIQ
emilmont 2:e9a661555b58 198
emilmont 2:e9a661555b58 199 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 2:e9a661555b58 200 Can only be executed in Privileged modes.
emilmont 2:e9a661555b58 201 */
emilmont 2:e9a661555b58 202 #define __disable_fault_irq __disable_fiq
emilmont 2:e9a661555b58 203
emilmont 2:e9a661555b58 204
emilmont 2:e9a661555b58 205 /** \brief Get Base Priority
emilmont 2:e9a661555b58 206
emilmont 2:e9a661555b58 207 This function returns the current value of the Base Priority register.
emilmont 2:e9a661555b58 208
emilmont 2:e9a661555b58 209 \return Base Priority register value
emilmont 2:e9a661555b58 210 */
emilmont 2:e9a661555b58 211 __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 2:e9a661555b58 212 {
emilmont 2:e9a661555b58 213 register uint32_t __regBasePri __ASM("basepri");
emilmont 2:e9a661555b58 214 return(__regBasePri);
emilmont 2:e9a661555b58 215 }
emilmont 2:e9a661555b58 216
emilmont 2:e9a661555b58 217
emilmont 2:e9a661555b58 218 /** \brief Set Base Priority
emilmont 2:e9a661555b58 219
emilmont 2:e9a661555b58 220 This function assigns the given value to the Base Priority register.
emilmont 2:e9a661555b58 221
emilmont 2:e9a661555b58 222 \param [in] basePri Base Priority value to set
emilmont 2:e9a661555b58 223 */
emilmont 2:e9a661555b58 224 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
emilmont 2:e9a661555b58 225 {
emilmont 2:e9a661555b58 226 register uint32_t __regBasePri __ASM("basepri");
emilmont 2:e9a661555b58 227 __regBasePri = (basePri & 0xff);
emilmont 2:e9a661555b58 228 }
emilmont 2:e9a661555b58 229
emilmont 2:e9a661555b58 230
emilmont 2:e9a661555b58 231 /** \brief Get Fault Mask
emilmont 2:e9a661555b58 232
emilmont 2:e9a661555b58 233 This function returns the current value of the Fault Mask register.
emilmont 2:e9a661555b58 234
emilmont 2:e9a661555b58 235 \return Fault Mask register value
emilmont 2:e9a661555b58 236 */
emilmont 2:e9a661555b58 237 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 2:e9a661555b58 238 {
emilmont 2:e9a661555b58 239 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 2:e9a661555b58 240 return(__regFaultMask);
emilmont 2:e9a661555b58 241 }
emilmont 2:e9a661555b58 242
emilmont 2:e9a661555b58 243
emilmont 2:e9a661555b58 244 /** \brief Set Fault Mask
emilmont 2:e9a661555b58 245
emilmont 2:e9a661555b58 246 This function assigns the given value to the Fault Mask register.
emilmont 2:e9a661555b58 247
emilmont 2:e9a661555b58 248 \param [in] faultMask Fault Mask value to set
emilmont 2:e9a661555b58 249 */
emilmont 2:e9a661555b58 250 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 2:e9a661555b58 251 {
emilmont 2:e9a661555b58 252 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 2:e9a661555b58 253 __regFaultMask = (faultMask & (uint32_t)1);
emilmont 2:e9a661555b58 254 }
emilmont 2:e9a661555b58 255
emilmont 2:e9a661555b58 256 #endif /* (__CORTEX_M >= 0x03) */
emilmont 2:e9a661555b58 257
emilmont 2:e9a661555b58 258
emilmont 2:e9a661555b58 259 #if (__CORTEX_M == 0x04)
emilmont 2:e9a661555b58 260
emilmont 2:e9a661555b58 261 /** \brief Get FPSCR
emilmont 2:e9a661555b58 262
emilmont 2:e9a661555b58 263 This function returns the current value of the Floating Point Status/Control register.
emilmont 2:e9a661555b58 264
emilmont 2:e9a661555b58 265 \return Floating Point Status/Control register value
emilmont 2:e9a661555b58 266 */
emilmont 2:e9a661555b58 267 __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 2:e9a661555b58 268 {
emilmont 2:e9a661555b58 269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 2:e9a661555b58 270 register uint32_t __regfpscr __ASM("fpscr");
emilmont 2:e9a661555b58 271 return(__regfpscr);
emilmont 2:e9a661555b58 272 #else
emilmont 2:e9a661555b58 273 return(0);
emilmont 2:e9a661555b58 274 #endif
emilmont 2:e9a661555b58 275 }
emilmont 2:e9a661555b58 276
emilmont 2:e9a661555b58 277
emilmont 2:e9a661555b58 278 /** \brief Set FPSCR
emilmont 2:e9a661555b58 279
emilmont 2:e9a661555b58 280 This function assigns the given value to the Floating Point Status/Control register.
emilmont 2:e9a661555b58 281
emilmont 2:e9a661555b58 282 \param [in] fpscr Floating Point Status/Control value to set
emilmont 2:e9a661555b58 283 */
emilmont 2:e9a661555b58 284 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 2:e9a661555b58 285 {
emilmont 2:e9a661555b58 286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 2:e9a661555b58 287 register uint32_t __regfpscr __ASM("fpscr");
emilmont 2:e9a661555b58 288 __regfpscr = (fpscr);
emilmont 2:e9a661555b58 289 #endif
emilmont 2:e9a661555b58 290 }
emilmont 2:e9a661555b58 291
emilmont 2:e9a661555b58 292 #endif /* (__CORTEX_M == 0x04) */
emilmont 2:e9a661555b58 293
emilmont 2:e9a661555b58 294
emilmont 2:e9a661555b58 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 2:e9a661555b58 296 /* IAR iccarm specific functions */
emilmont 2:e9a661555b58 297
emilmont 2:e9a661555b58 298 #include <cmsis_iar.h>
emilmont 2:e9a661555b58 299
emilmont 2:e9a661555b58 300
emilmont 2:e9a661555b58 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emilmont 2:e9a661555b58 302 /* TI CCS specific functions */
emilmont 2:e9a661555b58 303
emilmont 2:e9a661555b58 304 #include <cmsis_ccs.h>
emilmont 2:e9a661555b58 305
emilmont 2:e9a661555b58 306
emilmont 2:e9a661555b58 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 2:e9a661555b58 308 /* GNU gcc specific functions */
emilmont 2:e9a661555b58 309
emilmont 2:e9a661555b58 310 /** \brief Enable IRQ Interrupts
emilmont 2:e9a661555b58 311
emilmont 2:e9a661555b58 312 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 2:e9a661555b58 313 Can only be executed in Privileged modes.
emilmont 2:e9a661555b58 314 */
emilmont 2:e9a661555b58 315 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
emilmont 2:e9a661555b58 316 {
emilmont 2:e9a661555b58 317 __ASM volatile ("cpsie i" : : : "memory");
emilmont 2:e9a661555b58 318 }
emilmont 2:e9a661555b58 319
emilmont 2:e9a661555b58 320
emilmont 2:e9a661555b58 321 /** \brief Disable IRQ Interrupts
emilmont 2:e9a661555b58 322
emilmont 2:e9a661555b58 323 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 2:e9a661555b58 324 Can only be executed in Privileged modes.
emilmont 2:e9a661555b58 325 */
emilmont 2:e9a661555b58 326 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
emilmont 2:e9a661555b58 327 {
emilmont 2:e9a661555b58 328 __ASM volatile ("cpsid i" : : : "memory");
emilmont 2:e9a661555b58 329 }
emilmont 2:e9a661555b58 330
emilmont 2:e9a661555b58 331
emilmont 2:e9a661555b58 332 /** \brief Get Control Register
emilmont 2:e9a661555b58 333
emilmont 2:e9a661555b58 334 This function returns the content of the Control Register.
emilmont 2:e9a661555b58 335
emilmont 2:e9a661555b58 336 \return Control Register value
emilmont 2:e9a661555b58 337 */
emilmont 2:e9a661555b58 338 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 2:e9a661555b58 339 {
emilmont 2:e9a661555b58 340 uint32_t result;
emilmont 2:e9a661555b58 341
emilmont 2:e9a661555b58 342 __ASM volatile ("MRS %0, control" : "=r" (result) );
emilmont 2:e9a661555b58 343 return(result);
emilmont 2:e9a661555b58 344 }
emilmont 2:e9a661555b58 345
emilmont 2:e9a661555b58 346
emilmont 2:e9a661555b58 347 /** \brief Set Control Register
emilmont 2:e9a661555b58 348
emilmont 2:e9a661555b58 349 This function writes the given value to the Control Register.
emilmont 2:e9a661555b58 350
emilmont 2:e9a661555b58 351 \param [in] control Control Register value to set
emilmont 2:e9a661555b58 352 */
emilmont 2:e9a661555b58 353 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 2:e9a661555b58 354 {
emilmont 2:e9a661555b58 355 __ASM volatile ("MSR control, %0" : : "r" (control) );
emilmont 2:e9a661555b58 356 }
emilmont 2:e9a661555b58 357
emilmont 2:e9a661555b58 358
emilmont 2:e9a661555b58 359 /** \brief Get IPSR Register
emilmont 2:e9a661555b58 360
emilmont 2:e9a661555b58 361 This function returns the content of the IPSR Register.
emilmont 2:e9a661555b58 362
emilmont 2:e9a661555b58 363 \return IPSR Register value
emilmont 2:e9a661555b58 364 */
emilmont 2:e9a661555b58 365 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 2:e9a661555b58 366 {
emilmont 2:e9a661555b58 367 uint32_t result;
emilmont 2:e9a661555b58 368
emilmont 2:e9a661555b58 369 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
emilmont 2:e9a661555b58 370 return(result);
emilmont 2:e9a661555b58 371 }
emilmont 2:e9a661555b58 372
emilmont 2:e9a661555b58 373
emilmont 2:e9a661555b58 374 /** \brief Get APSR Register
emilmont 2:e9a661555b58 375
emilmont 2:e9a661555b58 376 This function returns the content of the APSR Register.
emilmont 2:e9a661555b58 377
emilmont 2:e9a661555b58 378 \return APSR Register value
emilmont 2:e9a661555b58 379 */
emilmont 2:e9a661555b58 380 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 2:e9a661555b58 381 {
emilmont 2:e9a661555b58 382 uint32_t result;
emilmont 2:e9a661555b58 383
emilmont 2:e9a661555b58 384 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
emilmont 2:e9a661555b58 385 return(result);
emilmont 2:e9a661555b58 386 }
emilmont 2:e9a661555b58 387
emilmont 2:e9a661555b58 388
emilmont 2:e9a661555b58 389 /** \brief Get xPSR Register
emilmont 2:e9a661555b58 390
emilmont 2:e9a661555b58 391 This function returns the content of the xPSR Register.
emilmont 2:e9a661555b58 392
emilmont 2:e9a661555b58 393 \return xPSR Register value
emilmont 2:e9a661555b58 394 */
emilmont 2:e9a661555b58 395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 2:e9a661555b58 396 {
emilmont 2:e9a661555b58 397 uint32_t result;
emilmont 2:e9a661555b58 398
emilmont 2:e9a661555b58 399 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
emilmont 2:e9a661555b58 400 return(result);
emilmont 2:e9a661555b58 401 }
emilmont 2:e9a661555b58 402
emilmont 2:e9a661555b58 403
emilmont 2:e9a661555b58 404 /** \brief Get Process Stack Pointer
emilmont 2:e9a661555b58 405
emilmont 2:e9a661555b58 406 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 2:e9a661555b58 407
emilmont 2:e9a661555b58 408 \return PSP Register value
emilmont 2:e9a661555b58 409 */
emilmont 2:e9a661555b58 410 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 2:e9a661555b58 411 {
emilmont 2:e9a661555b58 412 register uint32_t result;
emilmont 2:e9a661555b58 413
emilmont 2:e9a661555b58 414 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
emilmont 2:e9a661555b58 415 return(result);
emilmont 2:e9a661555b58 416 }
emilmont 2:e9a661555b58 417
emilmont 2:e9a661555b58 418
emilmont 2:e9a661555b58 419 /** \brief Set Process Stack Pointer
emilmont 2:e9a661555b58 420
emilmont 2:e9a661555b58 421 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 2:e9a661555b58 422
emilmont 2:e9a661555b58 423 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 2:e9a661555b58 424 */
emilmont 2:e9a661555b58 425 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 2:e9a661555b58 426 {
emilmont 2:e9a661555b58 427 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
emilmont 2:e9a661555b58 428 }
emilmont 2:e9a661555b58 429
emilmont 2:e9a661555b58 430
emilmont 2:e9a661555b58 431 /** \brief Get Main Stack Pointer
emilmont 2:e9a661555b58 432
emilmont 2:e9a661555b58 433 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 2:e9a661555b58 434
emilmont 2:e9a661555b58 435 \return MSP Register value
emilmont 2:e9a661555b58 436 */
emilmont 2:e9a661555b58 437 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 2:e9a661555b58 438 {
emilmont 2:e9a661555b58 439 register uint32_t result;
emilmont 2:e9a661555b58 440
emilmont 2:e9a661555b58 441 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
emilmont 2:e9a661555b58 442 return(result);
emilmont 2:e9a661555b58 443 }
emilmont 2:e9a661555b58 444
emilmont 2:e9a661555b58 445
emilmont 2:e9a661555b58 446 /** \brief Set Main Stack Pointer
emilmont 2:e9a661555b58 447
emilmont 2:e9a661555b58 448 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 2:e9a661555b58 449
emilmont 2:e9a661555b58 450 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 2:e9a661555b58 451 */
emilmont 2:e9a661555b58 452 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 2:e9a661555b58 453 {
emilmont 2:e9a661555b58 454 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
emilmont 2:e9a661555b58 455 }
emilmont 2:e9a661555b58 456
emilmont 2:e9a661555b58 457
emilmont 2:e9a661555b58 458 /** \brief Get Priority Mask
emilmont 2:e9a661555b58 459
emilmont 2:e9a661555b58 460 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 2:e9a661555b58 461
emilmont 2:e9a661555b58 462 \return Priority Mask value
emilmont 2:e9a661555b58 463 */
emilmont 2:e9a661555b58 464 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 2:e9a661555b58 465 {
emilmont 2:e9a661555b58 466 uint32_t result;
emilmont 2:e9a661555b58 467
emilmont 2:e9a661555b58 468 __ASM volatile ("MRS %0, primask" : "=r" (result) );
emilmont 2:e9a661555b58 469 return(result);
emilmont 2:e9a661555b58 470 }
emilmont 2:e9a661555b58 471
emilmont 2:e9a661555b58 472
emilmont 2:e9a661555b58 473 /** \brief Set Priority Mask
emilmont 2:e9a661555b58 474
emilmont 2:e9a661555b58 475 This function assigns the given value to the Priority Mask Register.
emilmont 2:e9a661555b58 476
emilmont 2:e9a661555b58 477 \param [in] priMask Priority Mask
emilmont 2:e9a661555b58 478 */
emilmont 2:e9a661555b58 479 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 2:e9a661555b58 480 {
emilmont 2:e9a661555b58 481 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
emilmont 2:e9a661555b58 482 }
emilmont 2:e9a661555b58 483
emilmont 2:e9a661555b58 484
emilmont 2:e9a661555b58 485 #if (__CORTEX_M >= 0x03)
emilmont 2:e9a661555b58 486
emilmont 2:e9a661555b58 487 /** \brief Enable FIQ
emilmont 2:e9a661555b58 488
emilmont 2:e9a661555b58 489 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 2:e9a661555b58 490 Can only be executed in Privileged modes.
emilmont 2:e9a661555b58 491 */
emilmont 2:e9a661555b58 492 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
emilmont 2:e9a661555b58 493 {
emilmont 2:e9a661555b58 494 __ASM volatile ("cpsie f" : : : "memory");
emilmont 2:e9a661555b58 495 }
emilmont 2:e9a661555b58 496
emilmont 2:e9a661555b58 497
emilmont 2:e9a661555b58 498 /** \brief Disable FIQ
emilmont 2:e9a661555b58 499
emilmont 2:e9a661555b58 500 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 2:e9a661555b58 501 Can only be executed in Privileged modes.
emilmont 2:e9a661555b58 502 */
emilmont 2:e9a661555b58 503 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
emilmont 2:e9a661555b58 504 {
emilmont 2:e9a661555b58 505 __ASM volatile ("cpsid f" : : : "memory");
emilmont 2:e9a661555b58 506 }
emilmont 2:e9a661555b58 507
emilmont 2:e9a661555b58 508
emilmont 2:e9a661555b58 509 /** \brief Get Base Priority
emilmont 2:e9a661555b58 510
emilmont 2:e9a661555b58 511 This function returns the current value of the Base Priority register.
emilmont 2:e9a661555b58 512
emilmont 2:e9a661555b58 513 \return Base Priority register value
emilmont 2:e9a661555b58 514 */
emilmont 2:e9a661555b58 515 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 2:e9a661555b58 516 {
emilmont 2:e9a661555b58 517 uint32_t result;
emilmont 2:e9a661555b58 518
emilmont 2:e9a661555b58 519 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
emilmont 2:e9a661555b58 520 return(result);
emilmont 2:e9a661555b58 521 }
emilmont 2:e9a661555b58 522
emilmont 2:e9a661555b58 523
emilmont 2:e9a661555b58 524 /** \brief Set Base Priority
emilmont 2:e9a661555b58 525
emilmont 2:e9a661555b58 526 This function assigns the given value to the Base Priority register.
emilmont 2:e9a661555b58 527
emilmont 2:e9a661555b58 528 \param [in] basePri Base Priority value to set
emilmont 2:e9a661555b58 529 */
emilmont 2:e9a661555b58 530 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
emilmont 2:e9a661555b58 531 {
emilmont 2:e9a661555b58 532 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
emilmont 2:e9a661555b58 533 }
emilmont 2:e9a661555b58 534
emilmont 2:e9a661555b58 535
emilmont 2:e9a661555b58 536 /** \brief Get Fault Mask
emilmont 2:e9a661555b58 537
emilmont 2:e9a661555b58 538 This function returns the current value of the Fault Mask register.
emilmont 2:e9a661555b58 539
emilmont 2:e9a661555b58 540 \return Fault Mask register value
emilmont 2:e9a661555b58 541 */
emilmont 2:e9a661555b58 542 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 2:e9a661555b58 543 {
emilmont 2:e9a661555b58 544 uint32_t result;
emilmont 2:e9a661555b58 545
emilmont 2:e9a661555b58 546 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
emilmont 2:e9a661555b58 547 return(result);
emilmont 2:e9a661555b58 548 }
emilmont 2:e9a661555b58 549
emilmont 2:e9a661555b58 550
emilmont 2:e9a661555b58 551 /** \brief Set Fault Mask
emilmont 2:e9a661555b58 552
emilmont 2:e9a661555b58 553 This function assigns the given value to the Fault Mask register.
emilmont 2:e9a661555b58 554
emilmont 2:e9a661555b58 555 \param [in] faultMask Fault Mask value to set
emilmont 2:e9a661555b58 556 */
emilmont 2:e9a661555b58 557 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 2:e9a661555b58 558 {
emilmont 2:e9a661555b58 559 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
emilmont 2:e9a661555b58 560 }
emilmont 2:e9a661555b58 561
emilmont 2:e9a661555b58 562 #endif /* (__CORTEX_M >= 0x03) */
emilmont 2:e9a661555b58 563
emilmont 2:e9a661555b58 564
emilmont 2:e9a661555b58 565 #if (__CORTEX_M == 0x04)
emilmont 2:e9a661555b58 566
emilmont 2:e9a661555b58 567 /** \brief Get FPSCR
emilmont 2:e9a661555b58 568
emilmont 2:e9a661555b58 569 This function returns the current value of the Floating Point Status/Control register.
emilmont 2:e9a661555b58 570
emilmont 2:e9a661555b58 571 \return Floating Point Status/Control register value
emilmont 2:e9a661555b58 572 */
emilmont 2:e9a661555b58 573 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 2:e9a661555b58 574 {
emilmont 2:e9a661555b58 575 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 2:e9a661555b58 576 uint32_t result;
emilmont 2:e9a661555b58 577
emilmont 2:e9a661555b58 578 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
emilmont 2:e9a661555b58 579 return(result);
emilmont 2:e9a661555b58 580 #else
emilmont 2:e9a661555b58 581 return(0);
emilmont 2:e9a661555b58 582 #endif
emilmont 2:e9a661555b58 583 }
emilmont 2:e9a661555b58 584
emilmont 2:e9a661555b58 585
emilmont 2:e9a661555b58 586 /** \brief Set FPSCR
emilmont 2:e9a661555b58 587
emilmont 2:e9a661555b58 588 This function assigns the given value to the Floating Point Status/Control register.
emilmont 2:e9a661555b58 589
emilmont 2:e9a661555b58 590 \param [in] fpscr Floating Point Status/Control value to set
emilmont 2:e9a661555b58 591 */
emilmont 2:e9a661555b58 592 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 2:e9a661555b58 593 {
emilmont 2:e9a661555b58 594 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 2:e9a661555b58 595 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
emilmont 2:e9a661555b58 596 #endif
emilmont 2:e9a661555b58 597 }
emilmont 2:e9a661555b58 598
emilmont 2:e9a661555b58 599 #endif /* (__CORTEX_M == 0x04) */
emilmont 2:e9a661555b58 600
emilmont 2:e9a661555b58 601
emilmont 2:e9a661555b58 602 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 2:e9a661555b58 603 /* TASKING carm specific functions */
emilmont 2:e9a661555b58 604
emilmont 2:e9a661555b58 605 /*
emilmont 2:e9a661555b58 606 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 2:e9a661555b58 607 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 2:e9a661555b58 608 * Including the CMSIS ones.
emilmont 2:e9a661555b58 609 */
emilmont 2:e9a661555b58 610
emilmont 2:e9a661555b58 611 #endif
emilmont 2:e9a661555b58 612
emilmont 2:e9a661555b58 613 /*@} end of CMSIS_Core_RegAccFunctions */
emilmont 2:e9a661555b58 614
emilmont 2:e9a661555b58 615
emilmont 2:e9a661555b58 616 #endif /* __CORE_CMFUNC_H */