mbed-KL25Z - mbed libraries for KL25Z

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mbed libraries for KL25Z

KL25Z/MKL25Z4.h@9:663789d7729f, 2013-02-18 (annotated)

Committer:: emilmont
Date:: Mon Feb 18 09:41:56 2013 +0000
Revision:: 9:663789d7729f
Parent:: 2:e9a661555b58

Update mbed-KL25Z to latest build

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	2:e9a661555b58	1	/*
emilmont	2:e9a661555b58	2	** ###################################################################
emilmont	2:e9a661555b58	3	** Processor: MKL25Z128VLK4
emilmont	2:e9a661555b58	4	** Compilers: ARM Compiler
emilmont	2:e9a661555b58	5	** Freescale C/C++ for Embedded ARM
emilmont	2:e9a661555b58	6	** GNU C Compiler
emilmont	2:e9a661555b58	7	** IAR ANSI C/C++ Compiler for ARM
emilmont	2:e9a661555b58	8	**
emilmont	2:e9a661555b58	9	** Reference manual: KL25RM, Rev.1, Jun 2012
emilmont	2:e9a661555b58	10	** Version: rev. 1.1, 2012-06-21
emilmont	2:e9a661555b58	11	**
emilmont	2:e9a661555b58	12	** Abstract:
emilmont	2:e9a661555b58	13	** CMSIS Peripheral Access Layer for MKL25Z4
emilmont	2:e9a661555b58	14	**
emilmont	2:e9a661555b58	15	** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
emilmont	2:e9a661555b58	16	**
emilmont	2:e9a661555b58	17	** http: www.freescale.com
emilmont	2:e9a661555b58	18	** mail: support@freescale.com
emilmont	2:e9a661555b58	19	**
emilmont	2:e9a661555b58	20	** Revisions:
emilmont	2:e9a661555b58	21	** - rev. 1.0 (2012-06-13)
emilmont	2:e9a661555b58	22	** Initial version.
emilmont	2:e9a661555b58	23	** - rev. 1.1 (2012-06-21)
emilmont	2:e9a661555b58	24	** Update according to reference manual rev. 1.
emilmont	2:e9a661555b58	25	**
emilmont	2:e9a661555b58	26	** ###################################################################
emilmont	2:e9a661555b58	27	*/
emilmont	2:e9a661555b58	28
emilmont	2:e9a661555b58	29	/**
emilmont	2:e9a661555b58	30	* @file MKL25Z4.h
emilmont	2:e9a661555b58	31	* @version 1.1
emilmont	2:e9a661555b58	32	* @date 2012-06-21
emilmont	2:e9a661555b58	33	* @brief CMSIS Peripheral Access Layer for MKL25Z4
emilmont	2:e9a661555b58	34	*
emilmont	2:e9a661555b58	35	* CMSIS Peripheral Access Layer for MKL25Z4
emilmont	2:e9a661555b58	36	*/
emilmont	2:e9a661555b58	37
emilmont	2:e9a661555b58	38	#if !defined(MKL25Z4_H_)
emilmont	2:e9a661555b58	39	#define MKL25Z4_H_ /*< Symbol preventing repeated inclusion /
emilmont	2:e9a661555b58	40
emilmont	2:e9a661555b58	41	/** Memory map major version (memory maps with equal major version number are
emilmont	2:e9a661555b58	42	* compatible) */
emilmont	2:e9a661555b58	43	#define MCU_MEM_MAP_VERSION 0x0100u
emilmont	2:e9a661555b58	44	/** Memory map minor version */
emilmont	2:e9a661555b58	45	#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
emilmont	2:e9a661555b58	46
emilmont	2:e9a661555b58	47
emilmont	2:e9a661555b58	48	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	49	-- Interrupt vector numbers
emilmont	2:e9a661555b58	50	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	51
emilmont	2:e9a661555b58	52	/**
emilmont	2:e9a661555b58	53	* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
emilmont	2:e9a661555b58	54	* @{
emilmont	2:e9a661555b58	55	*/
emilmont	2:e9a661555b58	56
emilmont	2:e9a661555b58	57	/** Interrupt Number Definitions */
emilmont	2:e9a661555b58	58	typedef enum IRQn {
emilmont	2:e9a661555b58	59	/* Core interrupts */
emilmont	2:e9a661555b58	60	NonMaskableInt_IRQn = -14, /*< Non Maskable Interrupt /
emilmont	2:e9a661555b58	61	HardFault_IRQn = -13, /*< Cortex-M0 SV Hard Fault Interrupt /
emilmont	2:e9a661555b58	62	SVCall_IRQn = -5, /*< Cortex-M0 SV Call Interrupt /
emilmont	2:e9a661555b58	63	PendSV_IRQn = -2, /*< Cortex-M0 Pend SV Interrupt /
emilmont	2:e9a661555b58	64	SysTick_IRQn = -1, /*< Cortex-M0 System Tick Interrupt /
emilmont	2:e9a661555b58	65
emilmont	2:e9a661555b58	66	/* Device specific interrupts */
emilmont	2:e9a661555b58	67	DMA0_IRQn = 0, /*< DMA channel 0 transfer complete interrupt /
emilmont	2:e9a661555b58	68	DMA1_IRQn = 1, /*< DMA channel 1 transfer complete interrupt /
emilmont	2:e9a661555b58	69	DMA2_IRQn = 2, /*< DMA channel 2 transfer complete interrupt /
emilmont	2:e9a661555b58	70	DMA3_IRQn = 3, /*< DMA channel 3 transfer complete interrupt /
emilmont	2:e9a661555b58	71	Reserved20_IRQn = 4, /*< Reserved interrupt 20 /
emilmont	2:e9a661555b58	72	FTFA_IRQn = 5, /*< FTFA interrupt /
emilmont	2:e9a661555b58	73	LVD_LVW_IRQn = 6, /*< Low Voltage Detect, Low Voltage Warning /
emilmont	2:e9a661555b58	74	LLW_IRQn = 7, /*< Low Leakage Wakeup /
emilmont	2:e9a661555b58	75	I2C0_IRQn = 8, /*< I2C0 interrupt /
emilmont	2:e9a661555b58	76	I2C1_IRQn = 9, /*< I2C0 interrupt 25 /
emilmont	2:e9a661555b58	77	SPI0_IRQn = 10, /*< SPI0 interrupt /
emilmont	2:e9a661555b58	78	SPI1_IRQn = 11, /*< SPI1 interrupt /
emilmont	2:e9a661555b58	79	UART0_IRQn = 12, /*< UART0 status/error interrupt /
emilmont	2:e9a661555b58	80	UART1_IRQn = 13, /*< UART1 status/error interrupt /
emilmont	2:e9a661555b58	81	UART2_IRQn = 14, /*< UART2 status/error interrupt /
emilmont	2:e9a661555b58	82	ADC0_IRQn = 15, /*< ADC0 interrupt /
emilmont	2:e9a661555b58	83	CMP0_IRQn = 16, /*< CMP0 interrupt /
emilmont	2:e9a661555b58	84	TPM0_IRQn = 17, /*< TPM0 fault, overflow and channels interrupt /
emilmont	2:e9a661555b58	85	TPM1_IRQn = 18, /*< TPM1 fault, overflow and channels interrupt /
emilmont	2:e9a661555b58	86	TPM2_IRQn = 19, /*< TPM2 fault, overflow and channels interrupt /
emilmont	2:e9a661555b58	87	RTC_IRQn = 20, /*< RTC interrupt /
emilmont	2:e9a661555b58	88	RTC_Seconds_IRQn = 21, /*< RTC seconds interrupt /
emilmont	2:e9a661555b58	89	PIT_IRQn = 22, /*< PIT timer interrupt /
emilmont	2:e9a661555b58	90	Reserved39_IRQn = 23, /*< Reserved interrupt 39 /
emilmont	2:e9a661555b58	91	USB0_IRQn = 24, /*< USB0 interrupt /
emilmont	2:e9a661555b58	92	DAC0_IRQn = 25, /*< DAC interrupt /
emilmont	2:e9a661555b58	93	TSI0_IRQn = 26, /*< TSI0 interrupt /
emilmont	2:e9a661555b58	94	MCG_IRQn = 27, /*< MCG interrupt /
emilmont	2:e9a661555b58	95	LPTimer_IRQn = 28, /*< LPTimer interrupt /
emilmont	2:e9a661555b58	96	Reserved45_IRQn = 29, /*< Reserved interrupt 45 /
emilmont	2:e9a661555b58	97	PORTA_IRQn = 30, /*< Port A interrupt /
emilmont	2:e9a661555b58	98	PORTD_IRQn = 31 /*< Port D interrupt /
emilmont	2:e9a661555b58	99	} IRQn_Type;
emilmont	2:e9a661555b58	100
emilmont	2:e9a661555b58	101	/**
emilmont	2:e9a661555b58	102	* @}
emilmont	2:e9a661555b58	103	/ / end of group Interrupt_vector_numbers */
emilmont	2:e9a661555b58	104
emilmont	2:e9a661555b58	105
emilmont	2:e9a661555b58	106	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	107	-- Cortex M0 Core Configuration
emilmont	2:e9a661555b58	108	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	109
emilmont	2:e9a661555b58	110	/**
emilmont	2:e9a661555b58	111	* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
emilmont	2:e9a661555b58	112	* @{
emilmont	2:e9a661555b58	113	*/
emilmont	2:e9a661555b58	114
emilmont	2:e9a661555b58	115	#define __CM0PLUS_REV 0x0000 /*< Core revision r0p0 /
emilmont	2:e9a661555b58	116	#define __MPU_PRESENT 0 /*< Defines if an MPU is present or not /
emilmont	2:e9a661555b58	117	#define __VTOR_PRESENT 1 /*< Defines if an MPU is present or not /
emilmont	2:e9a661555b58	118	#define __NVIC_PRIO_BITS 2 /*< Number of priority bits implemented in the NVIC /
emilmont	2:e9a661555b58	119	#define __Vendor_SysTickConfig 0 /*< Vendor specific implementation of SysTickConfig is defined /
emilmont	2:e9a661555b58	120
emilmont	2:e9a661555b58	121	#include "core_cm0plus.h" /* Core Peripheral Access Layer */
emilmont	2:e9a661555b58	122	#include "system_MKL25Z4.h" /* Device specific configuration file */
emilmont	2:e9a661555b58	123
emilmont	2:e9a661555b58	124	/**
emilmont	2:e9a661555b58	125	* @}
emilmont	2:e9a661555b58	126	/ / end of group Cortex_Core_Configuration */
emilmont	2:e9a661555b58	127
emilmont	2:e9a661555b58	128
emilmont	2:e9a661555b58	129	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	130	-- Device Peripheral Access Layer
emilmont	2:e9a661555b58	131	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	132
emilmont	2:e9a661555b58	133	/**
emilmont	2:e9a661555b58	134	* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
emilmont	2:e9a661555b58	135	* @{
emilmont	2:e9a661555b58	136	*/
emilmont	2:e9a661555b58	137
emilmont	2:e9a661555b58	138
emilmont	2:e9a661555b58	139	/*
emilmont	2:e9a661555b58	140	** Start of section using anonymous unions
emilmont	2:e9a661555b58	141	*/
emilmont	2:e9a661555b58	142
emilmont	2:e9a661555b58	143	#if defined(__ARMCC_VERSION)
emilmont	2:e9a661555b58	144	#pragma push
emilmont	2:e9a661555b58	145	#pragma anon_unions
emilmont	2:e9a661555b58	146	#elif defined(__CWCC__)
emilmont	2:e9a661555b58	147	#pragma push
emilmont	2:e9a661555b58	148	#pragma cpp_extensions on
emilmont	2:e9a661555b58	149	#elif defined(__GNUC__)
emilmont	2:e9a661555b58	150	/* anonymous unions are enabled by default */
emilmont	2:e9a661555b58	151	#elif defined(__IAR_SYSTEMS_ICC__)
emilmont	2:e9a661555b58	152	#pragma language=extended
emilmont	2:e9a661555b58	153	#else
emilmont	2:e9a661555b58	154	#error Not supported compiler type
emilmont	2:e9a661555b58	155	#endif
emilmont	2:e9a661555b58	156
emilmont	2:e9a661555b58	157	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	158	-- ADC Peripheral Access Layer
emilmont	2:e9a661555b58	159	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	160
emilmont	2:e9a661555b58	161	/**
emilmont	2:e9a661555b58	162	* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
emilmont	2:e9a661555b58	163	* @{
emilmont	2:e9a661555b58	164	*/
emilmont	2:e9a661555b58	165
emilmont	2:e9a661555b58	166	/** ADC - Register Layout Typedef */
emilmont	2:e9a661555b58	167	typedef struct {
emilmont	2:e9a661555b58	168	__IO uint32_t SC1[2]; /*< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 /
emilmont	2:e9a661555b58	169	__IO uint32_t CFG1; /*< ADC Configuration Register 1, offset: 0x8 /
emilmont	2:e9a661555b58	170	__IO uint32_t CFG2; /*< ADC Configuration Register 2, offset: 0xC /
emilmont	2:e9a661555b58	171	__I uint32_t R[2]; /*< ADC Data Result Register, array offset: 0x10, array step: 0x4 /
emilmont	2:e9a661555b58	172	__IO uint32_t CV1; /*< Compare Value Registers, offset: 0x18 /
emilmont	2:e9a661555b58	173	__IO uint32_t CV2; /*< Compare Value Registers, offset: 0x1C /
emilmont	2:e9a661555b58	174	__IO uint32_t SC2; /*< Status and Control Register 2, offset: 0x20 /
emilmont	2:e9a661555b58	175	__IO uint32_t SC3; /*< Status and Control Register 3, offset: 0x24 /
emilmont	2:e9a661555b58	176	__IO uint32_t OFS; /*< ADC Offset Correction Register, offset: 0x28 /
emilmont	2:e9a661555b58	177	__IO uint32_t PG; /*< ADC Plus-Side Gain Register, offset: 0x2C /
emilmont	2:e9a661555b58	178	__IO uint32_t MG; /*< ADC Minus-Side Gain Register, offset: 0x30 /
emilmont	2:e9a661555b58	179	__IO uint32_t CLPD; /*< ADC Plus-Side General Calibration Value Register, offset: 0x34 /
emilmont	2:e9a661555b58	180	__IO uint32_t CLPS; /*< ADC Plus-Side General Calibration Value Register, offset: 0x38 /
emilmont	2:e9a661555b58	181	__IO uint32_t CLP4; /*< ADC Plus-Side General Calibration Value Register, offset: 0x3C /
emilmont	2:e9a661555b58	182	__IO uint32_t CLP3; /*< ADC Plus-Side General Calibration Value Register, offset: 0x40 /
emilmont	2:e9a661555b58	183	__IO uint32_t CLP2; /*< ADC Plus-Side General Calibration Value Register, offset: 0x44 /
emilmont	2:e9a661555b58	184	__IO uint32_t CLP1; /*< ADC Plus-Side General Calibration Value Register, offset: 0x48 /
emilmont	2:e9a661555b58	185	__IO uint32_t CLP0; /*< ADC Plus-Side General Calibration Value Register, offset: 0x4C /
emilmont	2:e9a661555b58	186	uint8_t RESERVED_0[4];
emilmont	2:e9a661555b58	187	__IO uint32_t CLMD; /*< ADC Minus-Side General Calibration Value Register, offset: 0x54 /
emilmont	2:e9a661555b58	188	__IO uint32_t CLMS; /*< ADC Minus-Side General Calibration Value Register, offset: 0x58 /
emilmont	2:e9a661555b58	189	__IO uint32_t CLM4; /*< ADC Minus-Side General Calibration Value Register, offset: 0x5C /
emilmont	2:e9a661555b58	190	__IO uint32_t CLM3; /*< ADC Minus-Side General Calibration Value Register, offset: 0x60 /
emilmont	2:e9a661555b58	191	__IO uint32_t CLM2; /*< ADC Minus-Side General Calibration Value Register, offset: 0x64 /
emilmont	2:e9a661555b58	192	__IO uint32_t CLM1; /*< ADC Minus-Side General Calibration Value Register, offset: 0x68 /
emilmont	2:e9a661555b58	193	__IO uint32_t CLM0; /*< ADC Minus-Side General Calibration Value Register, offset: 0x6C /
emilmont	2:e9a661555b58	194	} ADC_Type;
emilmont	2:e9a661555b58	195
emilmont	2:e9a661555b58	196	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	197	-- ADC Register Masks
emilmont	2:e9a661555b58	198	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	199
emilmont	2:e9a661555b58	200	/**
emilmont	2:e9a661555b58	201	* @addtogroup ADC_Register_Masks ADC Register Masks
emilmont	2:e9a661555b58	202	* @{
emilmont	2:e9a661555b58	203	*/
emilmont	2:e9a661555b58	204
emilmont	2:e9a661555b58	205	/* SC1 Bit Fields */
emilmont	2:e9a661555b58	206	#define ADC_SC1_ADCH_MASK 0x1Fu
emilmont	2:e9a661555b58	207	#define ADC_SC1_ADCH_SHIFT 0
emilmont	2:e9a661555b58	208	#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
emilmont	2:e9a661555b58	209	#define ADC_SC1_DIFF_MASK 0x20u
emilmont	2:e9a661555b58	210	#define ADC_SC1_DIFF_SHIFT 5
emilmont	2:e9a661555b58	211	#define ADC_SC1_AIEN_MASK 0x40u
emilmont	2:e9a661555b58	212	#define ADC_SC1_AIEN_SHIFT 6
emilmont	2:e9a661555b58	213	#define ADC_SC1_COCO_MASK 0x80u
emilmont	2:e9a661555b58	214	#define ADC_SC1_COCO_SHIFT 7
emilmont	2:e9a661555b58	215	/* CFG1 Bit Fields */
emilmont	2:e9a661555b58	216	#define ADC_CFG1_ADICLK_MASK 0x3u
emilmont	2:e9a661555b58	217	#define ADC_CFG1_ADICLK_SHIFT 0
emilmont	2:e9a661555b58	218	#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
emilmont	2:e9a661555b58	219	#define ADC_CFG1_MODE_MASK 0xCu
emilmont	2:e9a661555b58	220	#define ADC_CFG1_MODE_SHIFT 2
emilmont	2:e9a661555b58	221	#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
emilmont	2:e9a661555b58	222	#define ADC_CFG1_ADLSMP_MASK 0x10u
emilmont	2:e9a661555b58	223	#define ADC_CFG1_ADLSMP_SHIFT 4
emilmont	2:e9a661555b58	224	#define ADC_CFG1_ADIV_MASK 0x60u
emilmont	2:e9a661555b58	225	#define ADC_CFG1_ADIV_SHIFT 5
emilmont	2:e9a661555b58	226	#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
emilmont	2:e9a661555b58	227	#define ADC_CFG1_ADLPC_MASK 0x80u
emilmont	2:e9a661555b58	228	#define ADC_CFG1_ADLPC_SHIFT 7
emilmont	2:e9a661555b58	229	/* CFG2 Bit Fields */
emilmont	2:e9a661555b58	230	#define ADC_CFG2_ADLSTS_MASK 0x3u
emilmont	2:e9a661555b58	231	#define ADC_CFG2_ADLSTS_SHIFT 0
emilmont	2:e9a661555b58	232	#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
emilmont	2:e9a661555b58	233	#define ADC_CFG2_ADHSC_MASK 0x4u
emilmont	2:e9a661555b58	234	#define ADC_CFG2_ADHSC_SHIFT 2
emilmont	2:e9a661555b58	235	#define ADC_CFG2_ADACKEN_MASK 0x8u
emilmont	2:e9a661555b58	236	#define ADC_CFG2_ADACKEN_SHIFT 3
emilmont	2:e9a661555b58	237	#define ADC_CFG2_MUXSEL_MASK 0x10u
emilmont	2:e9a661555b58	238	#define ADC_CFG2_MUXSEL_SHIFT 4
emilmont	2:e9a661555b58	239	/* R Bit Fields */
emilmont	2:e9a661555b58	240	#define ADC_R_D_MASK 0xFFFFu
emilmont	2:e9a661555b58	241	#define ADC_R_D_SHIFT 0
emilmont	2:e9a661555b58	242	#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
emilmont	2:e9a661555b58	243	/* CV1 Bit Fields */
emilmont	2:e9a661555b58	244	#define ADC_CV1_CV_MASK 0xFFFFu
emilmont	2:e9a661555b58	245	#define ADC_CV1_CV_SHIFT 0
emilmont	2:e9a661555b58	246	#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
emilmont	2:e9a661555b58	247	/* CV2 Bit Fields */
emilmont	2:e9a661555b58	248	#define ADC_CV2_CV_MASK 0xFFFFu
emilmont	2:e9a661555b58	249	#define ADC_CV2_CV_SHIFT 0
emilmont	2:e9a661555b58	250	#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
emilmont	2:e9a661555b58	251	/* SC2 Bit Fields */
emilmont	2:e9a661555b58	252	#define ADC_SC2_REFSEL_MASK 0x3u
emilmont	2:e9a661555b58	253	#define ADC_SC2_REFSEL_SHIFT 0
emilmont	2:e9a661555b58	254	#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
emilmont	2:e9a661555b58	255	#define ADC_SC2_DMAEN_MASK 0x4u
emilmont	2:e9a661555b58	256	#define ADC_SC2_DMAEN_SHIFT 2
emilmont	2:e9a661555b58	257	#define ADC_SC2_ACREN_MASK 0x8u
emilmont	2:e9a661555b58	258	#define ADC_SC2_ACREN_SHIFT 3
emilmont	2:e9a661555b58	259	#define ADC_SC2_ACFGT_MASK 0x10u
emilmont	2:e9a661555b58	260	#define ADC_SC2_ACFGT_SHIFT 4
emilmont	2:e9a661555b58	261	#define ADC_SC2_ACFE_MASK 0x20u
emilmont	2:e9a661555b58	262	#define ADC_SC2_ACFE_SHIFT 5
emilmont	2:e9a661555b58	263	#define ADC_SC2_ADTRG_MASK 0x40u
emilmont	2:e9a661555b58	264	#define ADC_SC2_ADTRG_SHIFT 6
emilmont	2:e9a661555b58	265	#define ADC_SC2_ADACT_MASK 0x80u
emilmont	2:e9a661555b58	266	#define ADC_SC2_ADACT_SHIFT 7
emilmont	2:e9a661555b58	267	/* SC3 Bit Fields */
emilmont	2:e9a661555b58	268	#define ADC_SC3_AVGS_MASK 0x3u
emilmont	2:e9a661555b58	269	#define ADC_SC3_AVGS_SHIFT 0
emilmont	2:e9a661555b58	270	#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
emilmont	2:e9a661555b58	271	#define ADC_SC3_AVGE_MASK 0x4u
emilmont	2:e9a661555b58	272	#define ADC_SC3_AVGE_SHIFT 2
emilmont	2:e9a661555b58	273	#define ADC_SC3_ADCO_MASK 0x8u
emilmont	2:e9a661555b58	274	#define ADC_SC3_ADCO_SHIFT 3
emilmont	2:e9a661555b58	275	#define ADC_SC3_CALF_MASK 0x40u
emilmont	2:e9a661555b58	276	#define ADC_SC3_CALF_SHIFT 6
emilmont	2:e9a661555b58	277	#define ADC_SC3_CAL_MASK 0x80u
emilmont	2:e9a661555b58	278	#define ADC_SC3_CAL_SHIFT 7
emilmont	2:e9a661555b58	279	/* OFS Bit Fields */
emilmont	2:e9a661555b58	280	#define ADC_OFS_OFS_MASK 0xFFFFu
emilmont	2:e9a661555b58	281	#define ADC_OFS_OFS_SHIFT 0
emilmont	2:e9a661555b58	282	#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
emilmont	2:e9a661555b58	283	/* PG Bit Fields */
emilmont	2:e9a661555b58	284	#define ADC_PG_PG_MASK 0xFFFFu
emilmont	2:e9a661555b58	285	#define ADC_PG_PG_SHIFT 0
emilmont	2:e9a661555b58	286	#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
emilmont	2:e9a661555b58	287	/* MG Bit Fields */
emilmont	2:e9a661555b58	288	#define ADC_MG_MG_MASK 0xFFFFu
emilmont	2:e9a661555b58	289	#define ADC_MG_MG_SHIFT 0
emilmont	2:e9a661555b58	290	#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
emilmont	2:e9a661555b58	291	/* CLPD Bit Fields */
emilmont	2:e9a661555b58	292	#define ADC_CLPD_CLPD_MASK 0x3Fu
emilmont	2:e9a661555b58	293	#define ADC_CLPD_CLPD_SHIFT 0
emilmont	2:e9a661555b58	294	#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
emilmont	2:e9a661555b58	295	/* CLPS Bit Fields */
emilmont	2:e9a661555b58	296	#define ADC_CLPS_CLPS_MASK 0x3Fu
emilmont	2:e9a661555b58	297	#define ADC_CLPS_CLPS_SHIFT 0
emilmont	2:e9a661555b58	298	#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
emilmont	2:e9a661555b58	299	/* CLP4 Bit Fields */
emilmont	2:e9a661555b58	300	#define ADC_CLP4_CLP4_MASK 0x3FFu
emilmont	2:e9a661555b58	301	#define ADC_CLP4_CLP4_SHIFT 0
emilmont	2:e9a661555b58	302	#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
emilmont	2:e9a661555b58	303	/* CLP3 Bit Fields */
emilmont	2:e9a661555b58	304	#define ADC_CLP3_CLP3_MASK 0x1FFu
emilmont	2:e9a661555b58	305	#define ADC_CLP3_CLP3_SHIFT 0
emilmont	2:e9a661555b58	306	#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
emilmont	2:e9a661555b58	307	/* CLP2 Bit Fields */
emilmont	2:e9a661555b58	308	#define ADC_CLP2_CLP2_MASK 0xFFu
emilmont	2:e9a661555b58	309	#define ADC_CLP2_CLP2_SHIFT 0
emilmont	2:e9a661555b58	310	#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
emilmont	2:e9a661555b58	311	/* CLP1 Bit Fields */
emilmont	2:e9a661555b58	312	#define ADC_CLP1_CLP1_MASK 0x7Fu
emilmont	2:e9a661555b58	313	#define ADC_CLP1_CLP1_SHIFT 0
emilmont	2:e9a661555b58	314	#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
emilmont	2:e9a661555b58	315	/* CLP0 Bit Fields */
emilmont	2:e9a661555b58	316	#define ADC_CLP0_CLP0_MASK 0x3Fu
emilmont	2:e9a661555b58	317	#define ADC_CLP0_CLP0_SHIFT 0
emilmont	2:e9a661555b58	318	#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
emilmont	2:e9a661555b58	319	/* CLMD Bit Fields */
emilmont	2:e9a661555b58	320	#define ADC_CLMD_CLMD_MASK 0x3Fu
emilmont	2:e9a661555b58	321	#define ADC_CLMD_CLMD_SHIFT 0
emilmont	2:e9a661555b58	322	#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
emilmont	2:e9a661555b58	323	/* CLMS Bit Fields */
emilmont	2:e9a661555b58	324	#define ADC_CLMS_CLMS_MASK 0x3Fu
emilmont	2:e9a661555b58	325	#define ADC_CLMS_CLMS_SHIFT 0
emilmont	2:e9a661555b58	326	#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
emilmont	2:e9a661555b58	327	/* CLM4 Bit Fields */
emilmont	2:e9a661555b58	328	#define ADC_CLM4_CLM4_MASK 0x3FFu
emilmont	2:e9a661555b58	329	#define ADC_CLM4_CLM4_SHIFT 0
emilmont	2:e9a661555b58	330	#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
emilmont	2:e9a661555b58	331	/* CLM3 Bit Fields */
emilmont	2:e9a661555b58	332	#define ADC_CLM3_CLM3_MASK 0x1FFu
emilmont	2:e9a661555b58	333	#define ADC_CLM3_CLM3_SHIFT 0
emilmont	2:e9a661555b58	334	#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
emilmont	2:e9a661555b58	335	/* CLM2 Bit Fields */
emilmont	2:e9a661555b58	336	#define ADC_CLM2_CLM2_MASK 0xFFu
emilmont	2:e9a661555b58	337	#define ADC_CLM2_CLM2_SHIFT 0
emilmont	2:e9a661555b58	338	#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
emilmont	2:e9a661555b58	339	/* CLM1 Bit Fields */
emilmont	2:e9a661555b58	340	#define ADC_CLM1_CLM1_MASK 0x7Fu
emilmont	2:e9a661555b58	341	#define ADC_CLM1_CLM1_SHIFT 0
emilmont	2:e9a661555b58	342	#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
emilmont	2:e9a661555b58	343	/* CLM0 Bit Fields */
emilmont	2:e9a661555b58	344	#define ADC_CLM0_CLM0_MASK 0x3Fu
emilmont	2:e9a661555b58	345	#define ADC_CLM0_CLM0_SHIFT 0
emilmont	2:e9a661555b58	346	#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
emilmont	2:e9a661555b58	347
emilmont	2:e9a661555b58	348	/**
emilmont	2:e9a661555b58	349	* @}
emilmont	2:e9a661555b58	350	/ / end of group ADC_Register_Masks */
emilmont	2:e9a661555b58	351
emilmont	2:e9a661555b58	352
emilmont	2:e9a661555b58	353	/* ADC - Peripheral instance base addresses */
emilmont	2:e9a661555b58	354	/** Peripheral ADC0 base address */
emilmont	2:e9a661555b58	355	#define ADC0_BASE (0x4003B000u)
emilmont	2:e9a661555b58	356	/** Peripheral ADC0 base pointer */
emilmont	2:e9a661555b58	357	#define ADC0 ((ADC_Type *)ADC0_BASE)
emilmont	2:e9a661555b58	358	/** Array initializer of ADC peripheral base pointers */
emilmont	2:e9a661555b58	359	#define ADC_BASES { ADC0 }
emilmont	2:e9a661555b58	360
emilmont	2:e9a661555b58	361	/**
emilmont	2:e9a661555b58	362	* @}
emilmont	2:e9a661555b58	363	/ / end of group ADC_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	364
emilmont	2:e9a661555b58	365
emilmont	2:e9a661555b58	366	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	367	-- CMP Peripheral Access Layer
emilmont	2:e9a661555b58	368	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	369
emilmont	2:e9a661555b58	370	/**
emilmont	2:e9a661555b58	371	* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
emilmont	2:e9a661555b58	372	* @{
emilmont	2:e9a661555b58	373	*/
emilmont	2:e9a661555b58	374
emilmont	2:e9a661555b58	375	/** CMP - Register Layout Typedef */
emilmont	2:e9a661555b58	376	typedef struct {
emilmont	2:e9a661555b58	377	__IO uint8_t CR0; /*< CMP Control Register 0, offset: 0x0 /
emilmont	2:e9a661555b58	378	__IO uint8_t CR1; /*< CMP Control Register 1, offset: 0x1 /
emilmont	2:e9a661555b58	379	__IO uint8_t FPR; /*< CMP Filter Period Register, offset: 0x2 /
emilmont	2:e9a661555b58	380	__IO uint8_t SCR; /*< CMP Status and Control Register, offset: 0x3 /
emilmont	2:e9a661555b58	381	__IO uint8_t DACCR; /*< DAC Control Register, offset: 0x4 /
emilmont	2:e9a661555b58	382	__IO uint8_t MUXCR; /*< MUX Control Register, offset: 0x5 /
emilmont	2:e9a661555b58	383	} CMP_Type;
emilmont	2:e9a661555b58	384
emilmont	2:e9a661555b58	385	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	386	-- CMP Register Masks
emilmont	2:e9a661555b58	387	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	388
emilmont	2:e9a661555b58	389	/**
emilmont	2:e9a661555b58	390	* @addtogroup CMP_Register_Masks CMP Register Masks
emilmont	2:e9a661555b58	391	* @{
emilmont	2:e9a661555b58	392	*/
emilmont	2:e9a661555b58	393
emilmont	2:e9a661555b58	394	/* CR0 Bit Fields */
emilmont	2:e9a661555b58	395	#define CMP_CR0_HYSTCTR_MASK 0x3u
emilmont	2:e9a661555b58	396	#define CMP_CR0_HYSTCTR_SHIFT 0
emilmont	2:e9a661555b58	397	#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
emilmont	2:e9a661555b58	398	#define CMP_CR0_FILTER_CNT_MASK 0x70u
emilmont	2:e9a661555b58	399	#define CMP_CR0_FILTER_CNT_SHIFT 4
emilmont	2:e9a661555b58	400	#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
emilmont	2:e9a661555b58	401	/* CR1 Bit Fields */
emilmont	2:e9a661555b58	402	#define CMP_CR1_EN_MASK 0x1u
emilmont	2:e9a661555b58	403	#define CMP_CR1_EN_SHIFT 0
emilmont	2:e9a661555b58	404	#define CMP_CR1_OPE_MASK 0x2u
emilmont	2:e9a661555b58	405	#define CMP_CR1_OPE_SHIFT 1
emilmont	2:e9a661555b58	406	#define CMP_CR1_COS_MASK 0x4u
emilmont	2:e9a661555b58	407	#define CMP_CR1_COS_SHIFT 2
emilmont	2:e9a661555b58	408	#define CMP_CR1_INV_MASK 0x8u
emilmont	2:e9a661555b58	409	#define CMP_CR1_INV_SHIFT 3
emilmont	2:e9a661555b58	410	#define CMP_CR1_PMODE_MASK 0x10u
emilmont	2:e9a661555b58	411	#define CMP_CR1_PMODE_SHIFT 4
emilmont	2:e9a661555b58	412	#define CMP_CR1_TRIGM_MASK 0x20u
emilmont	2:e9a661555b58	413	#define CMP_CR1_TRIGM_SHIFT 5
emilmont	2:e9a661555b58	414	#define CMP_CR1_WE_MASK 0x40u
emilmont	2:e9a661555b58	415	#define CMP_CR1_WE_SHIFT 6
emilmont	2:e9a661555b58	416	#define CMP_CR1_SE_MASK 0x80u
emilmont	2:e9a661555b58	417	#define CMP_CR1_SE_SHIFT 7
emilmont	2:e9a661555b58	418	/* FPR Bit Fields */
emilmont	2:e9a661555b58	419	#define CMP_FPR_FILT_PER_MASK 0xFFu
emilmont	2:e9a661555b58	420	#define CMP_FPR_FILT_PER_SHIFT 0
emilmont	2:e9a661555b58	421	#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
emilmont	2:e9a661555b58	422	/* SCR Bit Fields */
emilmont	2:e9a661555b58	423	#define CMP_SCR_COUT_MASK 0x1u
emilmont	2:e9a661555b58	424	#define CMP_SCR_COUT_SHIFT 0
emilmont	2:e9a661555b58	425	#define CMP_SCR_CFF_MASK 0x2u
emilmont	2:e9a661555b58	426	#define CMP_SCR_CFF_SHIFT 1
emilmont	2:e9a661555b58	427	#define CMP_SCR_CFR_MASK 0x4u
emilmont	2:e9a661555b58	428	#define CMP_SCR_CFR_SHIFT 2
emilmont	2:e9a661555b58	429	#define CMP_SCR_IEF_MASK 0x8u
emilmont	2:e9a661555b58	430	#define CMP_SCR_IEF_SHIFT 3
emilmont	2:e9a661555b58	431	#define CMP_SCR_IER_MASK 0x10u
emilmont	2:e9a661555b58	432	#define CMP_SCR_IER_SHIFT 4
emilmont	2:e9a661555b58	433	#define CMP_SCR_DMAEN_MASK 0x40u
emilmont	2:e9a661555b58	434	#define CMP_SCR_DMAEN_SHIFT 6
emilmont	2:e9a661555b58	435	/* DACCR Bit Fields */
emilmont	2:e9a661555b58	436	#define CMP_DACCR_VOSEL_MASK 0x3Fu
emilmont	2:e9a661555b58	437	#define CMP_DACCR_VOSEL_SHIFT 0
emilmont	2:e9a661555b58	438	#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
emilmont	2:e9a661555b58	439	#define CMP_DACCR_VRSEL_MASK 0x40u
emilmont	2:e9a661555b58	440	#define CMP_DACCR_VRSEL_SHIFT 6
emilmont	2:e9a661555b58	441	#define CMP_DACCR_DACEN_MASK 0x80u
emilmont	2:e9a661555b58	442	#define CMP_DACCR_DACEN_SHIFT 7
emilmont	2:e9a661555b58	443	/* MUXCR Bit Fields */
emilmont	2:e9a661555b58	444	#define CMP_MUXCR_MSEL_MASK 0x7u
emilmont	2:e9a661555b58	445	#define CMP_MUXCR_MSEL_SHIFT 0
emilmont	2:e9a661555b58	446	#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
emilmont	2:e9a661555b58	447	#define CMP_MUXCR_PSEL_MASK 0x38u
emilmont	2:e9a661555b58	448	#define CMP_MUXCR_PSEL_SHIFT 3
emilmont	2:e9a661555b58	449	#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
emilmont	2:e9a661555b58	450	#define CMP_MUXCR_PSTM_MASK 0x40u
emilmont	2:e9a661555b58	451	#define CMP_MUXCR_PSTM_SHIFT 6
emilmont	2:e9a661555b58	452
emilmont	2:e9a661555b58	453	/**
emilmont	2:e9a661555b58	454	* @}
emilmont	2:e9a661555b58	455	/ / end of group CMP_Register_Masks */
emilmont	2:e9a661555b58	456
emilmont	2:e9a661555b58	457
emilmont	2:e9a661555b58	458	/* CMP - Peripheral instance base addresses */
emilmont	2:e9a661555b58	459	/** Peripheral CMP0 base address */
emilmont	2:e9a661555b58	460	#define CMP0_BASE (0x40073000u)
emilmont	2:e9a661555b58	461	/** Peripheral CMP0 base pointer */
emilmont	2:e9a661555b58	462	#define CMP0 ((CMP_Type *)CMP0_BASE)
emilmont	2:e9a661555b58	463	/** Array initializer of CMP peripheral base pointers */
emilmont	2:e9a661555b58	464	#define CMP_BASES { CMP0 }
emilmont	2:e9a661555b58	465
emilmont	2:e9a661555b58	466	/**
emilmont	2:e9a661555b58	467	* @}
emilmont	2:e9a661555b58	468	/ / end of group CMP_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	469
emilmont	2:e9a661555b58	470
emilmont	2:e9a661555b58	471	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	472	-- DAC Peripheral Access Layer
emilmont	2:e9a661555b58	473	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	474
emilmont	2:e9a661555b58	475	/**
emilmont	2:e9a661555b58	476	* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
emilmont	2:e9a661555b58	477	* @{
emilmont	2:e9a661555b58	478	*/
emilmont	2:e9a661555b58	479
emilmont	2:e9a661555b58	480	/** DAC - Register Layout Typedef */
emilmont	2:e9a661555b58	481	typedef struct {
emilmont	2:e9a661555b58	482	struct { /* offset: 0x0, array step: 0x2 */
emilmont	2:e9a661555b58	483	__IO uint8_t DATL; /*< DAC Data Low Register, array offset: 0x0, array step: 0x2 /
emilmont	2:e9a661555b58	484	__IO uint8_t DATH; /*< DAC Data High Register, array offset: 0x1, array step: 0x2 /
emilmont	2:e9a661555b58	485	} DAT[2];
emilmont	2:e9a661555b58	486	uint8_t RESERVED_0[28];
emilmont	2:e9a661555b58	487	__IO uint8_t SR; /*< DAC Status Register, offset: 0x20 /
emilmont	2:e9a661555b58	488	__IO uint8_t C0; /*< DAC Control Register, offset: 0x21 /
emilmont	2:e9a661555b58	489	__IO uint8_t C1; /*< DAC Control Register 1, offset: 0x22 /
emilmont	2:e9a661555b58	490	__IO uint8_t C2; /*< DAC Control Register 2, offset: 0x23 /
emilmont	2:e9a661555b58	491	} DAC_Type;
emilmont	2:e9a661555b58	492
emilmont	2:e9a661555b58	493	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	494	-- DAC Register Masks
emilmont	2:e9a661555b58	495	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	496
emilmont	2:e9a661555b58	497	/**
emilmont	2:e9a661555b58	498	* @addtogroup DAC_Register_Masks DAC Register Masks
emilmont	2:e9a661555b58	499	* @{
emilmont	2:e9a661555b58	500	*/
emilmont	2:e9a661555b58	501
emilmont	2:e9a661555b58	502	/* DATL Bit Fields */
emilmont	2:e9a661555b58	503	#define DAC_DATL_DATA0_MASK 0xFFu
emilmont	2:e9a661555b58	504	#define DAC_DATL_DATA0_SHIFT 0
emilmont	2:e9a661555b58	505	#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
emilmont	2:e9a661555b58	506	/* DATH Bit Fields */
emilmont	2:e9a661555b58	507	#define DAC_DATH_DATA1_MASK 0xFu
emilmont	2:e9a661555b58	508	#define DAC_DATH_DATA1_SHIFT 0
emilmont	2:e9a661555b58	509	#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
emilmont	2:e9a661555b58	510	/* SR Bit Fields */
emilmont	2:e9a661555b58	511	#define DAC_SR_DACBFRPBF_MASK 0x1u
emilmont	2:e9a661555b58	512	#define DAC_SR_DACBFRPBF_SHIFT 0
emilmont	2:e9a661555b58	513	#define DAC_SR_DACBFRPTF_MASK 0x2u
emilmont	2:e9a661555b58	514	#define DAC_SR_DACBFRPTF_SHIFT 1
emilmont	2:e9a661555b58	515	/* C0 Bit Fields */
emilmont	2:e9a661555b58	516	#define DAC_C0_DACBBIEN_MASK 0x1u
emilmont	2:e9a661555b58	517	#define DAC_C0_DACBBIEN_SHIFT 0
emilmont	2:e9a661555b58	518	#define DAC_C0_DACBTIEN_MASK 0x2u
emilmont	2:e9a661555b58	519	#define DAC_C0_DACBTIEN_SHIFT 1
emilmont	2:e9a661555b58	520	#define DAC_C0_LPEN_MASK 0x8u
emilmont	2:e9a661555b58	521	#define DAC_C0_LPEN_SHIFT 3
emilmont	2:e9a661555b58	522	#define DAC_C0_DACSWTRG_MASK 0x10u
emilmont	2:e9a661555b58	523	#define DAC_C0_DACSWTRG_SHIFT 4
emilmont	2:e9a661555b58	524	#define DAC_C0_DACTRGSEL_MASK 0x20u
emilmont	2:e9a661555b58	525	#define DAC_C0_DACTRGSEL_SHIFT 5
emilmont	2:e9a661555b58	526	#define DAC_C0_DACRFS_MASK 0x40u
emilmont	2:e9a661555b58	527	#define DAC_C0_DACRFS_SHIFT 6
emilmont	2:e9a661555b58	528	#define DAC_C0_DACEN_MASK 0x80u
emilmont	2:e9a661555b58	529	#define DAC_C0_DACEN_SHIFT 7
emilmont	2:e9a661555b58	530	/* C1 Bit Fields */
emilmont	2:e9a661555b58	531	#define DAC_C1_DACBFEN_MASK 0x1u
emilmont	2:e9a661555b58	532	#define DAC_C1_DACBFEN_SHIFT 0
emilmont	2:e9a661555b58	533	#define DAC_C1_DACBFMD_MASK 0x4u
emilmont	2:e9a661555b58	534	#define DAC_C1_DACBFMD_SHIFT 2
emilmont	2:e9a661555b58	535	#define DAC_C1_DMAEN_MASK 0x80u
emilmont	2:e9a661555b58	536	#define DAC_C1_DMAEN_SHIFT 7
emilmont	2:e9a661555b58	537	/* C2 Bit Fields */
emilmont	2:e9a661555b58	538	#define DAC_C2_DACBFUP_MASK 0x1u
emilmont	2:e9a661555b58	539	#define DAC_C2_DACBFUP_SHIFT 0
emilmont	2:e9a661555b58	540	#define DAC_C2_DACBFRP_MASK 0x10u
emilmont	2:e9a661555b58	541	#define DAC_C2_DACBFRP_SHIFT 4
emilmont	2:e9a661555b58	542
emilmont	2:e9a661555b58	543	/**
emilmont	2:e9a661555b58	544	* @}
emilmont	2:e9a661555b58	545	/ / end of group DAC_Register_Masks */
emilmont	2:e9a661555b58	546
emilmont	2:e9a661555b58	547
emilmont	2:e9a661555b58	548	/* DAC - Peripheral instance base addresses */
emilmont	2:e9a661555b58	549	/** Peripheral DAC0 base address */
emilmont	2:e9a661555b58	550	#define DAC0_BASE (0x4003F000u)
emilmont	2:e9a661555b58	551	/** Peripheral DAC0 base pointer */
emilmont	2:e9a661555b58	552	#define DAC0 ((DAC_Type *)DAC0_BASE)
emilmont	2:e9a661555b58	553	/** Array initializer of DAC peripheral base pointers */
emilmont	2:e9a661555b58	554	#define DAC_BASES { DAC0 }
emilmont	2:e9a661555b58	555
emilmont	2:e9a661555b58	556	/**
emilmont	2:e9a661555b58	557	* @}
emilmont	2:e9a661555b58	558	/ / end of group DAC_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	559
emilmont	2:e9a661555b58	560
emilmont	2:e9a661555b58	561	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	562	-- DMA Peripheral Access Layer
emilmont	2:e9a661555b58	563	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	564
emilmont	2:e9a661555b58	565	/**
emilmont	2:e9a661555b58	566	* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
emilmont	2:e9a661555b58	567	* @{
emilmont	2:e9a661555b58	568	*/
emilmont	2:e9a661555b58	569
emilmont	2:e9a661555b58	570	/** DMA - Register Layout Typedef */
emilmont	2:e9a661555b58	571	typedef struct {
emilmont	2:e9a661555b58	572	union { /* offset: 0x0 */
emilmont	2:e9a661555b58	573	__IO uint8_t REQC_ARR[4]; /*< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 /
emilmont	2:e9a661555b58	574	};
emilmont	2:e9a661555b58	575	uint8_t RESERVED_0[252];
emilmont	2:e9a661555b58	576	struct { /* offset: 0x100, array step: 0x10 */
emilmont	2:e9a661555b58	577	__IO uint32_t SAR; /*< Source Address Register, array offset: 0x100, array step: 0x10 /
emilmont	2:e9a661555b58	578	__IO uint32_t DAR; /*< Destination Address Register, array offset: 0x104, array step: 0x10 /
emilmont	2:e9a661555b58	579	union { /* offset: 0x108, array step: 0x10 */
emilmont	2:e9a661555b58	580	__IO uint32_t DSR_BCR; /*< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 /
emilmont	2:e9a661555b58	581	struct { /* offset: 0x108, array step: 0x10 */
emilmont	2:e9a661555b58	582	uint8_t RESERVED_0[3];
emilmont	2:e9a661555b58	583	__IO uint8_t DSR; /*< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 /
emilmont	2:e9a661555b58	584	} DMA_DSR_ACCESS8BIT;
emilmont	2:e9a661555b58	585	};
emilmont	2:e9a661555b58	586	__IO uint32_t DCR; /*< DMA Control Register, array offset: 0x10C, array step: 0x10 /
emilmont	2:e9a661555b58	587	} DMA[4];
emilmont	2:e9a661555b58	588	} DMA_Type;
emilmont	2:e9a661555b58	589
emilmont	2:e9a661555b58	590	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	591	-- DMA Register Masks
emilmont	2:e9a661555b58	592	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	593
emilmont	2:e9a661555b58	594	/**
emilmont	2:e9a661555b58	595	* @addtogroup DMA_Register_Masks DMA Register Masks
emilmont	2:e9a661555b58	596	* @{
emilmont	2:e9a661555b58	597	*/
emilmont	2:e9a661555b58	598
emilmont	2:e9a661555b58	599	/* REQC_ARR Bit Fields */
emilmont	2:e9a661555b58	600	#define DMA_REQC_ARR_DMAC_MASK 0xFu
emilmont	2:e9a661555b58	601	#define DMA_REQC_ARR_DMAC_SHIFT 0
emilmont	2:e9a661555b58	602	#define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
emilmont	2:e9a661555b58	603	#define DMA_REQC_ARR_CFSM_MASK 0x80u
emilmont	2:e9a661555b58	604	#define DMA_REQC_ARR_CFSM_SHIFT 7
emilmont	2:e9a661555b58	605	/* SAR Bit Fields */
emilmont	2:e9a661555b58	606	#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	607	#define DMA_SAR_SAR_SHIFT 0
emilmont	2:e9a661555b58	608	#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
emilmont	2:e9a661555b58	609	/* DAR Bit Fields */
emilmont	2:e9a661555b58	610	#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	611	#define DMA_DAR_DAR_SHIFT 0
emilmont	2:e9a661555b58	612	#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
emilmont	2:e9a661555b58	613	/* DSR_BCR Bit Fields */
emilmont	2:e9a661555b58	614	#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
emilmont	2:e9a661555b58	615	#define DMA_DSR_BCR_BCR_SHIFT 0
emilmont	2:e9a661555b58	616	#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
emilmont	2:e9a661555b58	617	#define DMA_DSR_BCR_DONE_MASK 0x1000000u
emilmont	2:e9a661555b58	618	#define DMA_DSR_BCR_DONE_SHIFT 24
emilmont	2:e9a661555b58	619	#define DMA_DSR_BCR_BSY_MASK 0x2000000u
emilmont	2:e9a661555b58	620	#define DMA_DSR_BCR_BSY_SHIFT 25
emilmont	2:e9a661555b58	621	#define DMA_DSR_BCR_REQ_MASK 0x4000000u
emilmont	2:e9a661555b58	622	#define DMA_DSR_BCR_REQ_SHIFT 26
emilmont	2:e9a661555b58	623	#define DMA_DSR_BCR_BED_MASK 0x10000000u
emilmont	2:e9a661555b58	624	#define DMA_DSR_BCR_BED_SHIFT 28
emilmont	2:e9a661555b58	625	#define DMA_DSR_BCR_BES_MASK 0x20000000u
emilmont	2:e9a661555b58	626	#define DMA_DSR_BCR_BES_SHIFT 29
emilmont	2:e9a661555b58	627	#define DMA_DSR_BCR_CE_MASK 0x40000000u
emilmont	2:e9a661555b58	628	#define DMA_DSR_BCR_CE_SHIFT 30
emilmont	2:e9a661555b58	629	/* DCR Bit Fields */
emilmont	2:e9a661555b58	630	#define DMA_DCR_LCH2_MASK 0x3u
emilmont	2:e9a661555b58	631	#define DMA_DCR_LCH2_SHIFT 0
emilmont	2:e9a661555b58	632	#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
emilmont	2:e9a661555b58	633	#define DMA_DCR_LCH1_MASK 0xCu
emilmont	2:e9a661555b58	634	#define DMA_DCR_LCH1_SHIFT 2
emilmont	2:e9a661555b58	635	#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
emilmont	2:e9a661555b58	636	#define DMA_DCR_LINKCC_MASK 0x30u
emilmont	2:e9a661555b58	637	#define DMA_DCR_LINKCC_SHIFT 4
emilmont	2:e9a661555b58	638	#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
emilmont	2:e9a661555b58	639	#define DMA_DCR_D_REQ_MASK 0x80u
emilmont	2:e9a661555b58	640	#define DMA_DCR_D_REQ_SHIFT 7
emilmont	2:e9a661555b58	641	#define DMA_DCR_DMOD_MASK 0xF00u
emilmont	2:e9a661555b58	642	#define DMA_DCR_DMOD_SHIFT 8
emilmont	2:e9a661555b58	643	#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
emilmont	2:e9a661555b58	644	#define DMA_DCR_SMOD_MASK 0xF000u
emilmont	2:e9a661555b58	645	#define DMA_DCR_SMOD_SHIFT 12
emilmont	2:e9a661555b58	646	#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
emilmont	2:e9a661555b58	647	#define DMA_DCR_START_MASK 0x10000u
emilmont	2:e9a661555b58	648	#define DMA_DCR_START_SHIFT 16
emilmont	2:e9a661555b58	649	#define DMA_DCR_DSIZE_MASK 0x60000u
emilmont	2:e9a661555b58	650	#define DMA_DCR_DSIZE_SHIFT 17
emilmont	2:e9a661555b58	651	#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
emilmont	2:e9a661555b58	652	#define DMA_DCR_DINC_MASK 0x80000u
emilmont	2:e9a661555b58	653	#define DMA_DCR_DINC_SHIFT 19
emilmont	2:e9a661555b58	654	#define DMA_DCR_SSIZE_MASK 0x300000u
emilmont	2:e9a661555b58	655	#define DMA_DCR_SSIZE_SHIFT 20
emilmont	2:e9a661555b58	656	#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
emilmont	2:e9a661555b58	657	#define DMA_DCR_SINC_MASK 0x400000u
emilmont	2:e9a661555b58	658	#define DMA_DCR_SINC_SHIFT 22
emilmont	2:e9a661555b58	659	#define DMA_DCR_EADREQ_MASK 0x800000u
emilmont	2:e9a661555b58	660	#define DMA_DCR_EADREQ_SHIFT 23
emilmont	2:e9a661555b58	661	#define DMA_DCR_AA_MASK 0x10000000u
emilmont	2:e9a661555b58	662	#define DMA_DCR_AA_SHIFT 28
emilmont	2:e9a661555b58	663	#define DMA_DCR_CS_MASK 0x20000000u
emilmont	2:e9a661555b58	664	#define DMA_DCR_CS_SHIFT 29
emilmont	2:e9a661555b58	665	#define DMA_DCR_ERQ_MASK 0x40000000u
emilmont	2:e9a661555b58	666	#define DMA_DCR_ERQ_SHIFT 30
emilmont	2:e9a661555b58	667	#define DMA_DCR_EINT_MASK 0x80000000u
emilmont	2:e9a661555b58	668	#define DMA_DCR_EINT_SHIFT 31
emilmont	2:e9a661555b58	669
emilmont	2:e9a661555b58	670	/**
emilmont	2:e9a661555b58	671	* @}
emilmont	2:e9a661555b58	672	/ / end of group DMA_Register_Masks */
emilmont	2:e9a661555b58	673
emilmont	2:e9a661555b58	674
emilmont	2:e9a661555b58	675	/* DMA - Peripheral instance base addresses */
emilmont	2:e9a661555b58	676	/** Peripheral DMA base address */
emilmont	2:e9a661555b58	677	#define DMA_BASE (0x40008000u)
emilmont	2:e9a661555b58	678	/** Peripheral DMA base pointer */
emilmont	2:e9a661555b58	679	#define DMA0 ((DMA_Type *)DMA_BASE)
emilmont	2:e9a661555b58	680	/** Array initializer of DMA peripheral base pointers */
emilmont	2:e9a661555b58	681	#define DMA_BASES { DMA0 }
emilmont	2:e9a661555b58	682
emilmont	2:e9a661555b58	683	/**
emilmont	2:e9a661555b58	684	* @}
emilmont	2:e9a661555b58	685	/ / end of group DMA_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	686
emilmont	2:e9a661555b58	687
emilmont	2:e9a661555b58	688	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	689	-- DMAMUX Peripheral Access Layer
emilmont	2:e9a661555b58	690	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	691
emilmont	2:e9a661555b58	692	/**
emilmont	2:e9a661555b58	693	* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
emilmont	2:e9a661555b58	694	* @{
emilmont	2:e9a661555b58	695	*/
emilmont	2:e9a661555b58	696
emilmont	2:e9a661555b58	697	/** DMAMUX - Register Layout Typedef */
emilmont	2:e9a661555b58	698	typedef struct {
emilmont	2:e9a661555b58	699	__IO uint8_t CHCFG[4]; /*< Channel Configuration register, array offset: 0x0, array step: 0x1 /
emilmont	2:e9a661555b58	700	} DMAMUX_Type;
emilmont	2:e9a661555b58	701
emilmont	2:e9a661555b58	702	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	703	-- DMAMUX Register Masks
emilmont	2:e9a661555b58	704	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	705
emilmont	2:e9a661555b58	706	/**
emilmont	2:e9a661555b58	707	* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
emilmont	2:e9a661555b58	708	* @{
emilmont	2:e9a661555b58	709	*/
emilmont	2:e9a661555b58	710
emilmont	2:e9a661555b58	711	/* CHCFG Bit Fields */
emilmont	2:e9a661555b58	712	#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
emilmont	2:e9a661555b58	713	#define DMAMUX_CHCFG_SOURCE_SHIFT 0
emilmont	2:e9a661555b58	714	#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
emilmont	2:e9a661555b58	715	#define DMAMUX_CHCFG_TRIG_MASK 0x40u
emilmont	2:e9a661555b58	716	#define DMAMUX_CHCFG_TRIG_SHIFT 6
emilmont	2:e9a661555b58	717	#define DMAMUX_CHCFG_ENBL_MASK 0x80u
emilmont	2:e9a661555b58	718	#define DMAMUX_CHCFG_ENBL_SHIFT 7
emilmont	2:e9a661555b58	719
emilmont	2:e9a661555b58	720	/**
emilmont	2:e9a661555b58	721	* @}
emilmont	2:e9a661555b58	722	/ / end of group DMAMUX_Register_Masks */
emilmont	2:e9a661555b58	723
emilmont	2:e9a661555b58	724
emilmont	2:e9a661555b58	725	/* DMAMUX - Peripheral instance base addresses */
emilmont	2:e9a661555b58	726	/** Peripheral DMAMUX0 base address */
emilmont	2:e9a661555b58	727	#define DMAMUX0_BASE (0x40021000u)
emilmont	2:e9a661555b58	728	/** Peripheral DMAMUX0 base pointer */
emilmont	2:e9a661555b58	729	#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
emilmont	2:e9a661555b58	730	/** Array initializer of DMAMUX peripheral base pointers */
emilmont	2:e9a661555b58	731	#define DMAMUX_BASES { DMAMUX0 }
emilmont	2:e9a661555b58	732
emilmont	2:e9a661555b58	733	/**
emilmont	2:e9a661555b58	734	* @}
emilmont	2:e9a661555b58	735	/ / end of group DMAMUX_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	736
emilmont	2:e9a661555b58	737
emilmont	2:e9a661555b58	738	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	739	-- FGPIO Peripheral Access Layer
emilmont	2:e9a661555b58	740	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	741
emilmont	2:e9a661555b58	742	/**
emilmont	2:e9a661555b58	743	* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
emilmont	2:e9a661555b58	744	* @{
emilmont	2:e9a661555b58	745	*/
emilmont	2:e9a661555b58	746
emilmont	2:e9a661555b58	747	/** FGPIO - Register Layout Typedef */
emilmont	2:e9a661555b58	748	typedef struct {
emilmont	2:e9a661555b58	749	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
emilmont	2:e9a661555b58	750	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
emilmont	2:e9a661555b58	751	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
emilmont	2:e9a661555b58	752	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
emilmont	2:e9a661555b58	753	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
emilmont	2:e9a661555b58	754	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
emilmont	2:e9a661555b58	755	} FGPIO_Type;
emilmont	2:e9a661555b58	756
emilmont	2:e9a661555b58	757	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	758	-- FGPIO Register Masks
emilmont	2:e9a661555b58	759	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	760
emilmont	2:e9a661555b58	761	/**
emilmont	2:e9a661555b58	762	* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
emilmont	2:e9a661555b58	763	* @{
emilmont	2:e9a661555b58	764	*/
emilmont	2:e9a661555b58	765
emilmont	2:e9a661555b58	766	/* PDOR Bit Fields */
emilmont	2:e9a661555b58	767	#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	768	#define FGPIO_PDOR_PDO_SHIFT 0
emilmont	2:e9a661555b58	769	#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
emilmont	2:e9a661555b58	770	/* PSOR Bit Fields */
emilmont	2:e9a661555b58	771	#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	772	#define FGPIO_PSOR_PTSO_SHIFT 0
emilmont	2:e9a661555b58	773	#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
emilmont	2:e9a661555b58	774	/* PCOR Bit Fields */
emilmont	2:e9a661555b58	775	#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	776	#define FGPIO_PCOR_PTCO_SHIFT 0
emilmont	2:e9a661555b58	777	#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
emilmont	2:e9a661555b58	778	/* PTOR Bit Fields */
emilmont	2:e9a661555b58	779	#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	780	#define FGPIO_PTOR_PTTO_SHIFT 0
emilmont	2:e9a661555b58	781	#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
emilmont	2:e9a661555b58	782	/* PDIR Bit Fields */
emilmont	2:e9a661555b58	783	#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	784	#define FGPIO_PDIR_PDI_SHIFT 0
emilmont	2:e9a661555b58	785	#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
emilmont	2:e9a661555b58	786	/* PDDR Bit Fields */
emilmont	2:e9a661555b58	787	#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	788	#define FGPIO_PDDR_PDD_SHIFT 0
emilmont	2:e9a661555b58	789	#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
emilmont	2:e9a661555b58	790
emilmont	2:e9a661555b58	791	/**
emilmont	2:e9a661555b58	792	* @}
emilmont	2:e9a661555b58	793	/ / end of group FGPIO_Register_Masks */
emilmont	2:e9a661555b58	794
emilmont	2:e9a661555b58	795
emilmont	2:e9a661555b58	796	/* FGPIO - Peripheral instance base addresses */
emilmont	2:e9a661555b58	797	/** Peripheral FPTA base address */
emilmont	2:e9a661555b58	798	#define FPTA_BASE (0xF80FF000u)
emilmont	2:e9a661555b58	799	/** Peripheral FPTA base pointer */
emilmont	2:e9a661555b58	800	#define FPTA ((FGPIO_Type *)FPTA_BASE)
emilmont	2:e9a661555b58	801	/** Peripheral FPTB base address */
emilmont	2:e9a661555b58	802	#define FPTB_BASE (0xF80FF040u)
emilmont	2:e9a661555b58	803	/** Peripheral FPTB base pointer */
emilmont	2:e9a661555b58	804	#define FPTB ((FGPIO_Type *)FPTB_BASE)
emilmont	2:e9a661555b58	805	/** Peripheral FPTC base address */
emilmont	2:e9a661555b58	806	#define FPTC_BASE (0xF80FF080u)
emilmont	2:e9a661555b58	807	/** Peripheral FPTC base pointer */
emilmont	2:e9a661555b58	808	#define FPTC ((FGPIO_Type *)FPTC_BASE)
emilmont	2:e9a661555b58	809	/** Peripheral FPTD base address */
emilmont	2:e9a661555b58	810	#define FPTD_BASE (0xF80FF0C0u)
emilmont	2:e9a661555b58	811	/** Peripheral FPTD base pointer */
emilmont	2:e9a661555b58	812	#define FPTD ((FGPIO_Type *)FPTD_BASE)
emilmont	2:e9a661555b58	813	/** Peripheral FPTE base address */
emilmont	2:e9a661555b58	814	#define FPTE_BASE (0xF80FF100u)
emilmont	2:e9a661555b58	815	/** Peripheral FPTE base pointer */
emilmont	2:e9a661555b58	816	#define FPTE ((FGPIO_Type *)FPTE_BASE)
emilmont	2:e9a661555b58	817	/** Array initializer of FGPIO peripheral base pointers */
emilmont	2:e9a661555b58	818	#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
emilmont	2:e9a661555b58	819
emilmont	2:e9a661555b58	820	/**
emilmont	2:e9a661555b58	821	* @}
emilmont	2:e9a661555b58	822	/ / end of group FGPIO_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	823
emilmont	2:e9a661555b58	824
emilmont	2:e9a661555b58	825	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	826	-- FTFA Peripheral Access Layer
emilmont	2:e9a661555b58	827	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	828
emilmont	2:e9a661555b58	829	/**
emilmont	2:e9a661555b58	830	* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
emilmont	2:e9a661555b58	831	* @{
emilmont	2:e9a661555b58	832	*/
emilmont	2:e9a661555b58	833
emilmont	2:e9a661555b58	834	/** FTFA - Register Layout Typedef */
emilmont	2:e9a661555b58	835	typedef struct {
emilmont	2:e9a661555b58	836	__IO uint8_t FSTAT; /*< Flash Status Register, offset: 0x0 /
emilmont	2:e9a661555b58	837	__IO uint8_t FCNFG; /*< Flash Configuration Register, offset: 0x1 /
emilmont	2:e9a661555b58	838	__I uint8_t FSEC; /*< Flash Security Register, offset: 0x2 /
emilmont	2:e9a661555b58	839	__I uint8_t FOPT; /*< Flash Option Register, offset: 0x3 /
emilmont	2:e9a661555b58	840	__IO uint8_t FCCOB3; /*< Flash Common Command Object Registers, offset: 0x4 /
emilmont	2:e9a661555b58	841	__IO uint8_t FCCOB2; /*< Flash Common Command Object Registers, offset: 0x5 /
emilmont	2:e9a661555b58	842	__IO uint8_t FCCOB1; /*< Flash Common Command Object Registers, offset: 0x6 /
emilmont	2:e9a661555b58	843	__IO uint8_t FCCOB0; /*< Flash Common Command Object Registers, offset: 0x7 /
emilmont	2:e9a661555b58	844	__IO uint8_t FCCOB7; /*< Flash Common Command Object Registers, offset: 0x8 /
emilmont	2:e9a661555b58	845	__IO uint8_t FCCOB6; /*< Flash Common Command Object Registers, offset: 0x9 /
emilmont	2:e9a661555b58	846	__IO uint8_t FCCOB5; /*< Flash Common Command Object Registers, offset: 0xA /
emilmont	2:e9a661555b58	847	__IO uint8_t FCCOB4; /*< Flash Common Command Object Registers, offset: 0xB /
emilmont	2:e9a661555b58	848	__IO uint8_t FCCOBB; /*< Flash Common Command Object Registers, offset: 0xC /
emilmont	2:e9a661555b58	849	__IO uint8_t FCCOBA; /*< Flash Common Command Object Registers, offset: 0xD /
emilmont	2:e9a661555b58	850	__IO uint8_t FCCOB9; /*< Flash Common Command Object Registers, offset: 0xE /
emilmont	2:e9a661555b58	851	__IO uint8_t FCCOB8; /*< Flash Common Command Object Registers, offset: 0xF /
emilmont	2:e9a661555b58	852	__IO uint8_t FPROT3; /*< Program Flash Protection Registers, offset: 0x10 /
emilmont	2:e9a661555b58	853	__IO uint8_t FPROT2; /*< Program Flash Protection Registers, offset: 0x11 /
emilmont	2:e9a661555b58	854	__IO uint8_t FPROT1; /*< Program Flash Protection Registers, offset: 0x12 /
emilmont	2:e9a661555b58	855	__IO uint8_t FPROT0; /*< Program Flash Protection Registers, offset: 0x13 /
emilmont	2:e9a661555b58	856	} FTFA_Type;
emilmont	2:e9a661555b58	857
emilmont	2:e9a661555b58	858	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	859	-- FTFA Register Masks
emilmont	2:e9a661555b58	860	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	861
emilmont	2:e9a661555b58	862	/**
emilmont	2:e9a661555b58	863	* @addtogroup FTFA_Register_Masks FTFA Register Masks
emilmont	2:e9a661555b58	864	* @{
emilmont	2:e9a661555b58	865	*/
emilmont	2:e9a661555b58	866
emilmont	2:e9a661555b58	867	/* FSTAT Bit Fields */
emilmont	2:e9a661555b58	868	#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
emilmont	2:e9a661555b58	869	#define FTFA_FSTAT_MGSTAT0_SHIFT 0
emilmont	2:e9a661555b58	870	#define FTFA_FSTAT_FPVIOL_MASK 0x10u
emilmont	2:e9a661555b58	871	#define FTFA_FSTAT_FPVIOL_SHIFT 4
emilmont	2:e9a661555b58	872	#define FTFA_FSTAT_ACCERR_MASK 0x20u
emilmont	2:e9a661555b58	873	#define FTFA_FSTAT_ACCERR_SHIFT 5
emilmont	2:e9a661555b58	874	#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
emilmont	2:e9a661555b58	875	#define FTFA_FSTAT_RDCOLERR_SHIFT 6
emilmont	2:e9a661555b58	876	#define FTFA_FSTAT_CCIF_MASK 0x80u
emilmont	2:e9a661555b58	877	#define FTFA_FSTAT_CCIF_SHIFT 7
emilmont	2:e9a661555b58	878	/* FCNFG Bit Fields */
emilmont	2:e9a661555b58	879	#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
emilmont	2:e9a661555b58	880	#define FTFA_FCNFG_ERSSUSP_SHIFT 4
emilmont	2:e9a661555b58	881	#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
emilmont	2:e9a661555b58	882	#define FTFA_FCNFG_ERSAREQ_SHIFT 5
emilmont	2:e9a661555b58	883	#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
emilmont	2:e9a661555b58	884	#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
emilmont	2:e9a661555b58	885	#define FTFA_FCNFG_CCIE_MASK 0x80u
emilmont	2:e9a661555b58	886	#define FTFA_FCNFG_CCIE_SHIFT 7
emilmont	2:e9a661555b58	887	/* FSEC Bit Fields */
emilmont	2:e9a661555b58	888	#define FTFA_FSEC_SEC_MASK 0x3u
emilmont	2:e9a661555b58	889	#define FTFA_FSEC_SEC_SHIFT 0
emilmont	2:e9a661555b58	890	#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
emilmont	2:e9a661555b58	891	#define FTFA_FSEC_FSLACC_MASK 0xCu
emilmont	2:e9a661555b58	892	#define FTFA_FSEC_FSLACC_SHIFT 2
emilmont	2:e9a661555b58	893	#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
emilmont	2:e9a661555b58	894	#define FTFA_FSEC_MEEN_MASK 0x30u
emilmont	2:e9a661555b58	895	#define FTFA_FSEC_MEEN_SHIFT 4
emilmont	2:e9a661555b58	896	#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
emilmont	2:e9a661555b58	897	#define FTFA_FSEC_KEYEN_MASK 0xC0u
emilmont	2:e9a661555b58	898	#define FTFA_FSEC_KEYEN_SHIFT 6
emilmont	2:e9a661555b58	899	#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
emilmont	2:e9a661555b58	900	/* FOPT Bit Fields */
emilmont	2:e9a661555b58	901	#define FTFA_FOPT_OPT_MASK 0xFFu
emilmont	2:e9a661555b58	902	#define FTFA_FOPT_OPT_SHIFT 0
emilmont	2:e9a661555b58	903	#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
emilmont	2:e9a661555b58	904	/* FCCOB3 Bit Fields */
emilmont	2:e9a661555b58	905	#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	906	#define FTFA_FCCOB3_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	907	#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
emilmont	2:e9a661555b58	908	/* FCCOB2 Bit Fields */
emilmont	2:e9a661555b58	909	#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	910	#define FTFA_FCCOB2_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	911	#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
emilmont	2:e9a661555b58	912	/* FCCOB1 Bit Fields */
emilmont	2:e9a661555b58	913	#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	914	#define FTFA_FCCOB1_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	915	#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
emilmont	2:e9a661555b58	916	/* FCCOB0 Bit Fields */
emilmont	2:e9a661555b58	917	#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	918	#define FTFA_FCCOB0_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	919	#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
emilmont	2:e9a661555b58	920	/* FCCOB7 Bit Fields */
emilmont	2:e9a661555b58	921	#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	922	#define FTFA_FCCOB7_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	923	#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
emilmont	2:e9a661555b58	924	/* FCCOB6 Bit Fields */
emilmont	2:e9a661555b58	925	#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	926	#define FTFA_FCCOB6_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	927	#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
emilmont	2:e9a661555b58	928	/* FCCOB5 Bit Fields */
emilmont	2:e9a661555b58	929	#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	930	#define FTFA_FCCOB5_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	931	#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
emilmont	2:e9a661555b58	932	/* FCCOB4 Bit Fields */
emilmont	2:e9a661555b58	933	#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	934	#define FTFA_FCCOB4_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	935	#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
emilmont	2:e9a661555b58	936	/* FCCOBB Bit Fields */
emilmont	2:e9a661555b58	937	#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	938	#define FTFA_FCCOBB_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	939	#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
emilmont	2:e9a661555b58	940	/* FCCOBA Bit Fields */
emilmont	2:e9a661555b58	941	#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	942	#define FTFA_FCCOBA_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	943	#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
emilmont	2:e9a661555b58	944	/* FCCOB9 Bit Fields */
emilmont	2:e9a661555b58	945	#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	946	#define FTFA_FCCOB9_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	947	#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
emilmont	2:e9a661555b58	948	/* FCCOB8 Bit Fields */
emilmont	2:e9a661555b58	949	#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
emilmont	2:e9a661555b58	950	#define FTFA_FCCOB8_CCOBn_SHIFT 0
emilmont	2:e9a661555b58	951	#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
emilmont	2:e9a661555b58	952	/* FPROT3 Bit Fields */
emilmont	2:e9a661555b58	953	#define FTFA_FPROT3_PROT_MASK 0xFFu
emilmont	2:e9a661555b58	954	#define FTFA_FPROT3_PROT_SHIFT 0
emilmont	2:e9a661555b58	955	#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
emilmont	2:e9a661555b58	956	/* FPROT2 Bit Fields */
emilmont	2:e9a661555b58	957	#define FTFA_FPROT2_PROT_MASK 0xFFu
emilmont	2:e9a661555b58	958	#define FTFA_FPROT2_PROT_SHIFT 0
emilmont	2:e9a661555b58	959	#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
emilmont	2:e9a661555b58	960	/* FPROT1 Bit Fields */
emilmont	2:e9a661555b58	961	#define FTFA_FPROT1_PROT_MASK 0xFFu
emilmont	2:e9a661555b58	962	#define FTFA_FPROT1_PROT_SHIFT 0
emilmont	2:e9a661555b58	963	#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
emilmont	2:e9a661555b58	964	/* FPROT0 Bit Fields */
emilmont	2:e9a661555b58	965	#define FTFA_FPROT0_PROT_MASK 0xFFu
emilmont	2:e9a661555b58	966	#define FTFA_FPROT0_PROT_SHIFT 0
emilmont	2:e9a661555b58	967	#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
emilmont	2:e9a661555b58	968
emilmont	2:e9a661555b58	969	/**
emilmont	2:e9a661555b58	970	* @}
emilmont	2:e9a661555b58	971	/ / end of group FTFA_Register_Masks */
emilmont	2:e9a661555b58	972
emilmont	2:e9a661555b58	973
emilmont	2:e9a661555b58	974	/* FTFA - Peripheral instance base addresses */
emilmont	2:e9a661555b58	975	/** Peripheral FTFA base address */
emilmont	2:e9a661555b58	976	#define FTFA_BASE (0x40020000u)
emilmont	2:e9a661555b58	977	/** Peripheral FTFA base pointer */
emilmont	2:e9a661555b58	978	#define FTFA ((FTFA_Type *)FTFA_BASE)
emilmont	2:e9a661555b58	979	/** Array initializer of FTFA peripheral base pointers */
emilmont	2:e9a661555b58	980	#define FTFA_BASES { FTFA }
emilmont	2:e9a661555b58	981
emilmont	2:e9a661555b58	982	/**
emilmont	2:e9a661555b58	983	* @}
emilmont	2:e9a661555b58	984	/ / end of group FTFA_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	985
emilmont	2:e9a661555b58	986
emilmont	2:e9a661555b58	987	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	988	-- GPIO Peripheral Access Layer
emilmont	2:e9a661555b58	989	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	990
emilmont	2:e9a661555b58	991	/**
emilmont	2:e9a661555b58	992	* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
emilmont	2:e9a661555b58	993	* @{
emilmont	2:e9a661555b58	994	*/
emilmont	2:e9a661555b58	995
emilmont	2:e9a661555b58	996	/** GPIO - Register Layout Typedef */
emilmont	2:e9a661555b58	997	typedef struct {
emilmont	2:e9a661555b58	998	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
emilmont	2:e9a661555b58	999	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
emilmont	2:e9a661555b58	1000	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
emilmont	2:e9a661555b58	1001	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
emilmont	2:e9a661555b58	1002	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
emilmont	2:e9a661555b58	1003	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
emilmont	2:e9a661555b58	1004	} GPIO_Type;
emilmont	2:e9a661555b58	1005
emilmont	2:e9a661555b58	1006	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1007	-- GPIO Register Masks
emilmont	2:e9a661555b58	1008	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1009
emilmont	2:e9a661555b58	1010	/**
emilmont	2:e9a661555b58	1011	* @addtogroup GPIO_Register_Masks GPIO Register Masks
emilmont	2:e9a661555b58	1012	* @{
emilmont	2:e9a661555b58	1013	*/
emilmont	2:e9a661555b58	1014
emilmont	2:e9a661555b58	1015	/* PDOR Bit Fields */
emilmont	2:e9a661555b58	1016	#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1017	#define GPIO_PDOR_PDO_SHIFT 0
emilmont	2:e9a661555b58	1018	#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
emilmont	2:e9a661555b58	1019	/* PSOR Bit Fields */
emilmont	2:e9a661555b58	1020	#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1021	#define GPIO_PSOR_PTSO_SHIFT 0
emilmont	2:e9a661555b58	1022	#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
emilmont	2:e9a661555b58	1023	/* PCOR Bit Fields */
emilmont	2:e9a661555b58	1024	#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1025	#define GPIO_PCOR_PTCO_SHIFT 0
emilmont	2:e9a661555b58	1026	#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
emilmont	2:e9a661555b58	1027	/* PTOR Bit Fields */
emilmont	2:e9a661555b58	1028	#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1029	#define GPIO_PTOR_PTTO_SHIFT 0
emilmont	2:e9a661555b58	1030	#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
emilmont	2:e9a661555b58	1031	/* PDIR Bit Fields */
emilmont	2:e9a661555b58	1032	#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1033	#define GPIO_PDIR_PDI_SHIFT 0
emilmont	2:e9a661555b58	1034	#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
emilmont	2:e9a661555b58	1035	/* PDDR Bit Fields */
emilmont	2:e9a661555b58	1036	#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1037	#define GPIO_PDDR_PDD_SHIFT 0
emilmont	2:e9a661555b58	1038	#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
emilmont	2:e9a661555b58	1039
emilmont	2:e9a661555b58	1040	/**
emilmont	2:e9a661555b58	1041	* @}
emilmont	2:e9a661555b58	1042	/ / end of group GPIO_Register_Masks */
emilmont	2:e9a661555b58	1043
emilmont	2:e9a661555b58	1044
emilmont	2:e9a661555b58	1045	/* GPIO - Peripheral instance base addresses */
emilmont	2:e9a661555b58	1046	/** Peripheral PTA base address */
emilmont	2:e9a661555b58	1047	#define PTA_BASE (0x400FF000u)
emilmont	2:e9a661555b58	1048	/** Peripheral PTA base pointer */
emilmont	2:e9a661555b58	1049	#define PTA ((GPIO_Type *)PTA_BASE)
emilmont	2:e9a661555b58	1050	/** Peripheral PTB base address */
emilmont	2:e9a661555b58	1051	#define PTB_BASE (0x400FF040u)
emilmont	2:e9a661555b58	1052	/** Peripheral PTB base pointer */
emilmont	2:e9a661555b58	1053	#define PTB ((GPIO_Type *)PTB_BASE)
emilmont	2:e9a661555b58	1054	/** Peripheral PTC base address */
emilmont	2:e9a661555b58	1055	#define PTC_BASE (0x400FF080u)
emilmont	2:e9a661555b58	1056	/** Peripheral PTC base pointer */
emilmont	2:e9a661555b58	1057	#define PTC ((GPIO_Type *)PTC_BASE)
emilmont	2:e9a661555b58	1058	/** Peripheral PTD base address */
emilmont	2:e9a661555b58	1059	#define PTD_BASE (0x400FF0C0u)
emilmont	2:e9a661555b58	1060	/** Peripheral PTD base pointer */
emilmont	2:e9a661555b58	1061	#define PTD ((GPIO_Type *)PTD_BASE)
emilmont	2:e9a661555b58	1062	/** Peripheral PTE base address */
emilmont	2:e9a661555b58	1063	#define PTE_BASE (0x400FF100u)
emilmont	2:e9a661555b58	1064	/** Peripheral PTE base pointer */
emilmont	2:e9a661555b58	1065	#define PTE ((GPIO_Type *)PTE_BASE)
emilmont	2:e9a661555b58	1066	/** Array initializer of GPIO peripheral base pointers */
emilmont	2:e9a661555b58	1067	#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
emilmont	2:e9a661555b58	1068
emilmont	2:e9a661555b58	1069	/**
emilmont	2:e9a661555b58	1070	* @}
emilmont	2:e9a661555b58	1071	/ / end of group GPIO_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	1072
emilmont	2:e9a661555b58	1073
emilmont	2:e9a661555b58	1074	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1075	-- I2C Peripheral Access Layer
emilmont	2:e9a661555b58	1076	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1077
emilmont	2:e9a661555b58	1078	/**
emilmont	2:e9a661555b58	1079	* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
emilmont	2:e9a661555b58	1080	* @{
emilmont	2:e9a661555b58	1081	*/
emilmont	2:e9a661555b58	1082
emilmont	2:e9a661555b58	1083	/** I2C - Register Layout Typedef */
emilmont	2:e9a661555b58	1084	typedef struct {
emilmont	2:e9a661555b58	1085	__IO uint8_t A1; /*< I2C Address Register 1, offset: 0x0 /
emilmont	2:e9a661555b58	1086	__IO uint8_t F; /*< I2C Frequency Divider register, offset: 0x1 /
emilmont	2:e9a661555b58	1087	__IO uint8_t C1; /*< I2C Control Register 1, offset: 0x2 /
emilmont	2:e9a661555b58	1088	__IO uint8_t S; /*< I2C Status register, offset: 0x3 /
emilmont	2:e9a661555b58	1089	__IO uint8_t D; /*< I2C Data I/O register, offset: 0x4 /
emilmont	2:e9a661555b58	1090	__IO uint8_t C2; /*< I2C Control Register 2, offset: 0x5 /
emilmont	2:e9a661555b58	1091	__IO uint8_t FLT; /*< I2C Programmable Input Glitch Filter register, offset: 0x6 /
emilmont	2:e9a661555b58	1092	__IO uint8_t RA; /*< I2C Range Address register, offset: 0x7 /
emilmont	2:e9a661555b58	1093	__IO uint8_t SMB; /*< I2C SMBus Control and Status register, offset: 0x8 /
emilmont	2:e9a661555b58	1094	__IO uint8_t A2; /*< I2C Address Register 2, offset: 0x9 /
emilmont	2:e9a661555b58	1095	__IO uint8_t SLTH; /*< I2C SCL Low Timeout Register High, offset: 0xA /
emilmont	2:e9a661555b58	1096	__IO uint8_t SLTL; /*< I2C SCL Low Timeout Register Low, offset: 0xB /
emilmont	2:e9a661555b58	1097	} I2C_Type;
emilmont	2:e9a661555b58	1098
emilmont	2:e9a661555b58	1099	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1100	-- I2C Register Masks
emilmont	2:e9a661555b58	1101	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1102
emilmont	2:e9a661555b58	1103	/**
emilmont	2:e9a661555b58	1104	* @addtogroup I2C_Register_Masks I2C Register Masks
emilmont	2:e9a661555b58	1105	* @{
emilmont	2:e9a661555b58	1106	*/
emilmont	2:e9a661555b58	1107
emilmont	2:e9a661555b58	1108	/* A1 Bit Fields */
emilmont	2:e9a661555b58	1109	#define I2C_A1_AD_MASK 0xFEu
emilmont	2:e9a661555b58	1110	#define I2C_A1_AD_SHIFT 1
emilmont	2:e9a661555b58	1111	#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
emilmont	2:e9a661555b58	1112	/* F Bit Fields */
emilmont	2:e9a661555b58	1113	#define I2C_F_ICR_MASK 0x3Fu
emilmont	2:e9a661555b58	1114	#define I2C_F_ICR_SHIFT 0
emilmont	2:e9a661555b58	1115	#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
emilmont	2:e9a661555b58	1116	#define I2C_F_MULT_MASK 0xC0u
emilmont	2:e9a661555b58	1117	#define I2C_F_MULT_SHIFT 6
emilmont	2:e9a661555b58	1118	#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
emilmont	2:e9a661555b58	1119	/* C1 Bit Fields */
emilmont	2:e9a661555b58	1120	#define I2C_C1_DMAEN_MASK 0x1u
emilmont	2:e9a661555b58	1121	#define I2C_C1_DMAEN_SHIFT 0
emilmont	2:e9a661555b58	1122	#define I2C_C1_WUEN_MASK 0x2u
emilmont	2:e9a661555b58	1123	#define I2C_C1_WUEN_SHIFT 1
emilmont	2:e9a661555b58	1124	#define I2C_C1_RSTA_MASK 0x4u
emilmont	2:e9a661555b58	1125	#define I2C_C1_RSTA_SHIFT 2
emilmont	2:e9a661555b58	1126	#define I2C_C1_TXAK_MASK 0x8u
emilmont	2:e9a661555b58	1127	#define I2C_C1_TXAK_SHIFT 3
emilmont	2:e9a661555b58	1128	#define I2C_C1_TX_MASK 0x10u
emilmont	2:e9a661555b58	1129	#define I2C_C1_TX_SHIFT 4
emilmont	2:e9a661555b58	1130	#define I2C_C1_MST_MASK 0x20u
emilmont	2:e9a661555b58	1131	#define I2C_C1_MST_SHIFT 5
emilmont	2:e9a661555b58	1132	#define I2C_C1_IICIE_MASK 0x40u
emilmont	2:e9a661555b58	1133	#define I2C_C1_IICIE_SHIFT 6
emilmont	2:e9a661555b58	1134	#define I2C_C1_IICEN_MASK 0x80u
emilmont	2:e9a661555b58	1135	#define I2C_C1_IICEN_SHIFT 7
emilmont	2:e9a661555b58	1136	/* S Bit Fields */
emilmont	2:e9a661555b58	1137	#define I2C_S_RXAK_MASK 0x1u
emilmont	2:e9a661555b58	1138	#define I2C_S_RXAK_SHIFT 0
emilmont	2:e9a661555b58	1139	#define I2C_S_IICIF_MASK 0x2u
emilmont	2:e9a661555b58	1140	#define I2C_S_IICIF_SHIFT 1
emilmont	2:e9a661555b58	1141	#define I2C_S_SRW_MASK 0x4u
emilmont	2:e9a661555b58	1142	#define I2C_S_SRW_SHIFT 2
emilmont	2:e9a661555b58	1143	#define I2C_S_RAM_MASK 0x8u
emilmont	2:e9a661555b58	1144	#define I2C_S_RAM_SHIFT 3
emilmont	2:e9a661555b58	1145	#define I2C_S_ARBL_MASK 0x10u
emilmont	2:e9a661555b58	1146	#define I2C_S_ARBL_SHIFT 4
emilmont	2:e9a661555b58	1147	#define I2C_S_BUSY_MASK 0x20u
emilmont	2:e9a661555b58	1148	#define I2C_S_BUSY_SHIFT 5
emilmont	2:e9a661555b58	1149	#define I2C_S_IAAS_MASK 0x40u
emilmont	2:e9a661555b58	1150	#define I2C_S_IAAS_SHIFT 6
emilmont	2:e9a661555b58	1151	#define I2C_S_TCF_MASK 0x80u
emilmont	2:e9a661555b58	1152	#define I2C_S_TCF_SHIFT 7
emilmont	2:e9a661555b58	1153	/* D Bit Fields */
emilmont	2:e9a661555b58	1154	#define I2C_D_DATA_MASK 0xFFu
emilmont	2:e9a661555b58	1155	#define I2C_D_DATA_SHIFT 0
emilmont	2:e9a661555b58	1156	#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
emilmont	2:e9a661555b58	1157	/* C2 Bit Fields */
emilmont	2:e9a661555b58	1158	#define I2C_C2_AD_MASK 0x7u
emilmont	2:e9a661555b58	1159	#define I2C_C2_AD_SHIFT 0
emilmont	2:e9a661555b58	1160	#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
emilmont	2:e9a661555b58	1161	#define I2C_C2_RMEN_MASK 0x8u
emilmont	2:e9a661555b58	1162	#define I2C_C2_RMEN_SHIFT 3
emilmont	2:e9a661555b58	1163	#define I2C_C2_SBRC_MASK 0x10u
emilmont	2:e9a661555b58	1164	#define I2C_C2_SBRC_SHIFT 4
emilmont	2:e9a661555b58	1165	#define I2C_C2_HDRS_MASK 0x20u
emilmont	2:e9a661555b58	1166	#define I2C_C2_HDRS_SHIFT 5
emilmont	2:e9a661555b58	1167	#define I2C_C2_ADEXT_MASK 0x40u
emilmont	2:e9a661555b58	1168	#define I2C_C2_ADEXT_SHIFT 6
emilmont	2:e9a661555b58	1169	#define I2C_C2_GCAEN_MASK 0x80u
emilmont	2:e9a661555b58	1170	#define I2C_C2_GCAEN_SHIFT 7
emilmont	2:e9a661555b58	1171	/* FLT Bit Fields */
emilmont	2:e9a661555b58	1172	#define I2C_FLT_FLT_MASK 0x1Fu
emilmont	2:e9a661555b58	1173	#define I2C_FLT_FLT_SHIFT 0
emilmont	2:e9a661555b58	1174	#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
emilmont	2:e9a661555b58	1175	#define I2C_FLT_STOPIE_MASK 0x20u
emilmont	2:e9a661555b58	1176	#define I2C_FLT_STOPIE_SHIFT 5
emilmont	2:e9a661555b58	1177	#define I2C_FLT_STOPF_MASK 0x40u
emilmont	2:e9a661555b58	1178	#define I2C_FLT_STOPF_SHIFT 6
emilmont	2:e9a661555b58	1179	#define I2C_FLT_SHEN_MASK 0x80u
emilmont	2:e9a661555b58	1180	#define I2C_FLT_SHEN_SHIFT 7
emilmont	2:e9a661555b58	1181	/* RA Bit Fields */
emilmont	2:e9a661555b58	1182	#define I2C_RA_RAD_MASK 0xFEu
emilmont	2:e9a661555b58	1183	#define I2C_RA_RAD_SHIFT 1
emilmont	2:e9a661555b58	1184	#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
emilmont	2:e9a661555b58	1185	/* SMB Bit Fields */
emilmont	2:e9a661555b58	1186	#define I2C_SMB_SHTF2IE_MASK 0x1u
emilmont	2:e9a661555b58	1187	#define I2C_SMB_SHTF2IE_SHIFT 0
emilmont	2:e9a661555b58	1188	#define I2C_SMB_SHTF2_MASK 0x2u
emilmont	2:e9a661555b58	1189	#define I2C_SMB_SHTF2_SHIFT 1
emilmont	2:e9a661555b58	1190	#define I2C_SMB_SHTF1_MASK 0x4u
emilmont	2:e9a661555b58	1191	#define I2C_SMB_SHTF1_SHIFT 2
emilmont	2:e9a661555b58	1192	#define I2C_SMB_SLTF_MASK 0x8u
emilmont	2:e9a661555b58	1193	#define I2C_SMB_SLTF_SHIFT 3
emilmont	2:e9a661555b58	1194	#define I2C_SMB_TCKSEL_MASK 0x10u
emilmont	2:e9a661555b58	1195	#define I2C_SMB_TCKSEL_SHIFT 4
emilmont	2:e9a661555b58	1196	#define I2C_SMB_SIICAEN_MASK 0x20u
emilmont	2:e9a661555b58	1197	#define I2C_SMB_SIICAEN_SHIFT 5
emilmont	2:e9a661555b58	1198	#define I2C_SMB_ALERTEN_MASK 0x40u
emilmont	2:e9a661555b58	1199	#define I2C_SMB_ALERTEN_SHIFT 6
emilmont	2:e9a661555b58	1200	#define I2C_SMB_FACK_MASK 0x80u
emilmont	2:e9a661555b58	1201	#define I2C_SMB_FACK_SHIFT 7
emilmont	2:e9a661555b58	1202	/* A2 Bit Fields */
emilmont	2:e9a661555b58	1203	#define I2C_A2_SAD_MASK 0xFEu
emilmont	2:e9a661555b58	1204	#define I2C_A2_SAD_SHIFT 1
emilmont	2:e9a661555b58	1205	#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
emilmont	2:e9a661555b58	1206	/* SLTH Bit Fields */
emilmont	2:e9a661555b58	1207	#define I2C_SLTH_SSLT_MASK 0xFFu
emilmont	2:e9a661555b58	1208	#define I2C_SLTH_SSLT_SHIFT 0
emilmont	2:e9a661555b58	1209	#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
emilmont	2:e9a661555b58	1210	/* SLTL Bit Fields */
emilmont	2:e9a661555b58	1211	#define I2C_SLTL_SSLT_MASK 0xFFu
emilmont	2:e9a661555b58	1212	#define I2C_SLTL_SSLT_SHIFT 0
emilmont	2:e9a661555b58	1213	#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
emilmont	2:e9a661555b58	1214
emilmont	2:e9a661555b58	1215	/**
emilmont	2:e9a661555b58	1216	* @}
emilmont	2:e9a661555b58	1217	/ / end of group I2C_Register_Masks */
emilmont	2:e9a661555b58	1218
emilmont	2:e9a661555b58	1219
emilmont	2:e9a661555b58	1220	/* I2C - Peripheral instance base addresses */
emilmont	2:e9a661555b58	1221	/** Peripheral I2C0 base address */
emilmont	2:e9a661555b58	1222	#define I2C0_BASE (0x40066000u)
emilmont	2:e9a661555b58	1223	/** Peripheral I2C0 base pointer */
emilmont	2:e9a661555b58	1224	#define I2C0 ((I2C_Type *)I2C0_BASE)
emilmont	2:e9a661555b58	1225	/** Peripheral I2C1 base address */
emilmont	2:e9a661555b58	1226	#define I2C1_BASE (0x40067000u)
emilmont	2:e9a661555b58	1227	/** Peripheral I2C1 base pointer */
emilmont	2:e9a661555b58	1228	#define I2C1 ((I2C_Type *)I2C1_BASE)
emilmont	2:e9a661555b58	1229	/** Array initializer of I2C peripheral base pointers */
emilmont	2:e9a661555b58	1230	#define I2C_BASES { I2C0, I2C1 }
emilmont	2:e9a661555b58	1231
emilmont	2:e9a661555b58	1232	/**
emilmont	2:e9a661555b58	1233	* @}
emilmont	2:e9a661555b58	1234	/ / end of group I2C_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	1235
emilmont	2:e9a661555b58	1236
emilmont	2:e9a661555b58	1237	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1238	-- LLWU Peripheral Access Layer
emilmont	2:e9a661555b58	1239	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1240
emilmont	2:e9a661555b58	1241	/**
emilmont	2:e9a661555b58	1242	* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
emilmont	2:e9a661555b58	1243	* @{
emilmont	2:e9a661555b58	1244	*/
emilmont	2:e9a661555b58	1245
emilmont	2:e9a661555b58	1246	/** LLWU - Register Layout Typedef */
emilmont	2:e9a661555b58	1247	typedef struct {
emilmont	2:e9a661555b58	1248	__IO uint8_t PE1; /*< LLWU Pin Enable 1 register, offset: 0x0 /
emilmont	2:e9a661555b58	1249	__IO uint8_t PE2; /*< LLWU Pin Enable 2 register, offset: 0x1 /
emilmont	2:e9a661555b58	1250	__IO uint8_t PE3; /*< LLWU Pin Enable 3 register, offset: 0x2 /
emilmont	2:e9a661555b58	1251	__IO uint8_t PE4; /*< LLWU Pin Enable 4 register, offset: 0x3 /
emilmont	2:e9a661555b58	1252	__IO uint8_t ME; /*< LLWU Module Enable register, offset: 0x4 /
emilmont	2:e9a661555b58	1253	__IO uint8_t F1; /*< LLWU Flag 1 register, offset: 0x5 /
emilmont	2:e9a661555b58	1254	__IO uint8_t F2; /*< LLWU Flag 2 register, offset: 0x6 /
emilmont	2:e9a661555b58	1255	__I uint8_t F3; /*< LLWU Flag 3 register, offset: 0x7 /
emilmont	2:e9a661555b58	1256	__IO uint8_t FILT1; /*< LLWU Pin Filter 1 register, offset: 0x8 /
emilmont	2:e9a661555b58	1257	__IO uint8_t FILT2; /*< LLWU Pin Filter 2 register, offset: 0x9 /
emilmont	2:e9a661555b58	1258	} LLWU_Type;
emilmont	2:e9a661555b58	1259
emilmont	2:e9a661555b58	1260	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1261	-- LLWU Register Masks
emilmont	2:e9a661555b58	1262	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1263
emilmont	2:e9a661555b58	1264	/**
emilmont	2:e9a661555b58	1265	* @addtogroup LLWU_Register_Masks LLWU Register Masks
emilmont	2:e9a661555b58	1266	* @{
emilmont	2:e9a661555b58	1267	*/
emilmont	2:e9a661555b58	1268
emilmont	2:e9a661555b58	1269	/* PE1 Bit Fields */
emilmont	2:e9a661555b58	1270	#define LLWU_PE1_WUPE0_MASK 0x3u
emilmont	2:e9a661555b58	1271	#define LLWU_PE1_WUPE0_SHIFT 0
emilmont	2:e9a661555b58	1272	#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
emilmont	2:e9a661555b58	1273	#define LLWU_PE1_WUPE1_MASK 0xCu
emilmont	2:e9a661555b58	1274	#define LLWU_PE1_WUPE1_SHIFT 2
emilmont	2:e9a661555b58	1275	#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
emilmont	2:e9a661555b58	1276	#define LLWU_PE1_WUPE2_MASK 0x30u
emilmont	2:e9a661555b58	1277	#define LLWU_PE1_WUPE2_SHIFT 4
emilmont	2:e9a661555b58	1278	#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
emilmont	2:e9a661555b58	1279	#define LLWU_PE1_WUPE3_MASK 0xC0u
emilmont	2:e9a661555b58	1280	#define LLWU_PE1_WUPE3_SHIFT 6
emilmont	2:e9a661555b58	1281	#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
emilmont	2:e9a661555b58	1282	/* PE2 Bit Fields */
emilmont	2:e9a661555b58	1283	#define LLWU_PE2_WUPE4_MASK 0x3u
emilmont	2:e9a661555b58	1284	#define LLWU_PE2_WUPE4_SHIFT 0
emilmont	2:e9a661555b58	1285	#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
emilmont	2:e9a661555b58	1286	#define LLWU_PE2_WUPE5_MASK 0xCu
emilmont	2:e9a661555b58	1287	#define LLWU_PE2_WUPE5_SHIFT 2
emilmont	2:e9a661555b58	1288	#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
emilmont	2:e9a661555b58	1289	#define LLWU_PE2_WUPE6_MASK 0x30u
emilmont	2:e9a661555b58	1290	#define LLWU_PE2_WUPE6_SHIFT 4
emilmont	2:e9a661555b58	1291	#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
emilmont	2:e9a661555b58	1292	#define LLWU_PE2_WUPE7_MASK 0xC0u
emilmont	2:e9a661555b58	1293	#define LLWU_PE2_WUPE7_SHIFT 6
emilmont	2:e9a661555b58	1294	#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
emilmont	2:e9a661555b58	1295	/* PE3 Bit Fields */
emilmont	2:e9a661555b58	1296	#define LLWU_PE3_WUPE8_MASK 0x3u
emilmont	2:e9a661555b58	1297	#define LLWU_PE3_WUPE8_SHIFT 0
emilmont	2:e9a661555b58	1298	#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
emilmont	2:e9a661555b58	1299	#define LLWU_PE3_WUPE9_MASK 0xCu
emilmont	2:e9a661555b58	1300	#define LLWU_PE3_WUPE9_SHIFT 2
emilmont	2:e9a661555b58	1301	#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
emilmont	2:e9a661555b58	1302	#define LLWU_PE3_WUPE10_MASK 0x30u
emilmont	2:e9a661555b58	1303	#define LLWU_PE3_WUPE10_SHIFT 4
emilmont	2:e9a661555b58	1304	#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
emilmont	2:e9a661555b58	1305	#define LLWU_PE3_WUPE11_MASK 0xC0u
emilmont	2:e9a661555b58	1306	#define LLWU_PE3_WUPE11_SHIFT 6
emilmont	2:e9a661555b58	1307	#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
emilmont	2:e9a661555b58	1308	/* PE4 Bit Fields */
emilmont	2:e9a661555b58	1309	#define LLWU_PE4_WUPE12_MASK 0x3u
emilmont	2:e9a661555b58	1310	#define LLWU_PE4_WUPE12_SHIFT 0
emilmont	2:e9a661555b58	1311	#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
emilmont	2:e9a661555b58	1312	#define LLWU_PE4_WUPE13_MASK 0xCu
emilmont	2:e9a661555b58	1313	#define LLWU_PE4_WUPE13_SHIFT 2
emilmont	2:e9a661555b58	1314	#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
emilmont	2:e9a661555b58	1315	#define LLWU_PE4_WUPE14_MASK 0x30u
emilmont	2:e9a661555b58	1316	#define LLWU_PE4_WUPE14_SHIFT 4
emilmont	2:e9a661555b58	1317	#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
emilmont	2:e9a661555b58	1318	#define LLWU_PE4_WUPE15_MASK 0xC0u
emilmont	2:e9a661555b58	1319	#define LLWU_PE4_WUPE15_SHIFT 6
emilmont	2:e9a661555b58	1320	#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
emilmont	2:e9a661555b58	1321	/* ME Bit Fields */
emilmont	2:e9a661555b58	1322	#define LLWU_ME_WUME0_MASK 0x1u
emilmont	2:e9a661555b58	1323	#define LLWU_ME_WUME0_SHIFT 0
emilmont	2:e9a661555b58	1324	#define LLWU_ME_WUME1_MASK 0x2u
emilmont	2:e9a661555b58	1325	#define LLWU_ME_WUME1_SHIFT 1
emilmont	2:e9a661555b58	1326	#define LLWU_ME_WUME2_MASK 0x4u
emilmont	2:e9a661555b58	1327	#define LLWU_ME_WUME2_SHIFT 2
emilmont	2:e9a661555b58	1328	#define LLWU_ME_WUME3_MASK 0x8u
emilmont	2:e9a661555b58	1329	#define LLWU_ME_WUME3_SHIFT 3
emilmont	2:e9a661555b58	1330	#define LLWU_ME_WUME4_MASK 0x10u
emilmont	2:e9a661555b58	1331	#define LLWU_ME_WUME4_SHIFT 4
emilmont	2:e9a661555b58	1332	#define LLWU_ME_WUME5_MASK 0x20u
emilmont	2:e9a661555b58	1333	#define LLWU_ME_WUME5_SHIFT 5
emilmont	2:e9a661555b58	1334	#define LLWU_ME_WUME6_MASK 0x40u
emilmont	2:e9a661555b58	1335	#define LLWU_ME_WUME6_SHIFT 6
emilmont	2:e9a661555b58	1336	#define LLWU_ME_WUME7_MASK 0x80u
emilmont	2:e9a661555b58	1337	#define LLWU_ME_WUME7_SHIFT 7
emilmont	2:e9a661555b58	1338	/* F1 Bit Fields */
emilmont	2:e9a661555b58	1339	#define LLWU_F1_WUF0_MASK 0x1u
emilmont	2:e9a661555b58	1340	#define LLWU_F1_WUF0_SHIFT 0
emilmont	2:e9a661555b58	1341	#define LLWU_F1_WUF1_MASK 0x2u
emilmont	2:e9a661555b58	1342	#define LLWU_F1_WUF1_SHIFT 1
emilmont	2:e9a661555b58	1343	#define LLWU_F1_WUF2_MASK 0x4u
emilmont	2:e9a661555b58	1344	#define LLWU_F1_WUF2_SHIFT 2
emilmont	2:e9a661555b58	1345	#define LLWU_F1_WUF3_MASK 0x8u
emilmont	2:e9a661555b58	1346	#define LLWU_F1_WUF3_SHIFT 3
emilmont	2:e9a661555b58	1347	#define LLWU_F1_WUF4_MASK 0x10u
emilmont	2:e9a661555b58	1348	#define LLWU_F1_WUF4_SHIFT 4
emilmont	2:e9a661555b58	1349	#define LLWU_F1_WUF5_MASK 0x20u
emilmont	2:e9a661555b58	1350	#define LLWU_F1_WUF5_SHIFT 5
emilmont	2:e9a661555b58	1351	#define LLWU_F1_WUF6_MASK 0x40u
emilmont	2:e9a661555b58	1352	#define LLWU_F1_WUF6_SHIFT 6
emilmont	2:e9a661555b58	1353	#define LLWU_F1_WUF7_MASK 0x80u
emilmont	2:e9a661555b58	1354	#define LLWU_F1_WUF7_SHIFT 7
emilmont	2:e9a661555b58	1355	/* F2 Bit Fields */
emilmont	2:e9a661555b58	1356	#define LLWU_F2_WUF8_MASK 0x1u
emilmont	2:e9a661555b58	1357	#define LLWU_F2_WUF8_SHIFT 0
emilmont	2:e9a661555b58	1358	#define LLWU_F2_WUF9_MASK 0x2u
emilmont	2:e9a661555b58	1359	#define LLWU_F2_WUF9_SHIFT 1
emilmont	2:e9a661555b58	1360	#define LLWU_F2_WUF10_MASK 0x4u
emilmont	2:e9a661555b58	1361	#define LLWU_F2_WUF10_SHIFT 2
emilmont	2:e9a661555b58	1362	#define LLWU_F2_WUF11_MASK 0x8u
emilmont	2:e9a661555b58	1363	#define LLWU_F2_WUF11_SHIFT 3
emilmont	2:e9a661555b58	1364	#define LLWU_F2_WUF12_MASK 0x10u
emilmont	2:e9a661555b58	1365	#define LLWU_F2_WUF12_SHIFT 4
emilmont	2:e9a661555b58	1366	#define LLWU_F2_WUF13_MASK 0x20u
emilmont	2:e9a661555b58	1367	#define LLWU_F2_WUF13_SHIFT 5
emilmont	2:e9a661555b58	1368	#define LLWU_F2_WUF14_MASK 0x40u
emilmont	2:e9a661555b58	1369	#define LLWU_F2_WUF14_SHIFT 6
emilmont	2:e9a661555b58	1370	#define LLWU_F2_WUF15_MASK 0x80u
emilmont	2:e9a661555b58	1371	#define LLWU_F2_WUF15_SHIFT 7
emilmont	2:e9a661555b58	1372	/* F3 Bit Fields */
emilmont	2:e9a661555b58	1373	#define LLWU_F3_MWUF0_MASK 0x1u
emilmont	2:e9a661555b58	1374	#define LLWU_F3_MWUF0_SHIFT 0
emilmont	2:e9a661555b58	1375	#define LLWU_F3_MWUF1_MASK 0x2u
emilmont	2:e9a661555b58	1376	#define LLWU_F3_MWUF1_SHIFT 1
emilmont	2:e9a661555b58	1377	#define LLWU_F3_MWUF2_MASK 0x4u
emilmont	2:e9a661555b58	1378	#define LLWU_F3_MWUF2_SHIFT 2
emilmont	2:e9a661555b58	1379	#define LLWU_F3_MWUF3_MASK 0x8u
emilmont	2:e9a661555b58	1380	#define LLWU_F3_MWUF3_SHIFT 3
emilmont	2:e9a661555b58	1381	#define LLWU_F3_MWUF4_MASK 0x10u
emilmont	2:e9a661555b58	1382	#define LLWU_F3_MWUF4_SHIFT 4
emilmont	2:e9a661555b58	1383	#define LLWU_F3_MWUF5_MASK 0x20u
emilmont	2:e9a661555b58	1384	#define LLWU_F3_MWUF5_SHIFT 5
emilmont	2:e9a661555b58	1385	#define LLWU_F3_MWUF6_MASK 0x40u
emilmont	2:e9a661555b58	1386	#define LLWU_F3_MWUF6_SHIFT 6
emilmont	2:e9a661555b58	1387	#define LLWU_F3_MWUF7_MASK 0x80u
emilmont	2:e9a661555b58	1388	#define LLWU_F3_MWUF7_SHIFT 7
emilmont	2:e9a661555b58	1389	/* FILT1 Bit Fields */
emilmont	2:e9a661555b58	1390	#define LLWU_FILT1_FILTSEL_MASK 0xFu
emilmont	2:e9a661555b58	1391	#define LLWU_FILT1_FILTSEL_SHIFT 0
emilmont	2:e9a661555b58	1392	#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
emilmont	2:e9a661555b58	1393	#define LLWU_FILT1_FILTE_MASK 0x60u
emilmont	2:e9a661555b58	1394	#define LLWU_FILT1_FILTE_SHIFT 5
emilmont	2:e9a661555b58	1395	#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
emilmont	2:e9a661555b58	1396	#define LLWU_FILT1_FILTF_MASK 0x80u
emilmont	2:e9a661555b58	1397	#define LLWU_FILT1_FILTF_SHIFT 7
emilmont	2:e9a661555b58	1398	/* FILT2 Bit Fields */
emilmont	2:e9a661555b58	1399	#define LLWU_FILT2_FILTSEL_MASK 0xFu
emilmont	2:e9a661555b58	1400	#define LLWU_FILT2_FILTSEL_SHIFT 0
emilmont	2:e9a661555b58	1401	#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
emilmont	2:e9a661555b58	1402	#define LLWU_FILT2_FILTE_MASK 0x60u
emilmont	2:e9a661555b58	1403	#define LLWU_FILT2_FILTE_SHIFT 5
emilmont	2:e9a661555b58	1404	#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
emilmont	2:e9a661555b58	1405	#define LLWU_FILT2_FILTF_MASK 0x80u
emilmont	2:e9a661555b58	1406	#define LLWU_FILT2_FILTF_SHIFT 7
emilmont	2:e9a661555b58	1407
emilmont	2:e9a661555b58	1408	/**
emilmont	2:e9a661555b58	1409	* @}
emilmont	2:e9a661555b58	1410	/ / end of group LLWU_Register_Masks */
emilmont	2:e9a661555b58	1411
emilmont	2:e9a661555b58	1412
emilmont	2:e9a661555b58	1413	/* LLWU - Peripheral instance base addresses */
emilmont	2:e9a661555b58	1414	/** Peripheral LLWU base address */
emilmont	2:e9a661555b58	1415	#define LLWU_BASE (0x4007C000u)
emilmont	2:e9a661555b58	1416	/** Peripheral LLWU base pointer */
emilmont	2:e9a661555b58	1417	#define LLWU ((LLWU_Type *)LLWU_BASE)
emilmont	2:e9a661555b58	1418	/** Array initializer of LLWU peripheral base pointers */
emilmont	2:e9a661555b58	1419	#define LLWU_BASES { LLWU }
emilmont	2:e9a661555b58	1420
emilmont	2:e9a661555b58	1421	/**
emilmont	2:e9a661555b58	1422	* @}
emilmont	2:e9a661555b58	1423	/ / end of group LLWU_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	1424
emilmont	2:e9a661555b58	1425
emilmont	2:e9a661555b58	1426	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1427	-- LPTMR Peripheral Access Layer
emilmont	2:e9a661555b58	1428	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1429
emilmont	2:e9a661555b58	1430	/**
emilmont	2:e9a661555b58	1431	* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
emilmont	2:e9a661555b58	1432	* @{
emilmont	2:e9a661555b58	1433	*/
emilmont	2:e9a661555b58	1434
emilmont	2:e9a661555b58	1435	/** LPTMR - Register Layout Typedef */
emilmont	2:e9a661555b58	1436	typedef struct {
emilmont	2:e9a661555b58	1437	__IO uint32_t CSR; /*< Low Power Timer Control Status Register, offset: 0x0 /
emilmont	2:e9a661555b58	1438	__IO uint32_t PSR; /*< Low Power Timer Prescale Register, offset: 0x4 /
emilmont	2:e9a661555b58	1439	__IO uint32_t CMR; /*< Low Power Timer Compare Register, offset: 0x8 /
emilmont	2:e9a661555b58	1440	__I uint32_t CNR; /*< Low Power Timer Counter Register, offset: 0xC /
emilmont	2:e9a661555b58	1441	} LPTMR_Type;
emilmont	2:e9a661555b58	1442
emilmont	2:e9a661555b58	1443	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1444	-- LPTMR Register Masks
emilmont	2:e9a661555b58	1445	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1446
emilmont	2:e9a661555b58	1447	/**
emilmont	2:e9a661555b58	1448	* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
emilmont	2:e9a661555b58	1449	* @{
emilmont	2:e9a661555b58	1450	*/
emilmont	2:e9a661555b58	1451
emilmont	2:e9a661555b58	1452	/* CSR Bit Fields */
emilmont	2:e9a661555b58	1453	#define LPTMR_CSR_TEN_MASK 0x1u
emilmont	2:e9a661555b58	1454	#define LPTMR_CSR_TEN_SHIFT 0
emilmont	2:e9a661555b58	1455	#define LPTMR_CSR_TMS_MASK 0x2u
emilmont	2:e9a661555b58	1456	#define LPTMR_CSR_TMS_SHIFT 1
emilmont	2:e9a661555b58	1457	#define LPTMR_CSR_TFC_MASK 0x4u
emilmont	2:e9a661555b58	1458	#define LPTMR_CSR_TFC_SHIFT 2
emilmont	2:e9a661555b58	1459	#define LPTMR_CSR_TPP_MASK 0x8u
emilmont	2:e9a661555b58	1460	#define LPTMR_CSR_TPP_SHIFT 3
emilmont	2:e9a661555b58	1461	#define LPTMR_CSR_TPS_MASK 0x30u
emilmont	2:e9a661555b58	1462	#define LPTMR_CSR_TPS_SHIFT 4
emilmont	2:e9a661555b58	1463	#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
emilmont	2:e9a661555b58	1464	#define LPTMR_CSR_TIE_MASK 0x40u
emilmont	2:e9a661555b58	1465	#define LPTMR_CSR_TIE_SHIFT 6
emilmont	2:e9a661555b58	1466	#define LPTMR_CSR_TCF_MASK 0x80u
emilmont	2:e9a661555b58	1467	#define LPTMR_CSR_TCF_SHIFT 7
emilmont	2:e9a661555b58	1468	/* PSR Bit Fields */
emilmont	2:e9a661555b58	1469	#define LPTMR_PSR_PCS_MASK 0x3u
emilmont	2:e9a661555b58	1470	#define LPTMR_PSR_PCS_SHIFT 0
emilmont	2:e9a661555b58	1471	#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
emilmont	2:e9a661555b58	1472	#define LPTMR_PSR_PBYP_MASK 0x4u
emilmont	2:e9a661555b58	1473	#define LPTMR_PSR_PBYP_SHIFT 2
emilmont	2:e9a661555b58	1474	#define LPTMR_PSR_PRESCALE_MASK 0x78u
emilmont	2:e9a661555b58	1475	#define LPTMR_PSR_PRESCALE_SHIFT 3
emilmont	2:e9a661555b58	1476	#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
emilmont	2:e9a661555b58	1477	/* CMR Bit Fields */
emilmont	2:e9a661555b58	1478	#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
emilmont	2:e9a661555b58	1479	#define LPTMR_CMR_COMPARE_SHIFT 0
emilmont	2:e9a661555b58	1480	#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
emilmont	2:e9a661555b58	1481	/* CNR Bit Fields */
emilmont	2:e9a661555b58	1482	#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
emilmont	2:e9a661555b58	1483	#define LPTMR_CNR_COUNTER_SHIFT 0
emilmont	2:e9a661555b58	1484	#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
emilmont	2:e9a661555b58	1485
emilmont	2:e9a661555b58	1486	/**
emilmont	2:e9a661555b58	1487	* @}
emilmont	2:e9a661555b58	1488	/ / end of group LPTMR_Register_Masks */
emilmont	2:e9a661555b58	1489
emilmont	2:e9a661555b58	1490
emilmont	2:e9a661555b58	1491	/* LPTMR - Peripheral instance base addresses */
emilmont	2:e9a661555b58	1492	/** Peripheral LPTMR0 base address */
emilmont	2:e9a661555b58	1493	#define LPTMR0_BASE (0x40040000u)
emilmont	2:e9a661555b58	1494	/** Peripheral LPTMR0 base pointer */
emilmont	2:e9a661555b58	1495	#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
emilmont	2:e9a661555b58	1496	/** Array initializer of LPTMR peripheral base pointers */
emilmont	2:e9a661555b58	1497	#define LPTMR_BASES { LPTMR0 }
emilmont	2:e9a661555b58	1498
emilmont	2:e9a661555b58	1499	/**
emilmont	2:e9a661555b58	1500	* @}
emilmont	2:e9a661555b58	1501	/ / end of group LPTMR_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	1502
emilmont	2:e9a661555b58	1503
emilmont	2:e9a661555b58	1504	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1505	-- MCG Peripheral Access Layer
emilmont	2:e9a661555b58	1506	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1507
emilmont	2:e9a661555b58	1508	/**
emilmont	2:e9a661555b58	1509	* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
emilmont	2:e9a661555b58	1510	* @{
emilmont	2:e9a661555b58	1511	*/
emilmont	2:e9a661555b58	1512
emilmont	2:e9a661555b58	1513	/** MCG - Register Layout Typedef */
emilmont	2:e9a661555b58	1514	typedef struct {
emilmont	2:e9a661555b58	1515	__IO uint8_t C1; /*< MCG Control 1 Register, offset: 0x0 /
emilmont	2:e9a661555b58	1516	__IO uint8_t C2; /*< MCG Control 2 Register, offset: 0x1 /
emilmont	2:e9a661555b58	1517	__IO uint8_t C3; /*< MCG Control 3 Register, offset: 0x2 /
emilmont	2:e9a661555b58	1518	__IO uint8_t C4; /*< MCG Control 4 Register, offset: 0x3 /
emilmont	2:e9a661555b58	1519	__IO uint8_t C5; /*< MCG Control 5 Register, offset: 0x4 /
emilmont	2:e9a661555b58	1520	__IO uint8_t C6; /*< MCG Control 6 Register, offset: 0x5 /
emilmont	2:e9a661555b58	1521	__I uint8_t S; /*< MCG Status Register, offset: 0x6 /
emilmont	2:e9a661555b58	1522	uint8_t RESERVED_0[1];
emilmont	2:e9a661555b58	1523	__IO uint8_t SC; /*< MCG Status and Control Register, offset: 0x8 /
emilmont	2:e9a661555b58	1524	uint8_t RESERVED_1[1];
emilmont	2:e9a661555b58	1525	__IO uint8_t ATCVH; /*< MCG Auto Trim Compare Value High Register, offset: 0xA /
emilmont	2:e9a661555b58	1526	__IO uint8_t ATCVL; /*< MCG Auto Trim Compare Value Low Register, offset: 0xB /
emilmont	2:e9a661555b58	1527	__I uint8_t C7; /*< MCG Control 7 Register, offset: 0xC /
emilmont	2:e9a661555b58	1528	__IO uint8_t C8; /*< MCG Control 8 Register, offset: 0xD /
emilmont	2:e9a661555b58	1529	__I uint8_t C9; /*< MCG Control 9 Register, offset: 0xE /
emilmont	2:e9a661555b58	1530	__I uint8_t C10; /*< MCG Control 10 Register, offset: 0xF /
emilmont	2:e9a661555b58	1531	} MCG_Type;
emilmont	2:e9a661555b58	1532
emilmont	2:e9a661555b58	1533	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1534	-- MCG Register Masks
emilmont	2:e9a661555b58	1535	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1536
emilmont	2:e9a661555b58	1537	/**
emilmont	2:e9a661555b58	1538	* @addtogroup MCG_Register_Masks MCG Register Masks
emilmont	2:e9a661555b58	1539	* @{
emilmont	2:e9a661555b58	1540	*/
emilmont	2:e9a661555b58	1541
emilmont	2:e9a661555b58	1542	/* C1 Bit Fields */
emilmont	2:e9a661555b58	1543	#define MCG_C1_IREFSTEN_MASK 0x1u
emilmont	2:e9a661555b58	1544	#define MCG_C1_IREFSTEN_SHIFT 0
emilmont	2:e9a661555b58	1545	#define MCG_C1_IRCLKEN_MASK 0x2u
emilmont	2:e9a661555b58	1546	#define MCG_C1_IRCLKEN_SHIFT 1
emilmont	2:e9a661555b58	1547	#define MCG_C1_IREFS_MASK 0x4u
emilmont	2:e9a661555b58	1548	#define MCG_C1_IREFS_SHIFT 2
emilmont	2:e9a661555b58	1549	#define MCG_C1_FRDIV_MASK 0x38u
emilmont	2:e9a661555b58	1550	#define MCG_C1_FRDIV_SHIFT 3
emilmont	2:e9a661555b58	1551	#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
emilmont	2:e9a661555b58	1552	#define MCG_C1_CLKS_MASK 0xC0u
emilmont	2:e9a661555b58	1553	#define MCG_C1_CLKS_SHIFT 6
emilmont	2:e9a661555b58	1554	#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
emilmont	2:e9a661555b58	1555	/* C2 Bit Fields */
emilmont	2:e9a661555b58	1556	#define MCG_C2_IRCS_MASK 0x1u
emilmont	2:e9a661555b58	1557	#define MCG_C2_IRCS_SHIFT 0
emilmont	2:e9a661555b58	1558	#define MCG_C2_LP_MASK 0x2u
emilmont	2:e9a661555b58	1559	#define MCG_C2_LP_SHIFT 1
emilmont	2:e9a661555b58	1560	#define MCG_C2_EREFS0_MASK 0x4u
emilmont	2:e9a661555b58	1561	#define MCG_C2_EREFS0_SHIFT 2
emilmont	2:e9a661555b58	1562	#define MCG_C2_HGO0_MASK 0x8u
emilmont	2:e9a661555b58	1563	#define MCG_C2_HGO0_SHIFT 3
emilmont	2:e9a661555b58	1564	#define MCG_C2_RANGE0_MASK 0x30u
emilmont	2:e9a661555b58	1565	#define MCG_C2_RANGE0_SHIFT 4
emilmont	2:e9a661555b58	1566	#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
emilmont	2:e9a661555b58	1567	#define MCG_C2_LOCRE0_MASK 0x80u
emilmont	2:e9a661555b58	1568	#define MCG_C2_LOCRE0_SHIFT 7
emilmont	2:e9a661555b58	1569	/* C3 Bit Fields */
emilmont	2:e9a661555b58	1570	#define MCG_C3_SCTRIM_MASK 0xFFu
emilmont	2:e9a661555b58	1571	#define MCG_C3_SCTRIM_SHIFT 0
emilmont	2:e9a661555b58	1572	#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
emilmont	2:e9a661555b58	1573	/* C4 Bit Fields */
emilmont	2:e9a661555b58	1574	#define MCG_C4_SCFTRIM_MASK 0x1u
emilmont	2:e9a661555b58	1575	#define MCG_C4_SCFTRIM_SHIFT 0
emilmont	2:e9a661555b58	1576	#define MCG_C4_FCTRIM_MASK 0x1Eu
emilmont	2:e9a661555b58	1577	#define MCG_C4_FCTRIM_SHIFT 1
emilmont	2:e9a661555b58	1578	#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
emilmont	2:e9a661555b58	1579	#define MCG_C4_DRST_DRS_MASK 0x60u
emilmont	2:e9a661555b58	1580	#define MCG_C4_DRST_DRS_SHIFT 5
emilmont	2:e9a661555b58	1581	#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
emilmont	2:e9a661555b58	1582	#define MCG_C4_DMX32_MASK 0x80u
emilmont	2:e9a661555b58	1583	#define MCG_C4_DMX32_SHIFT 7
emilmont	2:e9a661555b58	1584	/* C5 Bit Fields */
emilmont	2:e9a661555b58	1585	#define MCG_C5_PRDIV0_MASK 0x1Fu
emilmont	2:e9a661555b58	1586	#define MCG_C5_PRDIV0_SHIFT 0
emilmont	2:e9a661555b58	1587	#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
emilmont	2:e9a661555b58	1588	#define MCG_C5_PLLSTEN0_MASK 0x20u
emilmont	2:e9a661555b58	1589	#define MCG_C5_PLLSTEN0_SHIFT 5
emilmont	2:e9a661555b58	1590	#define MCG_C5_PLLCLKEN0_MASK 0x40u
emilmont	2:e9a661555b58	1591	#define MCG_C5_PLLCLKEN0_SHIFT 6
emilmont	2:e9a661555b58	1592	/* C6 Bit Fields */
emilmont	2:e9a661555b58	1593	#define MCG_C6_VDIV0_MASK 0x1Fu
emilmont	2:e9a661555b58	1594	#define MCG_C6_VDIV0_SHIFT 0
emilmont	2:e9a661555b58	1595	#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
emilmont	2:e9a661555b58	1596	#define MCG_C6_CME0_MASK 0x20u
emilmont	2:e9a661555b58	1597	#define MCG_C6_CME0_SHIFT 5
emilmont	2:e9a661555b58	1598	#define MCG_C6_PLLS_MASK 0x40u
emilmont	2:e9a661555b58	1599	#define MCG_C6_PLLS_SHIFT 6
emilmont	2:e9a661555b58	1600	#define MCG_C6_LOLIE0_MASK 0x80u
emilmont	2:e9a661555b58	1601	#define MCG_C6_LOLIE0_SHIFT 7
emilmont	2:e9a661555b58	1602	/* S Bit Fields */
emilmont	2:e9a661555b58	1603	#define MCG_S_IRCST_MASK 0x1u
emilmont	2:e9a661555b58	1604	#define MCG_S_IRCST_SHIFT 0
emilmont	2:e9a661555b58	1605	#define MCG_S_OSCINIT0_MASK 0x2u
emilmont	2:e9a661555b58	1606	#define MCG_S_OSCINIT0_SHIFT 1
emilmont	2:e9a661555b58	1607	#define MCG_S_CLKST_MASK 0xCu
emilmont	2:e9a661555b58	1608	#define MCG_S_CLKST_SHIFT 2
emilmont	2:e9a661555b58	1609	#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
emilmont	2:e9a661555b58	1610	#define MCG_S_IREFST_MASK 0x10u
emilmont	2:e9a661555b58	1611	#define MCG_S_IREFST_SHIFT 4
emilmont	2:e9a661555b58	1612	#define MCG_S_PLLST_MASK 0x20u
emilmont	2:e9a661555b58	1613	#define MCG_S_PLLST_SHIFT 5
emilmont	2:e9a661555b58	1614	#define MCG_S_LOCK0_MASK 0x40u
emilmont	2:e9a661555b58	1615	#define MCG_S_LOCK0_SHIFT 6
emilmont	2:e9a661555b58	1616	#define MCG_S_LOLS_MASK 0x80u
emilmont	2:e9a661555b58	1617	#define MCG_S_LOLS_SHIFT 7
emilmont	2:e9a661555b58	1618	/* SC Bit Fields */
emilmont	2:e9a661555b58	1619	#define MCG_SC_LOCS0_MASK 0x1u
emilmont	2:e9a661555b58	1620	#define MCG_SC_LOCS0_SHIFT 0
emilmont	2:e9a661555b58	1621	#define MCG_SC_FCRDIV_MASK 0xEu
emilmont	2:e9a661555b58	1622	#define MCG_SC_FCRDIV_SHIFT 1
emilmont	2:e9a661555b58	1623	#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
emilmont	2:e9a661555b58	1624	#define MCG_SC_FLTPRSRV_MASK 0x10u
emilmont	2:e9a661555b58	1625	#define MCG_SC_FLTPRSRV_SHIFT 4
emilmont	2:e9a661555b58	1626	#define MCG_SC_ATMF_MASK 0x20u
emilmont	2:e9a661555b58	1627	#define MCG_SC_ATMF_SHIFT 5
emilmont	2:e9a661555b58	1628	#define MCG_SC_ATMS_MASK 0x40u
emilmont	2:e9a661555b58	1629	#define MCG_SC_ATMS_SHIFT 6
emilmont	2:e9a661555b58	1630	#define MCG_SC_ATME_MASK 0x80u
emilmont	2:e9a661555b58	1631	#define MCG_SC_ATME_SHIFT 7
emilmont	2:e9a661555b58	1632	/* ATCVH Bit Fields */
emilmont	2:e9a661555b58	1633	#define MCG_ATCVH_ATCVH_MASK 0xFFu
emilmont	2:e9a661555b58	1634	#define MCG_ATCVH_ATCVH_SHIFT 0
emilmont	2:e9a661555b58	1635	#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
emilmont	2:e9a661555b58	1636	/* ATCVL Bit Fields */
emilmont	2:e9a661555b58	1637	#define MCG_ATCVL_ATCVL_MASK 0xFFu
emilmont	2:e9a661555b58	1638	#define MCG_ATCVL_ATCVL_SHIFT 0
emilmont	2:e9a661555b58	1639	#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
emilmont	2:e9a661555b58	1640	/* C8 Bit Fields */
emilmont	2:e9a661555b58	1641	#define MCG_C8_LOLRE_MASK 0x40u
emilmont	2:e9a661555b58	1642	#define MCG_C8_LOLRE_SHIFT 6
emilmont	2:e9a661555b58	1643
emilmont	2:e9a661555b58	1644	/**
emilmont	2:e9a661555b58	1645	* @}
emilmont	2:e9a661555b58	1646	/ / end of group MCG_Register_Masks */
emilmont	2:e9a661555b58	1647
emilmont	2:e9a661555b58	1648
emilmont	2:e9a661555b58	1649	/* MCG - Peripheral instance base addresses */
emilmont	2:e9a661555b58	1650	/** Peripheral MCG base address */
emilmont	2:e9a661555b58	1651	#define MCG_BASE (0x40064000u)
emilmont	2:e9a661555b58	1652	/** Peripheral MCG base pointer */
emilmont	2:e9a661555b58	1653	#define MCG ((MCG_Type *)MCG_BASE)
emilmont	2:e9a661555b58	1654	/** Array initializer of MCG peripheral base pointers */
emilmont	2:e9a661555b58	1655	#define MCG_BASES { MCG }
emilmont	2:e9a661555b58	1656
emilmont	2:e9a661555b58	1657	/**
emilmont	2:e9a661555b58	1658	* @}
emilmont	2:e9a661555b58	1659	/ / end of group MCG_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	1660
emilmont	2:e9a661555b58	1661
emilmont	2:e9a661555b58	1662	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1663	-- MCM Peripheral Access Layer
emilmont	2:e9a661555b58	1664	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1665
emilmont	2:e9a661555b58	1666	/**
emilmont	2:e9a661555b58	1667	* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
emilmont	2:e9a661555b58	1668	* @{
emilmont	2:e9a661555b58	1669	*/
emilmont	2:e9a661555b58	1670
emilmont	2:e9a661555b58	1671	/** MCM - Register Layout Typedef */
emilmont	2:e9a661555b58	1672	typedef struct {
emilmont	2:e9a661555b58	1673	uint8_t RESERVED_0[8];
emilmont	2:e9a661555b58	1674	__I uint16_t PLASC; /*< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 /
emilmont	2:e9a661555b58	1675	__I uint16_t PLAMC; /*< Crossbar Switch (AXBS) Master Configuration, offset: 0xA /
emilmont	2:e9a661555b58	1676	__IO uint32_t PLACR; /*< Platform Control Register, offset: 0xC /
emilmont	2:e9a661555b58	1677	uint8_t RESERVED_1[48];
emilmont	2:e9a661555b58	1678	__IO uint32_t CPO; /*< Compute Operation Control Register, offset: 0x40 /
emilmont	2:e9a661555b58	1679	} MCM_Type;
emilmont	2:e9a661555b58	1680
emilmont	2:e9a661555b58	1681	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1682	-- MCM Register Masks
emilmont	2:e9a661555b58	1683	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1684
emilmont	2:e9a661555b58	1685	/**
emilmont	2:e9a661555b58	1686	* @addtogroup MCM_Register_Masks MCM Register Masks
emilmont	2:e9a661555b58	1687	* @{
emilmont	2:e9a661555b58	1688	*/
emilmont	2:e9a661555b58	1689
emilmont	2:e9a661555b58	1690	/* PLASC Bit Fields */
emilmont	2:e9a661555b58	1691	#define MCM_PLASC_ASC_MASK 0xFFu
emilmont	2:e9a661555b58	1692	#define MCM_PLASC_ASC_SHIFT 0
emilmont	2:e9a661555b58	1693	#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
emilmont	2:e9a661555b58	1694	/* PLAMC Bit Fields */
emilmont	2:e9a661555b58	1695	#define MCM_PLAMC_AMC_MASK 0xFFu
emilmont	2:e9a661555b58	1696	#define MCM_PLAMC_AMC_SHIFT 0
emilmont	2:e9a661555b58	1697	#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
emilmont	2:e9a661555b58	1698	/* PLACR Bit Fields */
emilmont	2:e9a661555b58	1699	#define MCM_PLACR_ARB_MASK 0x200u
emilmont	2:e9a661555b58	1700	#define MCM_PLACR_ARB_SHIFT 9
emilmont	2:e9a661555b58	1701	#define MCM_PLACR_CFCC_MASK 0x400u
emilmont	2:e9a661555b58	1702	#define MCM_PLACR_CFCC_SHIFT 10
emilmont	2:e9a661555b58	1703	#define MCM_PLACR_DFCDA_MASK 0x800u
emilmont	2:e9a661555b58	1704	#define MCM_PLACR_DFCDA_SHIFT 11
emilmont	2:e9a661555b58	1705	#define MCM_PLACR_DFCIC_MASK 0x1000u
emilmont	2:e9a661555b58	1706	#define MCM_PLACR_DFCIC_SHIFT 12
emilmont	2:e9a661555b58	1707	#define MCM_PLACR_DFCC_MASK 0x2000u
emilmont	2:e9a661555b58	1708	#define MCM_PLACR_DFCC_SHIFT 13
emilmont	2:e9a661555b58	1709	#define MCM_PLACR_EFDS_MASK 0x4000u
emilmont	2:e9a661555b58	1710	#define MCM_PLACR_EFDS_SHIFT 14
emilmont	2:e9a661555b58	1711	#define MCM_PLACR_DFCS_MASK 0x8000u
emilmont	2:e9a661555b58	1712	#define MCM_PLACR_DFCS_SHIFT 15
emilmont	2:e9a661555b58	1713	#define MCM_PLACR_ESFC_MASK 0x10000u
emilmont	2:e9a661555b58	1714	#define MCM_PLACR_ESFC_SHIFT 16
emilmont	2:e9a661555b58	1715	/* CPO Bit Fields */
emilmont	2:e9a661555b58	1716	#define MCM_CPO_CPOREQ_MASK 0x1u
emilmont	2:e9a661555b58	1717	#define MCM_CPO_CPOREQ_SHIFT 0
emilmont	2:e9a661555b58	1718	#define MCM_CPO_CPOACK_MASK 0x2u
emilmont	2:e9a661555b58	1719	#define MCM_CPO_CPOACK_SHIFT 1
emilmont	2:e9a661555b58	1720	#define MCM_CPO_CPOWOI_MASK 0x4u
emilmont	2:e9a661555b58	1721	#define MCM_CPO_CPOWOI_SHIFT 2
emilmont	2:e9a661555b58	1722
emilmont	2:e9a661555b58	1723	/**
emilmont	2:e9a661555b58	1724	* @}
emilmont	2:e9a661555b58	1725	/ / end of group MCM_Register_Masks */
emilmont	2:e9a661555b58	1726
emilmont	2:e9a661555b58	1727
emilmont	2:e9a661555b58	1728	/* MCM - Peripheral instance base addresses */
emilmont	2:e9a661555b58	1729	/** Peripheral MCM base address */
emilmont	2:e9a661555b58	1730	#define MCM_BASE (0xF0003000u)
emilmont	2:e9a661555b58	1731	/** Peripheral MCM base pointer */
emilmont	2:e9a661555b58	1732	#define MCM ((MCM_Type *)MCM_BASE)
emilmont	2:e9a661555b58	1733	/** Array initializer of MCM peripheral base pointers */
emilmont	2:e9a661555b58	1734	#define MCM_BASES { MCM }
emilmont	2:e9a661555b58	1735
emilmont	2:e9a661555b58	1736	/**
emilmont	2:e9a661555b58	1737	* @}
emilmont	2:e9a661555b58	1738	/ / end of group MCM_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	1739
emilmont	2:e9a661555b58	1740
emilmont	2:e9a661555b58	1741	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1742	-- MTB Peripheral Access Layer
emilmont	2:e9a661555b58	1743	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1744
emilmont	2:e9a661555b58	1745	/**
emilmont	2:e9a661555b58	1746	* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
emilmont	2:e9a661555b58	1747	* @{
emilmont	2:e9a661555b58	1748	*/
emilmont	2:e9a661555b58	1749
emilmont	2:e9a661555b58	1750	/** MTB - Register Layout Typedef */
emilmont	2:e9a661555b58	1751	typedef struct {
emilmont	2:e9a661555b58	1752	__IO uint32_t POSITION; /*< MTB Position Register, offset: 0x0 /
emilmont	2:e9a661555b58	1753	__IO uint32_t MASTER; /*< MTB Master Register, offset: 0x4 /
emilmont	2:e9a661555b58	1754	__IO uint32_t FLOW; /*< MTB Flow Register, offset: 0x8 /
emilmont	2:e9a661555b58	1755	__I uint32_t BASE; /*< MTB Base Register, offset: 0xC /
emilmont	2:e9a661555b58	1756	uint8_t RESERVED_0[3824];
emilmont	2:e9a661555b58	1757	__I uint32_t MODECTRL; /*< Integration Mode Control Register, offset: 0xF00 /
emilmont	2:e9a661555b58	1758	uint8_t RESERVED_1[156];
emilmont	2:e9a661555b58	1759	__I uint32_t TAGSET; /*< Claim TAG Set Register, offset: 0xFA0 /
emilmont	2:e9a661555b58	1760	__I uint32_t TAGCLEAR; /*< Claim TAG Clear Register, offset: 0xFA4 /
emilmont	2:e9a661555b58	1761	uint8_t RESERVED_2[8];
emilmont	2:e9a661555b58	1762	__I uint32_t LOCKACCESS; /*< Lock Access Register, offset: 0xFB0 /
emilmont	2:e9a661555b58	1763	__I uint32_t LOCKSTAT; /*< Lock Status Register, offset: 0xFB4 /
emilmont	2:e9a661555b58	1764	__I uint32_t AUTHSTAT; /*< Authentication Status Register, offset: 0xFB8 /
emilmont	2:e9a661555b58	1765	__I uint32_t DEVICEARCH; /*< Device Architecture Register, offset: 0xFBC /
emilmont	2:e9a661555b58	1766	uint8_t RESERVED_3[8];
emilmont	2:e9a661555b58	1767	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
emilmont	2:e9a661555b58	1768	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
emilmont	2:e9a661555b58	1769	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
emilmont	2:e9a661555b58	1770	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
emilmont	2:e9a661555b58	1771	} MTB_Type;
emilmont	2:e9a661555b58	1772
emilmont	2:e9a661555b58	1773	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1774	-- MTB Register Masks
emilmont	2:e9a661555b58	1775	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1776
emilmont	2:e9a661555b58	1777	/**
emilmont	2:e9a661555b58	1778	* @addtogroup MTB_Register_Masks MTB Register Masks
emilmont	2:e9a661555b58	1779	* @{
emilmont	2:e9a661555b58	1780	*/
emilmont	2:e9a661555b58	1781
emilmont	2:e9a661555b58	1782	/* POSITION Bit Fields */
emilmont	2:e9a661555b58	1783	#define MTB_POSITION_WRAP_MASK 0x4u
emilmont	2:e9a661555b58	1784	#define MTB_POSITION_WRAP_SHIFT 2
emilmont	2:e9a661555b58	1785	#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
emilmont	2:e9a661555b58	1786	#define MTB_POSITION_POINTER_SHIFT 3
emilmont	2:e9a661555b58	1787	#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
emilmont	2:e9a661555b58	1788	/* MASTER Bit Fields */
emilmont	2:e9a661555b58	1789	#define MTB_MASTER_MASK_MASK 0x1Fu
emilmont	2:e9a661555b58	1790	#define MTB_MASTER_MASK_SHIFT 0
emilmont	2:e9a661555b58	1791	#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
emilmont	2:e9a661555b58	1792	#define MTB_MASTER_TSTARTEN_MASK 0x20u
emilmont	2:e9a661555b58	1793	#define MTB_MASTER_TSTARTEN_SHIFT 5
emilmont	2:e9a661555b58	1794	#define MTB_MASTER_TSTOPEN_MASK 0x40u
emilmont	2:e9a661555b58	1795	#define MTB_MASTER_TSTOPEN_SHIFT 6
emilmont	2:e9a661555b58	1796	#define MTB_MASTER_SFRWPRIV_MASK 0x80u
emilmont	2:e9a661555b58	1797	#define MTB_MASTER_SFRWPRIV_SHIFT 7
emilmont	2:e9a661555b58	1798	#define MTB_MASTER_RAMPRIV_MASK 0x100u
emilmont	2:e9a661555b58	1799	#define MTB_MASTER_RAMPRIV_SHIFT 8
emilmont	2:e9a661555b58	1800	#define MTB_MASTER_HALTREQ_MASK 0x200u
emilmont	2:e9a661555b58	1801	#define MTB_MASTER_HALTREQ_SHIFT 9
emilmont	2:e9a661555b58	1802	#define MTB_MASTER_EN_MASK 0x80000000u
emilmont	2:e9a661555b58	1803	#define MTB_MASTER_EN_SHIFT 31
emilmont	2:e9a661555b58	1804	/* FLOW Bit Fields */
emilmont	2:e9a661555b58	1805	#define MTB_FLOW_AUTOSTOP_MASK 0x1u
emilmont	2:e9a661555b58	1806	#define MTB_FLOW_AUTOSTOP_SHIFT 0
emilmont	2:e9a661555b58	1807	#define MTB_FLOW_AUTOHALT_MASK 0x2u
emilmont	2:e9a661555b58	1808	#define MTB_FLOW_AUTOHALT_SHIFT 1
emilmont	2:e9a661555b58	1809	#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
emilmont	2:e9a661555b58	1810	#define MTB_FLOW_WATERMARK_SHIFT 3
emilmont	2:e9a661555b58	1811	#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
emilmont	2:e9a661555b58	1812	/* BASE Bit Fields */
emilmont	2:e9a661555b58	1813	#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1814	#define MTB_BASE_BASEADDR_SHIFT 0
emilmont	2:e9a661555b58	1815	#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
emilmont	2:e9a661555b58	1816	/* MODECTRL Bit Fields */
emilmont	2:e9a661555b58	1817	#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1818	#define MTB_MODECTRL_MODECTRL_SHIFT 0
emilmont	2:e9a661555b58	1819	#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
emilmont	2:e9a661555b58	1820	/* TAGSET Bit Fields */
emilmont	2:e9a661555b58	1821	#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1822	#define MTB_TAGSET_TAGSET_SHIFT 0
emilmont	2:e9a661555b58	1823	#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
emilmont	2:e9a661555b58	1824	/* TAGCLEAR Bit Fields */
emilmont	2:e9a661555b58	1825	#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1826	#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
emilmont	2:e9a661555b58	1827	#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
emilmont	2:e9a661555b58	1828	/* LOCKACCESS Bit Fields */
emilmont	2:e9a661555b58	1829	#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1830	#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
emilmont	2:e9a661555b58	1831	#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
emilmont	2:e9a661555b58	1832	/* LOCKSTAT Bit Fields */
emilmont	2:e9a661555b58	1833	#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1834	#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
emilmont	2:e9a661555b58	1835	#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
emilmont	2:e9a661555b58	1836	/* AUTHSTAT Bit Fields */
emilmont	2:e9a661555b58	1837	#define MTB_AUTHSTAT_BIT0_MASK 0x1u
emilmont	2:e9a661555b58	1838	#define MTB_AUTHSTAT_BIT0_SHIFT 0
emilmont	2:e9a661555b58	1839	#define MTB_AUTHSTAT_BIT1_MASK 0x2u
emilmont	2:e9a661555b58	1840	#define MTB_AUTHSTAT_BIT1_SHIFT 1
emilmont	2:e9a661555b58	1841	#define MTB_AUTHSTAT_BIT2_MASK 0x4u
emilmont	2:e9a661555b58	1842	#define MTB_AUTHSTAT_BIT2_SHIFT 2
emilmont	2:e9a661555b58	1843	#define MTB_AUTHSTAT_BIT3_MASK 0x8u
emilmont	2:e9a661555b58	1844	#define MTB_AUTHSTAT_BIT3_SHIFT 3
emilmont	2:e9a661555b58	1845	/* DEVICEARCH Bit Fields */
emilmont	2:e9a661555b58	1846	#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1847	#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
emilmont	2:e9a661555b58	1848	#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
emilmont	2:e9a661555b58	1849	/* DEVICECFG Bit Fields */
emilmont	2:e9a661555b58	1850	#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1851	#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
emilmont	2:e9a661555b58	1852	#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
emilmont	2:e9a661555b58	1853	/* DEVICETYPID Bit Fields */
emilmont	2:e9a661555b58	1854	#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1855	#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
emilmont	2:e9a661555b58	1856	#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
emilmont	2:e9a661555b58	1857	/* PERIPHID Bit Fields */
emilmont	2:e9a661555b58	1858	#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1859	#define MTB_PERIPHID_PERIPHID_SHIFT 0
emilmont	2:e9a661555b58	1860	#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
emilmont	2:e9a661555b58	1861	/* COMPID Bit Fields */
emilmont	2:e9a661555b58	1862	#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1863	#define MTB_COMPID_COMPID_SHIFT 0
emilmont	2:e9a661555b58	1864	#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
emilmont	2:e9a661555b58	1865
emilmont	2:e9a661555b58	1866	/**
emilmont	2:e9a661555b58	1867	* @}
emilmont	2:e9a661555b58	1868	/ / end of group MTB_Register_Masks */
emilmont	2:e9a661555b58	1869
emilmont	2:e9a661555b58	1870
emilmont	2:e9a661555b58	1871	/* MTB - Peripheral instance base addresses */
emilmont	2:e9a661555b58	1872	/** Peripheral MTB base address */
emilmont	2:e9a661555b58	1873	#define MTB_BASE (0xF0000000u)
emilmont	2:e9a661555b58	1874	/** Peripheral MTB base pointer */
emilmont	2:e9a661555b58	1875	#define MTB ((MTB_Type *)MTB_BASE)
emilmont	2:e9a661555b58	1876	/** Array initializer of MTB peripheral base pointers */
emilmont	2:e9a661555b58	1877	#define MTB_BASES { MTB }
emilmont	2:e9a661555b58	1878
emilmont	2:e9a661555b58	1879	/**
emilmont	2:e9a661555b58	1880	* @}
emilmont	2:e9a661555b58	1881	/ / end of group MTB_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	1882
emilmont	2:e9a661555b58	1883
emilmont	2:e9a661555b58	1884	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1885	-- MTBDWT Peripheral Access Layer
emilmont	2:e9a661555b58	1886	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1887
emilmont	2:e9a661555b58	1888	/**
emilmont	2:e9a661555b58	1889	* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
emilmont	2:e9a661555b58	1890	* @{
emilmont	2:e9a661555b58	1891	*/
emilmont	2:e9a661555b58	1892
emilmont	2:e9a661555b58	1893	/** MTBDWT - Register Layout Typedef */
emilmont	2:e9a661555b58	1894	typedef struct {
emilmont	2:e9a661555b58	1895	__I uint32_t CTRL; /*< MTB DWT Control Register, offset: 0x0 /
emilmont	2:e9a661555b58	1896	uint8_t RESERVED_0[28];
emilmont	2:e9a661555b58	1897	struct { /* offset: 0x20, array step: 0x10 */
emilmont	2:e9a661555b58	1898	__IO uint32_t COMP; /*< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 /
emilmont	2:e9a661555b58	1899	__IO uint32_t MASK; /*< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 /
emilmont	2:e9a661555b58	1900	__IO uint32_t FCT; /*< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 /
emilmont	2:e9a661555b58	1901	uint8_t RESERVED_0[4];
emilmont	2:e9a661555b58	1902	} COMPARATOR[2];
emilmont	2:e9a661555b58	1903	uint8_t RESERVED_1[448];
emilmont	2:e9a661555b58	1904	__IO uint32_t TBCTRL; /*< MTB_DWT Trace Buffer Control Register, offset: 0x200 /
emilmont	2:e9a661555b58	1905	uint8_t RESERVED_2[3524];
emilmont	2:e9a661555b58	1906	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
emilmont	2:e9a661555b58	1907	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
emilmont	2:e9a661555b58	1908	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
emilmont	2:e9a661555b58	1909	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
emilmont	2:e9a661555b58	1910	} MTBDWT_Type;
emilmont	2:e9a661555b58	1911
emilmont	2:e9a661555b58	1912	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1913	-- MTBDWT Register Masks
emilmont	2:e9a661555b58	1914	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1915
emilmont	2:e9a661555b58	1916	/**
emilmont	2:e9a661555b58	1917	* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
emilmont	2:e9a661555b58	1918	* @{
emilmont	2:e9a661555b58	1919	*/
emilmont	2:e9a661555b58	1920
emilmont	2:e9a661555b58	1921	/* CTRL Bit Fields */
emilmont	2:e9a661555b58	1922	#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
emilmont	2:e9a661555b58	1923	#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
emilmont	2:e9a661555b58	1924	#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
emilmont	2:e9a661555b58	1925	#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
emilmont	2:e9a661555b58	1926	#define MTBDWT_CTRL_NUMCMP_SHIFT 28
emilmont	2:e9a661555b58	1927	#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
emilmont	2:e9a661555b58	1928	/* COMP Bit Fields */
emilmont	2:e9a661555b58	1929	#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1930	#define MTBDWT_COMP_COMP_SHIFT 0
emilmont	2:e9a661555b58	1931	#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
emilmont	2:e9a661555b58	1932	/* MASK Bit Fields */
emilmont	2:e9a661555b58	1933	#define MTBDWT_MASK_MASK_MASK 0x1Fu
emilmont	2:e9a661555b58	1934	#define MTBDWT_MASK_MASK_SHIFT 0
emilmont	2:e9a661555b58	1935	#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
emilmont	2:e9a661555b58	1936	/* FCT Bit Fields */
emilmont	2:e9a661555b58	1937	#define MTBDWT_FCT_FUNCTION_MASK 0xFu
emilmont	2:e9a661555b58	1938	#define MTBDWT_FCT_FUNCTION_SHIFT 0
emilmont	2:e9a661555b58	1939	#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
emilmont	2:e9a661555b58	1940	#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
emilmont	2:e9a661555b58	1941	#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
emilmont	2:e9a661555b58	1942	#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
emilmont	2:e9a661555b58	1943	#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
emilmont	2:e9a661555b58	1944	#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
emilmont	2:e9a661555b58	1945	#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
emilmont	2:e9a661555b58	1946	#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
emilmont	2:e9a661555b58	1947	#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
emilmont	2:e9a661555b58	1948	#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
emilmont	2:e9a661555b58	1949	#define MTBDWT_FCT_MATCHED_SHIFT 24
emilmont	2:e9a661555b58	1950	/* TBCTRL Bit Fields */
emilmont	2:e9a661555b58	1951	#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
emilmont	2:e9a661555b58	1952	#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
emilmont	2:e9a661555b58	1953	#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
emilmont	2:e9a661555b58	1954	#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
emilmont	2:e9a661555b58	1955	#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
emilmont	2:e9a661555b58	1956	#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
emilmont	2:e9a661555b58	1957	#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
emilmont	2:e9a661555b58	1958	/* DEVICECFG Bit Fields */
emilmont	2:e9a661555b58	1959	#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1960	#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
emilmont	2:e9a661555b58	1961	#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
emilmont	2:e9a661555b58	1962	/* DEVICETYPID Bit Fields */
emilmont	2:e9a661555b58	1963	#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1964	#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
emilmont	2:e9a661555b58	1965	#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
emilmont	2:e9a661555b58	1966	/* PERIPHID Bit Fields */
emilmont	2:e9a661555b58	1967	#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1968	#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
emilmont	2:e9a661555b58	1969	#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
emilmont	2:e9a661555b58	1970	/* COMPID Bit Fields */
emilmont	2:e9a661555b58	1971	#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	1972	#define MTBDWT_COMPID_COMPID_SHIFT 0
emilmont	2:e9a661555b58	1973	#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
emilmont	2:e9a661555b58	1974
emilmont	2:e9a661555b58	1975	/**
emilmont	2:e9a661555b58	1976	* @}
emilmont	2:e9a661555b58	1977	/ / end of group MTBDWT_Register_Masks */
emilmont	2:e9a661555b58	1978
emilmont	2:e9a661555b58	1979
emilmont	2:e9a661555b58	1980	/* MTBDWT - Peripheral instance base addresses */
emilmont	2:e9a661555b58	1981	/** Peripheral MTBDWT base address */
emilmont	2:e9a661555b58	1982	#define MTBDWT_BASE (0xF0001000u)
emilmont	2:e9a661555b58	1983	/** Peripheral MTBDWT base pointer */
emilmont	2:e9a661555b58	1984	#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
emilmont	2:e9a661555b58	1985	/** Array initializer of MTBDWT peripheral base pointers */
emilmont	2:e9a661555b58	1986	#define MTBDWT_BASES { MTBDWT }
emilmont	2:e9a661555b58	1987
emilmont	2:e9a661555b58	1988	/**
emilmont	2:e9a661555b58	1989	* @}
emilmont	2:e9a661555b58	1990	/ / end of group MTBDWT_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	1991
emilmont	2:e9a661555b58	1992
emilmont	2:e9a661555b58	1993	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	1994	-- NV Peripheral Access Layer
emilmont	2:e9a661555b58	1995	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	1996
emilmont	2:e9a661555b58	1997	/**
emilmont	2:e9a661555b58	1998	* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
emilmont	2:e9a661555b58	1999	* @{
emilmont	2:e9a661555b58	2000	*/
emilmont	2:e9a661555b58	2001
emilmont	2:e9a661555b58	2002	/** NV - Register Layout Typedef */
emilmont	2:e9a661555b58	2003	typedef struct {
emilmont	2:e9a661555b58	2004	__I uint8_t BACKKEY3; /*< Backdoor Comparison Key 3., offset: 0x0 /
emilmont	2:e9a661555b58	2005	__I uint8_t BACKKEY2; /*< Backdoor Comparison Key 2., offset: 0x1 /
emilmont	2:e9a661555b58	2006	__I uint8_t BACKKEY1; /*< Backdoor Comparison Key 1., offset: 0x2 /
emilmont	2:e9a661555b58	2007	__I uint8_t BACKKEY0; /*< Backdoor Comparison Key 0., offset: 0x3 /
emilmont	2:e9a661555b58	2008	__I uint8_t BACKKEY7; /*< Backdoor Comparison Key 7., offset: 0x4 /
emilmont	2:e9a661555b58	2009	__I uint8_t BACKKEY6; /*< Backdoor Comparison Key 6., offset: 0x5 /
emilmont	2:e9a661555b58	2010	__I uint8_t BACKKEY5; /*< Backdoor Comparison Key 5., offset: 0x6 /
emilmont	2:e9a661555b58	2011	__I uint8_t BACKKEY4; /*< Backdoor Comparison Key 4., offset: 0x7 /
emilmont	2:e9a661555b58	2012	__I uint8_t FPROT3; /*< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 /
emilmont	2:e9a661555b58	2013	__I uint8_t FPROT2; /*< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 /
emilmont	2:e9a661555b58	2014	__I uint8_t FPROT1; /*< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA /
emilmont	2:e9a661555b58	2015	__I uint8_t FPROT0; /*< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB /
emilmont	2:e9a661555b58	2016	__I uint8_t FSEC; /*< Non-volatile Flash Security Register, offset: 0xC /
emilmont	2:e9a661555b58	2017	__I uint8_t FOPT; /*< Non-volatile Flash Option Register, offset: 0xD /
emilmont	2:e9a661555b58	2018	} NV_Type;
emilmont	2:e9a661555b58	2019
emilmont	2:e9a661555b58	2020	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2021	-- NV Register Masks
emilmont	2:e9a661555b58	2022	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2023
emilmont	2:e9a661555b58	2024	/**
emilmont	2:e9a661555b58	2025	* @addtogroup NV_Register_Masks NV Register Masks
emilmont	2:e9a661555b58	2026	* @{
emilmont	2:e9a661555b58	2027	*/
emilmont	2:e9a661555b58	2028
emilmont	2:e9a661555b58	2029	/* BACKKEY3 Bit Fields */
emilmont	2:e9a661555b58	2030	#define NV_BACKKEY3_KEY_MASK 0xFFu
emilmont	2:e9a661555b58	2031	#define NV_BACKKEY3_KEY_SHIFT 0
emilmont	2:e9a661555b58	2032	#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
emilmont	2:e9a661555b58	2033	/* BACKKEY2 Bit Fields */
emilmont	2:e9a661555b58	2034	#define NV_BACKKEY2_KEY_MASK 0xFFu
emilmont	2:e9a661555b58	2035	#define NV_BACKKEY2_KEY_SHIFT 0
emilmont	2:e9a661555b58	2036	#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
emilmont	2:e9a661555b58	2037	/* BACKKEY1 Bit Fields */
emilmont	2:e9a661555b58	2038	#define NV_BACKKEY1_KEY_MASK 0xFFu
emilmont	2:e9a661555b58	2039	#define NV_BACKKEY1_KEY_SHIFT 0
emilmont	2:e9a661555b58	2040	#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
emilmont	2:e9a661555b58	2041	/* BACKKEY0 Bit Fields */
emilmont	2:e9a661555b58	2042	#define NV_BACKKEY0_KEY_MASK 0xFFu
emilmont	2:e9a661555b58	2043	#define NV_BACKKEY0_KEY_SHIFT 0
emilmont	2:e9a661555b58	2044	#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
emilmont	2:e9a661555b58	2045	/* BACKKEY7 Bit Fields */
emilmont	2:e9a661555b58	2046	#define NV_BACKKEY7_KEY_MASK 0xFFu
emilmont	2:e9a661555b58	2047	#define NV_BACKKEY7_KEY_SHIFT 0
emilmont	2:e9a661555b58	2048	#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
emilmont	2:e9a661555b58	2049	/* BACKKEY6 Bit Fields */
emilmont	2:e9a661555b58	2050	#define NV_BACKKEY6_KEY_MASK 0xFFu
emilmont	2:e9a661555b58	2051	#define NV_BACKKEY6_KEY_SHIFT 0
emilmont	2:e9a661555b58	2052	#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
emilmont	2:e9a661555b58	2053	/* BACKKEY5 Bit Fields */
emilmont	2:e9a661555b58	2054	#define NV_BACKKEY5_KEY_MASK 0xFFu
emilmont	2:e9a661555b58	2055	#define NV_BACKKEY5_KEY_SHIFT 0
emilmont	2:e9a661555b58	2056	#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
emilmont	2:e9a661555b58	2057	/* BACKKEY4 Bit Fields */
emilmont	2:e9a661555b58	2058	#define NV_BACKKEY4_KEY_MASK 0xFFu
emilmont	2:e9a661555b58	2059	#define NV_BACKKEY4_KEY_SHIFT 0
emilmont	2:e9a661555b58	2060	#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
emilmont	2:e9a661555b58	2061	/* FPROT3 Bit Fields */
emilmont	2:e9a661555b58	2062	#define NV_FPROT3_PROT_MASK 0xFFu
emilmont	2:e9a661555b58	2063	#define NV_FPROT3_PROT_SHIFT 0
emilmont	2:e9a661555b58	2064	#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
emilmont	2:e9a661555b58	2065	/* FPROT2 Bit Fields */
emilmont	2:e9a661555b58	2066	#define NV_FPROT2_PROT_MASK 0xFFu
emilmont	2:e9a661555b58	2067	#define NV_FPROT2_PROT_SHIFT 0
emilmont	2:e9a661555b58	2068	#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
emilmont	2:e9a661555b58	2069	/* FPROT1 Bit Fields */
emilmont	2:e9a661555b58	2070	#define NV_FPROT1_PROT_MASK 0xFFu
emilmont	2:e9a661555b58	2071	#define NV_FPROT1_PROT_SHIFT 0
emilmont	2:e9a661555b58	2072	#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
emilmont	2:e9a661555b58	2073	/* FPROT0 Bit Fields */
emilmont	2:e9a661555b58	2074	#define NV_FPROT0_PROT_MASK 0xFFu
emilmont	2:e9a661555b58	2075	#define NV_FPROT0_PROT_SHIFT 0
emilmont	2:e9a661555b58	2076	#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
emilmont	2:e9a661555b58	2077	/* FSEC Bit Fields */
emilmont	2:e9a661555b58	2078	#define NV_FSEC_SEC_MASK 0x3u
emilmont	2:e9a661555b58	2079	#define NV_FSEC_SEC_SHIFT 0
emilmont	2:e9a661555b58	2080	#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
emilmont	2:e9a661555b58	2081	#define NV_FSEC_FSLACC_MASK 0xCu
emilmont	2:e9a661555b58	2082	#define NV_FSEC_FSLACC_SHIFT 2
emilmont	2:e9a661555b58	2083	#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
emilmont	2:e9a661555b58	2084	#define NV_FSEC_MEEN_MASK 0x30u
emilmont	2:e9a661555b58	2085	#define NV_FSEC_MEEN_SHIFT 4
emilmont	2:e9a661555b58	2086	#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
emilmont	2:e9a661555b58	2087	#define NV_FSEC_KEYEN_MASK 0xC0u
emilmont	2:e9a661555b58	2088	#define NV_FSEC_KEYEN_SHIFT 6
emilmont	2:e9a661555b58	2089	#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
emilmont	2:e9a661555b58	2090	/* FOPT Bit Fields */
emilmont	2:e9a661555b58	2091	#define NV_FOPT_LPBOOT0_MASK 0x1u
emilmont	2:e9a661555b58	2092	#define NV_FOPT_LPBOOT0_SHIFT 0
emilmont	2:e9a661555b58	2093	#define NV_FOPT_NMI_DIS_MASK 0x4u
emilmont	2:e9a661555b58	2094	#define NV_FOPT_NMI_DIS_SHIFT 2
emilmont	2:e9a661555b58	2095	#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
emilmont	2:e9a661555b58	2096	#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
emilmont	2:e9a661555b58	2097	#define NV_FOPT_LPBOOT1_MASK 0x10u
emilmont	2:e9a661555b58	2098	#define NV_FOPT_LPBOOT1_SHIFT 4
emilmont	2:e9a661555b58	2099	#define NV_FOPT_FAST_INIT_MASK 0x20u
emilmont	2:e9a661555b58	2100	#define NV_FOPT_FAST_INIT_SHIFT 5
emilmont	2:e9a661555b58	2101
emilmont	2:e9a661555b58	2102	/**
emilmont	2:e9a661555b58	2103	* @}
emilmont	2:e9a661555b58	2104	/ / end of group NV_Register_Masks */
emilmont	2:e9a661555b58	2105
emilmont	2:e9a661555b58	2106
emilmont	2:e9a661555b58	2107	/* NV - Peripheral instance base addresses */
emilmont	2:e9a661555b58	2108	/** Peripheral FTFA_FlashConfig base address */
emilmont	2:e9a661555b58	2109	#define FTFA_FlashConfig_BASE (0x400u)
emilmont	2:e9a661555b58	2110	/** Peripheral FTFA_FlashConfig base pointer */
emilmont	2:e9a661555b58	2111	#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
emilmont	2:e9a661555b58	2112	/** Array initializer of NV peripheral base pointers */
emilmont	2:e9a661555b58	2113	#define NV_BASES { FTFA_FlashConfig }
emilmont	2:e9a661555b58	2114
emilmont	2:e9a661555b58	2115	/**
emilmont	2:e9a661555b58	2116	* @}
emilmont	2:e9a661555b58	2117	/ / end of group NV_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	2118
emilmont	2:e9a661555b58	2119
emilmont	2:e9a661555b58	2120	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2121	-- OSC Peripheral Access Layer
emilmont	2:e9a661555b58	2122	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2123
emilmont	2:e9a661555b58	2124	/**
emilmont	2:e9a661555b58	2125	* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
emilmont	2:e9a661555b58	2126	* @{
emilmont	2:e9a661555b58	2127	*/
emilmont	2:e9a661555b58	2128
emilmont	2:e9a661555b58	2129	/** OSC - Register Layout Typedef */
emilmont	2:e9a661555b58	2130	typedef struct {
emilmont	2:e9a661555b58	2131	__IO uint8_t CR; /*< OSC Control Register, offset: 0x0 /
emilmont	2:e9a661555b58	2132	} OSC_Type;
emilmont	2:e9a661555b58	2133
emilmont	2:e9a661555b58	2134	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2135	-- OSC Register Masks
emilmont	2:e9a661555b58	2136	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2137
emilmont	2:e9a661555b58	2138	/**
emilmont	2:e9a661555b58	2139	* @addtogroup OSC_Register_Masks OSC Register Masks
emilmont	2:e9a661555b58	2140	* @{
emilmont	2:e9a661555b58	2141	*/
emilmont	2:e9a661555b58	2142
emilmont	2:e9a661555b58	2143	/* CR Bit Fields */
emilmont	2:e9a661555b58	2144	#define OSC_CR_SC16P_MASK 0x1u
emilmont	2:e9a661555b58	2145	#define OSC_CR_SC16P_SHIFT 0
emilmont	2:e9a661555b58	2146	#define OSC_CR_SC8P_MASK 0x2u
emilmont	2:e9a661555b58	2147	#define OSC_CR_SC8P_SHIFT 1
emilmont	2:e9a661555b58	2148	#define OSC_CR_SC4P_MASK 0x4u
emilmont	2:e9a661555b58	2149	#define OSC_CR_SC4P_SHIFT 2
emilmont	2:e9a661555b58	2150	#define OSC_CR_SC2P_MASK 0x8u
emilmont	2:e9a661555b58	2151	#define OSC_CR_SC2P_SHIFT 3
emilmont	2:e9a661555b58	2152	#define OSC_CR_EREFSTEN_MASK 0x20u
emilmont	2:e9a661555b58	2153	#define OSC_CR_EREFSTEN_SHIFT 5
emilmont	2:e9a661555b58	2154	#define OSC_CR_ERCLKEN_MASK 0x80u
emilmont	2:e9a661555b58	2155	#define OSC_CR_ERCLKEN_SHIFT 7
emilmont	2:e9a661555b58	2156
emilmont	2:e9a661555b58	2157	/**
emilmont	2:e9a661555b58	2158	* @}
emilmont	2:e9a661555b58	2159	/ / end of group OSC_Register_Masks */
emilmont	2:e9a661555b58	2160
emilmont	2:e9a661555b58	2161
emilmont	2:e9a661555b58	2162	/* OSC - Peripheral instance base addresses */
emilmont	2:e9a661555b58	2163	/** Peripheral OSC0 base address */
emilmont	2:e9a661555b58	2164	#define OSC0_BASE (0x40065000u)
emilmont	2:e9a661555b58	2165	/** Peripheral OSC0 base pointer */
emilmont	2:e9a661555b58	2166	#define OSC0 ((OSC_Type *)OSC0_BASE)
emilmont	2:e9a661555b58	2167	/** Array initializer of OSC peripheral base pointers */
emilmont	2:e9a661555b58	2168	#define OSC_BASES { OSC0 }
emilmont	2:e9a661555b58	2169
emilmont	2:e9a661555b58	2170	/**
emilmont	2:e9a661555b58	2171	* @}
emilmont	2:e9a661555b58	2172	/ / end of group OSC_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	2173
emilmont	2:e9a661555b58	2174
emilmont	2:e9a661555b58	2175	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2176	-- PIT Peripheral Access Layer
emilmont	2:e9a661555b58	2177	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2178
emilmont	2:e9a661555b58	2179	/**
emilmont	2:e9a661555b58	2180	* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
emilmont	2:e9a661555b58	2181	* @{
emilmont	2:e9a661555b58	2182	*/
emilmont	2:e9a661555b58	2183
emilmont	2:e9a661555b58	2184	/** PIT - Register Layout Typedef */
emilmont	2:e9a661555b58	2185	typedef struct {
emilmont	2:e9a661555b58	2186	__IO uint32_t MCR; /*< PIT Module Control Register, offset: 0x0 /
emilmont	2:e9a661555b58	2187	uint8_t RESERVED_0[220];
emilmont	2:e9a661555b58	2188	__I uint32_t LTMR64H; /*< PIT Upper Lifetime Timer Register, offset: 0xE0 /
emilmont	2:e9a661555b58	2189	__I uint32_t LTMR64L; /*< PIT Lower Lifetime Timer Register, offset: 0xE4 /
emilmont	2:e9a661555b58	2190	uint8_t RESERVED_1[24];
emilmont	2:e9a661555b58	2191	struct { /* offset: 0x100, array step: 0x10 */
emilmont	2:e9a661555b58	2192	__IO uint32_t LDVAL; /*< Timer Load Value Register, array offset: 0x100, array step: 0x10 /
emilmont	2:e9a661555b58	2193	__I uint32_t CVAL; /*< Current Timer Value Register, array offset: 0x104, array step: 0x10 /
emilmont	2:e9a661555b58	2194	__IO uint32_t TCTRL; /*< Timer Control Register, array offset: 0x108, array step: 0x10 /
emilmont	2:e9a661555b58	2195	__IO uint32_t TFLG; /*< Timer Flag Register, array offset: 0x10C, array step: 0x10 /
emilmont	2:e9a661555b58	2196	} CHANNEL[2];
emilmont	2:e9a661555b58	2197	} PIT_Type;
emilmont	2:e9a661555b58	2198
emilmont	2:e9a661555b58	2199	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2200	-- PIT Register Masks
emilmont	2:e9a661555b58	2201	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2202
emilmont	2:e9a661555b58	2203	/**
emilmont	2:e9a661555b58	2204	* @addtogroup PIT_Register_Masks PIT Register Masks
emilmont	2:e9a661555b58	2205	* @{
emilmont	2:e9a661555b58	2206	*/
emilmont	2:e9a661555b58	2207
emilmont	2:e9a661555b58	2208	/* MCR Bit Fields */
emilmont	2:e9a661555b58	2209	#define PIT_MCR_FRZ_MASK 0x1u
emilmont	2:e9a661555b58	2210	#define PIT_MCR_FRZ_SHIFT 0
emilmont	2:e9a661555b58	2211	#define PIT_MCR_MDIS_MASK 0x2u
emilmont	2:e9a661555b58	2212	#define PIT_MCR_MDIS_SHIFT 1
emilmont	2:e9a661555b58	2213	/* LTMR64H Bit Fields */
emilmont	2:e9a661555b58	2214	#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2215	#define PIT_LTMR64H_LTH_SHIFT 0
emilmont	2:e9a661555b58	2216	#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
emilmont	2:e9a661555b58	2217	/* LTMR64L Bit Fields */
emilmont	2:e9a661555b58	2218	#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2219	#define PIT_LTMR64L_LTL_SHIFT 0
emilmont	2:e9a661555b58	2220	#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
emilmont	2:e9a661555b58	2221	/* LDVAL Bit Fields */
emilmont	2:e9a661555b58	2222	#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2223	#define PIT_LDVAL_TSV_SHIFT 0
emilmont	2:e9a661555b58	2224	#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
emilmont	2:e9a661555b58	2225	/* CVAL Bit Fields */
emilmont	2:e9a661555b58	2226	#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2227	#define PIT_CVAL_TVL_SHIFT 0
emilmont	2:e9a661555b58	2228	#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
emilmont	2:e9a661555b58	2229	/* TCTRL Bit Fields */
emilmont	2:e9a661555b58	2230	#define PIT_TCTRL_TEN_MASK 0x1u
emilmont	2:e9a661555b58	2231	#define PIT_TCTRL_TEN_SHIFT 0
emilmont	2:e9a661555b58	2232	#define PIT_TCTRL_TIE_MASK 0x2u
emilmont	2:e9a661555b58	2233	#define PIT_TCTRL_TIE_SHIFT 1
emilmont	2:e9a661555b58	2234	#define PIT_TCTRL_CHN_MASK 0x4u
emilmont	2:e9a661555b58	2235	#define PIT_TCTRL_CHN_SHIFT 2
emilmont	2:e9a661555b58	2236	/* TFLG Bit Fields */
emilmont	2:e9a661555b58	2237	#define PIT_TFLG_TIF_MASK 0x1u
emilmont	2:e9a661555b58	2238	#define PIT_TFLG_TIF_SHIFT 0
emilmont	2:e9a661555b58	2239
emilmont	2:e9a661555b58	2240	/**
emilmont	2:e9a661555b58	2241	* @}
emilmont	2:e9a661555b58	2242	/ / end of group PIT_Register_Masks */
emilmont	2:e9a661555b58	2243
emilmont	2:e9a661555b58	2244
emilmont	2:e9a661555b58	2245	/* PIT - Peripheral instance base addresses */
emilmont	2:e9a661555b58	2246	/** Peripheral PIT base address */
emilmont	2:e9a661555b58	2247	#define PIT_BASE (0x40037000u)
emilmont	2:e9a661555b58	2248	/** Peripheral PIT base pointer */
emilmont	2:e9a661555b58	2249	#define PIT ((PIT_Type *)PIT_BASE)
emilmont	2:e9a661555b58	2250	/** Array initializer of PIT peripheral base pointers */
emilmont	2:e9a661555b58	2251	#define PIT_BASES { PIT }
emilmont	2:e9a661555b58	2252
emilmont	2:e9a661555b58	2253	/**
emilmont	2:e9a661555b58	2254	* @}
emilmont	2:e9a661555b58	2255	/ / end of group PIT_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	2256
emilmont	2:e9a661555b58	2257
emilmont	2:e9a661555b58	2258	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2259	-- PMC Peripheral Access Layer
emilmont	2:e9a661555b58	2260	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2261
emilmont	2:e9a661555b58	2262	/**
emilmont	2:e9a661555b58	2263	* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
emilmont	2:e9a661555b58	2264	* @{
emilmont	2:e9a661555b58	2265	*/
emilmont	2:e9a661555b58	2266
emilmont	2:e9a661555b58	2267	/** PMC - Register Layout Typedef */
emilmont	2:e9a661555b58	2268	typedef struct {
emilmont	2:e9a661555b58	2269	__IO uint8_t LVDSC1; /*< Low Voltage Detect Status And Control 1 register, offset: 0x0 /
emilmont	2:e9a661555b58	2270	__IO uint8_t LVDSC2; /*< Low Voltage Detect Status And Control 2 register, offset: 0x1 /
emilmont	2:e9a661555b58	2271	__IO uint8_t REGSC; /*< Regulator Status And Control register, offset: 0x2 /
emilmont	2:e9a661555b58	2272	} PMC_Type;
emilmont	2:e9a661555b58	2273
emilmont	2:e9a661555b58	2274	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2275	-- PMC Register Masks
emilmont	2:e9a661555b58	2276	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2277
emilmont	2:e9a661555b58	2278	/**
emilmont	2:e9a661555b58	2279	* @addtogroup PMC_Register_Masks PMC Register Masks
emilmont	2:e9a661555b58	2280	* @{
emilmont	2:e9a661555b58	2281	*/
emilmont	2:e9a661555b58	2282
emilmont	2:e9a661555b58	2283	/* LVDSC1 Bit Fields */
emilmont	2:e9a661555b58	2284	#define PMC_LVDSC1_LVDV_MASK 0x3u
emilmont	2:e9a661555b58	2285	#define PMC_LVDSC1_LVDV_SHIFT 0
emilmont	2:e9a661555b58	2286	#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
emilmont	2:e9a661555b58	2287	#define PMC_LVDSC1_LVDRE_MASK 0x10u
emilmont	2:e9a661555b58	2288	#define PMC_LVDSC1_LVDRE_SHIFT 4
emilmont	2:e9a661555b58	2289	#define PMC_LVDSC1_LVDIE_MASK 0x20u
emilmont	2:e9a661555b58	2290	#define PMC_LVDSC1_LVDIE_SHIFT 5
emilmont	2:e9a661555b58	2291	#define PMC_LVDSC1_LVDACK_MASK 0x40u
emilmont	2:e9a661555b58	2292	#define PMC_LVDSC1_LVDACK_SHIFT 6
emilmont	2:e9a661555b58	2293	#define PMC_LVDSC1_LVDF_MASK 0x80u
emilmont	2:e9a661555b58	2294	#define PMC_LVDSC1_LVDF_SHIFT 7
emilmont	2:e9a661555b58	2295	/* LVDSC2 Bit Fields */
emilmont	2:e9a661555b58	2296	#define PMC_LVDSC2_LVWV_MASK 0x3u
emilmont	2:e9a661555b58	2297	#define PMC_LVDSC2_LVWV_SHIFT 0
emilmont	2:e9a661555b58	2298	#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
emilmont	2:e9a661555b58	2299	#define PMC_LVDSC2_LVWIE_MASK 0x20u
emilmont	2:e9a661555b58	2300	#define PMC_LVDSC2_LVWIE_SHIFT 5
emilmont	2:e9a661555b58	2301	#define PMC_LVDSC2_LVWACK_MASK 0x40u
emilmont	2:e9a661555b58	2302	#define PMC_LVDSC2_LVWACK_SHIFT 6
emilmont	2:e9a661555b58	2303	#define PMC_LVDSC2_LVWF_MASK 0x80u
emilmont	2:e9a661555b58	2304	#define PMC_LVDSC2_LVWF_SHIFT 7
emilmont	2:e9a661555b58	2305	/* REGSC Bit Fields */
emilmont	2:e9a661555b58	2306	#define PMC_REGSC_BGBE_MASK 0x1u
emilmont	2:e9a661555b58	2307	#define PMC_REGSC_BGBE_SHIFT 0
emilmont	2:e9a661555b58	2308	#define PMC_REGSC_REGONS_MASK 0x4u
emilmont	2:e9a661555b58	2309	#define PMC_REGSC_REGONS_SHIFT 2
emilmont	2:e9a661555b58	2310	#define PMC_REGSC_ACKISO_MASK 0x8u
emilmont	2:e9a661555b58	2311	#define PMC_REGSC_ACKISO_SHIFT 3
emilmont	2:e9a661555b58	2312	#define PMC_REGSC_BGEN_MASK 0x10u
emilmont	2:e9a661555b58	2313	#define PMC_REGSC_BGEN_SHIFT 4
emilmont	2:e9a661555b58	2314
emilmont	2:e9a661555b58	2315	/**
emilmont	2:e9a661555b58	2316	* @}
emilmont	2:e9a661555b58	2317	/ / end of group PMC_Register_Masks */
emilmont	2:e9a661555b58	2318
emilmont	2:e9a661555b58	2319
emilmont	2:e9a661555b58	2320	/* PMC - Peripheral instance base addresses */
emilmont	2:e9a661555b58	2321	/** Peripheral PMC base address */
emilmont	2:e9a661555b58	2322	#define PMC_BASE (0x4007D000u)
emilmont	2:e9a661555b58	2323	/** Peripheral PMC base pointer */
emilmont	2:e9a661555b58	2324	#define PMC ((PMC_Type *)PMC_BASE)
emilmont	2:e9a661555b58	2325	/** Array initializer of PMC peripheral base pointers */
emilmont	2:e9a661555b58	2326	#define PMC_BASES { PMC }
emilmont	2:e9a661555b58	2327
emilmont	2:e9a661555b58	2328	/**
emilmont	2:e9a661555b58	2329	* @}
emilmont	2:e9a661555b58	2330	/ / end of group PMC_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	2331
emilmont	2:e9a661555b58	2332
emilmont	2:e9a661555b58	2333	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2334	-- PORT Peripheral Access Layer
emilmont	2:e9a661555b58	2335	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2336
emilmont	2:e9a661555b58	2337	/**
emilmont	2:e9a661555b58	2338	* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
emilmont	2:e9a661555b58	2339	* @{
emilmont	2:e9a661555b58	2340	*/
emilmont	2:e9a661555b58	2341
emilmont	2:e9a661555b58	2342	/** PORT - Register Layout Typedef */
emilmont	2:e9a661555b58	2343	typedef struct {
emilmont	2:e9a661555b58	2344	__IO uint32_t PCR[32]; /*< Pin Control Register n, array offset: 0x0, array step: 0x4 /
emilmont	2:e9a661555b58	2345	__O uint32_t GPCLR; /*< Global Pin Control Low Register, offset: 0x80 /
emilmont	2:e9a661555b58	2346	__O uint32_t GPCHR; /*< Global Pin Control High Register, offset: 0x84 /
emilmont	2:e9a661555b58	2347	uint8_t RESERVED_0[24];
emilmont	2:e9a661555b58	2348	__IO uint32_t ISFR; /*< Interrupt Status Flag Register, offset: 0xA0 /
emilmont	2:e9a661555b58	2349	} PORT_Type;
emilmont	2:e9a661555b58	2350
emilmont	2:e9a661555b58	2351	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2352	-- PORT Register Masks
emilmont	2:e9a661555b58	2353	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2354
emilmont	2:e9a661555b58	2355	/**
emilmont	2:e9a661555b58	2356	* @addtogroup PORT_Register_Masks PORT Register Masks
emilmont	2:e9a661555b58	2357	* @{
emilmont	2:e9a661555b58	2358	*/
emilmont	2:e9a661555b58	2359
emilmont	2:e9a661555b58	2360	/* PCR Bit Fields */
emilmont	2:e9a661555b58	2361	#define PORT_PCR_PS_MASK 0x1u
emilmont	2:e9a661555b58	2362	#define PORT_PCR_PS_SHIFT 0
emilmont	2:e9a661555b58	2363	#define PORT_PCR_PE_MASK 0x2u
emilmont	2:e9a661555b58	2364	#define PORT_PCR_PE_SHIFT 1
emilmont	2:e9a661555b58	2365	#define PORT_PCR_SRE_MASK 0x4u
emilmont	2:e9a661555b58	2366	#define PORT_PCR_SRE_SHIFT 2
emilmont	2:e9a661555b58	2367	#define PORT_PCR_PFE_MASK 0x10u
emilmont	2:e9a661555b58	2368	#define PORT_PCR_PFE_SHIFT 4
emilmont	2:e9a661555b58	2369	#define PORT_PCR_DSE_MASK 0x40u
emilmont	2:e9a661555b58	2370	#define PORT_PCR_DSE_SHIFT 6
emilmont	2:e9a661555b58	2371	#define PORT_PCR_MUX_MASK 0x700u
emilmont	2:e9a661555b58	2372	#define PORT_PCR_MUX_SHIFT 8
emilmont	2:e9a661555b58	2373	#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
emilmont	2:e9a661555b58	2374	#define PORT_PCR_IRQC_MASK 0xF0000u
emilmont	2:e9a661555b58	2375	#define PORT_PCR_IRQC_SHIFT 16
emilmont	2:e9a661555b58	2376	#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
emilmont	2:e9a661555b58	2377	#define PORT_PCR_ISF_MASK 0x1000000u
emilmont	2:e9a661555b58	2378	#define PORT_PCR_ISF_SHIFT 24
emilmont	2:e9a661555b58	2379	/* GPCLR Bit Fields */
emilmont	2:e9a661555b58	2380	#define PORT_GPCLR_GPWD_MASK 0xFFFFu
emilmont	2:e9a661555b58	2381	#define PORT_GPCLR_GPWD_SHIFT 0
emilmont	2:e9a661555b58	2382	#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
emilmont	2:e9a661555b58	2383	#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
emilmont	2:e9a661555b58	2384	#define PORT_GPCLR_GPWE_SHIFT 16
emilmont	2:e9a661555b58	2385	#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
emilmont	2:e9a661555b58	2386	/* GPCHR Bit Fields */
emilmont	2:e9a661555b58	2387	#define PORT_GPCHR_GPWD_MASK 0xFFFFu
emilmont	2:e9a661555b58	2388	#define PORT_GPCHR_GPWD_SHIFT 0
emilmont	2:e9a661555b58	2389	#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
emilmont	2:e9a661555b58	2390	#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
emilmont	2:e9a661555b58	2391	#define PORT_GPCHR_GPWE_SHIFT 16
emilmont	2:e9a661555b58	2392	#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
emilmont	2:e9a661555b58	2393	/* ISFR Bit Fields */
emilmont	2:e9a661555b58	2394	#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2395	#define PORT_ISFR_ISF_SHIFT 0
emilmont	2:e9a661555b58	2396	#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
emilmont	2:e9a661555b58	2397
emilmont	2:e9a661555b58	2398	/**
emilmont	2:e9a661555b58	2399	* @}
emilmont	2:e9a661555b58	2400	/ / end of group PORT_Register_Masks */
emilmont	2:e9a661555b58	2401
emilmont	2:e9a661555b58	2402
emilmont	2:e9a661555b58	2403	/* PORT - Peripheral instance base addresses */
emilmont	2:e9a661555b58	2404	/** Peripheral PORTA base address */
emilmont	2:e9a661555b58	2405	#define PORTA_BASE (0x40049000u)
emilmont	2:e9a661555b58	2406	/** Peripheral PORTA base pointer */
emilmont	2:e9a661555b58	2407	#define PORTA ((PORT_Type *)PORTA_BASE)
emilmont	2:e9a661555b58	2408	/** Peripheral PORTB base address */
emilmont	2:e9a661555b58	2409	#define PORTB_BASE (0x4004A000u)
emilmont	2:e9a661555b58	2410	/** Peripheral PORTB base pointer */
emilmont	2:e9a661555b58	2411	#define PORTB ((PORT_Type *)PORTB_BASE)
emilmont	2:e9a661555b58	2412	/** Peripheral PORTC base address */
emilmont	2:e9a661555b58	2413	#define PORTC_BASE (0x4004B000u)
emilmont	2:e9a661555b58	2414	/** Peripheral PORTC base pointer */
emilmont	2:e9a661555b58	2415	#define PORTC ((PORT_Type *)PORTC_BASE)
emilmont	2:e9a661555b58	2416	/** Peripheral PORTD base address */
emilmont	2:e9a661555b58	2417	#define PORTD_BASE (0x4004C000u)
emilmont	2:e9a661555b58	2418	/** Peripheral PORTD base pointer */
emilmont	2:e9a661555b58	2419	#define PORTD ((PORT_Type *)PORTD_BASE)
emilmont	2:e9a661555b58	2420	/** Peripheral PORTE base address */
emilmont	2:e9a661555b58	2421	#define PORTE_BASE (0x4004D000u)
emilmont	2:e9a661555b58	2422	/** Peripheral PORTE base pointer */
emilmont	2:e9a661555b58	2423	#define PORTE ((PORT_Type *)PORTE_BASE)
emilmont	2:e9a661555b58	2424	/** Array initializer of PORT peripheral base pointers */
emilmont	2:e9a661555b58	2425	#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
emilmont	2:e9a661555b58	2426
emilmont	2:e9a661555b58	2427	/**
emilmont	2:e9a661555b58	2428	* @}
emilmont	2:e9a661555b58	2429	/ / end of group PORT_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	2430
emilmont	2:e9a661555b58	2431
emilmont	2:e9a661555b58	2432	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2433	-- RCM Peripheral Access Layer
emilmont	2:e9a661555b58	2434	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2435
emilmont	2:e9a661555b58	2436	/**
emilmont	2:e9a661555b58	2437	* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
emilmont	2:e9a661555b58	2438	* @{
emilmont	2:e9a661555b58	2439	*/
emilmont	2:e9a661555b58	2440
emilmont	2:e9a661555b58	2441	/** RCM - Register Layout Typedef */
emilmont	2:e9a661555b58	2442	typedef struct {
emilmont	2:e9a661555b58	2443	__I uint8_t SRS0; /*< System Reset Status Register 0, offset: 0x0 /
emilmont	2:e9a661555b58	2444	__I uint8_t SRS1; /*< System Reset Status Register 1, offset: 0x1 /
emilmont	2:e9a661555b58	2445	uint8_t RESERVED_0[2];
emilmont	2:e9a661555b58	2446	__IO uint8_t RPFC; /*< Reset Pin Filter Control register, offset: 0x4 /
emilmont	2:e9a661555b58	2447	__IO uint8_t RPFW; /*< Reset Pin Filter Width register, offset: 0x5 /
emilmont	2:e9a661555b58	2448	} RCM_Type;
emilmont	2:e9a661555b58	2449
emilmont	2:e9a661555b58	2450	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2451	-- RCM Register Masks
emilmont	2:e9a661555b58	2452	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2453
emilmont	2:e9a661555b58	2454	/**
emilmont	2:e9a661555b58	2455	* @addtogroup RCM_Register_Masks RCM Register Masks
emilmont	2:e9a661555b58	2456	* @{
emilmont	2:e9a661555b58	2457	*/
emilmont	2:e9a661555b58	2458
emilmont	2:e9a661555b58	2459	/* SRS0 Bit Fields */
emilmont	2:e9a661555b58	2460	#define RCM_SRS0_WAKEUP_MASK 0x1u
emilmont	2:e9a661555b58	2461	#define RCM_SRS0_WAKEUP_SHIFT 0
emilmont	2:e9a661555b58	2462	#define RCM_SRS0_LVD_MASK 0x2u
emilmont	2:e9a661555b58	2463	#define RCM_SRS0_LVD_SHIFT 1
emilmont	2:e9a661555b58	2464	#define RCM_SRS0_LOC_MASK 0x4u
emilmont	2:e9a661555b58	2465	#define RCM_SRS0_LOC_SHIFT 2
emilmont	2:e9a661555b58	2466	#define RCM_SRS0_LOL_MASK 0x8u
emilmont	2:e9a661555b58	2467	#define RCM_SRS0_LOL_SHIFT 3
emilmont	2:e9a661555b58	2468	#define RCM_SRS0_WDOG_MASK 0x20u
emilmont	2:e9a661555b58	2469	#define RCM_SRS0_WDOG_SHIFT 5
emilmont	2:e9a661555b58	2470	#define RCM_SRS0_PIN_MASK 0x40u
emilmont	2:e9a661555b58	2471	#define RCM_SRS0_PIN_SHIFT 6
emilmont	2:e9a661555b58	2472	#define RCM_SRS0_POR_MASK 0x80u
emilmont	2:e9a661555b58	2473	#define RCM_SRS0_POR_SHIFT 7
emilmont	2:e9a661555b58	2474	/* SRS1 Bit Fields */
emilmont	2:e9a661555b58	2475	#define RCM_SRS1_LOCKUP_MASK 0x2u
emilmont	2:e9a661555b58	2476	#define RCM_SRS1_LOCKUP_SHIFT 1
emilmont	2:e9a661555b58	2477	#define RCM_SRS1_SW_MASK 0x4u
emilmont	2:e9a661555b58	2478	#define RCM_SRS1_SW_SHIFT 2
emilmont	2:e9a661555b58	2479	#define RCM_SRS1_MDM_AP_MASK 0x8u
emilmont	2:e9a661555b58	2480	#define RCM_SRS1_MDM_AP_SHIFT 3
emilmont	2:e9a661555b58	2481	#define RCM_SRS1_SACKERR_MASK 0x20u
emilmont	2:e9a661555b58	2482	#define RCM_SRS1_SACKERR_SHIFT 5
emilmont	2:e9a661555b58	2483	/* RPFC Bit Fields */
emilmont	2:e9a661555b58	2484	#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
emilmont	2:e9a661555b58	2485	#define RCM_RPFC_RSTFLTSRW_SHIFT 0
emilmont	2:e9a661555b58	2486	#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
emilmont	2:e9a661555b58	2487	#define RCM_RPFC_RSTFLTSS_MASK 0x4u
emilmont	2:e9a661555b58	2488	#define RCM_RPFC_RSTFLTSS_SHIFT 2
emilmont	2:e9a661555b58	2489	/* RPFW Bit Fields */
emilmont	2:e9a661555b58	2490	#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
emilmont	2:e9a661555b58	2491	#define RCM_RPFW_RSTFLTSEL_SHIFT 0
emilmont	2:e9a661555b58	2492	#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
emilmont	2:e9a661555b58	2493
emilmont	2:e9a661555b58	2494	/**
emilmont	2:e9a661555b58	2495	* @}
emilmont	2:e9a661555b58	2496	/ / end of group RCM_Register_Masks */
emilmont	2:e9a661555b58	2497
emilmont	2:e9a661555b58	2498
emilmont	2:e9a661555b58	2499	/* RCM - Peripheral instance base addresses */
emilmont	2:e9a661555b58	2500	/** Peripheral RCM base address */
emilmont	2:e9a661555b58	2501	#define RCM_BASE (0x4007F000u)
emilmont	2:e9a661555b58	2502	/** Peripheral RCM base pointer */
emilmont	2:e9a661555b58	2503	#define RCM ((RCM_Type *)RCM_BASE)
emilmont	2:e9a661555b58	2504	/** Array initializer of RCM peripheral base pointers */
emilmont	2:e9a661555b58	2505	#define RCM_BASES { RCM }
emilmont	2:e9a661555b58	2506
emilmont	2:e9a661555b58	2507	/**
emilmont	2:e9a661555b58	2508	* @}
emilmont	2:e9a661555b58	2509	/ / end of group RCM_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	2510
emilmont	2:e9a661555b58	2511
emilmont	2:e9a661555b58	2512	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2513	-- ROM Peripheral Access Layer
emilmont	2:e9a661555b58	2514	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2515
emilmont	2:e9a661555b58	2516	/**
emilmont	2:e9a661555b58	2517	* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
emilmont	2:e9a661555b58	2518	* @{
emilmont	2:e9a661555b58	2519	*/
emilmont	2:e9a661555b58	2520
emilmont	2:e9a661555b58	2521	/** ROM - Register Layout Typedef */
emilmont	2:e9a661555b58	2522	typedef struct {
emilmont	2:e9a661555b58	2523	__I uint32_t ENTRY[3]; /*< Entry, array offset: 0x0, array step: 0x4 /
emilmont	2:e9a661555b58	2524	__I uint32_t TABLEMARK; /*< End of Table Marker Register, offset: 0xC /
emilmont	2:e9a661555b58	2525	uint8_t RESERVED_0[4028];
emilmont	2:e9a661555b58	2526	__I uint32_t SYSACCESS; /*< System Access Register, offset: 0xFCC /
emilmont	2:e9a661555b58	2527	__I uint32_t PERIPHID4; /*< Peripheral ID Register, offset: 0xFD0 /
emilmont	2:e9a661555b58	2528	__I uint32_t PERIPHID5; /*< Peripheral ID Register, offset: 0xFD4 /
emilmont	2:e9a661555b58	2529	__I uint32_t PERIPHID6; /*< Peripheral ID Register, offset: 0xFD8 /
emilmont	2:e9a661555b58	2530	__I uint32_t PERIPHID7; /*< Peripheral ID Register, offset: 0xFDC /
emilmont	2:e9a661555b58	2531	__I uint32_t PERIPHID0; /*< Peripheral ID Register, offset: 0xFE0 /
emilmont	2:e9a661555b58	2532	__I uint32_t PERIPHID1; /*< Peripheral ID Register, offset: 0xFE4 /
emilmont	2:e9a661555b58	2533	__I uint32_t PERIPHID2; /*< Peripheral ID Register, offset: 0xFE8 /
emilmont	2:e9a661555b58	2534	__I uint32_t PERIPHID3; /*< Peripheral ID Register, offset: 0xFEC /
emilmont	2:e9a661555b58	2535	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
emilmont	2:e9a661555b58	2536	} ROM_Type;
emilmont	2:e9a661555b58	2537
emilmont	2:e9a661555b58	2538	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2539	-- ROM Register Masks
emilmont	2:e9a661555b58	2540	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2541
emilmont	2:e9a661555b58	2542	/**
emilmont	2:e9a661555b58	2543	* @addtogroup ROM_Register_Masks ROM Register Masks
emilmont	2:e9a661555b58	2544	* @{
emilmont	2:e9a661555b58	2545	*/
emilmont	2:e9a661555b58	2546
emilmont	2:e9a661555b58	2547	/* ENTRY Bit Fields */
emilmont	2:e9a661555b58	2548	#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2549	#define ROM_ENTRY_ENTRY_SHIFT 0
emilmont	2:e9a661555b58	2550	#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
emilmont	2:e9a661555b58	2551	/* TABLEMARK Bit Fields */
emilmont	2:e9a661555b58	2552	#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2553	#define ROM_TABLEMARK_MARK_SHIFT 0
emilmont	2:e9a661555b58	2554	#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
emilmont	2:e9a661555b58	2555	/* SYSACCESS Bit Fields */
emilmont	2:e9a661555b58	2556	#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2557	#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
emilmont	2:e9a661555b58	2558	#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
emilmont	2:e9a661555b58	2559	/* PERIPHID4 Bit Fields */
emilmont	2:e9a661555b58	2560	#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2561	#define ROM_PERIPHID4_PERIPHID_SHIFT 0
emilmont	2:e9a661555b58	2562	#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
emilmont	2:e9a661555b58	2563	/* PERIPHID5 Bit Fields */
emilmont	2:e9a661555b58	2564	#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2565	#define ROM_PERIPHID5_PERIPHID_SHIFT 0
emilmont	2:e9a661555b58	2566	#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
emilmont	2:e9a661555b58	2567	/* PERIPHID6 Bit Fields */
emilmont	2:e9a661555b58	2568	#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2569	#define ROM_PERIPHID6_PERIPHID_SHIFT 0
emilmont	2:e9a661555b58	2570	#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
emilmont	2:e9a661555b58	2571	/* PERIPHID7 Bit Fields */
emilmont	2:e9a661555b58	2572	#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2573	#define ROM_PERIPHID7_PERIPHID_SHIFT 0
emilmont	2:e9a661555b58	2574	#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
emilmont	2:e9a661555b58	2575	/* PERIPHID0 Bit Fields */
emilmont	2:e9a661555b58	2576	#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2577	#define ROM_PERIPHID0_PERIPHID_SHIFT 0
emilmont	2:e9a661555b58	2578	#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
emilmont	2:e9a661555b58	2579	/* PERIPHID1 Bit Fields */
emilmont	2:e9a661555b58	2580	#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2581	#define ROM_PERIPHID1_PERIPHID_SHIFT 0
emilmont	2:e9a661555b58	2582	#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
emilmont	2:e9a661555b58	2583	/* PERIPHID2 Bit Fields */
emilmont	2:e9a661555b58	2584	#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2585	#define ROM_PERIPHID2_PERIPHID_SHIFT 0
emilmont	2:e9a661555b58	2586	#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
emilmont	2:e9a661555b58	2587	/* PERIPHID3 Bit Fields */
emilmont	2:e9a661555b58	2588	#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2589	#define ROM_PERIPHID3_PERIPHID_SHIFT 0
emilmont	2:e9a661555b58	2590	#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
emilmont	2:e9a661555b58	2591	/* COMPID Bit Fields */
emilmont	2:e9a661555b58	2592	#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2593	#define ROM_COMPID_COMPID_SHIFT 0
emilmont	2:e9a661555b58	2594	#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
emilmont	2:e9a661555b58	2595
emilmont	2:e9a661555b58	2596	/**
emilmont	2:e9a661555b58	2597	* @}
emilmont	2:e9a661555b58	2598	/ / end of group ROM_Register_Masks */
emilmont	2:e9a661555b58	2599
emilmont	2:e9a661555b58	2600
emilmont	2:e9a661555b58	2601	/* ROM - Peripheral instance base addresses */
emilmont	2:e9a661555b58	2602	/** Peripheral ROM base address */
emilmont	2:e9a661555b58	2603	#define ROM_BASE (0xF0002000u)
emilmont	2:e9a661555b58	2604	/** Peripheral ROM base pointer */
emilmont	2:e9a661555b58	2605	#define ROM ((ROM_Type *)ROM_BASE)
emilmont	2:e9a661555b58	2606	/** Array initializer of ROM peripheral base pointers */
emilmont	2:e9a661555b58	2607	#define ROM_BASES { ROM }
emilmont	2:e9a661555b58	2608
emilmont	2:e9a661555b58	2609	/**
emilmont	2:e9a661555b58	2610	* @}
emilmont	2:e9a661555b58	2611	/ / end of group ROM_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	2612
emilmont	2:e9a661555b58	2613
emilmont	2:e9a661555b58	2614	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2615	-- RTC Peripheral Access Layer
emilmont	2:e9a661555b58	2616	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2617
emilmont	2:e9a661555b58	2618	/**
emilmont	2:e9a661555b58	2619	* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
emilmont	2:e9a661555b58	2620	* @{
emilmont	2:e9a661555b58	2621	*/
emilmont	2:e9a661555b58	2622
emilmont	2:e9a661555b58	2623	/** RTC - Register Layout Typedef */
emilmont	2:e9a661555b58	2624	typedef struct {
emilmont	2:e9a661555b58	2625	__IO uint32_t TSR; /*< RTC Time Seconds Register, offset: 0x0 /
emilmont	2:e9a661555b58	2626	__IO uint32_t TPR; /*< RTC Time Prescaler Register, offset: 0x4 /
emilmont	2:e9a661555b58	2627	__IO uint32_t TAR; /*< RTC Time Alarm Register, offset: 0x8 /
emilmont	2:e9a661555b58	2628	__IO uint32_t TCR; /*< RTC Time Compensation Register, offset: 0xC /
emilmont	2:e9a661555b58	2629	__IO uint32_t CR; /*< RTC Control Register, offset: 0x10 /
emilmont	2:e9a661555b58	2630	__IO uint32_t SR; /*< RTC Status Register, offset: 0x14 /
emilmont	2:e9a661555b58	2631	__IO uint32_t LR; /*< RTC Lock Register, offset: 0x18 /
emilmont	2:e9a661555b58	2632	__IO uint32_t IER; /*< RTC Interrupt Enable Register, offset: 0x1C /
emilmont	2:e9a661555b58	2633	} RTC_Type;
emilmont	2:e9a661555b58	2634
emilmont	2:e9a661555b58	2635	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2636	-- RTC Register Masks
emilmont	2:e9a661555b58	2637	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2638
emilmont	2:e9a661555b58	2639	/**
emilmont	2:e9a661555b58	2640	* @addtogroup RTC_Register_Masks RTC Register Masks
emilmont	2:e9a661555b58	2641	* @{
emilmont	2:e9a661555b58	2642	*/
emilmont	2:e9a661555b58	2643
emilmont	2:e9a661555b58	2644	/* TSR Bit Fields */
emilmont	2:e9a661555b58	2645	#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2646	#define RTC_TSR_TSR_SHIFT 0
emilmont	2:e9a661555b58	2647	#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
emilmont	2:e9a661555b58	2648	/* TPR Bit Fields */
emilmont	2:e9a661555b58	2649	#define RTC_TPR_TPR_MASK 0xFFFFu
emilmont	2:e9a661555b58	2650	#define RTC_TPR_TPR_SHIFT 0
emilmont	2:e9a661555b58	2651	#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
emilmont	2:e9a661555b58	2652	/* TAR Bit Fields */
emilmont	2:e9a661555b58	2653	#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2654	#define RTC_TAR_TAR_SHIFT 0
emilmont	2:e9a661555b58	2655	#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
emilmont	2:e9a661555b58	2656	/* TCR Bit Fields */
emilmont	2:e9a661555b58	2657	#define RTC_TCR_TCR_MASK 0xFFu
emilmont	2:e9a661555b58	2658	#define RTC_TCR_TCR_SHIFT 0
emilmont	2:e9a661555b58	2659	#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
emilmont	2:e9a661555b58	2660	#define RTC_TCR_CIR_MASK 0xFF00u
emilmont	2:e9a661555b58	2661	#define RTC_TCR_CIR_SHIFT 8
emilmont	2:e9a661555b58	2662	#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
emilmont	2:e9a661555b58	2663	#define RTC_TCR_TCV_MASK 0xFF0000u
emilmont	2:e9a661555b58	2664	#define RTC_TCR_TCV_SHIFT 16
emilmont	2:e9a661555b58	2665	#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
emilmont	2:e9a661555b58	2666	#define RTC_TCR_CIC_MASK 0xFF000000u
emilmont	2:e9a661555b58	2667	#define RTC_TCR_CIC_SHIFT 24
emilmont	2:e9a661555b58	2668	#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
emilmont	2:e9a661555b58	2669	/* CR Bit Fields */
emilmont	2:e9a661555b58	2670	#define RTC_CR_SWR_MASK 0x1u
emilmont	2:e9a661555b58	2671	#define RTC_CR_SWR_SHIFT 0
emilmont	2:e9a661555b58	2672	#define RTC_CR_WPE_MASK 0x2u
emilmont	2:e9a661555b58	2673	#define RTC_CR_WPE_SHIFT 1
emilmont	2:e9a661555b58	2674	#define RTC_CR_SUP_MASK 0x4u
emilmont	2:e9a661555b58	2675	#define RTC_CR_SUP_SHIFT 2
emilmont	2:e9a661555b58	2676	#define RTC_CR_UM_MASK 0x8u
emilmont	2:e9a661555b58	2677	#define RTC_CR_UM_SHIFT 3
emilmont	2:e9a661555b58	2678	#define RTC_CR_OSCE_MASK 0x100u
emilmont	2:e9a661555b58	2679	#define RTC_CR_OSCE_SHIFT 8
emilmont	2:e9a661555b58	2680	#define RTC_CR_CLKO_MASK 0x200u
emilmont	2:e9a661555b58	2681	#define RTC_CR_CLKO_SHIFT 9
emilmont	2:e9a661555b58	2682	#define RTC_CR_SC16P_MASK 0x400u
emilmont	2:e9a661555b58	2683	#define RTC_CR_SC16P_SHIFT 10
emilmont	2:e9a661555b58	2684	#define RTC_CR_SC8P_MASK 0x800u
emilmont	2:e9a661555b58	2685	#define RTC_CR_SC8P_SHIFT 11
emilmont	2:e9a661555b58	2686	#define RTC_CR_SC4P_MASK 0x1000u
emilmont	2:e9a661555b58	2687	#define RTC_CR_SC4P_SHIFT 12
emilmont	2:e9a661555b58	2688	#define RTC_CR_SC2P_MASK 0x2000u
emilmont	2:e9a661555b58	2689	#define RTC_CR_SC2P_SHIFT 13
emilmont	2:e9a661555b58	2690	/* SR Bit Fields */
emilmont	2:e9a661555b58	2691	#define RTC_SR_TIF_MASK 0x1u
emilmont	2:e9a661555b58	2692	#define RTC_SR_TIF_SHIFT 0
emilmont	2:e9a661555b58	2693	#define RTC_SR_TOF_MASK 0x2u
emilmont	2:e9a661555b58	2694	#define RTC_SR_TOF_SHIFT 1
emilmont	2:e9a661555b58	2695	#define RTC_SR_TAF_MASK 0x4u
emilmont	2:e9a661555b58	2696	#define RTC_SR_TAF_SHIFT 2
emilmont	2:e9a661555b58	2697	#define RTC_SR_TCE_MASK 0x10u
emilmont	2:e9a661555b58	2698	#define RTC_SR_TCE_SHIFT 4
emilmont	2:e9a661555b58	2699	/* LR Bit Fields */
emilmont	2:e9a661555b58	2700	#define RTC_LR_TCL_MASK 0x8u
emilmont	2:e9a661555b58	2701	#define RTC_LR_TCL_SHIFT 3
emilmont	2:e9a661555b58	2702	#define RTC_LR_CRL_MASK 0x10u
emilmont	2:e9a661555b58	2703	#define RTC_LR_CRL_SHIFT 4
emilmont	2:e9a661555b58	2704	#define RTC_LR_SRL_MASK 0x20u
emilmont	2:e9a661555b58	2705	#define RTC_LR_SRL_SHIFT 5
emilmont	2:e9a661555b58	2706	#define RTC_LR_LRL_MASK 0x40u
emilmont	2:e9a661555b58	2707	#define RTC_LR_LRL_SHIFT 6
emilmont	2:e9a661555b58	2708	/* IER Bit Fields */
emilmont	2:e9a661555b58	2709	#define RTC_IER_TIIE_MASK 0x1u
emilmont	2:e9a661555b58	2710	#define RTC_IER_TIIE_SHIFT 0
emilmont	2:e9a661555b58	2711	#define RTC_IER_TOIE_MASK 0x2u
emilmont	2:e9a661555b58	2712	#define RTC_IER_TOIE_SHIFT 1
emilmont	2:e9a661555b58	2713	#define RTC_IER_TAIE_MASK 0x4u
emilmont	2:e9a661555b58	2714	#define RTC_IER_TAIE_SHIFT 2
emilmont	2:e9a661555b58	2715	#define RTC_IER_TSIE_MASK 0x10u
emilmont	2:e9a661555b58	2716	#define RTC_IER_TSIE_SHIFT 4
emilmont	2:e9a661555b58	2717	#define RTC_IER_WPON_MASK 0x80u
emilmont	2:e9a661555b58	2718	#define RTC_IER_WPON_SHIFT 7
emilmont	2:e9a661555b58	2719
emilmont	2:e9a661555b58	2720	/**
emilmont	2:e9a661555b58	2721	* @}
emilmont	2:e9a661555b58	2722	/ / end of group RTC_Register_Masks */
emilmont	2:e9a661555b58	2723
emilmont	2:e9a661555b58	2724
emilmont	2:e9a661555b58	2725	/* RTC - Peripheral instance base addresses */
emilmont	2:e9a661555b58	2726	/** Peripheral RTC base address */
emilmont	2:e9a661555b58	2727	#define RTC_BASE (0x4003D000u)
emilmont	2:e9a661555b58	2728	/** Peripheral RTC base pointer */
emilmont	2:e9a661555b58	2729	#define RTC ((RTC_Type *)RTC_BASE)
emilmont	2:e9a661555b58	2730	/** Array initializer of RTC peripheral base pointers */
emilmont	2:e9a661555b58	2731	#define RTC_BASES { RTC }
emilmont	2:e9a661555b58	2732
emilmont	2:e9a661555b58	2733	/**
emilmont	2:e9a661555b58	2734	* @}
emilmont	2:e9a661555b58	2735	/ / end of group RTC_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	2736
emilmont	2:e9a661555b58	2737
emilmont	2:e9a661555b58	2738	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2739	-- SIM Peripheral Access Layer
emilmont	2:e9a661555b58	2740	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2741
emilmont	2:e9a661555b58	2742	/**
emilmont	2:e9a661555b58	2743	* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
emilmont	2:e9a661555b58	2744	* @{
emilmont	2:e9a661555b58	2745	*/
emilmont	2:e9a661555b58	2746
emilmont	2:e9a661555b58	2747	/** SIM - Register Layout Typedef */
emilmont	2:e9a661555b58	2748	typedef struct {
emilmont	2:e9a661555b58	2749	__IO uint32_t SOPT1; /*< System Options Register 1, offset: 0x0 /
emilmont	2:e9a661555b58	2750	__IO uint32_t SOPT1CFG; /*< SOPT1 Configuration Register, offset: 0x4 /
emilmont	2:e9a661555b58	2751	uint8_t RESERVED_0[4092];
emilmont	2:e9a661555b58	2752	__IO uint32_t SOPT2; /*< System Options Register 2, offset: 0x1004 /
emilmont	2:e9a661555b58	2753	uint8_t RESERVED_1[4];
emilmont	2:e9a661555b58	2754	__IO uint32_t SOPT4; /*< System Options Register 4, offset: 0x100C /
emilmont	2:e9a661555b58	2755	__IO uint32_t SOPT5; /*< System Options Register 5, offset: 0x1010 /
emilmont	2:e9a661555b58	2756	uint8_t RESERVED_2[4];
emilmont	2:e9a661555b58	2757	__IO uint32_t SOPT7; /*< System Options Register 7, offset: 0x1018 /
emilmont	2:e9a661555b58	2758	uint8_t RESERVED_3[8];
emilmont	2:e9a661555b58	2759	__I uint32_t SDID; /*< System Device Identification Register, offset: 0x1024 /
emilmont	2:e9a661555b58	2760	uint8_t RESERVED_4[12];
emilmont	2:e9a661555b58	2761	__IO uint32_t SCGC4; /*< System Clock Gating Control Register 4, offset: 0x1034 /
emilmont	2:e9a661555b58	2762	__IO uint32_t SCGC5; /*< System Clock Gating Control Register 5, offset: 0x1038 /
emilmont	2:e9a661555b58	2763	__IO uint32_t SCGC6; /*< System Clock Gating Control Register 6, offset: 0x103C /
emilmont	2:e9a661555b58	2764	__IO uint32_t SCGC7; /*< System Clock Gating Control Register 7, offset: 0x1040 /
emilmont	2:e9a661555b58	2765	__IO uint32_t CLKDIV1; /*< System Clock Divider Register 1, offset: 0x1044 /
emilmont	2:e9a661555b58	2766	uint8_t RESERVED_5[4];
emilmont	2:e9a661555b58	2767	__IO uint32_t FCFG1; /*< Flash Configuration Register 1, offset: 0x104C /
emilmont	2:e9a661555b58	2768	__I uint32_t FCFG2; /*< Flash Configuration Register 2, offset: 0x1050 /
emilmont	2:e9a661555b58	2769	uint8_t RESERVED_6[4];
emilmont	2:e9a661555b58	2770	__I uint32_t UIDMH; /*< Unique Identification Register Mid-High, offset: 0x1058 /
emilmont	2:e9a661555b58	2771	__I uint32_t UIDML; /*< Unique Identification Register Mid Low, offset: 0x105C /
emilmont	2:e9a661555b58	2772	__I uint32_t UIDL; /*< Unique Identification Register Low, offset: 0x1060 /
emilmont	2:e9a661555b58	2773	uint8_t RESERVED_7[156];
emilmont	2:e9a661555b58	2774	__IO uint32_t COPC; /*< COP Control Register, offset: 0x1100 /
emilmont	2:e9a661555b58	2775	__O uint32_t SRVCOP; /*< Service COP Register, offset: 0x1104 /
emilmont	2:e9a661555b58	2776	} SIM_Type;
emilmont	2:e9a661555b58	2777
emilmont	2:e9a661555b58	2778	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2779	-- SIM Register Masks
emilmont	2:e9a661555b58	2780	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2781
emilmont	2:e9a661555b58	2782	/**
emilmont	2:e9a661555b58	2783	* @addtogroup SIM_Register_Masks SIM Register Masks
emilmont	2:e9a661555b58	2784	* @{
emilmont	2:e9a661555b58	2785	*/
emilmont	2:e9a661555b58	2786
emilmont	2:e9a661555b58	2787	/* SOPT1 Bit Fields */
emilmont	2:e9a661555b58	2788	#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
emilmont	2:e9a661555b58	2789	#define SIM_SOPT1_OSC32KSEL_SHIFT 18
emilmont	2:e9a661555b58	2790	#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
emilmont	2:e9a661555b58	2791	#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
emilmont	2:e9a661555b58	2792	#define SIM_SOPT1_USBVSTBY_SHIFT 29
emilmont	2:e9a661555b58	2793	#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
emilmont	2:e9a661555b58	2794	#define SIM_SOPT1_USBSSTBY_SHIFT 30
emilmont	2:e9a661555b58	2795	#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
emilmont	2:e9a661555b58	2796	#define SIM_SOPT1_USBREGEN_SHIFT 31
emilmont	2:e9a661555b58	2797	/* SOPT1CFG Bit Fields */
emilmont	2:e9a661555b58	2798	#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
emilmont	2:e9a661555b58	2799	#define SIM_SOPT1CFG_URWE_SHIFT 24
emilmont	2:e9a661555b58	2800	#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
emilmont	2:e9a661555b58	2801	#define SIM_SOPT1CFG_UVSWE_SHIFT 25
emilmont	2:e9a661555b58	2802	#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
emilmont	2:e9a661555b58	2803	#define SIM_SOPT1CFG_USSWE_SHIFT 26
emilmont	2:e9a661555b58	2804	/* SOPT2 Bit Fields */
emilmont	2:e9a661555b58	2805	#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
emilmont	2:e9a661555b58	2806	#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
emilmont	2:e9a661555b58	2807	#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
emilmont	2:e9a661555b58	2808	#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
emilmont	2:e9a661555b58	2809	#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
emilmont	2:e9a661555b58	2810	#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
emilmont	2:e9a661555b58	2811	#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
emilmont	2:e9a661555b58	2812	#define SIM_SOPT2_USBSRC_MASK 0x40000u
emilmont	2:e9a661555b58	2813	#define SIM_SOPT2_USBSRC_SHIFT 18
emilmont	2:e9a661555b58	2814	#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
emilmont	2:e9a661555b58	2815	#define SIM_SOPT2_TPMSRC_SHIFT 24
emilmont	2:e9a661555b58	2816	#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
emilmont	2:e9a661555b58	2817	#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
emilmont	2:e9a661555b58	2818	#define SIM_SOPT2_UART0SRC_SHIFT 26
emilmont	2:e9a661555b58	2819	#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
emilmont	2:e9a661555b58	2820	/* SOPT4 Bit Fields */
emilmont	2:e9a661555b58	2821	#define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
emilmont	2:e9a661555b58	2822	#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
emilmont	2:e9a661555b58	2823	#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
emilmont	2:e9a661555b58	2824	#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
emilmont	2:e9a661555b58	2825	#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
emilmont	2:e9a661555b58	2826	#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
emilmont	2:e9a661555b58	2827	#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
emilmont	2:e9a661555b58	2828	#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
emilmont	2:e9a661555b58	2829	#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
emilmont	2:e9a661555b58	2830	#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
emilmont	2:e9a661555b58	2831	/* SOPT5 Bit Fields */
emilmont	2:e9a661555b58	2832	#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
emilmont	2:e9a661555b58	2833	#define SIM_SOPT5_UART0TXSRC_SHIFT 0
emilmont	2:e9a661555b58	2834	#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
emilmont	2:e9a661555b58	2835	#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
emilmont	2:e9a661555b58	2836	#define SIM_SOPT5_UART0RXSRC_SHIFT 2
emilmont	2:e9a661555b58	2837	#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
emilmont	2:e9a661555b58	2838	#define SIM_SOPT5_UART1TXSRC_SHIFT 4
emilmont	2:e9a661555b58	2839	#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
emilmont	2:e9a661555b58	2840	#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
emilmont	2:e9a661555b58	2841	#define SIM_SOPT5_UART1RXSRC_SHIFT 6
emilmont	2:e9a661555b58	2842	#define SIM_SOPT5_UART0ODE_MASK 0x10000u
emilmont	2:e9a661555b58	2843	#define SIM_SOPT5_UART0ODE_SHIFT 16
emilmont	2:e9a661555b58	2844	#define SIM_SOPT5_UART1ODE_MASK 0x20000u
emilmont	2:e9a661555b58	2845	#define SIM_SOPT5_UART1ODE_SHIFT 17
emilmont	2:e9a661555b58	2846	#define SIM_SOPT5_UART2ODE_MASK 0x40000u
emilmont	2:e9a661555b58	2847	#define SIM_SOPT5_UART2ODE_SHIFT 18
emilmont	2:e9a661555b58	2848	/* SOPT7 Bit Fields */
emilmont	2:e9a661555b58	2849	#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
emilmont	2:e9a661555b58	2850	#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
emilmont	2:e9a661555b58	2851	#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
emilmont	2:e9a661555b58	2852	#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
emilmont	2:e9a661555b58	2853	#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
emilmont	2:e9a661555b58	2854	#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
emilmont	2:e9a661555b58	2855	#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
emilmont	2:e9a661555b58	2856	/* SDID Bit Fields */
emilmont	2:e9a661555b58	2857	#define SIM_SDID_PINID_MASK 0xFu
emilmont	2:e9a661555b58	2858	#define SIM_SDID_PINID_SHIFT 0
emilmont	2:e9a661555b58	2859	#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
emilmont	2:e9a661555b58	2860	#define SIM_SDID_DIEID_MASK 0xF80u
emilmont	2:e9a661555b58	2861	#define SIM_SDID_DIEID_SHIFT 7
emilmont	2:e9a661555b58	2862	#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
emilmont	2:e9a661555b58	2863	#define SIM_SDID_REVID_MASK 0xF000u
emilmont	2:e9a661555b58	2864	#define SIM_SDID_REVID_SHIFT 12
emilmont	2:e9a661555b58	2865	#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
emilmont	2:e9a661555b58	2866	#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
emilmont	2:e9a661555b58	2867	#define SIM_SDID_SRAMSIZE_SHIFT 16
emilmont	2:e9a661555b58	2868	#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
emilmont	2:e9a661555b58	2869	#define SIM_SDID_SERIESID_MASK 0xF00000u
emilmont	2:e9a661555b58	2870	#define SIM_SDID_SERIESID_SHIFT 20
emilmont	2:e9a661555b58	2871	#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
emilmont	2:e9a661555b58	2872	#define SIM_SDID_SUBFAMID_MASK 0xF000000u
emilmont	2:e9a661555b58	2873	#define SIM_SDID_SUBFAMID_SHIFT 24
emilmont	2:e9a661555b58	2874	#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
emilmont	2:e9a661555b58	2875	#define SIM_SDID_FAMID_MASK 0xF0000000u
emilmont	2:e9a661555b58	2876	#define SIM_SDID_FAMID_SHIFT 28
emilmont	2:e9a661555b58	2877	#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
emilmont	2:e9a661555b58	2878	/* SCGC4 Bit Fields */
emilmont	2:e9a661555b58	2879	#define SIM_SCGC4_I2C0_MASK 0x40u
emilmont	2:e9a661555b58	2880	#define SIM_SCGC4_I2C0_SHIFT 6
emilmont	2:e9a661555b58	2881	#define SIM_SCGC4_I2C1_MASK 0x80u
emilmont	2:e9a661555b58	2882	#define SIM_SCGC4_I2C1_SHIFT 7
emilmont	2:e9a661555b58	2883	#define SIM_SCGC4_UART0_MASK 0x400u
emilmont	2:e9a661555b58	2884	#define SIM_SCGC4_UART0_SHIFT 10
emilmont	2:e9a661555b58	2885	#define SIM_SCGC4_UART1_MASK 0x800u
emilmont	2:e9a661555b58	2886	#define SIM_SCGC4_UART1_SHIFT 11
emilmont	2:e9a661555b58	2887	#define SIM_SCGC4_UART2_MASK 0x1000u
emilmont	2:e9a661555b58	2888	#define SIM_SCGC4_UART2_SHIFT 12
emilmont	2:e9a661555b58	2889	#define SIM_SCGC4_USBOTG_MASK 0x40000u
emilmont	2:e9a661555b58	2890	#define SIM_SCGC4_USBOTG_SHIFT 18
emilmont	2:e9a661555b58	2891	#define SIM_SCGC4_CMP_MASK 0x80000u
emilmont	2:e9a661555b58	2892	#define SIM_SCGC4_CMP_SHIFT 19
emilmont	2:e9a661555b58	2893	#define SIM_SCGC4_SPI0_MASK 0x400000u
emilmont	2:e9a661555b58	2894	#define SIM_SCGC4_SPI0_SHIFT 22
emilmont	2:e9a661555b58	2895	#define SIM_SCGC4_SPI1_MASK 0x800000u
emilmont	2:e9a661555b58	2896	#define SIM_SCGC4_SPI1_SHIFT 23
emilmont	2:e9a661555b58	2897	/* SCGC5 Bit Fields */
emilmont	2:e9a661555b58	2898	#define SIM_SCGC5_LPTMR_MASK 0x1u
emilmont	2:e9a661555b58	2899	#define SIM_SCGC5_LPTMR_SHIFT 0
emilmont	2:e9a661555b58	2900	#define SIM_SCGC5_TSI_MASK 0x20u
emilmont	2:e9a661555b58	2901	#define SIM_SCGC5_TSI_SHIFT 5
emilmont	2:e9a661555b58	2902	#define SIM_SCGC5_PORTA_MASK 0x200u
emilmont	2:e9a661555b58	2903	#define SIM_SCGC5_PORTA_SHIFT 9
emilmont	2:e9a661555b58	2904	#define SIM_SCGC5_PORTB_MASK 0x400u
emilmont	2:e9a661555b58	2905	#define SIM_SCGC5_PORTB_SHIFT 10
emilmont	2:e9a661555b58	2906	#define SIM_SCGC5_PORTC_MASK 0x800u
emilmont	2:e9a661555b58	2907	#define SIM_SCGC5_PORTC_SHIFT 11
emilmont	2:e9a661555b58	2908	#define SIM_SCGC5_PORTD_MASK 0x1000u
emilmont	2:e9a661555b58	2909	#define SIM_SCGC5_PORTD_SHIFT 12
emilmont	2:e9a661555b58	2910	#define SIM_SCGC5_PORTE_MASK 0x2000u
emilmont	2:e9a661555b58	2911	#define SIM_SCGC5_PORTE_SHIFT 13
emilmont	2:e9a661555b58	2912	/* SCGC6 Bit Fields */
emilmont	2:e9a661555b58	2913	#define SIM_SCGC6_FTF_MASK 0x1u
emilmont	2:e9a661555b58	2914	#define SIM_SCGC6_FTF_SHIFT 0
emilmont	2:e9a661555b58	2915	#define SIM_SCGC6_DMAMUX_MASK 0x2u
emilmont	2:e9a661555b58	2916	#define SIM_SCGC6_DMAMUX_SHIFT 1
emilmont	2:e9a661555b58	2917	#define SIM_SCGC6_PIT_MASK 0x800000u
emilmont	2:e9a661555b58	2918	#define SIM_SCGC6_PIT_SHIFT 23
emilmont	2:e9a661555b58	2919	#define SIM_SCGC6_TPM0_MASK 0x1000000u
emilmont	2:e9a661555b58	2920	#define SIM_SCGC6_TPM0_SHIFT 24
emilmont	2:e9a661555b58	2921	#define SIM_SCGC6_TPM1_MASK 0x2000000u
emilmont	2:e9a661555b58	2922	#define SIM_SCGC6_TPM1_SHIFT 25
emilmont	2:e9a661555b58	2923	#define SIM_SCGC6_TPM2_MASK 0x4000000u
emilmont	2:e9a661555b58	2924	#define SIM_SCGC6_TPM2_SHIFT 26
emilmont	2:e9a661555b58	2925	#define SIM_SCGC6_ADC0_MASK 0x8000000u
emilmont	2:e9a661555b58	2926	#define SIM_SCGC6_ADC0_SHIFT 27
emilmont	2:e9a661555b58	2927	#define SIM_SCGC6_RTC_MASK 0x20000000u
emilmont	2:e9a661555b58	2928	#define SIM_SCGC6_RTC_SHIFT 29
emilmont	2:e9a661555b58	2929	#define SIM_SCGC6_DAC0_MASK 0x80000000u
emilmont	2:e9a661555b58	2930	#define SIM_SCGC6_DAC0_SHIFT 31
emilmont	2:e9a661555b58	2931	/* SCGC7 Bit Fields */
emilmont	2:e9a661555b58	2932	#define SIM_SCGC7_DMA_MASK 0x100u
emilmont	2:e9a661555b58	2933	#define SIM_SCGC7_DMA_SHIFT 8
emilmont	2:e9a661555b58	2934	/* CLKDIV1 Bit Fields */
emilmont	2:e9a661555b58	2935	#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
emilmont	2:e9a661555b58	2936	#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
emilmont	2:e9a661555b58	2937	#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
emilmont	2:e9a661555b58	2938	#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
emilmont	2:e9a661555b58	2939	#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
emilmont	2:e9a661555b58	2940	#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
emilmont	2:e9a661555b58	2941	/* FCFG1 Bit Fields */
emilmont	2:e9a661555b58	2942	#define SIM_FCFG1_FLASHDIS_MASK 0x1u
emilmont	2:e9a661555b58	2943	#define SIM_FCFG1_FLASHDIS_SHIFT 0
emilmont	2:e9a661555b58	2944	#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
emilmont	2:e9a661555b58	2945	#define SIM_FCFG1_FLASHDOZE_SHIFT 1
emilmont	2:e9a661555b58	2946	#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
emilmont	2:e9a661555b58	2947	#define SIM_FCFG1_PFSIZE_SHIFT 24
emilmont	2:e9a661555b58	2948	#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
emilmont	2:e9a661555b58	2949	/* FCFG2 Bit Fields */
emilmont	2:e9a661555b58	2950	#define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
emilmont	2:e9a661555b58	2951	#define SIM_FCFG2_MAXADDR_SHIFT 24
emilmont	2:e9a661555b58	2952	#define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
emilmont	2:e9a661555b58	2953	/* UIDMH Bit Fields */
emilmont	2:e9a661555b58	2954	#define SIM_UIDMH_UID_MASK 0xFFFFu
emilmont	2:e9a661555b58	2955	#define SIM_UIDMH_UID_SHIFT 0
emilmont	2:e9a661555b58	2956	#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
emilmont	2:e9a661555b58	2957	/* UIDML Bit Fields */
emilmont	2:e9a661555b58	2958	#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2959	#define SIM_UIDML_UID_SHIFT 0
emilmont	2:e9a661555b58	2960	#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
emilmont	2:e9a661555b58	2961	/* UIDL Bit Fields */
emilmont	2:e9a661555b58	2962	#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
emilmont	2:e9a661555b58	2963	#define SIM_UIDL_UID_SHIFT 0
emilmont	2:e9a661555b58	2964	#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
emilmont	2:e9a661555b58	2965	/* COPC Bit Fields */
emilmont	2:e9a661555b58	2966	#define SIM_COPC_COPW_MASK 0x1u
emilmont	2:e9a661555b58	2967	#define SIM_COPC_COPW_SHIFT 0
emilmont	2:e9a661555b58	2968	#define SIM_COPC_COPCLKS_MASK 0x2u
emilmont	2:e9a661555b58	2969	#define SIM_COPC_COPCLKS_SHIFT 1
emilmont	2:e9a661555b58	2970	#define SIM_COPC_COPT_MASK 0xCu
emilmont	2:e9a661555b58	2971	#define SIM_COPC_COPT_SHIFT 2
emilmont	2:e9a661555b58	2972	#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
emilmont	2:e9a661555b58	2973	/* SRVCOP Bit Fields */
emilmont	2:e9a661555b58	2974	#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
emilmont	2:e9a661555b58	2975	#define SIM_SRVCOP_SRVCOP_SHIFT 0
emilmont	2:e9a661555b58	2976	#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
emilmont	2:e9a661555b58	2977
emilmont	2:e9a661555b58	2978	/**
emilmont	2:e9a661555b58	2979	* @}
emilmont	2:e9a661555b58	2980	/ / end of group SIM_Register_Masks */
emilmont	2:e9a661555b58	2981
emilmont	2:e9a661555b58	2982
emilmont	2:e9a661555b58	2983	/* SIM - Peripheral instance base addresses */
emilmont	2:e9a661555b58	2984	/** Peripheral SIM base address */
emilmont	2:e9a661555b58	2985	#define SIM_BASE (0x40047000u)
emilmont	2:e9a661555b58	2986	/** Peripheral SIM base pointer */
emilmont	2:e9a661555b58	2987	#define SIM ((SIM_Type *)SIM_BASE)
emilmont	2:e9a661555b58	2988	/** Array initializer of SIM peripheral base pointers */
emilmont	2:e9a661555b58	2989	#define SIM_BASES { SIM }
emilmont	2:e9a661555b58	2990
emilmont	2:e9a661555b58	2991	/**
emilmont	2:e9a661555b58	2992	* @}
emilmont	2:e9a661555b58	2993	/ / end of group SIM_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	2994
emilmont	2:e9a661555b58	2995
emilmont	2:e9a661555b58	2996	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	2997	-- SMC Peripheral Access Layer
emilmont	2:e9a661555b58	2998	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	2999
emilmont	2:e9a661555b58	3000	/**
emilmont	2:e9a661555b58	3001	* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
emilmont	2:e9a661555b58	3002	* @{
emilmont	2:e9a661555b58	3003	*/
emilmont	2:e9a661555b58	3004
emilmont	2:e9a661555b58	3005	/** SMC - Register Layout Typedef */
emilmont	2:e9a661555b58	3006	typedef struct {
emilmont	2:e9a661555b58	3007	__IO uint8_t PMPROT; /*< Power Mode Protection register, offset: 0x0 /
emilmont	2:e9a661555b58	3008	__IO uint8_t PMCTRL; /*< Power Mode Control register, offset: 0x1 /
emilmont	2:e9a661555b58	3009	__IO uint8_t STOPCTRL; /*< Stop Control Register, offset: 0x2 /
emilmont	2:e9a661555b58	3010	__I uint8_t PMSTAT; /*< Power Mode Status register, offset: 0x3 /
emilmont	2:e9a661555b58	3011	} SMC_Type;
emilmont	2:e9a661555b58	3012
emilmont	2:e9a661555b58	3013	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3014	-- SMC Register Masks
emilmont	2:e9a661555b58	3015	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3016
emilmont	2:e9a661555b58	3017	/**
emilmont	2:e9a661555b58	3018	* @addtogroup SMC_Register_Masks SMC Register Masks
emilmont	2:e9a661555b58	3019	* @{
emilmont	2:e9a661555b58	3020	*/
emilmont	2:e9a661555b58	3021
emilmont	2:e9a661555b58	3022	/* PMPROT Bit Fields */
emilmont	2:e9a661555b58	3023	#define SMC_PMPROT_AVLLS_MASK 0x2u
emilmont	2:e9a661555b58	3024	#define SMC_PMPROT_AVLLS_SHIFT 1
emilmont	2:e9a661555b58	3025	#define SMC_PMPROT_ALLS_MASK 0x8u
emilmont	2:e9a661555b58	3026	#define SMC_PMPROT_ALLS_SHIFT 3
emilmont	2:e9a661555b58	3027	#define SMC_PMPROT_AVLP_MASK 0x20u
emilmont	2:e9a661555b58	3028	#define SMC_PMPROT_AVLP_SHIFT 5
emilmont	2:e9a661555b58	3029	/* PMCTRL Bit Fields */
emilmont	2:e9a661555b58	3030	#define SMC_PMCTRL_STOPM_MASK 0x7u
emilmont	2:e9a661555b58	3031	#define SMC_PMCTRL_STOPM_SHIFT 0
emilmont	2:e9a661555b58	3032	#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
emilmont	2:e9a661555b58	3033	#define SMC_PMCTRL_STOPA_MASK 0x8u
emilmont	2:e9a661555b58	3034	#define SMC_PMCTRL_STOPA_SHIFT 3
emilmont	2:e9a661555b58	3035	#define SMC_PMCTRL_RUNM_MASK 0x60u
emilmont	2:e9a661555b58	3036	#define SMC_PMCTRL_RUNM_SHIFT 5
emilmont	2:e9a661555b58	3037	#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
emilmont	2:e9a661555b58	3038	/* STOPCTRL Bit Fields */
emilmont	2:e9a661555b58	3039	#define SMC_STOPCTRL_VLLSM_MASK 0x7u
emilmont	2:e9a661555b58	3040	#define SMC_STOPCTRL_VLLSM_SHIFT 0
emilmont	2:e9a661555b58	3041	#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
emilmont	2:e9a661555b58	3042	#define SMC_STOPCTRL_PORPO_MASK 0x20u
emilmont	2:e9a661555b58	3043	#define SMC_STOPCTRL_PORPO_SHIFT 5
emilmont	2:e9a661555b58	3044	#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
emilmont	2:e9a661555b58	3045	#define SMC_STOPCTRL_PSTOPO_SHIFT 6
emilmont	2:e9a661555b58	3046	#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
emilmont	2:e9a661555b58	3047	/* PMSTAT Bit Fields */
emilmont	2:e9a661555b58	3048	#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
emilmont	2:e9a661555b58	3049	#define SMC_PMSTAT_PMSTAT_SHIFT 0
emilmont	2:e9a661555b58	3050	#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
emilmont	2:e9a661555b58	3051
emilmont	2:e9a661555b58	3052	/**
emilmont	2:e9a661555b58	3053	* @}
emilmont	2:e9a661555b58	3054	/ / end of group SMC_Register_Masks */
emilmont	2:e9a661555b58	3055
emilmont	2:e9a661555b58	3056
emilmont	2:e9a661555b58	3057	/* SMC - Peripheral instance base addresses */
emilmont	2:e9a661555b58	3058	/** Peripheral SMC base address */
emilmont	2:e9a661555b58	3059	#define SMC_BASE (0x4007E000u)
emilmont	2:e9a661555b58	3060	/** Peripheral SMC base pointer */
emilmont	2:e9a661555b58	3061	#define SMC ((SMC_Type *)SMC_BASE)
emilmont	2:e9a661555b58	3062	/** Array initializer of SMC peripheral base pointers */
emilmont	2:e9a661555b58	3063	#define SMC_BASES { SMC }
emilmont	2:e9a661555b58	3064
emilmont	2:e9a661555b58	3065	/**
emilmont	2:e9a661555b58	3066	* @}
emilmont	2:e9a661555b58	3067	/ / end of group SMC_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	3068
emilmont	2:e9a661555b58	3069
emilmont	2:e9a661555b58	3070	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3071	-- SPI Peripheral Access Layer
emilmont	2:e9a661555b58	3072	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3073
emilmont	2:e9a661555b58	3074	/**
emilmont	2:e9a661555b58	3075	* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
emilmont	2:e9a661555b58	3076	* @{
emilmont	2:e9a661555b58	3077	*/
emilmont	2:e9a661555b58	3078
emilmont	2:e9a661555b58	3079	/** SPI - Register Layout Typedef */
emilmont	2:e9a661555b58	3080	typedef struct {
emilmont	2:e9a661555b58	3081	__IO uint8_t C1; /*< SPI control register 1, offset: 0x0 /
emilmont	2:e9a661555b58	3082	__IO uint8_t C2; /*< SPI control register 2, offset: 0x1 /
emilmont	2:e9a661555b58	3083	__IO uint8_t BR; /*< SPI baud rate register, offset: 0x2 /
emilmont	2:e9a661555b58	3084	__I uint8_t S; /*< SPI status register, offset: 0x3 /
emilmont	2:e9a661555b58	3085	uint8_t RESERVED_0[1];
emilmont	2:e9a661555b58	3086	__IO uint8_t D; /*< SPI data register, offset: 0x5 /
emilmont	2:e9a661555b58	3087	uint8_t RESERVED_1[1];
emilmont	2:e9a661555b58	3088	__IO uint8_t M; /*< SPI match register, offset: 0x7 /
emilmont	2:e9a661555b58	3089	} SPI_Type;
emilmont	2:e9a661555b58	3090
emilmont	2:e9a661555b58	3091	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3092	-- SPI Register Masks
emilmont	2:e9a661555b58	3093	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3094
emilmont	2:e9a661555b58	3095	/**
emilmont	2:e9a661555b58	3096	* @addtogroup SPI_Register_Masks SPI Register Masks
emilmont	2:e9a661555b58	3097	* @{
emilmont	2:e9a661555b58	3098	*/
emilmont	2:e9a661555b58	3099
emilmont	2:e9a661555b58	3100	/* C1 Bit Fields */
emilmont	2:e9a661555b58	3101	#define SPI_C1_LSBFE_MASK 0x1u
emilmont	2:e9a661555b58	3102	#define SPI_C1_LSBFE_SHIFT 0
emilmont	2:e9a661555b58	3103	#define SPI_C1_SSOE_MASK 0x2u
emilmont	2:e9a661555b58	3104	#define SPI_C1_SSOE_SHIFT 1
emilmont	2:e9a661555b58	3105	#define SPI_C1_CPHA_MASK 0x4u
emilmont	2:e9a661555b58	3106	#define SPI_C1_CPHA_SHIFT 2
emilmont	2:e9a661555b58	3107	#define SPI_C1_CPOL_MASK 0x8u
emilmont	2:e9a661555b58	3108	#define SPI_C1_CPOL_SHIFT 3
emilmont	2:e9a661555b58	3109	#define SPI_C1_MSTR_MASK 0x10u
emilmont	2:e9a661555b58	3110	#define SPI_C1_MSTR_SHIFT 4
emilmont	2:e9a661555b58	3111	#define SPI_C1_SPTIE_MASK 0x20u
emilmont	2:e9a661555b58	3112	#define SPI_C1_SPTIE_SHIFT 5
emilmont	2:e9a661555b58	3113	#define SPI_C1_SPE_MASK 0x40u
emilmont	2:e9a661555b58	3114	#define SPI_C1_SPE_SHIFT 6
emilmont	2:e9a661555b58	3115	#define SPI_C1_SPIE_MASK 0x80u
emilmont	2:e9a661555b58	3116	#define SPI_C1_SPIE_SHIFT 7
emilmont	2:e9a661555b58	3117	/* C2 Bit Fields */
emilmont	2:e9a661555b58	3118	#define SPI_C2_SPC0_MASK 0x1u
emilmont	2:e9a661555b58	3119	#define SPI_C2_SPC0_SHIFT 0
emilmont	2:e9a661555b58	3120	#define SPI_C2_SPISWAI_MASK 0x2u
emilmont	2:e9a661555b58	3121	#define SPI_C2_SPISWAI_SHIFT 1
emilmont	2:e9a661555b58	3122	#define SPI_C2_RXDMAE_MASK 0x4u
emilmont	2:e9a661555b58	3123	#define SPI_C2_RXDMAE_SHIFT 2
emilmont	2:e9a661555b58	3124	#define SPI_C2_BIDIROE_MASK 0x8u
emilmont	2:e9a661555b58	3125	#define SPI_C2_BIDIROE_SHIFT 3
emilmont	2:e9a661555b58	3126	#define SPI_C2_MODFEN_MASK 0x10u
emilmont	2:e9a661555b58	3127	#define SPI_C2_MODFEN_SHIFT 4
emilmont	2:e9a661555b58	3128	#define SPI_C2_TXDMAE_MASK 0x20u
emilmont	2:e9a661555b58	3129	#define SPI_C2_TXDMAE_SHIFT 5
emilmont	2:e9a661555b58	3130	#define SPI_C2_SPLPIE_MASK 0x40u
emilmont	2:e9a661555b58	3131	#define SPI_C2_SPLPIE_SHIFT 6
emilmont	2:e9a661555b58	3132	#define SPI_C2_SPMIE_MASK 0x80u
emilmont	2:e9a661555b58	3133	#define SPI_C2_SPMIE_SHIFT 7
emilmont	2:e9a661555b58	3134	/* BR Bit Fields */
emilmont	2:e9a661555b58	3135	#define SPI_BR_SPR_MASK 0xFu
emilmont	2:e9a661555b58	3136	#define SPI_BR_SPR_SHIFT 0
emilmont	2:e9a661555b58	3137	#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
emilmont	2:e9a661555b58	3138	#define SPI_BR_SPPR_MASK 0x70u
emilmont	2:e9a661555b58	3139	#define SPI_BR_SPPR_SHIFT 4
emilmont	2:e9a661555b58	3140	#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
emilmont	2:e9a661555b58	3141	/* S Bit Fields */
emilmont	2:e9a661555b58	3142	#define SPI_S_MODF_MASK 0x10u
emilmont	2:e9a661555b58	3143	#define SPI_S_MODF_SHIFT 4
emilmont	2:e9a661555b58	3144	#define SPI_S_SPTEF_MASK 0x20u
emilmont	2:e9a661555b58	3145	#define SPI_S_SPTEF_SHIFT 5
emilmont	2:e9a661555b58	3146	#define SPI_S_SPMF_MASK 0x40u
emilmont	2:e9a661555b58	3147	#define SPI_S_SPMF_SHIFT 6
emilmont	2:e9a661555b58	3148	#define SPI_S_SPRF_MASK 0x80u
emilmont	2:e9a661555b58	3149	#define SPI_S_SPRF_SHIFT 7
emilmont	2:e9a661555b58	3150	/* D Bit Fields */
emilmont	2:e9a661555b58	3151	#define SPI_D_Bits_MASK 0xFFu
emilmont	2:e9a661555b58	3152	#define SPI_D_Bits_SHIFT 0
emilmont	2:e9a661555b58	3153	#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
emilmont	2:e9a661555b58	3154	/* M Bit Fields */
emilmont	2:e9a661555b58	3155	#define SPI_M_Bits_MASK 0xFFu
emilmont	2:e9a661555b58	3156	#define SPI_M_Bits_SHIFT 0
emilmont	2:e9a661555b58	3157	#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
emilmont	2:e9a661555b58	3158
emilmont	2:e9a661555b58	3159	/**
emilmont	2:e9a661555b58	3160	* @}
emilmont	2:e9a661555b58	3161	/ / end of group SPI_Register_Masks */
emilmont	2:e9a661555b58	3162
emilmont	2:e9a661555b58	3163
emilmont	2:e9a661555b58	3164	/* SPI - Peripheral instance base addresses */
emilmont	2:e9a661555b58	3165	/** Peripheral SPI0 base address */
emilmont	2:e9a661555b58	3166	#define SPI0_BASE (0x40076000u)
emilmont	2:e9a661555b58	3167	/** Peripheral SPI0 base pointer */
emilmont	2:e9a661555b58	3168	#define SPI0 ((SPI_Type *)SPI0_BASE)
emilmont	2:e9a661555b58	3169	/** Peripheral SPI1 base address */
emilmont	2:e9a661555b58	3170	#define SPI1_BASE (0x40077000u)
emilmont	2:e9a661555b58	3171	/** Peripheral SPI1 base pointer */
emilmont	2:e9a661555b58	3172	#define SPI1 ((SPI_Type *)SPI1_BASE)
emilmont	2:e9a661555b58	3173	/** Array initializer of SPI peripheral base pointers */
emilmont	2:e9a661555b58	3174	#define SPI_BASES { SPI0, SPI1 }
emilmont	2:e9a661555b58	3175
emilmont	2:e9a661555b58	3176	/**
emilmont	2:e9a661555b58	3177	* @}
emilmont	2:e9a661555b58	3178	/ / end of group SPI_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	3179
emilmont	2:e9a661555b58	3180
emilmont	2:e9a661555b58	3181	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3182	-- TPM Peripheral Access Layer
emilmont	2:e9a661555b58	3183	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3184
emilmont	2:e9a661555b58	3185	/**
emilmont	2:e9a661555b58	3186	* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
emilmont	2:e9a661555b58	3187	* @{
emilmont	2:e9a661555b58	3188	*/
emilmont	2:e9a661555b58	3189
emilmont	2:e9a661555b58	3190	/** TPM - Register Layout Typedef */
emilmont	2:e9a661555b58	3191	typedef struct {
emilmont	2:e9a661555b58	3192	__IO uint32_t SC; /*< Status and Control, offset: 0x0 /
emilmont	2:e9a661555b58	3193	__IO uint32_t CNT; /*< Counter, offset: 0x4 /
emilmont	2:e9a661555b58	3194	__IO uint32_t MOD; /*< Modulo, offset: 0x8 /
emilmont	2:e9a661555b58	3195	struct { /* offset: 0xC, array step: 0x8 */
emilmont	2:e9a661555b58	3196	__IO uint32_t CnSC; /*< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 /
emilmont	2:e9a661555b58	3197	__IO uint32_t CnV; /*< Channel (n) Value, array offset: 0x10, array step: 0x8 /
emilmont	2:e9a661555b58	3198	} CONTROLS[6];
emilmont	2:e9a661555b58	3199	uint8_t RESERVED_0[20];
emilmont	2:e9a661555b58	3200	__IO uint32_t STATUS; /*< Capture and Compare Status, offset: 0x50 /
emilmont	2:e9a661555b58	3201	uint8_t RESERVED_1[48];
emilmont	2:e9a661555b58	3202	__IO uint32_t CONF; /*< Configuration, offset: 0x84 /
emilmont	2:e9a661555b58	3203	} TPM_Type;
emilmont	2:e9a661555b58	3204
emilmont	2:e9a661555b58	3205	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3206	-- TPM Register Masks
emilmont	2:e9a661555b58	3207	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3208
emilmont	2:e9a661555b58	3209	/**
emilmont	2:e9a661555b58	3210	* @addtogroup TPM_Register_Masks TPM Register Masks
emilmont	2:e9a661555b58	3211	* @{
emilmont	2:e9a661555b58	3212	*/
emilmont	2:e9a661555b58	3213
emilmont	2:e9a661555b58	3214	/* SC Bit Fields */
emilmont	2:e9a661555b58	3215	#define TPM_SC_PS_MASK 0x7u
emilmont	2:e9a661555b58	3216	#define TPM_SC_PS_SHIFT 0
emilmont	2:e9a661555b58	3217	#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
emilmont	2:e9a661555b58	3218	#define TPM_SC_CMOD_MASK 0x18u
emilmont	2:e9a661555b58	3219	#define TPM_SC_CMOD_SHIFT 3
emilmont	2:e9a661555b58	3220	#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
emilmont	2:e9a661555b58	3221	#define TPM_SC_CPWMS_MASK 0x20u
emilmont	2:e9a661555b58	3222	#define TPM_SC_CPWMS_SHIFT 5
emilmont	2:e9a661555b58	3223	#define TPM_SC_TOIE_MASK 0x40u
emilmont	2:e9a661555b58	3224	#define TPM_SC_TOIE_SHIFT 6
emilmont	2:e9a661555b58	3225	#define TPM_SC_TOF_MASK 0x80u
emilmont	2:e9a661555b58	3226	#define TPM_SC_TOF_SHIFT 7
emilmont	2:e9a661555b58	3227	#define TPM_SC_DMA_MASK 0x100u
emilmont	2:e9a661555b58	3228	#define TPM_SC_DMA_SHIFT 8
emilmont	2:e9a661555b58	3229	/* CNT Bit Fields */
emilmont	2:e9a661555b58	3230	#define TPM_CNT_COUNT_MASK 0xFFFFu
emilmont	2:e9a661555b58	3231	#define TPM_CNT_COUNT_SHIFT 0
emilmont	2:e9a661555b58	3232	#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
emilmont	2:e9a661555b58	3233	/* MOD Bit Fields */
emilmont	2:e9a661555b58	3234	#define TPM_MOD_MOD_MASK 0xFFFFu
emilmont	2:e9a661555b58	3235	#define TPM_MOD_MOD_SHIFT 0
emilmont	2:e9a661555b58	3236	#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
emilmont	2:e9a661555b58	3237	/* CnSC Bit Fields */
emilmont	2:e9a661555b58	3238	#define TPM_CnSC_DMA_MASK 0x1u
emilmont	2:e9a661555b58	3239	#define TPM_CnSC_DMA_SHIFT 0
emilmont	2:e9a661555b58	3240	#define TPM_CnSC_ELSA_MASK 0x4u
emilmont	2:e9a661555b58	3241	#define TPM_CnSC_ELSA_SHIFT 2
emilmont	2:e9a661555b58	3242	#define TPM_CnSC_ELSB_MASK 0x8u
emilmont	2:e9a661555b58	3243	#define TPM_CnSC_ELSB_SHIFT 3
emilmont	2:e9a661555b58	3244	#define TPM_CnSC_MSA_MASK 0x10u
emilmont	2:e9a661555b58	3245	#define TPM_CnSC_MSA_SHIFT 4
emilmont	2:e9a661555b58	3246	#define TPM_CnSC_MSB_MASK 0x20u
emilmont	2:e9a661555b58	3247	#define TPM_CnSC_MSB_SHIFT 5
emilmont	2:e9a661555b58	3248	#define TPM_CnSC_CHIE_MASK 0x40u
emilmont	2:e9a661555b58	3249	#define TPM_CnSC_CHIE_SHIFT 6
emilmont	2:e9a661555b58	3250	#define TPM_CnSC_CHF_MASK 0x80u
emilmont	2:e9a661555b58	3251	#define TPM_CnSC_CHF_SHIFT 7
emilmont	2:e9a661555b58	3252	/* CnV Bit Fields */
emilmont	2:e9a661555b58	3253	#define TPM_CnV_VAL_MASK 0xFFFFu
emilmont	2:e9a661555b58	3254	#define TPM_CnV_VAL_SHIFT 0
emilmont	2:e9a661555b58	3255	#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
emilmont	2:e9a661555b58	3256	/* STATUS Bit Fields */
emilmont	2:e9a661555b58	3257	#define TPM_STATUS_CH0F_MASK 0x1u
emilmont	2:e9a661555b58	3258	#define TPM_STATUS_CH0F_SHIFT 0
emilmont	2:e9a661555b58	3259	#define TPM_STATUS_CH1F_MASK 0x2u
emilmont	2:e9a661555b58	3260	#define TPM_STATUS_CH1F_SHIFT 1
emilmont	2:e9a661555b58	3261	#define TPM_STATUS_CH2F_MASK 0x4u
emilmont	2:e9a661555b58	3262	#define TPM_STATUS_CH2F_SHIFT 2
emilmont	2:e9a661555b58	3263	#define TPM_STATUS_CH3F_MASK 0x8u
emilmont	2:e9a661555b58	3264	#define TPM_STATUS_CH3F_SHIFT 3
emilmont	2:e9a661555b58	3265	#define TPM_STATUS_CH4F_MASK 0x10u
emilmont	2:e9a661555b58	3266	#define TPM_STATUS_CH4F_SHIFT 4
emilmont	2:e9a661555b58	3267	#define TPM_STATUS_CH5F_MASK 0x20u
emilmont	2:e9a661555b58	3268	#define TPM_STATUS_CH5F_SHIFT 5
emilmont	2:e9a661555b58	3269	#define TPM_STATUS_TOF_MASK 0x100u
emilmont	2:e9a661555b58	3270	#define TPM_STATUS_TOF_SHIFT 8
emilmont	2:e9a661555b58	3271	/* CONF Bit Fields */
emilmont	2:e9a661555b58	3272	#define TPM_CONF_DOZEEN_MASK 0x20u
emilmont	2:e9a661555b58	3273	#define TPM_CONF_DOZEEN_SHIFT 5
emilmont	2:e9a661555b58	3274	#define TPM_CONF_DBGMODE_MASK 0xC0u
emilmont	2:e9a661555b58	3275	#define TPM_CONF_DBGMODE_SHIFT 6
emilmont	2:e9a661555b58	3276	#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
emilmont	2:e9a661555b58	3277	#define TPM_CONF_GTBEEN_MASK 0x200u
emilmont	2:e9a661555b58	3278	#define TPM_CONF_GTBEEN_SHIFT 9
emilmont	2:e9a661555b58	3279	#define TPM_CONF_CSOT_MASK 0x10000u
emilmont	2:e9a661555b58	3280	#define TPM_CONF_CSOT_SHIFT 16
emilmont	2:e9a661555b58	3281	#define TPM_CONF_CSOO_MASK 0x20000u
emilmont	2:e9a661555b58	3282	#define TPM_CONF_CSOO_SHIFT 17
emilmont	2:e9a661555b58	3283	#define TPM_CONF_CROT_MASK 0x40000u
emilmont	2:e9a661555b58	3284	#define TPM_CONF_CROT_SHIFT 18
emilmont	2:e9a661555b58	3285	#define TPM_CONF_TRGSEL_MASK 0xF000000u
emilmont	2:e9a661555b58	3286	#define TPM_CONF_TRGSEL_SHIFT 24
emilmont	2:e9a661555b58	3287	#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
emilmont	2:e9a661555b58	3288
emilmont	2:e9a661555b58	3289	/**
emilmont	2:e9a661555b58	3290	* @}
emilmont	2:e9a661555b58	3291	/ / end of group TPM_Register_Masks */
emilmont	2:e9a661555b58	3292
emilmont	2:e9a661555b58	3293
emilmont	2:e9a661555b58	3294	/* TPM - Peripheral instance base addresses */
emilmont	2:e9a661555b58	3295	/** Peripheral TPM0 base address */
emilmont	2:e9a661555b58	3296	#define TPM0_BASE (0x40038000u)
emilmont	2:e9a661555b58	3297	/** Peripheral TPM0 base pointer */
emilmont	2:e9a661555b58	3298	#define TPM0 ((TPM_Type *)TPM0_BASE)
emilmont	2:e9a661555b58	3299	/** Peripheral TPM1 base address */
emilmont	2:e9a661555b58	3300	#define TPM1_BASE (0x40039000u)
emilmont	2:e9a661555b58	3301	/** Peripheral TPM1 base pointer */
emilmont	2:e9a661555b58	3302	#define TPM1 ((TPM_Type *)TPM1_BASE)
emilmont	2:e9a661555b58	3303	/** Peripheral TPM2 base address */
emilmont	2:e9a661555b58	3304	#define TPM2_BASE (0x4003A000u)
emilmont	2:e9a661555b58	3305	/** Peripheral TPM2 base pointer */
emilmont	2:e9a661555b58	3306	#define TPM2 ((TPM_Type *)TPM2_BASE)
emilmont	2:e9a661555b58	3307	/** Array initializer of TPM peripheral base pointers */
emilmont	2:e9a661555b58	3308	#define TPM_BASES { TPM0, TPM1, TPM2 }
emilmont	2:e9a661555b58	3309
emilmont	2:e9a661555b58	3310	/**
emilmont	2:e9a661555b58	3311	* @}
emilmont	2:e9a661555b58	3312	/ / end of group TPM_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	3313
emilmont	2:e9a661555b58	3314
emilmont	2:e9a661555b58	3315	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3316	-- TSI Peripheral Access Layer
emilmont	2:e9a661555b58	3317	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3318
emilmont	2:e9a661555b58	3319	/**
emilmont	2:e9a661555b58	3320	* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
emilmont	2:e9a661555b58	3321	* @{
emilmont	2:e9a661555b58	3322	*/
emilmont	2:e9a661555b58	3323
emilmont	2:e9a661555b58	3324	/** TSI - Register Layout Typedef */
emilmont	2:e9a661555b58	3325	typedef struct {
emilmont	2:e9a661555b58	3326	__IO uint32_t GENCS; /*< TSI General Control and Status Register, offset: 0x0 /
emilmont	2:e9a661555b58	3327	__IO uint32_t DATA; /*< TSI DATA Register, offset: 0x4 /
emilmont	2:e9a661555b58	3328	__IO uint32_t TSHD; /*< TSI Threshold Register, offset: 0x8 /
emilmont	2:e9a661555b58	3329	} TSI_Type;
emilmont	2:e9a661555b58	3330
emilmont	2:e9a661555b58	3331	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3332	-- TSI Register Masks
emilmont	2:e9a661555b58	3333	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3334
emilmont	2:e9a661555b58	3335	/**
emilmont	2:e9a661555b58	3336	* @addtogroup TSI_Register_Masks TSI Register Masks
emilmont	2:e9a661555b58	3337	* @{
emilmont	2:e9a661555b58	3338	*/
emilmont	2:e9a661555b58	3339
emilmont	2:e9a661555b58	3340	/* GENCS Bit Fields */
emilmont	2:e9a661555b58	3341	#define TSI_GENCS_CURSW_MASK 0x2u
emilmont	2:e9a661555b58	3342	#define TSI_GENCS_CURSW_SHIFT 1
emilmont	2:e9a661555b58	3343	#define TSI_GENCS_EOSF_MASK 0x4u
emilmont	2:e9a661555b58	3344	#define TSI_GENCS_EOSF_SHIFT 2
emilmont	2:e9a661555b58	3345	#define TSI_GENCS_SCNIP_MASK 0x8u
emilmont	2:e9a661555b58	3346	#define TSI_GENCS_SCNIP_SHIFT 3
emilmont	2:e9a661555b58	3347	#define TSI_GENCS_STM_MASK 0x10u
emilmont	2:e9a661555b58	3348	#define TSI_GENCS_STM_SHIFT 4
emilmont	2:e9a661555b58	3349	#define TSI_GENCS_STPE_MASK 0x20u
emilmont	2:e9a661555b58	3350	#define TSI_GENCS_STPE_SHIFT 5
emilmont	2:e9a661555b58	3351	#define TSI_GENCS_TSIIEN_MASK 0x40u
emilmont	2:e9a661555b58	3352	#define TSI_GENCS_TSIIEN_SHIFT 6
emilmont	2:e9a661555b58	3353	#define TSI_GENCS_TSIEN_MASK 0x80u
emilmont	2:e9a661555b58	3354	#define TSI_GENCS_TSIEN_SHIFT 7
emilmont	2:e9a661555b58	3355	#define TSI_GENCS_NSCN_MASK 0x1F00u
emilmont	2:e9a661555b58	3356	#define TSI_GENCS_NSCN_SHIFT 8
emilmont	2:e9a661555b58	3357	#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
emilmont	2:e9a661555b58	3358	#define TSI_GENCS_PS_MASK 0xE000u
emilmont	2:e9a661555b58	3359	#define TSI_GENCS_PS_SHIFT 13
emilmont	2:e9a661555b58	3360	#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
emilmont	2:e9a661555b58	3361	#define TSI_GENCS_EXTCHRG_MASK 0x70000u
emilmont	2:e9a661555b58	3362	#define TSI_GENCS_EXTCHRG_SHIFT 16
emilmont	2:e9a661555b58	3363	#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
emilmont	2:e9a661555b58	3364	#define TSI_GENCS_DVOLT_MASK 0x180000u
emilmont	2:e9a661555b58	3365	#define TSI_GENCS_DVOLT_SHIFT 19
emilmont	2:e9a661555b58	3366	#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
emilmont	2:e9a661555b58	3367	#define TSI_GENCS_REFCHRG_MASK 0xE00000u
emilmont	2:e9a661555b58	3368	#define TSI_GENCS_REFCHRG_SHIFT 21
emilmont	2:e9a661555b58	3369	#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
emilmont	2:e9a661555b58	3370	#define TSI_GENCS_MODE_MASK 0xF000000u
emilmont	2:e9a661555b58	3371	#define TSI_GENCS_MODE_SHIFT 24
emilmont	2:e9a661555b58	3372	#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
emilmont	2:e9a661555b58	3373	#define TSI_GENCS_ESOR_MASK 0x10000000u
emilmont	2:e9a661555b58	3374	#define TSI_GENCS_ESOR_SHIFT 28
emilmont	2:e9a661555b58	3375	#define TSI_GENCS_OUTRGF_MASK 0x80000000u
emilmont	2:e9a661555b58	3376	#define TSI_GENCS_OUTRGF_SHIFT 31
emilmont	2:e9a661555b58	3377	/* DATA Bit Fields */
emilmont	2:e9a661555b58	3378	#define TSI_DATA_TSICNT_MASK 0xFFFFu
emilmont	2:e9a661555b58	3379	#define TSI_DATA_TSICNT_SHIFT 0
emilmont	2:e9a661555b58	3380	#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
emilmont	2:e9a661555b58	3381	#define TSI_DATA_SWTS_MASK 0x400000u
emilmont	2:e9a661555b58	3382	#define TSI_DATA_SWTS_SHIFT 22
emilmont	2:e9a661555b58	3383	#define TSI_DATA_DMAEN_MASK 0x800000u
emilmont	2:e9a661555b58	3384	#define TSI_DATA_DMAEN_SHIFT 23
emilmont	2:e9a661555b58	3385	#define TSI_DATA_TSICH_MASK 0xF0000000u
emilmont	2:e9a661555b58	3386	#define TSI_DATA_TSICH_SHIFT 28
emilmont	2:e9a661555b58	3387	#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
emilmont	2:e9a661555b58	3388	/* TSHD Bit Fields */
emilmont	2:e9a661555b58	3389	#define TSI_TSHD_THRESL_MASK 0xFFFFu
emilmont	2:e9a661555b58	3390	#define TSI_TSHD_THRESL_SHIFT 0
emilmont	2:e9a661555b58	3391	#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
emilmont	2:e9a661555b58	3392	#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
emilmont	2:e9a661555b58	3393	#define TSI_TSHD_THRESH_SHIFT 16
emilmont	2:e9a661555b58	3394	#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
emilmont	2:e9a661555b58	3395
emilmont	2:e9a661555b58	3396	/**
emilmont	2:e9a661555b58	3397	* @}
emilmont	2:e9a661555b58	3398	/ / end of group TSI_Register_Masks */
emilmont	2:e9a661555b58	3399
emilmont	2:e9a661555b58	3400
emilmont	2:e9a661555b58	3401	/* TSI - Peripheral instance base addresses */
emilmont	2:e9a661555b58	3402	/** Peripheral TSI0 base address */
emilmont	2:e9a661555b58	3403	#define TSI0_BASE (0x40045000u)
emilmont	2:e9a661555b58	3404	/** Peripheral TSI0 base pointer */
emilmont	2:e9a661555b58	3405	#define TSI0 ((TSI_Type *)TSI0_BASE)
emilmont	2:e9a661555b58	3406	/** Array initializer of TSI peripheral base pointers */
emilmont	2:e9a661555b58	3407	#define TSI_BASES { TSI0 }
emilmont	2:e9a661555b58	3408
emilmont	2:e9a661555b58	3409	/**
emilmont	2:e9a661555b58	3410	* @}
emilmont	2:e9a661555b58	3411	/ / end of group TSI_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	3412
emilmont	2:e9a661555b58	3413
emilmont	2:e9a661555b58	3414	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3415	-- UART Peripheral Access Layer
emilmont	2:e9a661555b58	3416	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3417
emilmont	2:e9a661555b58	3418	/**
emilmont	2:e9a661555b58	3419	* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
emilmont	2:e9a661555b58	3420	* @{
emilmont	2:e9a661555b58	3421	*/
emilmont	2:e9a661555b58	3422
emilmont	2:e9a661555b58	3423	/** UART - Register Layout Typedef */
emilmont	2:e9a661555b58	3424	typedef struct {
emilmont	2:e9a661555b58	3425	__IO uint8_t BDH; /*< UART Baud Rate Register: High, offset: 0x0 /
emilmont	2:e9a661555b58	3426	__IO uint8_t BDL; /*< UART Baud Rate Register: Low, offset: 0x1 /
emilmont	2:e9a661555b58	3427	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
emilmont	2:e9a661555b58	3428	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
emilmont	2:e9a661555b58	3429	__I uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
emilmont	2:e9a661555b58	3430	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
emilmont	2:e9a661555b58	3431	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
emilmont	2:e9a661555b58	3432	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
emilmont	2:e9a661555b58	3433	__IO uint8_t C4; /*< UART Control Register 4, offset: 0x8 /
emilmont	2:e9a661555b58	3434	} UART_Type;
emilmont	2:e9a661555b58	3435
emilmont	2:e9a661555b58	3436	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3437	-- UART Register Masks
emilmont	2:e9a661555b58	3438	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3439
emilmont	2:e9a661555b58	3440	/**
emilmont	2:e9a661555b58	3441	* @addtogroup UART_Register_Masks UART Register Masks
emilmont	2:e9a661555b58	3442	* @{
emilmont	2:e9a661555b58	3443	*/
emilmont	2:e9a661555b58	3444
emilmont	2:e9a661555b58	3445	/* BDH Bit Fields */
emilmont	2:e9a661555b58	3446	#define UART_BDH_SBR_MASK 0x1Fu
emilmont	2:e9a661555b58	3447	#define UART_BDH_SBR_SHIFT 0
emilmont	2:e9a661555b58	3448	#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
emilmont	2:e9a661555b58	3449	#define UART_BDH_SBNS_MASK 0x20u
emilmont	2:e9a661555b58	3450	#define UART_BDH_SBNS_SHIFT 5
emilmont	2:e9a661555b58	3451	#define UART_BDH_RXEDGIE_MASK 0x40u
emilmont	2:e9a661555b58	3452	#define UART_BDH_RXEDGIE_SHIFT 6
emilmont	2:e9a661555b58	3453	#define UART_BDH_LBKDIE_MASK 0x80u
emilmont	2:e9a661555b58	3454	#define UART_BDH_LBKDIE_SHIFT 7
emilmont	2:e9a661555b58	3455	/* BDL Bit Fields */
emilmont	2:e9a661555b58	3456	#define UART_BDL_SBR_MASK 0xFFu
emilmont	2:e9a661555b58	3457	#define UART_BDL_SBR_SHIFT 0
emilmont	2:e9a661555b58	3458	#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
emilmont	2:e9a661555b58	3459	/* C1 Bit Fields */
emilmont	2:e9a661555b58	3460	#define UART_C1_PT_MASK 0x1u
emilmont	2:e9a661555b58	3461	#define UART_C1_PT_SHIFT 0
emilmont	2:e9a661555b58	3462	#define UART_C1_PE_MASK 0x2u
emilmont	2:e9a661555b58	3463	#define UART_C1_PE_SHIFT 1
emilmont	2:e9a661555b58	3464	#define UART_C1_ILT_MASK 0x4u
emilmont	2:e9a661555b58	3465	#define UART_C1_ILT_SHIFT 2
emilmont	2:e9a661555b58	3466	#define UART_C1_WAKE_MASK 0x8u
emilmont	2:e9a661555b58	3467	#define UART_C1_WAKE_SHIFT 3
emilmont	2:e9a661555b58	3468	#define UART_C1_M_MASK 0x10u
emilmont	2:e9a661555b58	3469	#define UART_C1_M_SHIFT 4
emilmont	2:e9a661555b58	3470	#define UART_C1_RSRC_MASK 0x20u
emilmont	2:e9a661555b58	3471	#define UART_C1_RSRC_SHIFT 5
emilmont	2:e9a661555b58	3472	#define UART_C1_UARTSWAI_MASK 0x40u
emilmont	2:e9a661555b58	3473	#define UART_C1_UARTSWAI_SHIFT 6
emilmont	2:e9a661555b58	3474	#define UART_C1_LOOPS_MASK 0x80u
emilmont	2:e9a661555b58	3475	#define UART_C1_LOOPS_SHIFT 7
emilmont	2:e9a661555b58	3476	/* C2 Bit Fields */
emilmont	2:e9a661555b58	3477	#define UART_C2_SBK_MASK 0x1u
emilmont	2:e9a661555b58	3478	#define UART_C2_SBK_SHIFT 0
emilmont	2:e9a661555b58	3479	#define UART_C2_RWU_MASK 0x2u
emilmont	2:e9a661555b58	3480	#define UART_C2_RWU_SHIFT 1
emilmont	2:e9a661555b58	3481	#define UART_C2_RE_MASK 0x4u
emilmont	2:e9a661555b58	3482	#define UART_C2_RE_SHIFT 2
emilmont	2:e9a661555b58	3483	#define UART_C2_TE_MASK 0x8u
emilmont	2:e9a661555b58	3484	#define UART_C2_TE_SHIFT 3
emilmont	2:e9a661555b58	3485	#define UART_C2_ILIE_MASK 0x10u
emilmont	2:e9a661555b58	3486	#define UART_C2_ILIE_SHIFT 4
emilmont	2:e9a661555b58	3487	#define UART_C2_RIE_MASK 0x20u
emilmont	2:e9a661555b58	3488	#define UART_C2_RIE_SHIFT 5
emilmont	2:e9a661555b58	3489	#define UART_C2_TCIE_MASK 0x40u
emilmont	2:e9a661555b58	3490	#define UART_C2_TCIE_SHIFT 6
emilmont	2:e9a661555b58	3491	#define UART_C2_TIE_MASK 0x80u
emilmont	2:e9a661555b58	3492	#define UART_C2_TIE_SHIFT 7
emilmont	2:e9a661555b58	3493	/* S1 Bit Fields */
emilmont	2:e9a661555b58	3494	#define UART_S1_PF_MASK 0x1u
emilmont	2:e9a661555b58	3495	#define UART_S1_PF_SHIFT 0
emilmont	2:e9a661555b58	3496	#define UART_S1_FE_MASK 0x2u
emilmont	2:e9a661555b58	3497	#define UART_S1_FE_SHIFT 1
emilmont	2:e9a661555b58	3498	#define UART_S1_NF_MASK 0x4u
emilmont	2:e9a661555b58	3499	#define UART_S1_NF_SHIFT 2
emilmont	2:e9a661555b58	3500	#define UART_S1_OR_MASK 0x8u
emilmont	2:e9a661555b58	3501	#define UART_S1_OR_SHIFT 3
emilmont	2:e9a661555b58	3502	#define UART_S1_IDLE_MASK 0x10u
emilmont	2:e9a661555b58	3503	#define UART_S1_IDLE_SHIFT 4
emilmont	2:e9a661555b58	3504	#define UART_S1_RDRF_MASK 0x20u
emilmont	2:e9a661555b58	3505	#define UART_S1_RDRF_SHIFT 5
emilmont	2:e9a661555b58	3506	#define UART_S1_TC_MASK 0x40u
emilmont	2:e9a661555b58	3507	#define UART_S1_TC_SHIFT 6
emilmont	2:e9a661555b58	3508	#define UART_S1_TDRE_MASK 0x80u
emilmont	2:e9a661555b58	3509	#define UART_S1_TDRE_SHIFT 7
emilmont	2:e9a661555b58	3510	/* S2 Bit Fields */
emilmont	2:e9a661555b58	3511	#define UART_S2_RAF_MASK 0x1u
emilmont	2:e9a661555b58	3512	#define UART_S2_RAF_SHIFT 0
emilmont	2:e9a661555b58	3513	#define UART_S2_LBKDE_MASK 0x2u
emilmont	2:e9a661555b58	3514	#define UART_S2_LBKDE_SHIFT 1
emilmont	2:e9a661555b58	3515	#define UART_S2_BRK13_MASK 0x4u
emilmont	2:e9a661555b58	3516	#define UART_S2_BRK13_SHIFT 2
emilmont	2:e9a661555b58	3517	#define UART_S2_RWUID_MASK 0x8u
emilmont	2:e9a661555b58	3518	#define UART_S2_RWUID_SHIFT 3
emilmont	2:e9a661555b58	3519	#define UART_S2_RXINV_MASK 0x10u
emilmont	2:e9a661555b58	3520	#define UART_S2_RXINV_SHIFT 4
emilmont	2:e9a661555b58	3521	#define UART_S2_RXEDGIF_MASK 0x40u
emilmont	2:e9a661555b58	3522	#define UART_S2_RXEDGIF_SHIFT 6
emilmont	2:e9a661555b58	3523	#define UART_S2_LBKDIF_MASK 0x80u
emilmont	2:e9a661555b58	3524	#define UART_S2_LBKDIF_SHIFT 7
emilmont	2:e9a661555b58	3525	/* C3 Bit Fields */
emilmont	2:e9a661555b58	3526	#define UART_C3_PEIE_MASK 0x1u
emilmont	2:e9a661555b58	3527	#define UART_C3_PEIE_SHIFT 0
emilmont	2:e9a661555b58	3528	#define UART_C3_FEIE_MASK 0x2u
emilmont	2:e9a661555b58	3529	#define UART_C3_FEIE_SHIFT 1
emilmont	2:e9a661555b58	3530	#define UART_C3_NEIE_MASK 0x4u
emilmont	2:e9a661555b58	3531	#define UART_C3_NEIE_SHIFT 2
emilmont	2:e9a661555b58	3532	#define UART_C3_ORIE_MASK 0x8u
emilmont	2:e9a661555b58	3533	#define UART_C3_ORIE_SHIFT 3
emilmont	2:e9a661555b58	3534	#define UART_C3_TXINV_MASK 0x10u
emilmont	2:e9a661555b58	3535	#define UART_C3_TXINV_SHIFT 4
emilmont	2:e9a661555b58	3536	#define UART_C3_TXDIR_MASK 0x20u
emilmont	2:e9a661555b58	3537	#define UART_C3_TXDIR_SHIFT 5
emilmont	2:e9a661555b58	3538	#define UART_C3_T8_MASK 0x40u
emilmont	2:e9a661555b58	3539	#define UART_C3_T8_SHIFT 6
emilmont	2:e9a661555b58	3540	#define UART_C3_R8_MASK 0x80u
emilmont	2:e9a661555b58	3541	#define UART_C3_R8_SHIFT 7
emilmont	2:e9a661555b58	3542	/* D Bit Fields */
emilmont	2:e9a661555b58	3543	#define UART_D_R0T0_MASK 0x1u
emilmont	2:e9a661555b58	3544	#define UART_D_R0T0_SHIFT 0
emilmont	2:e9a661555b58	3545	#define UART_D_R1T1_MASK 0x2u
emilmont	2:e9a661555b58	3546	#define UART_D_R1T1_SHIFT 1
emilmont	2:e9a661555b58	3547	#define UART_D_R2T2_MASK 0x4u
emilmont	2:e9a661555b58	3548	#define UART_D_R2T2_SHIFT 2
emilmont	2:e9a661555b58	3549	#define UART_D_R3T3_MASK 0x8u
emilmont	2:e9a661555b58	3550	#define UART_D_R3T3_SHIFT 3
emilmont	2:e9a661555b58	3551	#define UART_D_R4T4_MASK 0x10u
emilmont	2:e9a661555b58	3552	#define UART_D_R4T4_SHIFT 4
emilmont	2:e9a661555b58	3553	#define UART_D_R5T5_MASK 0x20u
emilmont	2:e9a661555b58	3554	#define UART_D_R5T5_SHIFT 5
emilmont	2:e9a661555b58	3555	#define UART_D_R6T6_MASK 0x40u
emilmont	2:e9a661555b58	3556	#define UART_D_R6T6_SHIFT 6
emilmont	2:e9a661555b58	3557	#define UART_D_R7T7_MASK 0x80u
emilmont	2:e9a661555b58	3558	#define UART_D_R7T7_SHIFT 7
emilmont	2:e9a661555b58	3559	/* C4 Bit Fields */
emilmont	2:e9a661555b58	3560	#define UART_C4_LBKDDMAS_MASK 0x8u
emilmont	2:e9a661555b58	3561	#define UART_C4_LBKDDMAS_SHIFT 3
emilmont	2:e9a661555b58	3562	#define UART_C4_ILDMAS_MASK 0x10u
emilmont	2:e9a661555b58	3563	#define UART_C4_ILDMAS_SHIFT 4
emilmont	2:e9a661555b58	3564	#define UART_C4_RDMAS_MASK 0x20u
emilmont	2:e9a661555b58	3565	#define UART_C4_RDMAS_SHIFT 5
emilmont	2:e9a661555b58	3566	#define UART_C4_TCDMAS_MASK 0x40u
emilmont	2:e9a661555b58	3567	#define UART_C4_TCDMAS_SHIFT 6
emilmont	2:e9a661555b58	3568	#define UART_C4_TDMAS_MASK 0x80u
emilmont	2:e9a661555b58	3569	#define UART_C4_TDMAS_SHIFT 7
emilmont	2:e9a661555b58	3570
emilmont	2:e9a661555b58	3571	/**
emilmont	2:e9a661555b58	3572	* @}
emilmont	2:e9a661555b58	3573	/ / end of group UART_Register_Masks */
emilmont	2:e9a661555b58	3574
emilmont	2:e9a661555b58	3575
emilmont	2:e9a661555b58	3576	/* UART - Peripheral instance base addresses */
emilmont	2:e9a661555b58	3577	/** Peripheral UART1 base address */
emilmont	2:e9a661555b58	3578	#define UART1_BASE (0x4006B000u)
emilmont	2:e9a661555b58	3579	/** Peripheral UART1 base pointer */
emilmont	2:e9a661555b58	3580	#define UART1 ((UART_Type *)UART1_BASE)
emilmont	2:e9a661555b58	3581	/** Peripheral UART2 base address */
emilmont	2:e9a661555b58	3582	#define UART2_BASE (0x4006C000u)
emilmont	2:e9a661555b58	3583	/** Peripheral UART2 base pointer */
emilmont	2:e9a661555b58	3584	#define UART2 ((UART_Type *)UART2_BASE)
emilmont	2:e9a661555b58	3585	/** Array initializer of UART peripheral base pointers */
emilmont	2:e9a661555b58	3586	#define UART_BASES { UART1, UART2 }
emilmont	2:e9a661555b58	3587
emilmont	2:e9a661555b58	3588	/**
emilmont	2:e9a661555b58	3589	* @}
emilmont	2:e9a661555b58	3590	/ / end of group UART_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	3591
emilmont	2:e9a661555b58	3592
emilmont	2:e9a661555b58	3593	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3594	-- UARTLP Peripheral Access Layer
emilmont	2:e9a661555b58	3595	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3596
emilmont	2:e9a661555b58	3597	/**
emilmont	2:e9a661555b58	3598	* @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
emilmont	2:e9a661555b58	3599	* @{
emilmont	2:e9a661555b58	3600	*/
emilmont	2:e9a661555b58	3601
emilmont	2:e9a661555b58	3602	/** UARTLP - Register Layout Typedef */
emilmont	2:e9a661555b58	3603	typedef struct {
emilmont	2:e9a661555b58	3604	__IO uint8_t BDH; /*< UART Baud Rate Register High, offset: 0x0 /
emilmont	2:e9a661555b58	3605	__IO uint8_t BDL; /*< UART Baud Rate Register Low, offset: 0x1 /
emilmont	2:e9a661555b58	3606	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
emilmont	2:e9a661555b58	3607	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
emilmont	2:e9a661555b58	3608	__IO uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
emilmont	2:e9a661555b58	3609	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
emilmont	2:e9a661555b58	3610	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
emilmont	2:e9a661555b58	3611	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
emilmont	2:e9a661555b58	3612	__IO uint8_t MA1; /*< UART Match Address Registers 1, offset: 0x8 /
emilmont	2:e9a661555b58	3613	__IO uint8_t MA2; /*< UART Match Address Registers 2, offset: 0x9 /
emilmont	2:e9a661555b58	3614	__IO uint8_t C4; /*< UART Control Register 4, offset: 0xA /
emilmont	2:e9a661555b58	3615	__IO uint8_t C5; /*< UART Control Register 5, offset: 0xB /
emilmont	2:e9a661555b58	3616	} UARTLP_Type;
emilmont	2:e9a661555b58	3617
emilmont	2:e9a661555b58	3618	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3619	-- UARTLP Register Masks
emilmont	2:e9a661555b58	3620	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3621
emilmont	2:e9a661555b58	3622	/**
emilmont	2:e9a661555b58	3623	* @addtogroup UARTLP_Register_Masks UARTLP Register Masks
emilmont	2:e9a661555b58	3624	* @{
emilmont	2:e9a661555b58	3625	*/
emilmont	2:e9a661555b58	3626
emilmont	2:e9a661555b58	3627	/* BDH Bit Fields */
emilmont	2:e9a661555b58	3628	#define UARTLP_BDH_SBR_MASK 0x1Fu
emilmont	2:e9a661555b58	3629	#define UARTLP_BDH_SBR_SHIFT 0
emilmont	2:e9a661555b58	3630	#define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
emilmont	2:e9a661555b58	3631	#define UARTLP_BDH_SBNS_MASK 0x20u
emilmont	2:e9a661555b58	3632	#define UARTLP_BDH_SBNS_SHIFT 5
emilmont	2:e9a661555b58	3633	#define UARTLP_BDH_RXEDGIE_MASK 0x40u
emilmont	2:e9a661555b58	3634	#define UARTLP_BDH_RXEDGIE_SHIFT 6
emilmont	2:e9a661555b58	3635	#define UARTLP_BDH_LBKDIE_MASK 0x80u
emilmont	2:e9a661555b58	3636	#define UARTLP_BDH_LBKDIE_SHIFT 7
emilmont	2:e9a661555b58	3637	/* BDL Bit Fields */
emilmont	2:e9a661555b58	3638	#define UARTLP_BDL_SBR_MASK 0xFFu
emilmont	2:e9a661555b58	3639	#define UARTLP_BDL_SBR_SHIFT 0
emilmont	2:e9a661555b58	3640	#define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
emilmont	2:e9a661555b58	3641	/* C1 Bit Fields */
emilmont	2:e9a661555b58	3642	#define UARTLP_C1_PT_MASK 0x1u
emilmont	2:e9a661555b58	3643	#define UARTLP_C1_PT_SHIFT 0
emilmont	2:e9a661555b58	3644	#define UARTLP_C1_PE_MASK 0x2u
emilmont	2:e9a661555b58	3645	#define UARTLP_C1_PE_SHIFT 1
emilmont	2:e9a661555b58	3646	#define UARTLP_C1_ILT_MASK 0x4u
emilmont	2:e9a661555b58	3647	#define UARTLP_C1_ILT_SHIFT 2
emilmont	2:e9a661555b58	3648	#define UARTLP_C1_WAKE_MASK 0x8u
emilmont	2:e9a661555b58	3649	#define UARTLP_C1_WAKE_SHIFT 3
emilmont	2:e9a661555b58	3650	#define UARTLP_C1_M_MASK 0x10u
emilmont	2:e9a661555b58	3651	#define UARTLP_C1_M_SHIFT 4
emilmont	2:e9a661555b58	3652	#define UARTLP_C1_RSRC_MASK 0x20u
emilmont	2:e9a661555b58	3653	#define UARTLP_C1_RSRC_SHIFT 5
emilmont	2:e9a661555b58	3654	#define UARTLP_C1_DOZEEN_MASK 0x40u
emilmont	2:e9a661555b58	3655	#define UARTLP_C1_DOZEEN_SHIFT 6
emilmont	2:e9a661555b58	3656	#define UARTLP_C1_LOOPS_MASK 0x80u
emilmont	2:e9a661555b58	3657	#define UARTLP_C1_LOOPS_SHIFT 7
emilmont	2:e9a661555b58	3658	/* C2 Bit Fields */
emilmont	2:e9a661555b58	3659	#define UARTLP_C2_SBK_MASK 0x1u
emilmont	2:e9a661555b58	3660	#define UARTLP_C2_SBK_SHIFT 0
emilmont	2:e9a661555b58	3661	#define UARTLP_C2_RWU_MASK 0x2u
emilmont	2:e9a661555b58	3662	#define UARTLP_C2_RWU_SHIFT 1
emilmont	2:e9a661555b58	3663	#define UARTLP_C2_RE_MASK 0x4u
emilmont	2:e9a661555b58	3664	#define UARTLP_C2_RE_SHIFT 2
emilmont	2:e9a661555b58	3665	#define UARTLP_C2_TE_MASK 0x8u
emilmont	2:e9a661555b58	3666	#define UARTLP_C2_TE_SHIFT 3
emilmont	2:e9a661555b58	3667	#define UARTLP_C2_ILIE_MASK 0x10u
emilmont	2:e9a661555b58	3668	#define UARTLP_C2_ILIE_SHIFT 4
emilmont	2:e9a661555b58	3669	#define UARTLP_C2_RIE_MASK 0x20u
emilmont	2:e9a661555b58	3670	#define UARTLP_C2_RIE_SHIFT 5
emilmont	2:e9a661555b58	3671	#define UARTLP_C2_TCIE_MASK 0x40u
emilmont	2:e9a661555b58	3672	#define UARTLP_C2_TCIE_SHIFT 6
emilmont	2:e9a661555b58	3673	#define UARTLP_C2_TIE_MASK 0x80u
emilmont	2:e9a661555b58	3674	#define UARTLP_C2_TIE_SHIFT 7
emilmont	2:e9a661555b58	3675	/* S1 Bit Fields */
emilmont	2:e9a661555b58	3676	#define UARTLP_S1_PF_MASK 0x1u
emilmont	2:e9a661555b58	3677	#define UARTLP_S1_PF_SHIFT 0
emilmont	2:e9a661555b58	3678	#define UARTLP_S1_FE_MASK 0x2u
emilmont	2:e9a661555b58	3679	#define UARTLP_S1_FE_SHIFT 1
emilmont	2:e9a661555b58	3680	#define UARTLP_S1_NF_MASK 0x4u
emilmont	2:e9a661555b58	3681	#define UARTLP_S1_NF_SHIFT 2
emilmont	2:e9a661555b58	3682	#define UARTLP_S1_OR_MASK 0x8u
emilmont	2:e9a661555b58	3683	#define UARTLP_S1_OR_SHIFT 3
emilmont	2:e9a661555b58	3684	#define UARTLP_S1_IDLE_MASK 0x10u
emilmont	2:e9a661555b58	3685	#define UARTLP_S1_IDLE_SHIFT 4
emilmont	2:e9a661555b58	3686	#define UARTLP_S1_RDRF_MASK 0x20u
emilmont	2:e9a661555b58	3687	#define UARTLP_S1_RDRF_SHIFT 5
emilmont	2:e9a661555b58	3688	#define UARTLP_S1_TC_MASK 0x40u
emilmont	2:e9a661555b58	3689	#define UARTLP_S1_TC_SHIFT 6
emilmont	2:e9a661555b58	3690	#define UARTLP_S1_TDRE_MASK 0x80u
emilmont	2:e9a661555b58	3691	#define UARTLP_S1_TDRE_SHIFT 7
emilmont	2:e9a661555b58	3692	/* S2 Bit Fields */
emilmont	2:e9a661555b58	3693	#define UARTLP_S2_RAF_MASK 0x1u
emilmont	2:e9a661555b58	3694	#define UARTLP_S2_RAF_SHIFT 0
emilmont	2:e9a661555b58	3695	#define UARTLP_S2_LBKDE_MASK 0x2u
emilmont	2:e9a661555b58	3696	#define UARTLP_S2_LBKDE_SHIFT 1
emilmont	2:e9a661555b58	3697	#define UARTLP_S2_BRK13_MASK 0x4u
emilmont	2:e9a661555b58	3698	#define UARTLP_S2_BRK13_SHIFT 2
emilmont	2:e9a661555b58	3699	#define UARTLP_S2_RWUID_MASK 0x8u
emilmont	2:e9a661555b58	3700	#define UARTLP_S2_RWUID_SHIFT 3
emilmont	2:e9a661555b58	3701	#define UARTLP_S2_RXINV_MASK 0x10u
emilmont	2:e9a661555b58	3702	#define UARTLP_S2_RXINV_SHIFT 4
emilmont	2:e9a661555b58	3703	#define UARTLP_S2_MSBF_MASK 0x20u
emilmont	2:e9a661555b58	3704	#define UARTLP_S2_MSBF_SHIFT 5
emilmont	2:e9a661555b58	3705	#define UARTLP_S2_RXEDGIF_MASK 0x40u
emilmont	2:e9a661555b58	3706	#define UARTLP_S2_RXEDGIF_SHIFT 6
emilmont	2:e9a661555b58	3707	#define UARTLP_S2_LBKDIF_MASK 0x80u
emilmont	2:e9a661555b58	3708	#define UARTLP_S2_LBKDIF_SHIFT 7
emilmont	2:e9a661555b58	3709	/* C3 Bit Fields */
emilmont	2:e9a661555b58	3710	#define UARTLP_C3_PEIE_MASK 0x1u
emilmont	2:e9a661555b58	3711	#define UARTLP_C3_PEIE_SHIFT 0
emilmont	2:e9a661555b58	3712	#define UARTLP_C3_FEIE_MASK 0x2u
emilmont	2:e9a661555b58	3713	#define UARTLP_C3_FEIE_SHIFT 1
emilmont	2:e9a661555b58	3714	#define UARTLP_C3_NEIE_MASK 0x4u
emilmont	2:e9a661555b58	3715	#define UARTLP_C3_NEIE_SHIFT 2
emilmont	2:e9a661555b58	3716	#define UARTLP_C3_ORIE_MASK 0x8u
emilmont	2:e9a661555b58	3717	#define UARTLP_C3_ORIE_SHIFT 3
emilmont	2:e9a661555b58	3718	#define UARTLP_C3_TXINV_MASK 0x10u
emilmont	2:e9a661555b58	3719	#define UARTLP_C3_TXINV_SHIFT 4
emilmont	2:e9a661555b58	3720	#define UARTLP_C3_TXDIR_MASK 0x20u
emilmont	2:e9a661555b58	3721	#define UARTLP_C3_TXDIR_SHIFT 5
emilmont	2:e9a661555b58	3722	#define UARTLP_C3_R9T8_MASK 0x40u
emilmont	2:e9a661555b58	3723	#define UARTLP_C3_R9T8_SHIFT 6
emilmont	2:e9a661555b58	3724	#define UARTLP_C3_R8T9_MASK 0x80u
emilmont	2:e9a661555b58	3725	#define UARTLP_C3_R8T9_SHIFT 7
emilmont	2:e9a661555b58	3726	/* D Bit Fields */
emilmont	2:e9a661555b58	3727	#define UARTLP_D_R0T0_MASK 0x1u
emilmont	2:e9a661555b58	3728	#define UARTLP_D_R0T0_SHIFT 0
emilmont	2:e9a661555b58	3729	#define UARTLP_D_R1T1_MASK 0x2u
emilmont	2:e9a661555b58	3730	#define UARTLP_D_R1T1_SHIFT 1
emilmont	2:e9a661555b58	3731	#define UARTLP_D_R2T2_MASK 0x4u
emilmont	2:e9a661555b58	3732	#define UARTLP_D_R2T2_SHIFT 2
emilmont	2:e9a661555b58	3733	#define UARTLP_D_R3T3_MASK 0x8u
emilmont	2:e9a661555b58	3734	#define UARTLP_D_R3T3_SHIFT 3
emilmont	2:e9a661555b58	3735	#define UARTLP_D_R4T4_MASK 0x10u
emilmont	2:e9a661555b58	3736	#define UARTLP_D_R4T4_SHIFT 4
emilmont	2:e9a661555b58	3737	#define UARTLP_D_R5T5_MASK 0x20u
emilmont	2:e9a661555b58	3738	#define UARTLP_D_R5T5_SHIFT 5
emilmont	2:e9a661555b58	3739	#define UARTLP_D_R6T6_MASK 0x40u
emilmont	2:e9a661555b58	3740	#define UARTLP_D_R6T6_SHIFT 6
emilmont	2:e9a661555b58	3741	#define UARTLP_D_R7T7_MASK 0x80u
emilmont	2:e9a661555b58	3742	#define UARTLP_D_R7T7_SHIFT 7
emilmont	2:e9a661555b58	3743	/* MA1 Bit Fields */
emilmont	2:e9a661555b58	3744	#define UARTLP_MA1_MA_MASK 0xFFu
emilmont	2:e9a661555b58	3745	#define UARTLP_MA1_MA_SHIFT 0
emilmont	2:e9a661555b58	3746	#define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
emilmont	2:e9a661555b58	3747	/* MA2 Bit Fields */
emilmont	2:e9a661555b58	3748	#define UARTLP_MA2_MA_MASK 0xFFu
emilmont	2:e9a661555b58	3749	#define UARTLP_MA2_MA_SHIFT 0
emilmont	2:e9a661555b58	3750	#define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
emilmont	2:e9a661555b58	3751	/* C4 Bit Fields */
emilmont	2:e9a661555b58	3752	#define UARTLP_C4_OSR_MASK 0x1Fu
emilmont	2:e9a661555b58	3753	#define UARTLP_C4_OSR_SHIFT 0
emilmont	2:e9a661555b58	3754	#define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
emilmont	2:e9a661555b58	3755	#define UARTLP_C4_M10_MASK 0x20u
emilmont	2:e9a661555b58	3756	#define UARTLP_C4_M10_SHIFT 5
emilmont	2:e9a661555b58	3757	#define UARTLP_C4_MAEN2_MASK 0x40u
emilmont	2:e9a661555b58	3758	#define UARTLP_C4_MAEN2_SHIFT 6
emilmont	2:e9a661555b58	3759	#define UARTLP_C4_MAEN1_MASK 0x80u
emilmont	2:e9a661555b58	3760	#define UARTLP_C4_MAEN1_SHIFT 7
emilmont	2:e9a661555b58	3761	/* C5 Bit Fields */
emilmont	2:e9a661555b58	3762	#define UARTLP_C5_RESYNCDIS_MASK 0x1u
emilmont	2:e9a661555b58	3763	#define UARTLP_C5_RESYNCDIS_SHIFT 0
emilmont	2:e9a661555b58	3764	#define UARTLP_C5_BOTHEDGE_MASK 0x2u
emilmont	2:e9a661555b58	3765	#define UARTLP_C5_BOTHEDGE_SHIFT 1
emilmont	2:e9a661555b58	3766	#define UARTLP_C5_RDMAE_MASK 0x20u
emilmont	2:e9a661555b58	3767	#define UARTLP_C5_RDMAE_SHIFT 5
emilmont	2:e9a661555b58	3768	#define UARTLP_C5_TDMAE_MASK 0x80u
emilmont	2:e9a661555b58	3769	#define UARTLP_C5_TDMAE_SHIFT 7
emilmont	2:e9a661555b58	3770
emilmont	2:e9a661555b58	3771	/**
emilmont	2:e9a661555b58	3772	* @}
emilmont	2:e9a661555b58	3773	/ / end of group UARTLP_Register_Masks */
emilmont	2:e9a661555b58	3774
emilmont	2:e9a661555b58	3775
emilmont	2:e9a661555b58	3776	/* UARTLP - Peripheral instance base addresses */
emilmont	2:e9a661555b58	3777	/** Peripheral UART0 base address */
emilmont	2:e9a661555b58	3778	#define UART0_BASE (0x4006A000u)
emilmont	2:e9a661555b58	3779	/** Peripheral UART0 base pointer */
emilmont	2:e9a661555b58	3780	#define UART0 ((UARTLP_Type *)UART0_BASE)
emilmont	2:e9a661555b58	3781	/** Array initializer of UARTLP peripheral base pointers */
emilmont	2:e9a661555b58	3782	#define UARTLP_BASES { UART0 }
emilmont	2:e9a661555b58	3783
emilmont	2:e9a661555b58	3784	/**
emilmont	2:e9a661555b58	3785	* @}
emilmont	2:e9a661555b58	3786	/ / end of group UARTLP_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	3787
emilmont	2:e9a661555b58	3788
emilmont	2:e9a661555b58	3789	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3790	-- USB Peripheral Access Layer
emilmont	2:e9a661555b58	3791	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3792
emilmont	2:e9a661555b58	3793	/**
emilmont	2:e9a661555b58	3794	* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
emilmont	2:e9a661555b58	3795	* @{
emilmont	2:e9a661555b58	3796	*/
emilmont	2:e9a661555b58	3797
emilmont	2:e9a661555b58	3798	/** USB - Register Layout Typedef */
emilmont	2:e9a661555b58	3799	typedef struct {
emilmont	2:e9a661555b58	3800	__I uint8_t PERID; /*< Peripheral ID register, offset: 0x0 /
emilmont	2:e9a661555b58	3801	uint8_t RESERVED_0[3];
emilmont	2:e9a661555b58	3802	__I uint8_t IDCOMP; /*< Peripheral ID Complement register, offset: 0x4 /
emilmont	2:e9a661555b58	3803	uint8_t RESERVED_1[3];
emilmont	2:e9a661555b58	3804	__I uint8_t REV; /*< Peripheral Revision register, offset: 0x8 /
emilmont	2:e9a661555b58	3805	uint8_t RESERVED_2[3];
emilmont	2:e9a661555b58	3806	__I uint8_t ADDINFO; /*< Peripheral Additional Info register, offset: 0xC /
emilmont	2:e9a661555b58	3807	uint8_t RESERVED_3[3];
emilmont	2:e9a661555b58	3808	__IO uint8_t OTGISTAT; /*< OTG Interrupt Status register, offset: 0x10 /
emilmont	2:e9a661555b58	3809	uint8_t RESERVED_4[3];
emilmont	2:e9a661555b58	3810	__IO uint8_t OTGICR; /*< OTG Interrupt Control Register, offset: 0x14 /
emilmont	2:e9a661555b58	3811	uint8_t RESERVED_5[3];
emilmont	2:e9a661555b58	3812	__IO uint8_t OTGSTAT; /*< OTG Status register, offset: 0x18 /
emilmont	2:e9a661555b58	3813	uint8_t RESERVED_6[3];
emilmont	2:e9a661555b58	3814	__IO uint8_t OTGCTL; /*< OTG Control register, offset: 0x1C /
emilmont	2:e9a661555b58	3815	uint8_t RESERVED_7[99];
emilmont	2:e9a661555b58	3816	__IO uint8_t ISTAT; /*< Interrupt Status register, offset: 0x80 /
emilmont	2:e9a661555b58	3817	uint8_t RESERVED_8[3];
emilmont	2:e9a661555b58	3818	__IO uint8_t INTEN; /*< Interrupt Enable register, offset: 0x84 /
emilmont	2:e9a661555b58	3819	uint8_t RESERVED_9[3];
emilmont	2:e9a661555b58	3820	__IO uint8_t ERRSTAT; /*< Error Interrupt Status register, offset: 0x88 /
emilmont	2:e9a661555b58	3821	uint8_t RESERVED_10[3];
emilmont	2:e9a661555b58	3822	__IO uint8_t ERREN; /*< Error Interrupt Enable register, offset: 0x8C /
emilmont	2:e9a661555b58	3823	uint8_t RESERVED_11[3];
emilmont	2:e9a661555b58	3824	__I uint8_t STAT; /*< Status register, offset: 0x90 /
emilmont	2:e9a661555b58	3825	uint8_t RESERVED_12[3];
emilmont	2:e9a661555b58	3826	__IO uint8_t CTL; /*< Control register, offset: 0x94 /
emilmont	2:e9a661555b58	3827	uint8_t RESERVED_13[3];
emilmont	2:e9a661555b58	3828	__IO uint8_t ADDR; /*< Address register, offset: 0x98 /
emilmont	2:e9a661555b58	3829	uint8_t RESERVED_14[3];
emilmont	2:e9a661555b58	3830	__IO uint8_t BDTPAGE1; /*< BDT Page Register 1, offset: 0x9C /
emilmont	2:e9a661555b58	3831	uint8_t RESERVED_15[3];
emilmont	2:e9a661555b58	3832	__IO uint8_t FRMNUML; /*< Frame Number Register Low, offset: 0xA0 /
emilmont	2:e9a661555b58	3833	uint8_t RESERVED_16[3];
emilmont	2:e9a661555b58	3834	__IO uint8_t FRMNUMH; /*< Frame Number Register High, offset: 0xA4 /
emilmont	2:e9a661555b58	3835	uint8_t RESERVED_17[3];
emilmont	2:e9a661555b58	3836	__IO uint8_t TOKEN; /*< Token register, offset: 0xA8 /
emilmont	2:e9a661555b58	3837	uint8_t RESERVED_18[3];
emilmont	2:e9a661555b58	3838	__IO uint8_t SOFTHLD; /*< SOF Threshold Register, offset: 0xAC /
emilmont	2:e9a661555b58	3839	uint8_t RESERVED_19[3];
emilmont	2:e9a661555b58	3840	__IO uint8_t BDTPAGE2; /*< BDT Page Register 2, offset: 0xB0 /
emilmont	2:e9a661555b58	3841	uint8_t RESERVED_20[3];
emilmont	2:e9a661555b58	3842	__IO uint8_t BDTPAGE3; /*< BDT Page Register 3, offset: 0xB4 /
emilmont	2:e9a661555b58	3843	uint8_t RESERVED_21[11];
emilmont	2:e9a661555b58	3844	struct { /* offset: 0xC0, array step: 0x4 */
emilmont	2:e9a661555b58	3845	__IO uint8_t ENDPT; /*< Endpoint Control register, array offset: 0xC0, array step: 0x4 /
emilmont	2:e9a661555b58	3846	uint8_t RESERVED_0[3];
emilmont	2:e9a661555b58	3847	} ENDPOINT[16];
emilmont	2:e9a661555b58	3848	__IO uint8_t USBCTRL; /*< USB Control register, offset: 0x100 /
emilmont	2:e9a661555b58	3849	uint8_t RESERVED_22[3];
emilmont	2:e9a661555b58	3850	__I uint8_t OBSERVE; /*< USB OTG Observe register, offset: 0x104 /
emilmont	2:e9a661555b58	3851	uint8_t RESERVED_23[3];
emilmont	2:e9a661555b58	3852	__IO uint8_t CONTROL; /*< USB OTG Control register, offset: 0x108 /
emilmont	2:e9a661555b58	3853	uint8_t RESERVED_24[3];
emilmont	2:e9a661555b58	3854	__IO uint8_t USBTRC0; /*< USB Transceiver Control Register 0, offset: 0x10C /
emilmont	2:e9a661555b58	3855	} USB_Type;
emilmont	2:e9a661555b58	3856
emilmont	2:e9a661555b58	3857	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	3858	-- USB Register Masks
emilmont	2:e9a661555b58	3859	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	3860
emilmont	2:e9a661555b58	3861	/**
emilmont	2:e9a661555b58	3862	* @addtogroup USB_Register_Masks USB Register Masks
emilmont	2:e9a661555b58	3863	* @{
emilmont	2:e9a661555b58	3864	*/
emilmont	2:e9a661555b58	3865
emilmont	2:e9a661555b58	3866	/* PERID Bit Fields */
emilmont	2:e9a661555b58	3867	#define USB_PERID_ID_MASK 0x3Fu
emilmont	2:e9a661555b58	3868	#define USB_PERID_ID_SHIFT 0
emilmont	2:e9a661555b58	3869	#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
emilmont	2:e9a661555b58	3870	/* IDCOMP Bit Fields */
emilmont	2:e9a661555b58	3871	#define USB_IDCOMP_NID_MASK 0x3Fu
emilmont	2:e9a661555b58	3872	#define USB_IDCOMP_NID_SHIFT 0
emilmont	2:e9a661555b58	3873	#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
emilmont	2:e9a661555b58	3874	/* REV Bit Fields */
emilmont	2:e9a661555b58	3875	#define USB_REV_REV_MASK 0xFFu
emilmont	2:e9a661555b58	3876	#define USB_REV_REV_SHIFT 0
emilmont	2:e9a661555b58	3877	#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
emilmont	2:e9a661555b58	3878	/* ADDINFO Bit Fields */
emilmont	2:e9a661555b58	3879	#define USB_ADDINFO_IEHOST_MASK 0x1u
emilmont	2:e9a661555b58	3880	#define USB_ADDINFO_IEHOST_SHIFT 0
emilmont	2:e9a661555b58	3881	#define USB_ADDINFO_IRQNUM_MASK 0xF8u
emilmont	2:e9a661555b58	3882	#define USB_ADDINFO_IRQNUM_SHIFT 3
emilmont	2:e9a661555b58	3883	#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
emilmont	2:e9a661555b58	3884	/* OTGISTAT Bit Fields */
emilmont	2:e9a661555b58	3885	#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
emilmont	2:e9a661555b58	3886	#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
emilmont	2:e9a661555b58	3887	#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
emilmont	2:e9a661555b58	3888	#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
emilmont	2:e9a661555b58	3889	#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
emilmont	2:e9a661555b58	3890	#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
emilmont	2:e9a661555b58	3891	#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
emilmont	2:e9a661555b58	3892	#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
emilmont	2:e9a661555b58	3893	#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
emilmont	2:e9a661555b58	3894	#define USB_OTGISTAT_ONEMSEC_SHIFT 6
emilmont	2:e9a661555b58	3895	#define USB_OTGISTAT_IDCHG_MASK 0x80u
emilmont	2:e9a661555b58	3896	#define USB_OTGISTAT_IDCHG_SHIFT 7
emilmont	2:e9a661555b58	3897	/* OTGICR Bit Fields */
emilmont	2:e9a661555b58	3898	#define USB_OTGICR_AVBUSEN_MASK 0x1u
emilmont	2:e9a661555b58	3899	#define USB_OTGICR_AVBUSEN_SHIFT 0
emilmont	2:e9a661555b58	3900	#define USB_OTGICR_BSESSEN_MASK 0x4u
emilmont	2:e9a661555b58	3901	#define USB_OTGICR_BSESSEN_SHIFT 2
emilmont	2:e9a661555b58	3902	#define USB_OTGICR_SESSVLDEN_MASK 0x8u
emilmont	2:e9a661555b58	3903	#define USB_OTGICR_SESSVLDEN_SHIFT 3
emilmont	2:e9a661555b58	3904	#define USB_OTGICR_LINESTATEEN_MASK 0x20u
emilmont	2:e9a661555b58	3905	#define USB_OTGICR_LINESTATEEN_SHIFT 5
emilmont	2:e9a661555b58	3906	#define USB_OTGICR_ONEMSECEN_MASK 0x40u
emilmont	2:e9a661555b58	3907	#define USB_OTGICR_ONEMSECEN_SHIFT 6
emilmont	2:e9a661555b58	3908	#define USB_OTGICR_IDEN_MASK 0x80u
emilmont	2:e9a661555b58	3909	#define USB_OTGICR_IDEN_SHIFT 7
emilmont	2:e9a661555b58	3910	/* OTGSTAT Bit Fields */
emilmont	2:e9a661555b58	3911	#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
emilmont	2:e9a661555b58	3912	#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
emilmont	2:e9a661555b58	3913	#define USB_OTGSTAT_BSESSEND_MASK 0x4u
emilmont	2:e9a661555b58	3914	#define USB_OTGSTAT_BSESSEND_SHIFT 2
emilmont	2:e9a661555b58	3915	#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
emilmont	2:e9a661555b58	3916	#define USB_OTGSTAT_SESS_VLD_SHIFT 3
emilmont	2:e9a661555b58	3917	#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
emilmont	2:e9a661555b58	3918	#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
emilmont	2:e9a661555b58	3919	#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
emilmont	2:e9a661555b58	3920	#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
emilmont	2:e9a661555b58	3921	#define USB_OTGSTAT_ID_MASK 0x80u
emilmont	2:e9a661555b58	3922	#define USB_OTGSTAT_ID_SHIFT 7
emilmont	2:e9a661555b58	3923	/* OTGCTL Bit Fields */
emilmont	2:e9a661555b58	3924	#define USB_OTGCTL_OTGEN_MASK 0x4u
emilmont	2:e9a661555b58	3925	#define USB_OTGCTL_OTGEN_SHIFT 2
emilmont	2:e9a661555b58	3926	#define USB_OTGCTL_DMLOW_MASK 0x10u
emilmont	2:e9a661555b58	3927	#define USB_OTGCTL_DMLOW_SHIFT 4
emilmont	2:e9a661555b58	3928	#define USB_OTGCTL_DPLOW_MASK 0x20u
emilmont	2:e9a661555b58	3929	#define USB_OTGCTL_DPLOW_SHIFT 5
emilmont	2:e9a661555b58	3930	#define USB_OTGCTL_DPHIGH_MASK 0x80u
emilmont	2:e9a661555b58	3931	#define USB_OTGCTL_DPHIGH_SHIFT 7
emilmont	2:e9a661555b58	3932	/* ISTAT Bit Fields */
emilmont	2:e9a661555b58	3933	#define USB_ISTAT_USBRST_MASK 0x1u
emilmont	2:e9a661555b58	3934	#define USB_ISTAT_USBRST_SHIFT 0
emilmont	2:e9a661555b58	3935	#define USB_ISTAT_ERROR_MASK 0x2u
emilmont	2:e9a661555b58	3936	#define USB_ISTAT_ERROR_SHIFT 1
emilmont	2:e9a661555b58	3937	#define USB_ISTAT_SOFTOK_MASK 0x4u
emilmont	2:e9a661555b58	3938	#define USB_ISTAT_SOFTOK_SHIFT 2
emilmont	2:e9a661555b58	3939	#define USB_ISTAT_TOKDNE_MASK 0x8u
emilmont	2:e9a661555b58	3940	#define USB_ISTAT_TOKDNE_SHIFT 3
emilmont	2:e9a661555b58	3941	#define USB_ISTAT_SLEEP_MASK 0x10u
emilmont	2:e9a661555b58	3942	#define USB_ISTAT_SLEEP_SHIFT 4
emilmont	2:e9a661555b58	3943	#define USB_ISTAT_RESUME_MASK 0x20u
emilmont	2:e9a661555b58	3944	#define USB_ISTAT_RESUME_SHIFT 5
emilmont	2:e9a661555b58	3945	#define USB_ISTAT_ATTACH_MASK 0x40u
emilmont	2:e9a661555b58	3946	#define USB_ISTAT_ATTACH_SHIFT 6
emilmont	2:e9a661555b58	3947	#define USB_ISTAT_STALL_MASK 0x80u
emilmont	2:e9a661555b58	3948	#define USB_ISTAT_STALL_SHIFT 7
emilmont	2:e9a661555b58	3949	/* INTEN Bit Fields */
emilmont	2:e9a661555b58	3950	#define USB_INTEN_USBRSTEN_MASK 0x1u
emilmont	2:e9a661555b58	3951	#define USB_INTEN_USBRSTEN_SHIFT 0
emilmont	2:e9a661555b58	3952	#define USB_INTEN_ERROREN_MASK 0x2u
emilmont	2:e9a661555b58	3953	#define USB_INTEN_ERROREN_SHIFT 1
emilmont	2:e9a661555b58	3954	#define USB_INTEN_SOFTOKEN_MASK 0x4u
emilmont	2:e9a661555b58	3955	#define USB_INTEN_SOFTOKEN_SHIFT 2
emilmont	2:e9a661555b58	3956	#define USB_INTEN_TOKDNEEN_MASK 0x8u
emilmont	2:e9a661555b58	3957	#define USB_INTEN_TOKDNEEN_SHIFT 3
emilmont	2:e9a661555b58	3958	#define USB_INTEN_SLEEPEN_MASK 0x10u
emilmont	2:e9a661555b58	3959	#define USB_INTEN_SLEEPEN_SHIFT 4
emilmont	2:e9a661555b58	3960	#define USB_INTEN_RESUMEEN_MASK 0x20u
emilmont	2:e9a661555b58	3961	#define USB_INTEN_RESUMEEN_SHIFT 5
emilmont	2:e9a661555b58	3962	#define USB_INTEN_ATTACHEN_MASK 0x40u
emilmont	2:e9a661555b58	3963	#define USB_INTEN_ATTACHEN_SHIFT 6
emilmont	2:e9a661555b58	3964	#define USB_INTEN_STALLEN_MASK 0x80u
emilmont	2:e9a661555b58	3965	#define USB_INTEN_STALLEN_SHIFT 7
emilmont	2:e9a661555b58	3966	/* ERRSTAT Bit Fields */
emilmont	2:e9a661555b58	3967	#define USB_ERRSTAT_PIDERR_MASK 0x1u
emilmont	2:e9a661555b58	3968	#define USB_ERRSTAT_PIDERR_SHIFT 0
emilmont	2:e9a661555b58	3969	#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
emilmont	2:e9a661555b58	3970	#define USB_ERRSTAT_CRC5EOF_SHIFT 1
emilmont	2:e9a661555b58	3971	#define USB_ERRSTAT_CRC16_MASK 0x4u
emilmont	2:e9a661555b58	3972	#define USB_ERRSTAT_CRC16_SHIFT 2
emilmont	2:e9a661555b58	3973	#define USB_ERRSTAT_DFN8_MASK 0x8u
emilmont	2:e9a661555b58	3974	#define USB_ERRSTAT_DFN8_SHIFT 3
emilmont	2:e9a661555b58	3975	#define USB_ERRSTAT_BTOERR_MASK 0x10u
emilmont	2:e9a661555b58	3976	#define USB_ERRSTAT_BTOERR_SHIFT 4
emilmont	2:e9a661555b58	3977	#define USB_ERRSTAT_DMAERR_MASK 0x20u
emilmont	2:e9a661555b58	3978	#define USB_ERRSTAT_DMAERR_SHIFT 5
emilmont	2:e9a661555b58	3979	#define USB_ERRSTAT_BTSERR_MASK 0x80u
emilmont	2:e9a661555b58	3980	#define USB_ERRSTAT_BTSERR_SHIFT 7
emilmont	2:e9a661555b58	3981	/* ERREN Bit Fields */
emilmont	2:e9a661555b58	3982	#define USB_ERREN_PIDERREN_MASK 0x1u
emilmont	2:e9a661555b58	3983	#define USB_ERREN_PIDERREN_SHIFT 0
emilmont	2:e9a661555b58	3984	#define USB_ERREN_CRC5EOFEN_MASK 0x2u
emilmont	2:e9a661555b58	3985	#define USB_ERREN_CRC5EOFEN_SHIFT 1
emilmont	2:e9a661555b58	3986	#define USB_ERREN_CRC16EN_MASK 0x4u
emilmont	2:e9a661555b58	3987	#define USB_ERREN_CRC16EN_SHIFT 2
emilmont	2:e9a661555b58	3988	#define USB_ERREN_DFN8EN_MASK 0x8u
emilmont	2:e9a661555b58	3989	#define USB_ERREN_DFN8EN_SHIFT 3
emilmont	2:e9a661555b58	3990	#define USB_ERREN_BTOERREN_MASK 0x10u
emilmont	2:e9a661555b58	3991	#define USB_ERREN_BTOERREN_SHIFT 4
emilmont	2:e9a661555b58	3992	#define USB_ERREN_DMAERREN_MASK 0x20u
emilmont	2:e9a661555b58	3993	#define USB_ERREN_DMAERREN_SHIFT 5
emilmont	2:e9a661555b58	3994	#define USB_ERREN_BTSERREN_MASK 0x80u
emilmont	2:e9a661555b58	3995	#define USB_ERREN_BTSERREN_SHIFT 7
emilmont	2:e9a661555b58	3996	/* STAT Bit Fields */
emilmont	2:e9a661555b58	3997	#define USB_STAT_ODD_MASK 0x4u
emilmont	2:e9a661555b58	3998	#define USB_STAT_ODD_SHIFT 2
emilmont	2:e9a661555b58	3999	#define USB_STAT_TX_MASK 0x8u
emilmont	2:e9a661555b58	4000	#define USB_STAT_TX_SHIFT 3
emilmont	2:e9a661555b58	4001	#define USB_STAT_ENDP_MASK 0xF0u
emilmont	2:e9a661555b58	4002	#define USB_STAT_ENDP_SHIFT 4
emilmont	2:e9a661555b58	4003	#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
emilmont	2:e9a661555b58	4004	/* CTL Bit Fields */
emilmont	2:e9a661555b58	4005	#define USB_CTL_USBENSOFEN_MASK 0x1u
emilmont	2:e9a661555b58	4006	#define USB_CTL_USBENSOFEN_SHIFT 0
emilmont	2:e9a661555b58	4007	#define USB_CTL_ODDRST_MASK 0x2u
emilmont	2:e9a661555b58	4008	#define USB_CTL_ODDRST_SHIFT 1
emilmont	2:e9a661555b58	4009	#define USB_CTL_RESUME_MASK 0x4u
emilmont	2:e9a661555b58	4010	#define USB_CTL_RESUME_SHIFT 2
emilmont	2:e9a661555b58	4011	#define USB_CTL_HOSTMODEEN_MASK 0x8u
emilmont	2:e9a661555b58	4012	#define USB_CTL_HOSTMODEEN_SHIFT 3
emilmont	2:e9a661555b58	4013	#define USB_CTL_RESET_MASK 0x10u
emilmont	2:e9a661555b58	4014	#define USB_CTL_RESET_SHIFT 4
emilmont	2:e9a661555b58	4015	#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
emilmont	2:e9a661555b58	4016	#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
emilmont	2:e9a661555b58	4017	#define USB_CTL_SE0_MASK 0x40u
emilmont	2:e9a661555b58	4018	#define USB_CTL_SE0_SHIFT 6
emilmont	2:e9a661555b58	4019	#define USB_CTL_JSTATE_MASK 0x80u
emilmont	2:e9a661555b58	4020	#define USB_CTL_JSTATE_SHIFT 7
emilmont	2:e9a661555b58	4021	/* ADDR Bit Fields */
emilmont	2:e9a661555b58	4022	#define USB_ADDR_ADDR_MASK 0x7Fu
emilmont	2:e9a661555b58	4023	#define USB_ADDR_ADDR_SHIFT 0
emilmont	2:e9a661555b58	4024	#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
emilmont	2:e9a661555b58	4025	#define USB_ADDR_LSEN_MASK 0x80u
emilmont	2:e9a661555b58	4026	#define USB_ADDR_LSEN_SHIFT 7
emilmont	2:e9a661555b58	4027	/* BDTPAGE1 Bit Fields */
emilmont	2:e9a661555b58	4028	#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
emilmont	2:e9a661555b58	4029	#define USB_BDTPAGE1_BDTBA_SHIFT 1
emilmont	2:e9a661555b58	4030	#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
emilmont	2:e9a661555b58	4031	/* FRMNUML Bit Fields */
emilmont	2:e9a661555b58	4032	#define USB_FRMNUML_FRM_MASK 0xFFu
emilmont	2:e9a661555b58	4033	#define USB_FRMNUML_FRM_SHIFT 0
emilmont	2:e9a661555b58	4034	#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
emilmont	2:e9a661555b58	4035	/* FRMNUMH Bit Fields */
emilmont	2:e9a661555b58	4036	#define USB_FRMNUMH_FRM_MASK 0x7u
emilmont	2:e9a661555b58	4037	#define USB_FRMNUMH_FRM_SHIFT 0
emilmont	2:e9a661555b58	4038	#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
emilmont	2:e9a661555b58	4039	/* TOKEN Bit Fields */
emilmont	2:e9a661555b58	4040	#define USB_TOKEN_TOKENENDPT_MASK 0xFu
emilmont	2:e9a661555b58	4041	#define USB_TOKEN_TOKENENDPT_SHIFT 0
emilmont	2:e9a661555b58	4042	#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
emilmont	2:e9a661555b58	4043	#define USB_TOKEN_TOKENPID_MASK 0xF0u
emilmont	2:e9a661555b58	4044	#define USB_TOKEN_TOKENPID_SHIFT 4
emilmont	2:e9a661555b58	4045	#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
emilmont	2:e9a661555b58	4046	/* SOFTHLD Bit Fields */
emilmont	2:e9a661555b58	4047	#define USB_SOFTHLD_CNT_MASK 0xFFu
emilmont	2:e9a661555b58	4048	#define USB_SOFTHLD_CNT_SHIFT 0
emilmont	2:e9a661555b58	4049	#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
emilmont	2:e9a661555b58	4050	/* BDTPAGE2 Bit Fields */
emilmont	2:e9a661555b58	4051	#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
emilmont	2:e9a661555b58	4052	#define USB_BDTPAGE2_BDTBA_SHIFT 0
emilmont	2:e9a661555b58	4053	#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
emilmont	2:e9a661555b58	4054	/* BDTPAGE3 Bit Fields */
emilmont	2:e9a661555b58	4055	#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
emilmont	2:e9a661555b58	4056	#define USB_BDTPAGE3_BDTBA_SHIFT 0
emilmont	2:e9a661555b58	4057	#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
emilmont	2:e9a661555b58	4058	/* ENDPT Bit Fields */
emilmont	2:e9a661555b58	4059	#define USB_ENDPT_EPHSHK_MASK 0x1u
emilmont	2:e9a661555b58	4060	#define USB_ENDPT_EPHSHK_SHIFT 0
emilmont	2:e9a661555b58	4061	#define USB_ENDPT_EPSTALL_MASK 0x2u
emilmont	2:e9a661555b58	4062	#define USB_ENDPT_EPSTALL_SHIFT 1
emilmont	2:e9a661555b58	4063	#define USB_ENDPT_EPTXEN_MASK 0x4u
emilmont	2:e9a661555b58	4064	#define USB_ENDPT_EPTXEN_SHIFT 2
emilmont	2:e9a661555b58	4065	#define USB_ENDPT_EPRXEN_MASK 0x8u
emilmont	2:e9a661555b58	4066	#define USB_ENDPT_EPRXEN_SHIFT 3
emilmont	2:e9a661555b58	4067	#define USB_ENDPT_EPCTLDIS_MASK 0x10u
emilmont	2:e9a661555b58	4068	#define USB_ENDPT_EPCTLDIS_SHIFT 4
emilmont	2:e9a661555b58	4069	#define USB_ENDPT_RETRYDIS_MASK 0x40u
emilmont	2:e9a661555b58	4070	#define USB_ENDPT_RETRYDIS_SHIFT 6
emilmont	2:e9a661555b58	4071	#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
emilmont	2:e9a661555b58	4072	#define USB_ENDPT_HOSTWOHUB_SHIFT 7
emilmont	2:e9a661555b58	4073	/* USBCTRL Bit Fields */
emilmont	2:e9a661555b58	4074	#define USB_USBCTRL_PDE_MASK 0x40u
emilmont	2:e9a661555b58	4075	#define USB_USBCTRL_PDE_SHIFT 6
emilmont	2:e9a661555b58	4076	#define USB_USBCTRL_SUSP_MASK 0x80u
emilmont	2:e9a661555b58	4077	#define USB_USBCTRL_SUSP_SHIFT 7
emilmont	2:e9a661555b58	4078	/* OBSERVE Bit Fields */
emilmont	2:e9a661555b58	4079	#define USB_OBSERVE_DMPD_MASK 0x10u
emilmont	2:e9a661555b58	4080	#define USB_OBSERVE_DMPD_SHIFT 4
emilmont	2:e9a661555b58	4081	#define USB_OBSERVE_DPPD_MASK 0x40u
emilmont	2:e9a661555b58	4082	#define USB_OBSERVE_DPPD_SHIFT 6
emilmont	2:e9a661555b58	4083	#define USB_OBSERVE_DPPU_MASK 0x80u
emilmont	2:e9a661555b58	4084	#define USB_OBSERVE_DPPU_SHIFT 7
emilmont	2:e9a661555b58	4085	/* CONTROL Bit Fields */
emilmont	2:e9a661555b58	4086	#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
emilmont	2:e9a661555b58	4087	#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
emilmont	2:e9a661555b58	4088	/* USBTRC0 Bit Fields */
emilmont	2:e9a661555b58	4089	#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
emilmont	2:e9a661555b58	4090	#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
emilmont	2:e9a661555b58	4091	#define USB_USBTRC0_SYNC_DET_MASK 0x2u
emilmont	2:e9a661555b58	4092	#define USB_USBTRC0_SYNC_DET_SHIFT 1
emilmont	2:e9a661555b58	4093	#define USB_USBTRC0_USBRESMEN_MASK 0x20u
emilmont	2:e9a661555b58	4094	#define USB_USBTRC0_USBRESMEN_SHIFT 5
emilmont	2:e9a661555b58	4095	#define USB_USBTRC0_USBRESET_MASK 0x80u
emilmont	2:e9a661555b58	4096	#define USB_USBTRC0_USBRESET_SHIFT 7
emilmont	2:e9a661555b58	4097
emilmont	2:e9a661555b58	4098	/**
emilmont	2:e9a661555b58	4099	* @}
emilmont	2:e9a661555b58	4100	/ / end of group USB_Register_Masks */
emilmont	2:e9a661555b58	4101
emilmont	2:e9a661555b58	4102
emilmont	2:e9a661555b58	4103	/* USB - Peripheral instance base addresses */
emilmont	2:e9a661555b58	4104	/** Peripheral USB0 base address */
emilmont	2:e9a661555b58	4105	#define USB0_BASE (0x40072000u)
emilmont	2:e9a661555b58	4106	/** Peripheral USB0 base pointer */
emilmont	2:e9a661555b58	4107	#define USB0 ((USB_Type *)USB0_BASE)
emilmont	2:e9a661555b58	4108	/** Array initializer of USB peripheral base pointers */
emilmont	2:e9a661555b58	4109	#define USB_BASES { USB0 }
emilmont	2:e9a661555b58	4110
emilmont	2:e9a661555b58	4111	/**
emilmont	2:e9a661555b58	4112	* @}
emilmont	2:e9a661555b58	4113	/ / end of group USB_Peripheral_Access_Layer */
emilmont	2:e9a661555b58	4114
emilmont	2:e9a661555b58	4115
emilmont	2:e9a661555b58	4116	/*
emilmont	2:e9a661555b58	4117	** End of section using anonymous unions
emilmont	2:e9a661555b58	4118	*/
emilmont	2:e9a661555b58	4119
emilmont	2:e9a661555b58	4120	#if defined(__ARMCC_VERSION)
emilmont	2:e9a661555b58	4121	#pragma pop
emilmont	2:e9a661555b58	4122	#elif defined(__CWCC__)
emilmont	2:e9a661555b58	4123	#pragma pop
emilmont	2:e9a661555b58	4124	#elif defined(__GNUC__)
emilmont	2:e9a661555b58	4125	/* leave anonymous unions enabled */
emilmont	2:e9a661555b58	4126	#elif defined(__IAR_SYSTEMS_ICC__)
emilmont	2:e9a661555b58	4127	#pragma language=default
emilmont	2:e9a661555b58	4128	#else
emilmont	2:e9a661555b58	4129	#error Not supported compiler type
emilmont	2:e9a661555b58	4130	#endif
emilmont	2:e9a661555b58	4131
emilmont	2:e9a661555b58	4132	/**
emilmont	2:e9a661555b58	4133	* @}
emilmont	2:e9a661555b58	4134	/ / end of group Peripheral_access_layer */
emilmont	2:e9a661555b58	4135
emilmont	2:e9a661555b58	4136
emilmont	2:e9a661555b58	4137	/* ----------------------------------------------------------------------------
emilmont	2:e9a661555b58	4138	-- Backward Compatibility
emilmont	2:e9a661555b58	4139	---------------------------------------------------------------------------- */
emilmont	2:e9a661555b58	4140
emilmont	2:e9a661555b58	4141	/**
emilmont	2:e9a661555b58	4142	* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
emilmont	2:e9a661555b58	4143	* @{
emilmont	2:e9a661555b58	4144	*/
emilmont	2:e9a661555b58	4145
emilmont	2:e9a661555b58	4146	/* No backward compatibility issues. */
emilmont	2:e9a661555b58	4147
emilmont	2:e9a661555b58	4148	/**
emilmont	2:e9a661555b58	4149	* @}
emilmont	2:e9a661555b58	4150	/ / end of group Backward_Compatibility_Symbols */
emilmont	2:e9a661555b58	4151
emilmont	2:e9a661555b58	4152
emilmont	2:e9a661555b58	4153	#endif /* #if !defined(MKL25Z4_H_) */
emilmont	2:e9a661555b58	4154
emilmont	2:e9a661555b58	4155	/* MKL25Z4.h, eof. */