Eli Hughes / CMSIS_DSP_401

V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.

Dependents:   MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more

BasicMathFunctions/arm_dot_prod_q7.c@0:3d9c67d97d6f, 2014-07-28 (annotated)

Committer:
emh203
Date:
Mon Jul 28 15:03:15 2014 +0000
Revision:
0:3d9c67d97d6f
1st working commit.   Had to remove arm_bitreversal2.s     arm_cfft_f32.c and arm_rfft_fast_f32.c.    The .s will not assemble.      For now I removed these functions so we could at least have a library for the other functions.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emh203 0:3d9c67d97d6f 1 /* ----------------------------------------------------------------------
emh203 0:3d9c67d97d6f 2 * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
emh203 0:3d9c67d97d6f 3 *
emh203 0:3d9c67d97d6f 4 * $Date: 12. March 2014
emh203 0:3d9c67d97d6f 5 * $Revision: V1.4.3
emh203 0:3d9c67d97d6f 6 *
emh203 0:3d9c67d97d6f 7 * Project: CMSIS DSP Library
emh203 0:3d9c67d97d6f 8 * Title: arm_dot_prod_q7.c
emh203 0:3d9c67d97d6f 9 *
emh203 0:3d9c67d97d6f 10 * Description: Q7 dot product.
emh203 0:3d9c67d97d6f 11 *
emh203 0:3d9c67d97d6f 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emh203 0:3d9c67d97d6f 13 *
emh203 0:3d9c67d97d6f 14 * Redistribution and use in source and binary forms, with or without
emh203 0:3d9c67d97d6f 15 * modification, are permitted provided that the following conditions
emh203 0:3d9c67d97d6f 16 * are met:
emh203 0:3d9c67d97d6f 17 * - Redistributions of source code must retain the above copyright
emh203 0:3d9c67d97d6f 18 * notice, this list of conditions and the following disclaimer.
emh203 0:3d9c67d97d6f 19 * - Redistributions in binary form must reproduce the above copyright
emh203 0:3d9c67d97d6f 20 * notice, this list of conditions and the following disclaimer in
emh203 0:3d9c67d97d6f 21 * the documentation and/or other materials provided with the
emh203 0:3d9c67d97d6f 22 * distribution.
emh203 0:3d9c67d97d6f 23 * - Neither the name of ARM LIMITED nor the names of its contributors
emh203 0:3d9c67d97d6f 24 * may be used to endorse or promote products derived from this
emh203 0:3d9c67d97d6f 25 * software without specific prior written permission.
emh203 0:3d9c67d97d6f 26 *
emh203 0:3d9c67d97d6f 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
emh203 0:3d9c67d97d6f 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
emh203 0:3d9c67d97d6f 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
emh203 0:3d9c67d97d6f 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
emh203 0:3d9c67d97d6f 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
emh203 0:3d9c67d97d6f 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
emh203 0:3d9c67d97d6f 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
emh203 0:3d9c67d97d6f 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emh203 0:3d9c67d97d6f 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
emh203 0:3d9c67d97d6f 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
emh203 0:3d9c67d97d6f 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emh203 0:3d9c67d97d6f 38 * POSSIBILITY OF SUCH DAMAGE.
emh203 0:3d9c67d97d6f 39 * -------------------------------------------------------------------- */
emh203 0:3d9c67d97d6f 40
emh203 0:3d9c67d97d6f 41 #include "arm_math.h"
emh203 0:3d9c67d97d6f 42
emh203 0:3d9c67d97d6f 43 /**
emh203 0:3d9c67d97d6f 44 * @ingroup groupMath
emh203 0:3d9c67d97d6f 45 */
emh203 0:3d9c67d97d6f 46
emh203 0:3d9c67d97d6f 47 /**
emh203 0:3d9c67d97d6f 48 * @addtogroup dot_prod
emh203 0:3d9c67d97d6f 49 * @{
emh203 0:3d9c67d97d6f 50 */
emh203 0:3d9c67d97d6f 51
emh203 0:3d9c67d97d6f 52 /**
emh203 0:3d9c67d97d6f 53 * @brief Dot product of Q7 vectors.
emh203 0:3d9c67d97d6f 54 * @param[in] *pSrcA points to the first input vector
emh203 0:3d9c67d97d6f 55 * @param[in] *pSrcB points to the second input vector
emh203 0:3d9c67d97d6f 56 * @param[in] blockSize number of samples in each vector
emh203 0:3d9c67d97d6f 57 * @param[out] *result output result returned here
emh203 0:3d9c67d97d6f 58 * @return none.
emh203 0:3d9c67d97d6f 59 *
emh203 0:3d9c67d97d6f 60 * <b>Scaling and Overflow Behavior:</b>
emh203 0:3d9c67d97d6f 61 * \par
emh203 0:3d9c67d97d6f 62 * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these
emh203 0:3d9c67d97d6f 63 * results are added to an accumulator in 18.14 format.
emh203 0:3d9c67d97d6f 64 * Nonsaturating additions are used and there is no danger of wrap around as long as
emh203 0:3d9c67d97d6f 65 * the vectors are less than 2^18 elements long.
emh203 0:3d9c67d97d6f 66 * The return result is in 18.14 format.
emh203 0:3d9c67d97d6f 67 */
emh203 0:3d9c67d97d6f 68
emh203 0:3d9c67d97d6f 69 void arm_dot_prod_q7(
emh203 0:3d9c67d97d6f 70 q7_t * pSrcA,
emh203 0:3d9c67d97d6f 71 q7_t * pSrcB,
emh203 0:3d9c67d97d6f 72 uint32_t blockSize,
emh203 0:3d9c67d97d6f 73 q31_t * result)
emh203 0:3d9c67d97d6f 74 {
emh203 0:3d9c67d97d6f 75 uint32_t blkCnt; /* loop counter */
emh203 0:3d9c67d97d6f 76
emh203 0:3d9c67d97d6f 77 q31_t sum = 0; /* Temporary variables to store output */
emh203 0:3d9c67d97d6f 78
emh203 0:3d9c67d97d6f 79 #ifndef ARM_MATH_CM0_FAMILY
emh203 0:3d9c67d97d6f 80
emh203 0:3d9c67d97d6f 81 /* Run the below code for Cortex-M4 and Cortex-M3 */
emh203 0:3d9c67d97d6f 82
emh203 0:3d9c67d97d6f 83 q31_t input1, input2; /* Temporary variables to store input */
emh203 0:3d9c67d97d6f 84 q31_t inA1, inA2, inB1, inB2; /* Temporary variables to store input */
emh203 0:3d9c67d97d6f 85
emh203 0:3d9c67d97d6f 86
emh203 0:3d9c67d97d6f 87
emh203 0:3d9c67d97d6f 88 /*loop Unrolling */
emh203 0:3d9c67d97d6f 89 blkCnt = blockSize >> 2u;
emh203 0:3d9c67d97d6f 90
emh203 0:3d9c67d97d6f 91 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emh203 0:3d9c67d97d6f 92 ** a second loop below computes the remaining 1 to 3 samples. */
emh203 0:3d9c67d97d6f 93 while(blkCnt > 0u)
emh203 0:3d9c67d97d6f 94 {
emh203 0:3d9c67d97d6f 95 /* read 4 samples at a time from sourceA */
emh203 0:3d9c67d97d6f 96 input1 = *__SIMD32(pSrcA)++;
emh203 0:3d9c67d97d6f 97 /* read 4 samples at a time from sourceB */
emh203 0:3d9c67d97d6f 98 input2 = *__SIMD32(pSrcB)++;
emh203 0:3d9c67d97d6f 99
emh203 0:3d9c67d97d6f 100 /* extract two q7_t samples to q15_t samples */
emh203 0:3d9c67d97d6f 101 inA1 = __SXTB16(__ROR(input1, 8));
emh203 0:3d9c67d97d6f 102 /* extract reminaing two samples */
emh203 0:3d9c67d97d6f 103 inA2 = __SXTB16(input1);
emh203 0:3d9c67d97d6f 104 /* extract two q7_t samples to q15_t samples */
emh203 0:3d9c67d97d6f 105 inB1 = __SXTB16(__ROR(input2, 8));
emh203 0:3d9c67d97d6f 106 /* extract reminaing two samples */
emh203 0:3d9c67d97d6f 107 inB2 = __SXTB16(input2);
emh203 0:3d9c67d97d6f 108
emh203 0:3d9c67d97d6f 109 /* multiply and accumulate two samples at a time */
emh203 0:3d9c67d97d6f 110 sum = __SMLAD(inA1, inB1, sum);
emh203 0:3d9c67d97d6f 111 sum = __SMLAD(inA2, inB2, sum);
emh203 0:3d9c67d97d6f 112
emh203 0:3d9c67d97d6f 113 /* Decrement the loop counter */
emh203 0:3d9c67d97d6f 114 blkCnt--;
emh203 0:3d9c67d97d6f 115 }
emh203 0:3d9c67d97d6f 116
emh203 0:3d9c67d97d6f 117 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emh203 0:3d9c67d97d6f 118 ** No loop unrolling is used. */
emh203 0:3d9c67d97d6f 119 blkCnt = blockSize % 0x4u;
emh203 0:3d9c67d97d6f 120
emh203 0:3d9c67d97d6f 121 while(blkCnt > 0u)
emh203 0:3d9c67d97d6f 122 {
emh203 0:3d9c67d97d6f 123 /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
emh203 0:3d9c67d97d6f 124 /* Dot product and then store the results in a temporary buffer. */
emh203 0:3d9c67d97d6f 125 sum = __SMLAD(*pSrcA++, *pSrcB++, sum);
emh203 0:3d9c67d97d6f 126
emh203 0:3d9c67d97d6f 127 /* Decrement the loop counter */
emh203 0:3d9c67d97d6f 128 blkCnt--;
emh203 0:3d9c67d97d6f 129 }
emh203 0:3d9c67d97d6f 130
emh203 0:3d9c67d97d6f 131 #else
emh203 0:3d9c67d97d6f 132
emh203 0:3d9c67d97d6f 133 /* Run the below code for Cortex-M0 */
emh203 0:3d9c67d97d6f 134
emh203 0:3d9c67d97d6f 135
emh203 0:3d9c67d97d6f 136
emh203 0:3d9c67d97d6f 137 /* Initialize blkCnt with number of samples */
emh203 0:3d9c67d97d6f 138 blkCnt = blockSize;
emh203 0:3d9c67d97d6f 139
emh203 0:3d9c67d97d6f 140 while(blkCnt > 0u)
emh203 0:3d9c67d97d6f 141 {
emh203 0:3d9c67d97d6f 142 /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */
emh203 0:3d9c67d97d6f 143 /* Dot product and then store the results in a temporary buffer. */
emh203 0:3d9c67d97d6f 144 sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++);
emh203 0:3d9c67d97d6f 145
emh203 0:3d9c67d97d6f 146 /* Decrement the loop counter */
emh203 0:3d9c67d97d6f 147 blkCnt--;
emh203 0:3d9c67d97d6f 148 }
emh203 0:3d9c67d97d6f 149
emh203 0:3d9c67d97d6f 150 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emh203 0:3d9c67d97d6f 151
emh203 0:3d9c67d97d6f 152
emh203 0:3d9c67d97d6f 153 /* Store the result in the destination buffer in 18.14 format */
emh203 0:3d9c67d97d6f 154 *result = sum;
emh203 0:3d9c67d97d6f 155 }
emh203 0:3d9c67d97d6f 156
emh203 0:3d9c67d97d6f 157 /**
emh203 0:3d9c67d97d6f 158 * @} end of dot_prod group
emh203 0:3d9c67d97d6f 159 */