LPC4088 QuickStart Board - How to Expand - SPI

Overview

There are three SPI interfaces on the LPC4088 QuickStart Board. The SPI interface is perfect for expanding to peripherals that need fast updates/sampling. SPI busses do not need to be point-to-point connections. There are ways to expand so that multiple peripherals can be connected to the same SPI bus, see example schematics.

  1. SPI0 is available on p5, p6, p7.
  2. SPI1 is available on p11, p12, p13.
  3. SPI2 is available on p32, p38, p39.

The advantages of the SPI bus are:

  • Synchronous high speed communication, several MHz clock rate.
  • Full duplex communication (simultaneous communication in both directions).
  • Serial bus with relatively few pins required (3 for one-way communication and 4 for duplex communication).
  • Signal naming/specification minimize risk for connecting master and slave data signals wrong.

The disadvantages are:

  • Limited bus length (typically less than 20 cm, the higher bit rate the shorter communication distance)
  • Very simple, shift register like, protocol. No error handling exist.
  • One chip select (SSEL) is needed per connected device. Can be many signals to control if there are many SPI slaves.
  • One master and one, or more, slaves per SPI bus. Multiple masters are not supported.

For more information about SPI, see http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus

The three SPI busses can be used simultaneously. One SPI bus can be shared by different parts of the application program, for example when running several processes/tasks in an RTOS (Real-Time Operating System). Some kind of mutual-exclusive protection or driver abstraction must then be created so that the use of the bus is serialized in time, i.e., two or more users do not try to use the bus simultaneously.
On the other hand, using several separate SPI busses can make the program control simpler. Separate parts of the program can control separate SPI busses.

Example Schematic

One page covers example SPI expansion in the example interface design schematic. General shift registers, an accelerimeter and an e2prom (25LC040) are used as examples. For the shift registers, both a cascaded and parallel designs are presented.

Note:

  • The SPI0 interface is also available on the display expansion connector. Do not use this interface on p5-p7 is used on the display expansion connector.
  • For cascaded solutions (connecting several SPI slaves in series) the SSEL signal must be low for the complete transmission of all bits in the chain.
  • When connecting several slaves to one SPI bus (parallel connection, as demonstrated in the example schematics) make sure the MISO signal is only driven by active slaves (SSEL low). The other slaves must have high.-impedance MISO pins when respective SSEL input is high.
  • It is possible to save GPO pins when multiple SSEL pins must be controlled. Use a 74LVC138 demultiplexor as demonstrated in the example schematics.

Example Code


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