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Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents: 1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

TARGET_NUCLEO_F401RE/stm32_hal_legacy.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:: Kojto
Date:: Wed May 13 08:08:21 2015 +0200
Revision:: 99:dbbf35b96557
Child:: 106:ba1f97679dad

Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	99:dbbf35b96557	1	/**
Kojto	99:dbbf35b96557	2	******************************************************************************
Kojto	99:dbbf35b96557	3	* @file stm32_hal_legacy.h
Kojto	99:dbbf35b96557	4	* @author MCD Application Team
Kojto	99:dbbf35b96557	5	* @version V1.3.0
Kojto	99:dbbf35b96557	6	* @date 09-March-2015
Kojto	99:dbbf35b96557	7	* @brief This file contains aliases definition for the STM32Cube HAL constants
Kojto	99:dbbf35b96557	8	* macros and functions maintained for legacy purpose.
Kojto	99:dbbf35b96557	9	******************************************************************************
Kojto	99:dbbf35b96557	10	* @attention
Kojto	99:dbbf35b96557	11	*
Kojto	99:dbbf35b96557	12	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	99:dbbf35b96557	13	*
Kojto	99:dbbf35b96557	14	* Redistribution and use in source and binary forms, with or without modification,
Kojto	99:dbbf35b96557	15	* are permitted provided that the following conditions are met:
Kojto	99:dbbf35b96557	16	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	99:dbbf35b96557	17	* this list of conditions and the following disclaimer.
Kojto	99:dbbf35b96557	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	99:dbbf35b96557	19	* this list of conditions and the following disclaimer in the documentation
Kojto	99:dbbf35b96557	20	* and/or other materials provided with the distribution.
Kojto	99:dbbf35b96557	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	99:dbbf35b96557	22	* may be used to endorse or promote products derived from this software
Kojto	99:dbbf35b96557	23	* without specific prior written permission.
Kojto	99:dbbf35b96557	24	*
Kojto	99:dbbf35b96557	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	99:dbbf35b96557	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	99:dbbf35b96557	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	99:dbbf35b96557	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	99:dbbf35b96557	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	99:dbbf35b96557	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	99:dbbf35b96557	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	99:dbbf35b96557	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	99:dbbf35b96557	33	UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	99:dbbf35b96557	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	99:dbbf35b96557	35	*
Kojto	99:dbbf35b96557	36	******************************************************************************
Kojto	99:dbbf35b96557	37	*/
Kojto	99:dbbf35b96557	38
Kojto	99:dbbf35b96557	39	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	99:dbbf35b96557	40	#ifndef __STM32_HAL_LEGACY
Kojto	99:dbbf35b96557	41	#define __STM32_HAL_LEGACY
Kojto	99:dbbf35b96557	42
Kojto	99:dbbf35b96557	43	#ifdef __cplusplus
Kojto	99:dbbf35b96557	44	extern "C" {
Kojto	99:dbbf35b96557	45	#endif
Kojto	99:dbbf35b96557	46
Kojto	99:dbbf35b96557	47	/* Includes ------------------------------------------------------------------*/
Kojto	99:dbbf35b96557	48	/* Exported types ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	49	/* Exported constants --------------------------------------------------------*/
Kojto	99:dbbf35b96557	50
Kojto	99:dbbf35b96557	51	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	52	* @{
Kojto	99:dbbf35b96557	53	*/
Kojto	99:dbbf35b96557	54	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
Kojto	99:dbbf35b96557	55	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
Kojto	99:dbbf35b96557	56	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
Kojto	99:dbbf35b96557	57	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
Kojto	99:dbbf35b96557	58	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
Kojto	99:dbbf35b96557	59
Kojto	99:dbbf35b96557	60	/**
Kojto	99:dbbf35b96557	61	* @}
Kojto	99:dbbf35b96557	62	*/
Kojto	99:dbbf35b96557	63
Kojto	99:dbbf35b96557	64	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	65	* @{
Kojto	99:dbbf35b96557	66	*/
Kojto	99:dbbf35b96557	67	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
Kojto	99:dbbf35b96557	68	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
Kojto	99:dbbf35b96557	69	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
Kojto	99:dbbf35b96557	70	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
Kojto	99:dbbf35b96557	71	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
Kojto	99:dbbf35b96557	72	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
Kojto	99:dbbf35b96557	73	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
Kojto	99:dbbf35b96557	74	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
Kojto	99:dbbf35b96557	75	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
Kojto	99:dbbf35b96557	76	#define REGULAR_GROUP ADC_REGULAR_GROUP
Kojto	99:dbbf35b96557	77	#define INJECTED_GROUP ADC_INJECTED_GROUP
Kojto	99:dbbf35b96557	78	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
Kojto	99:dbbf35b96557	79	#define AWD_EVENT ADC_AWD_EVENT
Kojto	99:dbbf35b96557	80	#define AWD1_EVENT ADC_AWD1_EVENT
Kojto	99:dbbf35b96557	81	#define AWD2_EVENT ADC_AWD2_EVENT
Kojto	99:dbbf35b96557	82	#define AWD3_EVENT ADC_AWD3_EVENT
Kojto	99:dbbf35b96557	83	#define OVR_EVENT ADC_OVR_EVENT
Kojto	99:dbbf35b96557	84	#define JQOVF_EVENT ADC_JQOVF_EVENT
Kojto	99:dbbf35b96557	85	#define ALL_CHANNELS ADC_ALL_CHANNELS
Kojto	99:dbbf35b96557	86	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
Kojto	99:dbbf35b96557	87	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
Kojto	99:dbbf35b96557	88	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
Kojto	99:dbbf35b96557	89	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
Kojto	99:dbbf35b96557	90	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
Kojto	99:dbbf35b96557	91	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
Kojto	99:dbbf35b96557	92	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
Kojto	99:dbbf35b96557	93	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
Kojto	99:dbbf35b96557	94	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
Kojto	99:dbbf35b96557	95	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
Kojto	99:dbbf35b96557	96	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
Kojto	99:dbbf35b96557	97	#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
Kojto	99:dbbf35b96557	98	#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
Kojto	99:dbbf35b96557	99	#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
Kojto	99:dbbf35b96557	100	#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
Kojto	99:dbbf35b96557	101	/**
Kojto	99:dbbf35b96557	102	* @}
Kojto	99:dbbf35b96557	103	*/
Kojto	99:dbbf35b96557	104
Kojto	99:dbbf35b96557	105	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	106	* @{
Kojto	99:dbbf35b96557	107	*/
Kojto	99:dbbf35b96557	108
Kojto	99:dbbf35b96557	109	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
Kojto	99:dbbf35b96557	110
Kojto	99:dbbf35b96557	111	/**
Kojto	99:dbbf35b96557	112	* @}
Kojto	99:dbbf35b96557	113	*/
Kojto	99:dbbf35b96557	114
Kojto	99:dbbf35b96557	115	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	116	* @{
Kojto	99:dbbf35b96557	117	*/
Kojto	99:dbbf35b96557	118
Kojto	99:dbbf35b96557	119	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
Kojto	99:dbbf35b96557	120	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
Kojto	99:dbbf35b96557	121	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
Kojto	99:dbbf35b96557	122	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
Kojto	99:dbbf35b96557	123
Kojto	99:dbbf35b96557	124	/**
Kojto	99:dbbf35b96557	125	* @}
Kojto	99:dbbf35b96557	126	*/
Kojto	99:dbbf35b96557	127
Kojto	99:dbbf35b96557	128	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	129	* @{
Kojto	99:dbbf35b96557	130	*/
Kojto	99:dbbf35b96557	131
Kojto	99:dbbf35b96557	132	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
Kojto	99:dbbf35b96557	133	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
Kojto	99:dbbf35b96557	134
Kojto	99:dbbf35b96557	135	/**
Kojto	99:dbbf35b96557	136	* @}
Kojto	99:dbbf35b96557	137	*/
Kojto	99:dbbf35b96557	138
Kojto	99:dbbf35b96557	139	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	140	* @{
Kojto	99:dbbf35b96557	141	*/
Kojto	99:dbbf35b96557	142
Kojto	99:dbbf35b96557	143	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
Kojto	99:dbbf35b96557	144	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
Kojto	99:dbbf35b96557	145	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
Kojto	99:dbbf35b96557	146	#define DAC_WAVE_NONE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	147	#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
Kojto	99:dbbf35b96557	148	#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
Kojto	99:dbbf35b96557	149	#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
Kojto	99:dbbf35b96557	150	#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
Kojto	99:dbbf35b96557	151	#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
Kojto	99:dbbf35b96557	152
Kojto	99:dbbf35b96557	153	/**
Kojto	99:dbbf35b96557	154	* @}
Kojto	99:dbbf35b96557	155	*/
Kojto	99:dbbf35b96557	156
Kojto	99:dbbf35b96557	157
Kojto	99:dbbf35b96557	158	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	159	* @{
Kojto	99:dbbf35b96557	160	*/
Kojto	99:dbbf35b96557	161
Kojto	99:dbbf35b96557	162	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
Kojto	99:dbbf35b96557	163	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto	99:dbbf35b96557	164	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
Kojto	99:dbbf35b96557	165	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
Kojto	99:dbbf35b96557	166	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
Kojto	99:dbbf35b96557	167	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
Kojto	99:dbbf35b96557	168	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
Kojto	99:dbbf35b96557	169	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
Kojto	99:dbbf35b96557	170	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
Kojto	99:dbbf35b96557	171	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
Kojto	99:dbbf35b96557	172	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
Kojto	99:dbbf35b96557	173	#define OBEX_PCROP OPTIONBYTE_PCROP
Kojto	99:dbbf35b96557	174	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
Kojto	99:dbbf35b96557	175	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
Kojto	99:dbbf35b96557	176	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
Kojto	99:dbbf35b96557	177	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
Kojto	99:dbbf35b96557	178	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
Kojto	99:dbbf35b96557	179	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
Kojto	99:dbbf35b96557	180	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
Kojto	99:dbbf35b96557	181	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
Kojto	99:dbbf35b96557	182	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
Kojto	99:dbbf35b96557	183	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
Kojto	99:dbbf35b96557	184	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
Kojto	99:dbbf35b96557	185	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
Kojto	99:dbbf35b96557	186	#define PAGESIZE FLASH_PAGE_SIZE
Kojto	99:dbbf35b96557	187	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
Kojto	99:dbbf35b96557	188	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto	99:dbbf35b96557	189	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
Kojto	99:dbbf35b96557	190	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
Kojto	99:dbbf35b96557	191	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
Kojto	99:dbbf35b96557	192	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
Kojto	99:dbbf35b96557	193	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
Kojto	99:dbbf35b96557	194	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
Kojto	99:dbbf35b96557	195	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
Kojto	99:dbbf35b96557	196	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
Kojto	99:dbbf35b96557	197	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
Kojto	99:dbbf35b96557	198	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
Kojto	99:dbbf35b96557	199	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
Kojto	99:dbbf35b96557	200	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
Kojto	99:dbbf35b96557	201	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
Kojto	99:dbbf35b96557	202	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
Kojto	99:dbbf35b96557	203	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
Kojto	99:dbbf35b96557	204	#define IS_NBSECTORS IS_FLASH_NBSECTORS
Kojto	99:dbbf35b96557	205	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
Kojto	99:dbbf35b96557	206	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
Kojto	99:dbbf35b96557	207	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
Kojto	99:dbbf35b96557	208	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
Kojto	99:dbbf35b96557	209	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
Kojto	99:dbbf35b96557	210	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
Kojto	99:dbbf35b96557	211	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
Kojto	99:dbbf35b96557	212	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
Kojto	99:dbbf35b96557	213	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
Kojto	99:dbbf35b96557	214	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
Kojto	99:dbbf35b96557	215	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
Kojto	99:dbbf35b96557	216	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
Kojto	99:dbbf35b96557	217	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
Kojto	99:dbbf35b96557	218	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
Kojto	99:dbbf35b96557	219	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
Kojto	99:dbbf35b96557	220	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
Kojto	99:dbbf35b96557	221	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
Kojto	99:dbbf35b96557	222	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
Kojto	99:dbbf35b96557	223	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
Kojto	99:dbbf35b96557	224
Kojto	99:dbbf35b96557	225	/**
Kojto	99:dbbf35b96557	226	* @}
Kojto	99:dbbf35b96557	227	*/
Kojto	99:dbbf35b96557	228
Kojto	99:dbbf35b96557	229	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	230	* @{
Kojto	99:dbbf35b96557	231	*/
Kojto	99:dbbf35b96557	232
Kojto	99:dbbf35b96557	233	#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
Kojto	99:dbbf35b96557	234	#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
Kojto	99:dbbf35b96557	235	#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
Kojto	99:dbbf35b96557	236	#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
Kojto	99:dbbf35b96557	237	#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
Kojto	99:dbbf35b96557	238	#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
Kojto	99:dbbf35b96557	239	#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
Kojto	99:dbbf35b96557	240
Kojto	99:dbbf35b96557	241	/**
Kojto	99:dbbf35b96557	242	* @}
Kojto	99:dbbf35b96557	243	*/
Kojto	99:dbbf35b96557	244
Kojto	99:dbbf35b96557	245
Kojto	99:dbbf35b96557	246	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	247	* @{
Kojto	99:dbbf35b96557	248	*/
Kojto	99:dbbf35b96557	249
Kojto	99:dbbf35b96557	250	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
Kojto	99:dbbf35b96557	251	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
Kojto	99:dbbf35b96557	252	/**
Kojto	99:dbbf35b96557	253	* @}
Kojto	99:dbbf35b96557	254	*/
Kojto	99:dbbf35b96557	255
Kojto	99:dbbf35b96557	256	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	257	* @{
Kojto	99:dbbf35b96557	258	*/
Kojto	99:dbbf35b96557	259	#define GET_GPIO_SOURCE GPIO_GET_INDEX
Kojto	99:dbbf35b96557	260	#define GET_GPIO_INDEX GPIO_GET_INDEX
Kojto	99:dbbf35b96557	261	/**
Kojto	99:dbbf35b96557	262	* @}
Kojto	99:dbbf35b96557	263	*/
Kojto	99:dbbf35b96557	264
Kojto	99:dbbf35b96557	265
Kojto	99:dbbf35b96557	266	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	267	* @{
Kojto	99:dbbf35b96557	268	*/
Kojto	99:dbbf35b96557	269	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
Kojto	99:dbbf35b96557	270	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
Kojto	99:dbbf35b96557	271	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
Kojto	99:dbbf35b96557	272	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
Kojto	99:dbbf35b96557	273	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
Kojto	99:dbbf35b96557	274	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
Kojto	99:dbbf35b96557	275	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
Kojto	99:dbbf35b96557	276	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
Kojto	99:dbbf35b96557	277	/**
Kojto	99:dbbf35b96557	278	* @}
Kojto	99:dbbf35b96557	279	*/
Kojto	99:dbbf35b96557	280
Kojto	99:dbbf35b96557	281	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	282	* @{
Kojto	99:dbbf35b96557	283	*/
Kojto	99:dbbf35b96557	284	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
Kojto	99:dbbf35b96557	285	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
Kojto	99:dbbf35b96557	286
Kojto	99:dbbf35b96557	287	/**
Kojto	99:dbbf35b96557	288	* @}
Kojto	99:dbbf35b96557	289	*/
Kojto	99:dbbf35b96557	290
Kojto	99:dbbf35b96557	291	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	292	* @{
Kojto	99:dbbf35b96557	293	*/
Kojto	99:dbbf35b96557	294	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
Kojto	99:dbbf35b96557	295	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
Kojto	99:dbbf35b96557	296	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
Kojto	99:dbbf35b96557	297	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
Kojto	99:dbbf35b96557	298	/**
Kojto	99:dbbf35b96557	299	* @}
Kojto	99:dbbf35b96557	300	*/
Kojto	99:dbbf35b96557	301
Kojto	99:dbbf35b96557	302	/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	303	* @{
Kojto	99:dbbf35b96557	304	*/
Kojto	99:dbbf35b96557	305
Kojto	99:dbbf35b96557	306	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
Kojto	99:dbbf35b96557	307	#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
Kojto	99:dbbf35b96557	308	#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
Kojto	99:dbbf35b96557	309	#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
Kojto	99:dbbf35b96557	310
Kojto	99:dbbf35b96557	311	#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
Kojto	99:dbbf35b96557	312	#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
Kojto	99:dbbf35b96557	313	#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
Kojto	99:dbbf35b96557	314	/**
Kojto	99:dbbf35b96557	315	* @}
Kojto	99:dbbf35b96557	316	*/
Kojto	99:dbbf35b96557	317
Kojto	99:dbbf35b96557	318	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	319	* @{
Kojto	99:dbbf35b96557	320	*/
Kojto	99:dbbf35b96557	321	#define NAND_AddressTypedef NAND_AddressTypeDef
Kojto	99:dbbf35b96557	322
Kojto	99:dbbf35b96557	323	#define __ARRAY_ADDRESS ARRAY_ADDRESS
Kojto	99:dbbf35b96557	324	#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
Kojto	99:dbbf35b96557	325	#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
Kojto	99:dbbf35b96557	326	#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
Kojto	99:dbbf35b96557	327	#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
Kojto	99:dbbf35b96557	328	/**
Kojto	99:dbbf35b96557	329	* @}
Kojto	99:dbbf35b96557	330	*/
Kojto	99:dbbf35b96557	331
Kojto	99:dbbf35b96557	332	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	333	* @{
Kojto	99:dbbf35b96557	334	*/
Kojto	99:dbbf35b96557	335	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
Kojto	99:dbbf35b96557	336	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
Kojto	99:dbbf35b96557	337	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
Kojto	99:dbbf35b96557	338	#define NOR_ERROR HAL_NOR_STATUS_ERROR
Kojto	99:dbbf35b96557	339	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
Kojto	99:dbbf35b96557	340
Kojto	99:dbbf35b96557	341	#define __NOR_WRITE NOR_WRITE
Kojto	99:dbbf35b96557	342	#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
Kojto	99:dbbf35b96557	343	/**
Kojto	99:dbbf35b96557	344	* @}
Kojto	99:dbbf35b96557	345	*/
Kojto	99:dbbf35b96557	346
Kojto	99:dbbf35b96557	347	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	348	* @{
Kojto	99:dbbf35b96557	349	*/
Kojto	99:dbbf35b96557	350
Kojto	99:dbbf35b96557	351	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
Kojto	99:dbbf35b96557	352	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
Kojto	99:dbbf35b96557	353	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
Kojto	99:dbbf35b96557	354	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
Kojto	99:dbbf35b96557	355
Kojto	99:dbbf35b96557	356	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
Kojto	99:dbbf35b96557	357	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
Kojto	99:dbbf35b96557	358	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
Kojto	99:dbbf35b96557	359	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
Kojto	99:dbbf35b96557	360
Kojto	99:dbbf35b96557	361	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto	99:dbbf35b96557	362	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto	99:dbbf35b96557	363
Kojto	99:dbbf35b96557	364	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto	99:dbbf35b96557	365	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto	99:dbbf35b96557	366
Kojto	99:dbbf35b96557	367	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
Kojto	99:dbbf35b96557	368	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
Kojto	99:dbbf35b96557	369
Kojto	99:dbbf35b96557	370	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
Kojto	99:dbbf35b96557	371
Kojto	99:dbbf35b96557	372	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
Kojto	99:dbbf35b96557	373	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
Kojto	99:dbbf35b96557	374	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
Kojto	99:dbbf35b96557	375
Kojto	99:dbbf35b96557	376	/**
Kojto	99:dbbf35b96557	377	* @}
Kojto	99:dbbf35b96557	378	*/
Kojto	99:dbbf35b96557	379
Kojto	99:dbbf35b96557	380	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	381	* @{
Kojto	99:dbbf35b96557	382	*/
Kojto	99:dbbf35b96557	383	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
Kojto	99:dbbf35b96557	384	/**
Kojto	99:dbbf35b96557	385	* @}
Kojto	99:dbbf35b96557	386	*/
Kojto	99:dbbf35b96557	387
Kojto	99:dbbf35b96557	388	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	389	* @{
Kojto	99:dbbf35b96557	390	*/
Kojto	99:dbbf35b96557	391
Kojto	99:dbbf35b96557	392	/* Compact Flash-ATA registers description */
Kojto	99:dbbf35b96557	393	#define CF_DATA ATA_DATA
Kojto	99:dbbf35b96557	394	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
Kojto	99:dbbf35b96557	395	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
Kojto	99:dbbf35b96557	396	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
Kojto	99:dbbf35b96557	397	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
Kojto	99:dbbf35b96557	398	#define CF_CARD_HEAD ATA_CARD_HEAD
Kojto	99:dbbf35b96557	399	#define CF_STATUS_CMD ATA_STATUS_CMD
Kojto	99:dbbf35b96557	400	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
Kojto	99:dbbf35b96557	401	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
Kojto	99:dbbf35b96557	402
Kojto	99:dbbf35b96557	403	/* Compact Flash-ATA commands */
Kojto	99:dbbf35b96557	404	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
Kojto	99:dbbf35b96557	405	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
Kojto	99:dbbf35b96557	406	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
Kojto	99:dbbf35b96557	407	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
Kojto	99:dbbf35b96557	408
Kojto	99:dbbf35b96557	409	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
Kojto	99:dbbf35b96557	410	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
Kojto	99:dbbf35b96557	411	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
Kojto	99:dbbf35b96557	412	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
Kojto	99:dbbf35b96557	413	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
Kojto	99:dbbf35b96557	414	/**
Kojto	99:dbbf35b96557	415	* @}
Kojto	99:dbbf35b96557	416	*/
Kojto	99:dbbf35b96557	417
Kojto	99:dbbf35b96557	418	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	419	* @{
Kojto	99:dbbf35b96557	420	*/
Kojto	99:dbbf35b96557	421
Kojto	99:dbbf35b96557	422	#define FORMAT_BIN RTC_FORMAT_BIN
Kojto	99:dbbf35b96557	423	#define FORMAT_BCD RTC_FORMAT_BCD
Kojto	99:dbbf35b96557	424
Kojto	99:dbbf35b96557	425	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
Kojto	99:dbbf35b96557	426	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto	99:dbbf35b96557	427	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto	99:dbbf35b96557	428	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto	99:dbbf35b96557	429	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto	99:dbbf35b96557	430
Kojto	99:dbbf35b96557	431	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto	99:dbbf35b96557	432	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto	99:dbbf35b96557	433	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto	99:dbbf35b96557	434	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto	99:dbbf35b96557	435	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto	99:dbbf35b96557	436	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto	99:dbbf35b96557	437	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto	99:dbbf35b96557	438	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto	99:dbbf35b96557	439
Kojto	99:dbbf35b96557	440	/**
Kojto	99:dbbf35b96557	441	* @}
Kojto	99:dbbf35b96557	442	*/
Kojto	99:dbbf35b96557	443
Kojto	99:dbbf35b96557	444
Kojto	99:dbbf35b96557	445	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	446	* @{
Kojto	99:dbbf35b96557	447	*/
Kojto	99:dbbf35b96557	448	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
Kojto	99:dbbf35b96557	449	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
Kojto	99:dbbf35b96557	450
Kojto	99:dbbf35b96557	451	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto	99:dbbf35b96557	452	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto	99:dbbf35b96557	453	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto	99:dbbf35b96557	454	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto	99:dbbf35b96557	455
Kojto	99:dbbf35b96557	456	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
Kojto	99:dbbf35b96557	457	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
Kojto	99:dbbf35b96557	458
Kojto	99:dbbf35b96557	459	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
Kojto	99:dbbf35b96557	460	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
Kojto	99:dbbf35b96557	461	/**
Kojto	99:dbbf35b96557	462	* @}
Kojto	99:dbbf35b96557	463	*/
Kojto	99:dbbf35b96557	464
Kojto	99:dbbf35b96557	465
Kojto	99:dbbf35b96557	466	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	467	* @{
Kojto	99:dbbf35b96557	468	*/
Kojto	99:dbbf35b96557	469	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
Kojto	99:dbbf35b96557	470	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
Kojto	99:dbbf35b96557	471	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
Kojto	99:dbbf35b96557	472	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
Kojto	99:dbbf35b96557	473	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
Kojto	99:dbbf35b96557	474	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
Kojto	99:dbbf35b96557	475	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
Kojto	99:dbbf35b96557	476	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
Kojto	99:dbbf35b96557	477	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
Kojto	99:dbbf35b96557	478	/**
Kojto	99:dbbf35b96557	479	* @}
Kojto	99:dbbf35b96557	480	*/
Kojto	99:dbbf35b96557	481
Kojto	99:dbbf35b96557	482	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	483	* @{
Kojto	99:dbbf35b96557	484	*/
Kojto	99:dbbf35b96557	485	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
Kojto	99:dbbf35b96557	486	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
Kojto	99:dbbf35b96557	487
Kojto	99:dbbf35b96557	488	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
Kojto	99:dbbf35b96557	489	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
Kojto	99:dbbf35b96557	490
Kojto	99:dbbf35b96557	491	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
Kojto	99:dbbf35b96557	492	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
Kojto	99:dbbf35b96557	493
Kojto	99:dbbf35b96557	494	/**
Kojto	99:dbbf35b96557	495	* @}
Kojto	99:dbbf35b96557	496	*/
Kojto	99:dbbf35b96557	497
Kojto	99:dbbf35b96557	498	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	499	* @{
Kojto	99:dbbf35b96557	500	*/
Kojto	99:dbbf35b96557	501	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
Kojto	99:dbbf35b96557	502	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
Kojto	99:dbbf35b96557	503
Kojto	99:dbbf35b96557	504	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
Kojto	99:dbbf35b96557	505	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
Kojto	99:dbbf35b96557	506	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
Kojto	99:dbbf35b96557	507	#define TIM_DMABase_DIER TIM_DMABASE_DIER
Kojto	99:dbbf35b96557	508	#define TIM_DMABase_SR TIM_DMABASE_SR
Kojto	99:dbbf35b96557	509	#define TIM_DMABase_EGR TIM_DMABASE_EGR
Kojto	99:dbbf35b96557	510	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
Kojto	99:dbbf35b96557	511	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
Kojto	99:dbbf35b96557	512	#define TIM_DMABase_CCER TIM_DMABASE_CCER
Kojto	99:dbbf35b96557	513	#define TIM_DMABase_CNT TIM_DMABASE_CNT
Kojto	99:dbbf35b96557	514	#define TIM_DMABase_PSC TIM_DMABASE_PSC
Kojto	99:dbbf35b96557	515	#define TIM_DMABase_ARR TIM_DMABASE_ARR
Kojto	99:dbbf35b96557	516	#define TIM_DMABase_RCR TIM_DMABASE_RCR
Kojto	99:dbbf35b96557	517	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
Kojto	99:dbbf35b96557	518	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
Kojto	99:dbbf35b96557	519	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
Kojto	99:dbbf35b96557	520	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
Kojto	99:dbbf35b96557	521	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
Kojto	99:dbbf35b96557	522	#define TIM_DMABase_DCR TIM_DMABASE_DCR
Kojto	99:dbbf35b96557	523	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
Kojto	99:dbbf35b96557	524	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
Kojto	99:dbbf35b96557	525	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
Kojto	99:dbbf35b96557	526	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
Kojto	99:dbbf35b96557	527	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
Kojto	99:dbbf35b96557	528	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
Kojto	99:dbbf35b96557	529	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
Kojto	99:dbbf35b96557	530	#define TIM_DMABase_OR TIM_DMABASE_OR
Kojto	99:dbbf35b96557	531
Kojto	99:dbbf35b96557	532	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
Kojto	99:dbbf35b96557	533	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
Kojto	99:dbbf35b96557	534	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
Kojto	99:dbbf35b96557	535	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
Kojto	99:dbbf35b96557	536	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
Kojto	99:dbbf35b96557	537	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
Kojto	99:dbbf35b96557	538	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
Kojto	99:dbbf35b96557	539	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
Kojto	99:dbbf35b96557	540	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
Kojto	99:dbbf35b96557	541
Kojto	99:dbbf35b96557	542	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
Kojto	99:dbbf35b96557	543	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
Kojto	99:dbbf35b96557	544	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
Kojto	99:dbbf35b96557	545	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
Kojto	99:dbbf35b96557	546	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
Kojto	99:dbbf35b96557	547	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
Kojto	99:dbbf35b96557	548	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
Kojto	99:dbbf35b96557	549	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
Kojto	99:dbbf35b96557	550	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
Kojto	99:dbbf35b96557	551	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
Kojto	99:dbbf35b96557	552	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
Kojto	99:dbbf35b96557	553	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
Kojto	99:dbbf35b96557	554	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
Kojto	99:dbbf35b96557	555	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
Kojto	99:dbbf35b96557	556	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
Kojto	99:dbbf35b96557	557	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
Kojto	99:dbbf35b96557	558	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
Kojto	99:dbbf35b96557	559	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
Kojto	99:dbbf35b96557	560
Kojto	99:dbbf35b96557	561	/**
Kojto	99:dbbf35b96557	562	* @}
Kojto	99:dbbf35b96557	563	*/
Kojto	99:dbbf35b96557	564
Kojto	99:dbbf35b96557	565	/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	566	* @{
Kojto	99:dbbf35b96557	567	*/
Kojto	99:dbbf35b96557	568	#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
Kojto	99:dbbf35b96557	569	#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
Kojto	99:dbbf35b96557	570	/**
Kojto	99:dbbf35b96557	571	* @}
Kojto	99:dbbf35b96557	572	*/
Kojto	99:dbbf35b96557	573
Kojto	99:dbbf35b96557	574	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	575	* @{
Kojto	99:dbbf35b96557	576	*/
Kojto	99:dbbf35b96557	577	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto	99:dbbf35b96557	578	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto	99:dbbf35b96557	579	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto	99:dbbf35b96557	580	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto	99:dbbf35b96557	581
Kojto	99:dbbf35b96557	582	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
Kojto	99:dbbf35b96557	583	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
Kojto	99:dbbf35b96557	584
Kojto	99:dbbf35b96557	585	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
Kojto	99:dbbf35b96557	586	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
Kojto	99:dbbf35b96557	587	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
Kojto	99:dbbf35b96557	588	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
Kojto	99:dbbf35b96557	589
Kojto	99:dbbf35b96557	590	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
Kojto	99:dbbf35b96557	591	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
Kojto	99:dbbf35b96557	592	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
Kojto	99:dbbf35b96557	593	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
Kojto	99:dbbf35b96557	594
Kojto	99:dbbf35b96557	595	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
Kojto	99:dbbf35b96557	596	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
Kojto	99:dbbf35b96557	597
Kojto	99:dbbf35b96557	598	/**
Kojto	99:dbbf35b96557	599	* @}
Kojto	99:dbbf35b96557	600	*/
Kojto	99:dbbf35b96557	601
Kojto	99:dbbf35b96557	602
Kojto	99:dbbf35b96557	603	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	604	* @{
Kojto	99:dbbf35b96557	605	*/
Kojto	99:dbbf35b96557	606
Kojto	99:dbbf35b96557	607	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
Kojto	99:dbbf35b96557	608	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
Kojto	99:dbbf35b96557	609
Kojto	99:dbbf35b96557	610	#define USARTNACK_ENABLED USART_NACK_ENABLE
Kojto	99:dbbf35b96557	611	#define USARTNACK_DISABLED USART_NACK_DISABLE
Kojto	99:dbbf35b96557	612	/**
Kojto	99:dbbf35b96557	613	* @}
Kojto	99:dbbf35b96557	614	*/
Kojto	99:dbbf35b96557	615
Kojto	99:dbbf35b96557	616	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	617	* @{
Kojto	99:dbbf35b96557	618	*/
Kojto	99:dbbf35b96557	619	#define CFR_BASE WWDG_CFR_BASE
Kojto	99:dbbf35b96557	620
Kojto	99:dbbf35b96557	621	/**
Kojto	99:dbbf35b96557	622	* @}
Kojto	99:dbbf35b96557	623	*/
Kojto	99:dbbf35b96557	624
Kojto	99:dbbf35b96557	625	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	626	* @{
Kojto	99:dbbf35b96557	627	*/
Kojto	99:dbbf35b96557	628	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
Kojto	99:dbbf35b96557	629	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
Kojto	99:dbbf35b96557	630	#define CAN_IT_RQCP0 CAN_IT_TME
Kojto	99:dbbf35b96557	631	#define CAN_IT_RQCP1 CAN_IT_TME
Kojto	99:dbbf35b96557	632	#define CAN_IT_RQCP2 CAN_IT_TME
Kojto	99:dbbf35b96557	633	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto	99:dbbf35b96557	634	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto	99:dbbf35b96557	635	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
Kojto	99:dbbf35b96557	636	#define CAN_TXSTATUS_OK ((uint8_t)0x01)
Kojto	99:dbbf35b96557	637	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
Kojto	99:dbbf35b96557	638
Kojto	99:dbbf35b96557	639	/**
Kojto	99:dbbf35b96557	640	* @}
Kojto	99:dbbf35b96557	641	*/
Kojto	99:dbbf35b96557	642
Kojto	99:dbbf35b96557	643	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	644	* @{
Kojto	99:dbbf35b96557	645	*/
Kojto	99:dbbf35b96557	646
Kojto	99:dbbf35b96557	647	#define VLAN_TAG ETH_VLAN_TAG
Kojto	99:dbbf35b96557	648	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
Kojto	99:dbbf35b96557	649	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
Kojto	99:dbbf35b96557	650	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
Kojto	99:dbbf35b96557	651	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
Kojto	99:dbbf35b96557	652	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
Kojto	99:dbbf35b96557	653	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
Kojto	99:dbbf35b96557	654	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
Kojto	99:dbbf35b96557	655
Kojto	99:dbbf35b96557	656	#define ETH_MMCCR ((uint32_t)0x00000100)
Kojto	99:dbbf35b96557	657	#define ETH_MMCRIR ((uint32_t)0x00000104)
Kojto	99:dbbf35b96557	658	#define ETH_MMCTIR ((uint32_t)0x00000108)
Kojto	99:dbbf35b96557	659	#define ETH_MMCRIMR ((uint32_t)0x0000010C)
Kojto	99:dbbf35b96557	660	#define ETH_MMCTIMR ((uint32_t)0x00000110)
Kojto	99:dbbf35b96557	661	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
Kojto	99:dbbf35b96557	662	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
Kojto	99:dbbf35b96557	663	#define ETH_MMCTGFCR ((uint32_t)0x00000168)
Kojto	99:dbbf35b96557	664	#define ETH_MMCRFCECR ((uint32_t)0x00000194)
Kojto	99:dbbf35b96557	665	#define ETH_MMCRFAECR ((uint32_t)0x00000198)
Kojto	99:dbbf35b96557	666	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
Kojto	99:dbbf35b96557	667
Kojto	99:dbbf35b96557	668	/**
Kojto	99:dbbf35b96557	669	* @}
Kojto	99:dbbf35b96557	670	*/
Kojto	99:dbbf35b96557	671
Kojto	99:dbbf35b96557	672	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
Kojto	99:dbbf35b96557	673	* @{
Kojto	99:dbbf35b96557	674	*/
Kojto	99:dbbf35b96557	675
Kojto	99:dbbf35b96557	676	/**
Kojto	99:dbbf35b96557	677	* @}
Kojto	99:dbbf35b96557	678	*/
Kojto	99:dbbf35b96557	679
Kojto	99:dbbf35b96557	680	/* Exported functions --------------------------------------------------------*/
Kojto	99:dbbf35b96557	681
Kojto	99:dbbf35b96557	682	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
Kojto	99:dbbf35b96557	683	* @{
Kojto	99:dbbf35b96557	684	*/
Kojto	99:dbbf35b96557	685	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
Kojto	99:dbbf35b96557	686	/**
Kojto	99:dbbf35b96557	687	* @}
Kojto	99:dbbf35b96557	688	*/
Kojto	99:dbbf35b96557	689
Kojto	99:dbbf35b96557	690	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
Kojto	99:dbbf35b96557	691	* @{
Kojto	99:dbbf35b96557	692	*/
Kojto	99:dbbf35b96557	693
Kojto	99:dbbf35b96557	694	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
Kojto	99:dbbf35b96557	695	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
Kojto	99:dbbf35b96557	696	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
Kojto	99:dbbf35b96557	697	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
Kojto	99:dbbf35b96557	698
Kojto	99:dbbf35b96557	699	/HASH Algorithm Selection/
Kojto	99:dbbf35b96557	700
Kojto	99:dbbf35b96557	701	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
Kojto	99:dbbf35b96557	702	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
Kojto	99:dbbf35b96557	703	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
Kojto	99:dbbf35b96557	704	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
Kojto	99:dbbf35b96557	705
Kojto	99:dbbf35b96557	706	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
Kojto	99:dbbf35b96557	707	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
Kojto	99:dbbf35b96557	708
Kojto	99:dbbf35b96557	709	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
Kojto	99:dbbf35b96557	710	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
Kojto	99:dbbf35b96557	711	/**
Kojto	99:dbbf35b96557	712	* @}
Kojto	99:dbbf35b96557	713	*/
Kojto	99:dbbf35b96557	714
Kojto	99:dbbf35b96557	715	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
Kojto	99:dbbf35b96557	716	* @{
Kojto	99:dbbf35b96557	717	*/
Kojto	99:dbbf35b96557	718	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
Kojto	99:dbbf35b96557	719	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
Kojto	99:dbbf35b96557	720	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
Kojto	99:dbbf35b96557	721	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
Kojto	99:dbbf35b96557	722	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
Kojto	99:dbbf35b96557	723	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
Kojto	99:dbbf35b96557	724	#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
Kojto	99:dbbf35b96557	725	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
Kojto	99:dbbf35b96557	726	#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
Kojto	99:dbbf35b96557	727	#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
Kojto	99:dbbf35b96557	728	#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
Kojto	99:dbbf35b96557	729	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
Kojto	99:dbbf35b96557	730	/**
Kojto	99:dbbf35b96557	731	* @}
Kojto	99:dbbf35b96557	732	*/
Kojto	99:dbbf35b96557	733
Kojto	99:dbbf35b96557	734	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
Kojto	99:dbbf35b96557	735	* @{
Kojto	99:dbbf35b96557	736	*/
Kojto	99:dbbf35b96557	737	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
Kojto	99:dbbf35b96557	738	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
Kojto	99:dbbf35b96557	739	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
Kojto	99:dbbf35b96557	740	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
Kojto	99:dbbf35b96557	741	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
Kojto	99:dbbf35b96557	742	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
Kojto	99:dbbf35b96557	743	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
Kojto	99:dbbf35b96557	744
Kojto	99:dbbf35b96557	745	/**
Kojto	99:dbbf35b96557	746	* @}
Kojto	99:dbbf35b96557	747	*/
Kojto	99:dbbf35b96557	748
Kojto	99:dbbf35b96557	749	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
Kojto	99:dbbf35b96557	750	* @{
Kojto	99:dbbf35b96557	751	*/
Kojto	99:dbbf35b96557	752	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
Kojto	99:dbbf35b96557	753	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
Kojto	99:dbbf35b96557	754
Kojto	99:dbbf35b96557	755	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
Kojto	99:dbbf35b96557	756	/**
Kojto	99:dbbf35b96557	757	* @}
Kojto	99:dbbf35b96557	758	*/
Kojto	99:dbbf35b96557	759
Kojto	99:dbbf35b96557	760	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
Kojto	99:dbbf35b96557	761	* @{
Kojto	99:dbbf35b96557	762	*/
Kojto	99:dbbf35b96557	763	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
Kojto	99:dbbf35b96557	764	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
Kojto	99:dbbf35b96557	765	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
Kojto	99:dbbf35b96557	766	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
Kojto	99:dbbf35b96557	767	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
Kojto	99:dbbf35b96557	768	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
Kojto	99:dbbf35b96557	769	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
Kojto	99:dbbf35b96557	770	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
Kojto	99:dbbf35b96557	771	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
Kojto	99:dbbf35b96557	772	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
Kojto	99:dbbf35b96557	773	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
Kojto	99:dbbf35b96557	774	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
Kojto	99:dbbf35b96557	775	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
Kojto	99:dbbf35b96557	776	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
Kojto	99:dbbf35b96557	777	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
Kojto	99:dbbf35b96557	778	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
Kojto	99:dbbf35b96557	779
Kojto	99:dbbf35b96557	780	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
Kojto	99:dbbf35b96557	781	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
Kojto	99:dbbf35b96557	782	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
Kojto	99:dbbf35b96557	783	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
Kojto	99:dbbf35b96557	784	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
Kojto	99:dbbf35b96557	785	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
Kojto	99:dbbf35b96557	786	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
Kojto	99:dbbf35b96557	787
Kojto	99:dbbf35b96557	788	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
Kojto	99:dbbf35b96557	789	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
Kojto	99:dbbf35b96557	790
Kojto	99:dbbf35b96557	791	#define DBP_BitNumber DBP_BIT_NUMBER
Kojto	99:dbbf35b96557	792	#define PVDE_BitNumber PVDE_BIT_NUMBER
Kojto	99:dbbf35b96557	793	#define PMODE_BitNumber PMODE_BIT_NUMBER
Kojto	99:dbbf35b96557	794	#define EWUP_BitNumber EWUP_BIT_NUMBER
Kojto	99:dbbf35b96557	795	#define FPDS_BitNumber FPDS_BIT_NUMBER
Kojto	99:dbbf35b96557	796	#define ODEN_BitNumber ODEN_BIT_NUMBER
Kojto	99:dbbf35b96557	797	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
Kojto	99:dbbf35b96557	798	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
Kojto	99:dbbf35b96557	799	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
Kojto	99:dbbf35b96557	800	#define BRE_BitNumber BRE_BIT_NUMBER
Kojto	99:dbbf35b96557	801
Kojto	99:dbbf35b96557	802	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
Kojto	99:dbbf35b96557	803
Kojto	99:dbbf35b96557	804	#define IS_PWR_REGULATOR_VOLTAGE IS_PWR_VOLTAGE_SCALING_RANGE
Kojto	99:dbbf35b96557	805	/**
Kojto	99:dbbf35b96557	806	* @}
Kojto	99:dbbf35b96557	807	*/
Kojto	99:dbbf35b96557	808
Kojto	99:dbbf35b96557	809	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
Kojto	99:dbbf35b96557	810	* @{
Kojto	99:dbbf35b96557	811	*/
Kojto	99:dbbf35b96557	812	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
Kojto	99:dbbf35b96557	813	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
Kojto	99:dbbf35b96557	814	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
Kojto	99:dbbf35b96557	815	/**
Kojto	99:dbbf35b96557	816	* @}
Kojto	99:dbbf35b96557	817	*/
Kojto	99:dbbf35b96557	818
Kojto	99:dbbf35b96557	819	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
Kojto	99:dbbf35b96557	820	* @{
Kojto	99:dbbf35b96557	821	*/
Kojto	99:dbbf35b96557	822	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
Kojto	99:dbbf35b96557	823	/**
Kojto	99:dbbf35b96557	824	* @}
Kojto	99:dbbf35b96557	825	*/
Kojto	99:dbbf35b96557	826
Kojto	99:dbbf35b96557	827	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
Kojto	99:dbbf35b96557	828	* @{
Kojto	99:dbbf35b96557	829	*/
Kojto	99:dbbf35b96557	830	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
Kojto	99:dbbf35b96557	831	#define HAL_TIM_DMAError TIM_DMAError
Kojto	99:dbbf35b96557	832	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
Kojto	99:dbbf35b96557	833	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
Kojto	99:dbbf35b96557	834	/**
Kojto	99:dbbf35b96557	835	* @}
Kojto	99:dbbf35b96557	836	*/
Kojto	99:dbbf35b96557	837
Kojto	99:dbbf35b96557	838	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
Kojto	99:dbbf35b96557	839	* @{
Kojto	99:dbbf35b96557	840	*/
Kojto	99:dbbf35b96557	841	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
Kojto	99:dbbf35b96557	842	/**
Kojto	99:dbbf35b96557	843	* @}
Kojto	99:dbbf35b96557	844	*/
Kojto	99:dbbf35b96557	845
Kojto	99:dbbf35b96557	846
Kojto	99:dbbf35b96557	847	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
Kojto	99:dbbf35b96557	848	* @{
Kojto	99:dbbf35b96557	849	*/
Kojto	99:dbbf35b96557	850
Kojto	99:dbbf35b96557	851	/**
Kojto	99:dbbf35b96557	852	* @}
Kojto	99:dbbf35b96557	853	*/
Kojto	99:dbbf35b96557	854
Kojto	99:dbbf35b96557	855	/* Exported macros ------------------------------------------------------------*/
Kojto	99:dbbf35b96557	856
Kojto	99:dbbf35b96557	857	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	858	* @{
Kojto	99:dbbf35b96557	859	*/
Kojto	99:dbbf35b96557	860	#define AES_IT_CC CRYP_IT_CC
Kojto	99:dbbf35b96557	861	#define AES_IT_ERR CRYP_IT_ERR
Kojto	99:dbbf35b96557	862	#define AES_FLAG_CCF CRYP_FLAG_CCF
Kojto	99:dbbf35b96557	863	/**
Kojto	99:dbbf35b96557	864	* @}
Kojto	99:dbbf35b96557	865	*/
Kojto	99:dbbf35b96557	866
Kojto	99:dbbf35b96557	867	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	868	* @{
Kojto	99:dbbf35b96557	869	*/
Kojto	99:dbbf35b96557	870	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
Kojto	99:dbbf35b96557	871	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
Kojto	99:dbbf35b96557	872	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
Kojto	99:dbbf35b96557	873	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
Kojto	99:dbbf35b96557	874	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
Kojto	99:dbbf35b96557	875	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
Kojto	99:dbbf35b96557	876	#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
Kojto	99:dbbf35b96557	877	#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
Kojto	99:dbbf35b96557	878	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
Kojto	99:dbbf35b96557	879	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
Kojto	99:dbbf35b96557	880	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
Kojto	99:dbbf35b96557	881	#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
Kojto	99:dbbf35b96557	882	#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
Kojto	99:dbbf35b96557	883
Kojto	99:dbbf35b96557	884	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
Kojto	99:dbbf35b96557	885	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
Kojto	99:dbbf35b96557	886	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
Kojto	99:dbbf35b96557	887	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
Kojto	99:dbbf35b96557	888	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
Kojto	99:dbbf35b96557	889
Kojto	99:dbbf35b96557	890	/**
Kojto	99:dbbf35b96557	891	* @}
Kojto	99:dbbf35b96557	892	*/
Kojto	99:dbbf35b96557	893
Kojto	99:dbbf35b96557	894
Kojto	99:dbbf35b96557	895	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	896	* @{
Kojto	99:dbbf35b96557	897	*/
Kojto	99:dbbf35b96557	898	#define __ADC_ENABLE __HAL_ADC_ENABLE
Kojto	99:dbbf35b96557	899	#define __ADC_DISABLE __HAL_ADC_DISABLE
Kojto	99:dbbf35b96557	900	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
Kojto	99:dbbf35b96557	901	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
Kojto	99:dbbf35b96557	902	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
Kojto	99:dbbf35b96557	903	#define __ADC_IS_ENABLED ADC_IS_ENABLE
Kojto	99:dbbf35b96557	904	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
Kojto	99:dbbf35b96557	905	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
Kojto	99:dbbf35b96557	906	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
Kojto	99:dbbf35b96557	907	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
Kojto	99:dbbf35b96557	908	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
Kojto	99:dbbf35b96557	909	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
Kojto	99:dbbf35b96557	910	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
Kojto	99:dbbf35b96557	911
Kojto	99:dbbf35b96557	912	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto	99:dbbf35b96557	913	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
Kojto	99:dbbf35b96557	914	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
Kojto	99:dbbf35b96557	915	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
Kojto	99:dbbf35b96557	916	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
Kojto	99:dbbf35b96557	917	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
Kojto	99:dbbf35b96557	918	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
Kojto	99:dbbf35b96557	919	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
Kojto	99:dbbf35b96557	920	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
Kojto	99:dbbf35b96557	921	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
Kojto	99:dbbf35b96557	922	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
Kojto	99:dbbf35b96557	923	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
Kojto	99:dbbf35b96557	924	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
Kojto	99:dbbf35b96557	925	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
Kojto	99:dbbf35b96557	926	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
Kojto	99:dbbf35b96557	927	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
Kojto	99:dbbf35b96557	928	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
Kojto	99:dbbf35b96557	929	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
Kojto	99:dbbf35b96557	930	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
Kojto	99:dbbf35b96557	931	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
Kojto	99:dbbf35b96557	932
Kojto	99:dbbf35b96557	933	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
Kojto	99:dbbf35b96557	934	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
Kojto	99:dbbf35b96557	935	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
Kojto	99:dbbf35b96557	936	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
Kojto	99:dbbf35b96557	937	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
Kojto	99:dbbf35b96557	938	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto	99:dbbf35b96557	939	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto	99:dbbf35b96557	940	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
Kojto	99:dbbf35b96557	941	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
Kojto	99:dbbf35b96557	942	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
Kojto	99:dbbf35b96557	943
Kojto	99:dbbf35b96557	944	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
Kojto	99:dbbf35b96557	945	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
Kojto	99:dbbf35b96557	946	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
Kojto	99:dbbf35b96557	947	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
Kojto	99:dbbf35b96557	948	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
Kojto	99:dbbf35b96557	949	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
Kojto	99:dbbf35b96557	950	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
Kojto	99:dbbf35b96557	951	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
Kojto	99:dbbf35b96557	952
Kojto	99:dbbf35b96557	953	#define __HAL_ADC_SQR1 ADC_SQR1
Kojto	99:dbbf35b96557	954	#define __HAL_ADC_SMPR1 ADC_SMPR1
Kojto	99:dbbf35b96557	955	#define __HAL_ADC_SMPR2 ADC_SMPR2
Kojto	99:dbbf35b96557	956	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
Kojto	99:dbbf35b96557	957	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
Kojto	99:dbbf35b96557	958	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
Kojto	99:dbbf35b96557	959	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
Kojto	99:dbbf35b96557	960	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
Kojto	99:dbbf35b96557	961	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
Kojto	99:dbbf35b96557	962	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
Kojto	99:dbbf35b96557	963	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
Kojto	99:dbbf35b96557	964	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto	99:dbbf35b96557	965	#define __HAL_ADC_JSQR ADC_JSQR
Kojto	99:dbbf35b96557	966
Kojto	99:dbbf35b96557	967	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
Kojto	99:dbbf35b96557	968	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
Kojto	99:dbbf35b96557	969	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
Kojto	99:dbbf35b96557	970	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
Kojto	99:dbbf35b96557	971	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
Kojto	99:dbbf35b96557	972	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
Kojto	99:dbbf35b96557	973	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
Kojto	99:dbbf35b96557	974	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
Kojto	99:dbbf35b96557	975
Kojto	99:dbbf35b96557	976	/**
Kojto	99:dbbf35b96557	977	* @}
Kojto	99:dbbf35b96557	978	*/
Kojto	99:dbbf35b96557	979
Kojto	99:dbbf35b96557	980	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	981	* @{
Kojto	99:dbbf35b96557	982	*/
Kojto	99:dbbf35b96557	983	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
Kojto	99:dbbf35b96557	984	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
Kojto	99:dbbf35b96557	985	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
Kojto	99:dbbf35b96557	986	#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
Kojto	99:dbbf35b96557	987
Kojto	99:dbbf35b96557	988	/**
Kojto	99:dbbf35b96557	989	* @}
Kojto	99:dbbf35b96557	990	*/
Kojto	99:dbbf35b96557	991
Kojto	99:dbbf35b96557	992	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	993	* @{
Kojto	99:dbbf35b96557	994	*/
Kojto	99:dbbf35b96557	995	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
Kojto	99:dbbf35b96557	996	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
Kojto	99:dbbf35b96557	997	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
Kojto	99:dbbf35b96557	998	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
Kojto	99:dbbf35b96557	999	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
Kojto	99:dbbf35b96557	1000	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
Kojto	99:dbbf35b96557	1001	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
Kojto	99:dbbf35b96557	1002	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
Kojto	99:dbbf35b96557	1003	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
Kojto	99:dbbf35b96557	1004	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
Kojto	99:dbbf35b96557	1005	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
Kojto	99:dbbf35b96557	1006	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
Kojto	99:dbbf35b96557	1007	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
Kojto	99:dbbf35b96557	1008	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
Kojto	99:dbbf35b96557	1009	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
Kojto	99:dbbf35b96557	1010	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
Kojto	99:dbbf35b96557	1011
Kojto	99:dbbf35b96557	1012	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
Kojto	99:dbbf35b96557	1013	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
Kojto	99:dbbf35b96557	1014	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
Kojto	99:dbbf35b96557	1015	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
Kojto	99:dbbf35b96557	1016	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
Kojto	99:dbbf35b96557	1017	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
Kojto	99:dbbf35b96557	1018	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
Kojto	99:dbbf35b96557	1019	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
Kojto	99:dbbf35b96557	1020	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
Kojto	99:dbbf35b96557	1021	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
Kojto	99:dbbf35b96557	1022	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
Kojto	99:dbbf35b96557	1023	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
Kojto	99:dbbf35b96557	1024	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
Kojto	99:dbbf35b96557	1025	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
Kojto	99:dbbf35b96557	1026
Kojto	99:dbbf35b96557	1027
Kojto	99:dbbf35b96557	1028	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
Kojto	99:dbbf35b96557	1029	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
Kojto	99:dbbf35b96557	1030	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
Kojto	99:dbbf35b96557	1031	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
Kojto	99:dbbf35b96557	1032	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
Kojto	99:dbbf35b96557	1033	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
Kojto	99:dbbf35b96557	1034	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
Kojto	99:dbbf35b96557	1035	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
Kojto	99:dbbf35b96557	1036	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
Kojto	99:dbbf35b96557	1037	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
Kojto	99:dbbf35b96557	1038	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
Kojto	99:dbbf35b96557	1039	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
Kojto	99:dbbf35b96557	1040	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
Kojto	99:dbbf35b96557	1041	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
Kojto	99:dbbf35b96557	1042	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
Kojto	99:dbbf35b96557	1043	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
Kojto	99:dbbf35b96557	1044	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
Kojto	99:dbbf35b96557	1045	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
Kojto	99:dbbf35b96557	1046	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
Kojto	99:dbbf35b96557	1047	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
Kojto	99:dbbf35b96557	1048	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
Kojto	99:dbbf35b96557	1049	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
Kojto	99:dbbf35b96557	1050	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
Kojto	99:dbbf35b96557	1051	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
Kojto	99:dbbf35b96557	1052
Kojto	99:dbbf35b96557	1053	/**
Kojto	99:dbbf35b96557	1054	* @}
Kojto	99:dbbf35b96557	1055	*/
Kojto	99:dbbf35b96557	1056
Kojto	99:dbbf35b96557	1057	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1058	* @{
Kojto	99:dbbf35b96557	1059	*/
Kojto	99:dbbf35b96557	1060
Kojto	99:dbbf35b96557	1061	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto	99:dbbf35b96557	1062	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto	99:dbbf35b96557	1063	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto	99:dbbf35b96557	1064	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto	99:dbbf35b96557	1065	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	99:dbbf35b96557	1066	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto	99:dbbf35b96557	1067	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto	99:dbbf35b96557	1068	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto	99:dbbf35b96557	1069	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto	99:dbbf35b96557	1070	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto	99:dbbf35b96557	1071	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto	99:dbbf35b96557	1072	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto	99:dbbf35b96557	1073	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto	99:dbbf35b96557	1074	__HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto	99:dbbf35b96557	1075	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto	99:dbbf35b96557	1076	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto	99:dbbf35b96557	1077	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
Kojto	99:dbbf35b96557	1078
Kojto	99:dbbf35b96557	1079	/**
Kojto	99:dbbf35b96557	1080	* @}
Kojto	99:dbbf35b96557	1081	*/
Kojto	99:dbbf35b96557	1082
Kojto	99:dbbf35b96557	1083	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1084	* @{
Kojto	99:dbbf35b96557	1085	*/
Kojto	99:dbbf35b96557	1086
Kojto	99:dbbf35b96557	1087	#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) \|\| \
Kojto	99:dbbf35b96557	1088	((WAVE) == DAC_WAVE_NOISE)\|\| \
Kojto	99:dbbf35b96557	1089	((WAVE) == DAC_WAVE_TRIANGLE))
Kojto	99:dbbf35b96557	1090
Kojto	99:dbbf35b96557	1091	/**
Kojto	99:dbbf35b96557	1092	* @}
Kojto	99:dbbf35b96557	1093	*/
Kojto	99:dbbf35b96557	1094
Kojto	99:dbbf35b96557	1095	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1096	* @{
Kojto	99:dbbf35b96557	1097	*/
Kojto	99:dbbf35b96557	1098
Kojto	99:dbbf35b96557	1099	#define IS_WRPAREA IS_OB_WRPAREA
Kojto	99:dbbf35b96557	1100	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
Kojto	99:dbbf35b96557	1101	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
Kojto	99:dbbf35b96557	1102	#define IS_TYPEERASE IS_FLASH_TYPEERASE
Kojto	99:dbbf35b96557	1103
Kojto	99:dbbf35b96557	1104	/**
Kojto	99:dbbf35b96557	1105	* @}
Kojto	99:dbbf35b96557	1106	*/
Kojto	99:dbbf35b96557	1107
Kojto	99:dbbf35b96557	1108	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1109	* @{
Kojto	99:dbbf35b96557	1110	*/
Kojto	99:dbbf35b96557	1111
Kojto	99:dbbf35b96557	1112	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
Kojto	99:dbbf35b96557	1113	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
Kojto	99:dbbf35b96557	1114	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
Kojto	99:dbbf35b96557	1115	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
Kojto	99:dbbf35b96557	1116	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
Kojto	99:dbbf35b96557	1117	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
Kojto	99:dbbf35b96557	1118	#define __HAL_I2C_SPEED I2C_SPEED
Kojto	99:dbbf35b96557	1119	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
Kojto	99:dbbf35b96557	1120	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
Kojto	99:dbbf35b96557	1121	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
Kojto	99:dbbf35b96557	1122	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
Kojto	99:dbbf35b96557	1123	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
Kojto	99:dbbf35b96557	1124	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
Kojto	99:dbbf35b96557	1125	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
Kojto	99:dbbf35b96557	1126	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
Kojto	99:dbbf35b96557	1127	/**
Kojto	99:dbbf35b96557	1128	* @}
Kojto	99:dbbf35b96557	1129	*/
Kojto	99:dbbf35b96557	1130
Kojto	99:dbbf35b96557	1131	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1132	* @{
Kojto	99:dbbf35b96557	1133	*/
Kojto	99:dbbf35b96557	1134
Kojto	99:dbbf35b96557	1135	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
Kojto	99:dbbf35b96557	1136	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
Kojto	99:dbbf35b96557	1137
Kojto	99:dbbf35b96557	1138	/**
Kojto	99:dbbf35b96557	1139	* @}
Kojto	99:dbbf35b96557	1140	*/
Kojto	99:dbbf35b96557	1141
Kojto	99:dbbf35b96557	1142	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1143	* @{
Kojto	99:dbbf35b96557	1144	*/
Kojto	99:dbbf35b96557	1145
Kojto	99:dbbf35b96557	1146	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
Kojto	99:dbbf35b96557	1147	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
Kojto	99:dbbf35b96557	1148
Kojto	99:dbbf35b96557	1149	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto	99:dbbf35b96557	1150	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto	99:dbbf35b96557	1151	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto	99:dbbf35b96557	1152	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto	99:dbbf35b96557	1153
Kojto	99:dbbf35b96557	1154	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
Kojto	99:dbbf35b96557	1155
Kojto	99:dbbf35b96557	1156
Kojto	99:dbbf35b96557	1157	/**
Kojto	99:dbbf35b96557	1158	* @}
Kojto	99:dbbf35b96557	1159	*/
Kojto	99:dbbf35b96557	1160
Kojto	99:dbbf35b96557	1161
Kojto	99:dbbf35b96557	1162	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1163	* @{
Kojto	99:dbbf35b96557	1164	*/
Kojto	99:dbbf35b96557	1165	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
Kojto	99:dbbf35b96557	1166	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
Kojto	99:dbbf35b96557	1167	/**
Kojto	99:dbbf35b96557	1168	* @}
Kojto	99:dbbf35b96557	1169	*/
Kojto	99:dbbf35b96557	1170
Kojto	99:dbbf35b96557	1171
Kojto	99:dbbf35b96557	1172	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1173	* @{
Kojto	99:dbbf35b96557	1174	*/
Kojto	99:dbbf35b96557	1175
Kojto	99:dbbf35b96557	1176	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
Kojto	99:dbbf35b96557	1177	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
Kojto	99:dbbf35b96557	1178	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
Kojto	99:dbbf35b96557	1179
Kojto	99:dbbf35b96557	1180	/**
Kojto	99:dbbf35b96557	1181	* @}
Kojto	99:dbbf35b96557	1182	*/
Kojto	99:dbbf35b96557	1183
Kojto	99:dbbf35b96557	1184
Kojto	99:dbbf35b96557	1185	/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1186	* @{
Kojto	99:dbbf35b96557	1187	*/
Kojto	99:dbbf35b96557	1188	#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
Kojto	99:dbbf35b96557	1189	#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
Kojto	99:dbbf35b96557	1190	#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
Kojto	99:dbbf35b96557	1191	#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
Kojto	99:dbbf35b96557	1192	#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
Kojto	99:dbbf35b96557	1193	#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
Kojto	99:dbbf35b96557	1194	#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
Kojto	99:dbbf35b96557	1195	#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
Kojto	99:dbbf35b96557	1196	#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
Kojto	99:dbbf35b96557	1197	#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
Kojto	99:dbbf35b96557	1198	#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
Kojto	99:dbbf35b96557	1199	#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
Kojto	99:dbbf35b96557	1200	#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
Kojto	99:dbbf35b96557	1201
Kojto	99:dbbf35b96557	1202	/**
Kojto	99:dbbf35b96557	1203	* @}
Kojto	99:dbbf35b96557	1204	*/
Kojto	99:dbbf35b96557	1205
Kojto	99:dbbf35b96557	1206
Kojto	99:dbbf35b96557	1207	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1208	* @{
Kojto	99:dbbf35b96557	1209	*/
Kojto	99:dbbf35b96557	1210	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto	99:dbbf35b96557	1211	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto	99:dbbf35b96557	1212	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto	99:dbbf35b96557	1213	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto	99:dbbf35b96557	1214	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto	99:dbbf35b96557	1215	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto	99:dbbf35b96557	1216	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
Kojto	99:dbbf35b96557	1217	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
Kojto	99:dbbf35b96557	1218	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
Kojto	99:dbbf35b96557	1219	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
Kojto	99:dbbf35b96557	1220	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
Kojto	99:dbbf35b96557	1221	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
Kojto	99:dbbf35b96557	1222	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
Kojto	99:dbbf35b96557	1223	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
Kojto	99:dbbf35b96557	1224	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
Kojto	99:dbbf35b96557	1225	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
Kojto	99:dbbf35b96557	1226	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
Kojto	99:dbbf35b96557	1227	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto	99:dbbf35b96557	1228	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto	99:dbbf35b96557	1229	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto	99:dbbf35b96557	1230	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto	99:dbbf35b96557	1231	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto	99:dbbf35b96557	1232	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto	99:dbbf35b96557	1233	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto	99:dbbf35b96557	1234	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto	99:dbbf35b96557	1235	#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
Kojto	99:dbbf35b96557	1236	#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
Kojto	99:dbbf35b96557	1237	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
Kojto	99:dbbf35b96557	1238	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
Kojto	99:dbbf35b96557	1239	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
Kojto	99:dbbf35b96557	1240	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
Kojto	99:dbbf35b96557	1241	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
Kojto	99:dbbf35b96557	1242	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
Kojto	99:dbbf35b96557	1243	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
Kojto	99:dbbf35b96557	1244	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
Kojto	99:dbbf35b96557	1245
Kojto	99:dbbf35b96557	1246	#if defined (STM32F4)
Kojto	99:dbbf35b96557	1247	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
Kojto	99:dbbf35b96557	1248	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
Kojto	99:dbbf35b96557	1249	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
Kojto	99:dbbf35b96557	1250	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
Kojto	99:dbbf35b96557	1251	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
Kojto	99:dbbf35b96557	1252	#else
Kojto	99:dbbf35b96557	1253	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
Kojto	99:dbbf35b96557	1254	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
Kojto	99:dbbf35b96557	1255	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
Kojto	99:dbbf35b96557	1256	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
Kojto	99:dbbf35b96557	1257	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
Kojto	99:dbbf35b96557	1258	#endif /* STM32F4 */
Kojto	99:dbbf35b96557	1259	/**
Kojto	99:dbbf35b96557	1260	* @}
Kojto	99:dbbf35b96557	1261	*/
Kojto	99:dbbf35b96557	1262
Kojto	99:dbbf35b96557	1263
Kojto	99:dbbf35b96557	1264	/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
Kojto	99:dbbf35b96557	1265	* @{
Kojto	99:dbbf35b96557	1266	*/
Kojto	99:dbbf35b96557	1267
Kojto	99:dbbf35b96557	1268	#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
Kojto	99:dbbf35b96557	1269	#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
Kojto	99:dbbf35b96557	1270
Kojto	99:dbbf35b96557	1271	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
Kojto	99:dbbf35b96557	1272	#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
Kojto	99:dbbf35b96557	1273
Kojto	99:dbbf35b96557	1274	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
Kojto	99:dbbf35b96557	1275	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
Kojto	99:dbbf35b96557	1276	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1277	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1278	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
Kojto	99:dbbf35b96557	1279	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
Kojto	99:dbbf35b96557	1280	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
Kojto	99:dbbf35b96557	1281	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
Kojto	99:dbbf35b96557	1282	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
Kojto	99:dbbf35b96557	1283	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
Kojto	99:dbbf35b96557	1284	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1285	#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1286	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
Kojto	99:dbbf35b96557	1287	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
Kojto	99:dbbf35b96557	1288	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
Kojto	99:dbbf35b96557	1289	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
Kojto	99:dbbf35b96557	1290	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
Kojto	99:dbbf35b96557	1291	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
Kojto	99:dbbf35b96557	1292	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
Kojto	99:dbbf35b96557	1293	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
Kojto	99:dbbf35b96557	1294	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
Kojto	99:dbbf35b96557	1295	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
Kojto	99:dbbf35b96557	1296	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1297	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1298	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
Kojto	99:dbbf35b96557	1299	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
Kojto	99:dbbf35b96557	1300	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1301	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1302	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
Kojto	99:dbbf35b96557	1303	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
Kojto	99:dbbf35b96557	1304	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto	99:dbbf35b96557	1305	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
Kojto	99:dbbf35b96557	1306	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
Kojto	99:dbbf35b96557	1307	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
Kojto	99:dbbf35b96557	1308	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
Kojto	99:dbbf35b96557	1309	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
Kojto	99:dbbf35b96557	1310	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
Kojto	99:dbbf35b96557	1311	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
Kojto	99:dbbf35b96557	1312	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
Kojto	99:dbbf35b96557	1313	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
Kojto	99:dbbf35b96557	1314	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
Kojto	99:dbbf35b96557	1315	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
Kojto	99:dbbf35b96557	1316	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
Kojto	99:dbbf35b96557	1317	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
Kojto	99:dbbf35b96557	1318	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
Kojto	99:dbbf35b96557	1319	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
Kojto	99:dbbf35b96557	1320	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
Kojto	99:dbbf35b96557	1321	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
Kojto	99:dbbf35b96557	1322	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
Kojto	99:dbbf35b96557	1323	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
Kojto	99:dbbf35b96557	1324	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
Kojto	99:dbbf35b96557	1325	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
Kojto	99:dbbf35b96557	1326	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto	99:dbbf35b96557	1327	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto	99:dbbf35b96557	1328	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1329	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1330	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto	99:dbbf35b96557	1331	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto	99:dbbf35b96557	1332	#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto	99:dbbf35b96557	1333	#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto	99:dbbf35b96557	1334	#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto	99:dbbf35b96557	1335	#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto	99:dbbf35b96557	1336	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
Kojto	99:dbbf35b96557	1337	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
Kojto	99:dbbf35b96557	1338	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
Kojto	99:dbbf35b96557	1339	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
Kojto	99:dbbf35b96557	1340	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
Kojto	99:dbbf35b96557	1341	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
Kojto	99:dbbf35b96557	1342	#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
Kojto	99:dbbf35b96557	1343	#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
Kojto	99:dbbf35b96557	1344	#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
Kojto	99:dbbf35b96557	1345	#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
Kojto	99:dbbf35b96557	1346	#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1347	#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1348	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
Kojto	99:dbbf35b96557	1349	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
Kojto	99:dbbf35b96557	1350	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
Kojto	99:dbbf35b96557	1351	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
Kojto	99:dbbf35b96557	1352	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1353	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1354	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
Kojto	99:dbbf35b96557	1355	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
Kojto	99:dbbf35b96557	1356	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
Kojto	99:dbbf35b96557	1357	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
Kojto	99:dbbf35b96557	1358	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
Kojto	99:dbbf35b96557	1359	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
Kojto	99:dbbf35b96557	1360	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
Kojto	99:dbbf35b96557	1361	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
Kojto	99:dbbf35b96557	1362	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1363	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1364	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
Kojto	99:dbbf35b96557	1365	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
Kojto	99:dbbf35b96557	1366	#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
Kojto	99:dbbf35b96557	1367	#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
Kojto	99:dbbf35b96557	1368	#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
Kojto	99:dbbf35b96557	1369	#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
Kojto	99:dbbf35b96557	1370	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
Kojto	99:dbbf35b96557	1371	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
Kojto	99:dbbf35b96557	1372	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1373	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1374	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
Kojto	99:dbbf35b96557	1375	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
Kojto	99:dbbf35b96557	1376	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
Kojto	99:dbbf35b96557	1377	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
Kojto	99:dbbf35b96557	1378	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1379	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1380	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
Kojto	99:dbbf35b96557	1381	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
Kojto	99:dbbf35b96557	1382	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
Kojto	99:dbbf35b96557	1383	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
Kojto	99:dbbf35b96557	1384	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1385	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1386	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
Kojto	99:dbbf35b96557	1387	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
Kojto	99:dbbf35b96557	1388	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
Kojto	99:dbbf35b96557	1389	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
Kojto	99:dbbf35b96557	1390	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
Kojto	99:dbbf35b96557	1391	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
Kojto	99:dbbf35b96557	1392	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
Kojto	99:dbbf35b96557	1393	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
Kojto	99:dbbf35b96557	1394	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
Kojto	99:dbbf35b96557	1395	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
Kojto	99:dbbf35b96557	1396	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
Kojto	99:dbbf35b96557	1397	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
Kojto	99:dbbf35b96557	1398	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
Kojto	99:dbbf35b96557	1399	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
Kojto	99:dbbf35b96557	1400	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1401	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1402	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
Kojto	99:dbbf35b96557	1403	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
Kojto	99:dbbf35b96557	1404	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
Kojto	99:dbbf35b96557	1405	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
Kojto	99:dbbf35b96557	1406	#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
Kojto	99:dbbf35b96557	1407	#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
Kojto	99:dbbf35b96557	1408	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1409	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1410	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
Kojto	99:dbbf35b96557	1411	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
Kojto	99:dbbf35b96557	1412	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1413	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1414	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
Kojto	99:dbbf35b96557	1415	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
Kojto	99:dbbf35b96557	1416	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
Kojto	99:dbbf35b96557	1417	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
Kojto	99:dbbf35b96557	1418	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
Kojto	99:dbbf35b96557	1419	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
Kojto	99:dbbf35b96557	1420	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1421	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1422	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
Kojto	99:dbbf35b96557	1423	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
Kojto	99:dbbf35b96557	1424	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
Kojto	99:dbbf35b96557	1425	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
Kojto	99:dbbf35b96557	1426	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1427	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1428	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
Kojto	99:dbbf35b96557	1429	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
Kojto	99:dbbf35b96557	1430	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
Kojto	99:dbbf35b96557	1431	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
Kojto	99:dbbf35b96557	1432	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1433	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1434	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
Kojto	99:dbbf35b96557	1435	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
Kojto	99:dbbf35b96557	1436	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
Kojto	99:dbbf35b96557	1437	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
Kojto	99:dbbf35b96557	1438	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1439	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1440	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
Kojto	99:dbbf35b96557	1441	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
Kojto	99:dbbf35b96557	1442	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
Kojto	99:dbbf35b96557	1443	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
Kojto	99:dbbf35b96557	1444	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1445	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1446	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
Kojto	99:dbbf35b96557	1447	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
Kojto	99:dbbf35b96557	1448	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
Kojto	99:dbbf35b96557	1449	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
Kojto	99:dbbf35b96557	1450	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1451	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1452	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
Kojto	99:dbbf35b96557	1453	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
Kojto	99:dbbf35b96557	1454	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
Kojto	99:dbbf35b96557	1455	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
Kojto	99:dbbf35b96557	1456	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1457	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1458	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
Kojto	99:dbbf35b96557	1459	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
Kojto	99:dbbf35b96557	1460	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
Kojto	99:dbbf35b96557	1461	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
Kojto	99:dbbf35b96557	1462	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1463	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1464	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
Kojto	99:dbbf35b96557	1465	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
Kojto	99:dbbf35b96557	1466	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
Kojto	99:dbbf35b96557	1467	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
Kojto	99:dbbf35b96557	1468	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1469	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1470	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
Kojto	99:dbbf35b96557	1471	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
Kojto	99:dbbf35b96557	1472	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
Kojto	99:dbbf35b96557	1473	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
Kojto	99:dbbf35b96557	1474	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1475	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1476	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
Kojto	99:dbbf35b96557	1477	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
Kojto	99:dbbf35b96557	1478	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
Kojto	99:dbbf35b96557	1479	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
Kojto	99:dbbf35b96557	1480	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1481	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1482	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
Kojto	99:dbbf35b96557	1483	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
Kojto	99:dbbf35b96557	1484	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
Kojto	99:dbbf35b96557	1485	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
Kojto	99:dbbf35b96557	1486	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1487	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1488	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
Kojto	99:dbbf35b96557	1489	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
Kojto	99:dbbf35b96557	1490	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
Kojto	99:dbbf35b96557	1491	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
Kojto	99:dbbf35b96557	1492	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1493	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1494	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
Kojto	99:dbbf35b96557	1495	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
Kojto	99:dbbf35b96557	1496	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
Kojto	99:dbbf35b96557	1497	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
Kojto	99:dbbf35b96557	1498	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1499	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1500	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
Kojto	99:dbbf35b96557	1501	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
Kojto	99:dbbf35b96557	1502	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
Kojto	99:dbbf35b96557	1503	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
Kojto	99:dbbf35b96557	1504	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1505	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1506	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
Kojto	99:dbbf35b96557	1507	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
Kojto	99:dbbf35b96557	1508	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
Kojto	99:dbbf35b96557	1509	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
Kojto	99:dbbf35b96557	1510	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1511	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1512	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
Kojto	99:dbbf35b96557	1513	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
Kojto	99:dbbf35b96557	1514	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
Kojto	99:dbbf35b96557	1515	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
Kojto	99:dbbf35b96557	1516	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1517	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1518	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
Kojto	99:dbbf35b96557	1519	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
Kojto	99:dbbf35b96557	1520	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
Kojto	99:dbbf35b96557	1521	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
Kojto	99:dbbf35b96557	1522	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1523	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1524	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
Kojto	99:dbbf35b96557	1525	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
Kojto	99:dbbf35b96557	1526	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
Kojto	99:dbbf35b96557	1527	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
Kojto	99:dbbf35b96557	1528	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1529	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1530	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
Kojto	99:dbbf35b96557	1531	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
Kojto	99:dbbf35b96557	1532	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
Kojto	99:dbbf35b96557	1533	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
Kojto	99:dbbf35b96557	1534	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1535	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1536	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
Kojto	99:dbbf35b96557	1537	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
Kojto	99:dbbf35b96557	1538	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
Kojto	99:dbbf35b96557	1539	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
Kojto	99:dbbf35b96557	1540	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1541	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1542	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
Kojto	99:dbbf35b96557	1543	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
Kojto	99:dbbf35b96557	1544	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
Kojto	99:dbbf35b96557	1545	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
Kojto	99:dbbf35b96557	1546	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1547	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1548	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
Kojto	99:dbbf35b96557	1549	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
Kojto	99:dbbf35b96557	1550	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto	99:dbbf35b96557	1551	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto	99:dbbf35b96557	1552	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
Kojto	99:dbbf35b96557	1553	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
Kojto	99:dbbf35b96557	1554	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1555	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1556	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
Kojto	99:dbbf35b96557	1557	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
Kojto	99:dbbf35b96557	1558	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
Kojto	99:dbbf35b96557	1559	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
Kojto	99:dbbf35b96557	1560	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1561	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1562	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
Kojto	99:dbbf35b96557	1563	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
Kojto	99:dbbf35b96557	1564	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
Kojto	99:dbbf35b96557	1565	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
Kojto	99:dbbf35b96557	1566	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1567	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1568	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
Kojto	99:dbbf35b96557	1569	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
Kojto	99:dbbf35b96557	1570	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
Kojto	99:dbbf35b96557	1571	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
Kojto	99:dbbf35b96557	1572	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1573	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1574	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
Kojto	99:dbbf35b96557	1575	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
Kojto	99:dbbf35b96557	1576	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
Kojto	99:dbbf35b96557	1577	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
Kojto	99:dbbf35b96557	1578	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1579	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1580	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1581	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1582	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
Kojto	99:dbbf35b96557	1583	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
Kojto	99:dbbf35b96557	1584	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1585	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1586	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
Kojto	99:dbbf35b96557	1587	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
Kojto	99:dbbf35b96557	1588	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
Kojto	99:dbbf35b96557	1589	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
Kojto	99:dbbf35b96557	1590	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1591	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1592	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
Kojto	99:dbbf35b96557	1593	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
Kojto	99:dbbf35b96557	1594	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
Kojto	99:dbbf35b96557	1595	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
Kojto	99:dbbf35b96557	1596	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1597	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1598	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
Kojto	99:dbbf35b96557	1599	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
Kojto	99:dbbf35b96557	1600	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
Kojto	99:dbbf35b96557	1601	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
Kojto	99:dbbf35b96557	1602	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
Kojto	99:dbbf35b96557	1603	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
Kojto	99:dbbf35b96557	1604	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
Kojto	99:dbbf35b96557	1605	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
Kojto	99:dbbf35b96557	1606	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
Kojto	99:dbbf35b96557	1607	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
Kojto	99:dbbf35b96557	1608	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
Kojto	99:dbbf35b96557	1609	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
Kojto	99:dbbf35b96557	1610	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
Kojto	99:dbbf35b96557	1611	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
Kojto	99:dbbf35b96557	1612	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
Kojto	99:dbbf35b96557	1613	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
Kojto	99:dbbf35b96557	1614	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
Kojto	99:dbbf35b96557	1615	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
Kojto	99:dbbf35b96557	1616	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
Kojto	99:dbbf35b96557	1617	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
Kojto	99:dbbf35b96557	1618	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
Kojto	99:dbbf35b96557	1619	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
Kojto	99:dbbf35b96557	1620	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
Kojto	99:dbbf35b96557	1621	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
Kojto	99:dbbf35b96557	1622	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1623	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1624	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
Kojto	99:dbbf35b96557	1625	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
Kojto	99:dbbf35b96557	1626	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
Kojto	99:dbbf35b96557	1627	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
Kojto	99:dbbf35b96557	1628	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1629	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1630	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
Kojto	99:dbbf35b96557	1631	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
Kojto	99:dbbf35b96557	1632	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
Kojto	99:dbbf35b96557	1633	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
Kojto	99:dbbf35b96557	1634	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1635	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1636	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
Kojto	99:dbbf35b96557	1637	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
Kojto	99:dbbf35b96557	1638	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
Kojto	99:dbbf35b96557	1639	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
Kojto	99:dbbf35b96557	1640	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1641	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1642	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
Kojto	99:dbbf35b96557	1643	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
Kojto	99:dbbf35b96557	1644	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
Kojto	99:dbbf35b96557	1645	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
Kojto	99:dbbf35b96557	1646	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1647	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1648	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
Kojto	99:dbbf35b96557	1649	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
Kojto	99:dbbf35b96557	1650	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
Kojto	99:dbbf35b96557	1651	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
Kojto	99:dbbf35b96557	1652	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1653	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1654	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
Kojto	99:dbbf35b96557	1655	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
Kojto	99:dbbf35b96557	1656	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
Kojto	99:dbbf35b96557	1657	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
Kojto	99:dbbf35b96557	1658	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1659	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1660	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
Kojto	99:dbbf35b96557	1661	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
Kojto	99:dbbf35b96557	1662	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
Kojto	99:dbbf35b96557	1663	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
Kojto	99:dbbf35b96557	1664	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1665	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1666	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
Kojto	99:dbbf35b96557	1667	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
Kojto	99:dbbf35b96557	1668	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
Kojto	99:dbbf35b96557	1669	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
Kojto	99:dbbf35b96557	1670	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1671	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1672	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
Kojto	99:dbbf35b96557	1673	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
Kojto	99:dbbf35b96557	1674	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
Kojto	99:dbbf35b96557	1675	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
Kojto	99:dbbf35b96557	1676	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1677	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1678	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
Kojto	99:dbbf35b96557	1679	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
Kojto	99:dbbf35b96557	1680	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
Kojto	99:dbbf35b96557	1681	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
Kojto	99:dbbf35b96557	1682	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
Kojto	99:dbbf35b96557	1683	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
Kojto	99:dbbf35b96557	1684	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
Kojto	99:dbbf35b96557	1685	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
Kojto	99:dbbf35b96557	1686	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1687	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1688	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
Kojto	99:dbbf35b96557	1689	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
Kojto	99:dbbf35b96557	1690	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
Kojto	99:dbbf35b96557	1691	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
Kojto	99:dbbf35b96557	1692	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1693	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1694	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
Kojto	99:dbbf35b96557	1695	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
Kojto	99:dbbf35b96557	1696	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
Kojto	99:dbbf35b96557	1697	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
Kojto	99:dbbf35b96557	1698	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1699	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1700	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
Kojto	99:dbbf35b96557	1701	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
Kojto	99:dbbf35b96557	1702	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
Kojto	99:dbbf35b96557	1703	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
Kojto	99:dbbf35b96557	1704	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1705	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1706	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
Kojto	99:dbbf35b96557	1707	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
Kojto	99:dbbf35b96557	1708	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
Kojto	99:dbbf35b96557	1709	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
Kojto	99:dbbf35b96557	1710	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1711	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1712	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
Kojto	99:dbbf35b96557	1713	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
Kojto	99:dbbf35b96557	1714	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
Kojto	99:dbbf35b96557	1715	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
Kojto	99:dbbf35b96557	1716	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1717	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1718	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
Kojto	99:dbbf35b96557	1719	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
Kojto	99:dbbf35b96557	1720	#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
Kojto	99:dbbf35b96557	1721	#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
Kojto	99:dbbf35b96557	1722	#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1723	#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1724	#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
Kojto	99:dbbf35b96557	1725	#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
Kojto	99:dbbf35b96557	1726	#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
Kojto	99:dbbf35b96557	1727	#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
Kojto	99:dbbf35b96557	1728	#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1729	#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1730	#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
Kojto	99:dbbf35b96557	1731	#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
Kojto	99:dbbf35b96557	1732	#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
Kojto	99:dbbf35b96557	1733	#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
Kojto	99:dbbf35b96557	1734	#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
Kojto	99:dbbf35b96557	1735	#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
Kojto	99:dbbf35b96557	1736	#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
Kojto	99:dbbf35b96557	1737	#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
Kojto	99:dbbf35b96557	1738	#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
Kojto	99:dbbf35b96557	1739	#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
Kojto	99:dbbf35b96557	1740	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
Kojto	99:dbbf35b96557	1741	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
Kojto	99:dbbf35b96557	1742	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
Kojto	99:dbbf35b96557	1743	#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1744	#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1745	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
Kojto	99:dbbf35b96557	1746	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
Kojto	99:dbbf35b96557	1747	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
Kojto	99:dbbf35b96557	1748	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
Kojto	99:dbbf35b96557	1749	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
Kojto	99:dbbf35b96557	1750	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1751	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1752	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
Kojto	99:dbbf35b96557	1753	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
Kojto	99:dbbf35b96557	1754	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
Kojto	99:dbbf35b96557	1755	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
Kojto	99:dbbf35b96557	1756	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
Kojto	99:dbbf35b96557	1757	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
Kojto	99:dbbf35b96557	1758	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1759	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1760	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
Kojto	99:dbbf35b96557	1761	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
Kojto	99:dbbf35b96557	1762	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
Kojto	99:dbbf35b96557	1763	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
Kojto	99:dbbf35b96557	1764	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1765	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1766	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
Kojto	99:dbbf35b96557	1767	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
Kojto	99:dbbf35b96557	1768	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1769	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1770	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
Kojto	99:dbbf35b96557	1771	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
Kojto	99:dbbf35b96557	1772	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
Kojto	99:dbbf35b96557	1773	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
Kojto	99:dbbf35b96557	1774
Kojto	99:dbbf35b96557	1775	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto	99:dbbf35b96557	1776	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto	99:dbbf35b96557	1777	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1778	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1779	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
Kojto	99:dbbf35b96557	1780	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
Kojto	99:dbbf35b96557	1781	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
Kojto	99:dbbf35b96557	1782	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
Kojto	99:dbbf35b96557	1783	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1784	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1785	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1786	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1787	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1788	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1789	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1790	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1791	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
Kojto	99:dbbf35b96557	1792	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
Kojto	99:dbbf35b96557	1793	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
Kojto	99:dbbf35b96557	1794	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
Kojto	99:dbbf35b96557	1795	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
Kojto	99:dbbf35b96557	1796	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1797	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1798	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
Kojto	99:dbbf35b96557	1799	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
Kojto	99:dbbf35b96557	1800	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
Kojto	99:dbbf35b96557	1801	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
Kojto	99:dbbf35b96557	1802	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
Kojto	99:dbbf35b96557	1803	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1804	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1805	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
Kojto	99:dbbf35b96557	1806	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
Kojto	99:dbbf35b96557	1807	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
Kojto	99:dbbf35b96557	1808	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
Kojto	99:dbbf35b96557	1809	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1810	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1811	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
Kojto	99:dbbf35b96557	1812	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
Kojto	99:dbbf35b96557	1813	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
Kojto	99:dbbf35b96557	1814	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
Kojto	99:dbbf35b96557	1815	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1816	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1817	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1818	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1819	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1820	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1821	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1822	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1823	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1824	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1825	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1826	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1827	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1828	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
Kojto	99:dbbf35b96557	1829	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
Kojto	99:dbbf35b96557	1830	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1831	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1832	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
Kojto	99:dbbf35b96557	1833	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
Kojto	99:dbbf35b96557	1834	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
Kojto	99:dbbf35b96557	1835	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
Kojto	99:dbbf35b96557	1836	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
Kojto	99:dbbf35b96557	1837	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
Kojto	99:dbbf35b96557	1838	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1839	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1840	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
Kojto	99:dbbf35b96557	1841	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
Kojto	99:dbbf35b96557	1842	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
Kojto	99:dbbf35b96557	1843	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
Kojto	99:dbbf35b96557	1844	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1845	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1846	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
Kojto	99:dbbf35b96557	1847	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
Kojto	99:dbbf35b96557	1848	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
Kojto	99:dbbf35b96557	1849	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
Kojto	99:dbbf35b96557	1850	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1851	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1852	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
Kojto	99:dbbf35b96557	1853	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
Kojto	99:dbbf35b96557	1854	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
Kojto	99:dbbf35b96557	1855	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
Kojto	99:dbbf35b96557	1856	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1857	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1858	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
Kojto	99:dbbf35b96557	1859	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
Kojto	99:dbbf35b96557	1860	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
Kojto	99:dbbf35b96557	1861	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1862	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1863	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
Kojto	99:dbbf35b96557	1864	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
Kojto	99:dbbf35b96557	1865	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
Kojto	99:dbbf35b96557	1866	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
Kojto	99:dbbf35b96557	1867	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
Kojto	99:dbbf35b96557	1868	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
Kojto	99:dbbf35b96557	1869	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1870	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1871	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
Kojto	99:dbbf35b96557	1872	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
Kojto	99:dbbf35b96557	1873	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
Kojto	99:dbbf35b96557	1874	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
Kojto	99:dbbf35b96557	1875	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1876	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1877	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
Kojto	99:dbbf35b96557	1878	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
Kojto	99:dbbf35b96557	1879	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
Kojto	99:dbbf35b96557	1880	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
Kojto	99:dbbf35b96557	1881	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1882	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1883	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1884	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1885	#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto	99:dbbf35b96557	1886	#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto	99:dbbf35b96557	1887	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1888	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1889	#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1890	#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1891	#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto	99:dbbf35b96557	1892	#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto	99:dbbf35b96557	1893	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1894	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1895	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto	99:dbbf35b96557	1896	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1897	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1898	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1899	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1900	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1901	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1902	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1903	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1904	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1905	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
Kojto	99:dbbf35b96557	1906	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
Kojto	99:dbbf35b96557	1907	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1908	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1909	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto	99:dbbf35b96557	1910	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto	99:dbbf35b96557	1911	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1912	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1913	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
Kojto	99:dbbf35b96557	1914	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
Kojto	99:dbbf35b96557	1915	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
Kojto	99:dbbf35b96557	1916	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
Kojto	99:dbbf35b96557	1917	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
Kojto	99:dbbf35b96557	1918	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
Kojto	99:dbbf35b96557	1919
Kojto	99:dbbf35b96557	1920	/* alias define maintained for legacy */
Kojto	99:dbbf35b96557	1921	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto	99:dbbf35b96557	1922	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto	99:dbbf35b96557	1923
Kojto	99:dbbf35b96557	1924	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
Kojto	99:dbbf35b96557	1925	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
Kojto	99:dbbf35b96557	1926
Kojto	99:dbbf35b96557	1927	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
Kojto	99:dbbf35b96557	1928
Kojto	99:dbbf35b96557	1929	#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
Kojto	99:dbbf35b96557	1930	#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
Kojto	99:dbbf35b96557	1931	#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
Kojto	99:dbbf35b96557	1932	#define IS_RCC_HCLK_DIV IS_RCC_PCLK
Kojto	99:dbbf35b96557	1933
Kojto	99:dbbf35b96557	1934	#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
Kojto	99:dbbf35b96557	1935	#define RCC_MCO_NODIV RCC_MCODIV_1
Kojto	99:dbbf35b96557	1936	#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
Kojto	99:dbbf35b96557	1937
Kojto	99:dbbf35b96557	1938	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
Kojto	99:dbbf35b96557	1939	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
Kojto	99:dbbf35b96557	1940	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
Kojto	99:dbbf35b96557	1941	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
Kojto	99:dbbf35b96557	1942	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
Kojto	99:dbbf35b96557	1943	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
Kojto	99:dbbf35b96557	1944	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
Kojto	99:dbbf35b96557	1945	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
Kojto	99:dbbf35b96557	1946	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
Kojto	99:dbbf35b96557	1947	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
Kojto	99:dbbf35b96557	1948
Kojto	99:dbbf35b96557	1949	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
Kojto	99:dbbf35b96557	1950	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
Kojto	99:dbbf35b96557	1951	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
Kojto	99:dbbf35b96557	1952	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
Kojto	99:dbbf35b96557	1953	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
Kojto	99:dbbf35b96557	1954	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
Kojto	99:dbbf35b96557	1955
Kojto	99:dbbf35b96557	1956	#define CR_HSION_BB RCC_CR_HSION_BB
Kojto	99:dbbf35b96557	1957	#define CR_CSSON_BB RCC_CR_CSSON_BB
Kojto	99:dbbf35b96557	1958	#define CR_PLLON_BB RCC_CR_PLLON_BB
Kojto	99:dbbf35b96557	1959	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
Kojto	99:dbbf35b96557	1960	#define CR_MSION_BB RCC_CR_MSION_BB
Kojto	99:dbbf35b96557	1961	#define CSR_LSION_BB RCC_CSR_LSION_BB
Kojto	99:dbbf35b96557	1962	#define CSR_LSEON_BB RCC_CSR_LSEON_BB
Kojto	99:dbbf35b96557	1963	#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
Kojto	99:dbbf35b96557	1964	#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
Kojto	99:dbbf35b96557	1965	#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
Kojto	99:dbbf35b96557	1966	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
Kojto	99:dbbf35b96557	1967	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
Kojto	99:dbbf35b96557	1968	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
Kojto	99:dbbf35b96557	1969	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
Kojto	99:dbbf35b96557	1970	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
Kojto	99:dbbf35b96557	1971
Kojto	99:dbbf35b96557	1972	/**
Kojto	99:dbbf35b96557	1973	* @}
Kojto	99:dbbf35b96557	1974	*/
Kojto	99:dbbf35b96557	1975
Kojto	99:dbbf35b96557	1976	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1977	* @{
Kojto	99:dbbf35b96557	1978	*/
Kojto	99:dbbf35b96557	1979	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
Kojto	99:dbbf35b96557	1980
Kojto	99:dbbf35b96557	1981	/**
Kojto	99:dbbf35b96557	1982	* @}
Kojto	99:dbbf35b96557	1983	*/
Kojto	99:dbbf35b96557	1984
Kojto	99:dbbf35b96557	1985	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	1986	* @{
Kojto	99:dbbf35b96557	1987	*/
Kojto	99:dbbf35b96557	1988
Kojto	99:dbbf35b96557	1989	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
Kojto	99:dbbf35b96557	1990	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
Kojto	99:dbbf35b96557	1991	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
Kojto	99:dbbf35b96557	1992	#if defined (STM32F1)
Kojto	99:dbbf35b96557	1993	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
Kojto	99:dbbf35b96557	1994
Kojto	99:dbbf35b96557	1995	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
Kojto	99:dbbf35b96557	1996
Kojto	99:dbbf35b96557	1997	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
Kojto	99:dbbf35b96557	1998
Kojto	99:dbbf35b96557	1999	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
Kojto	99:dbbf35b96557	2000
Kojto	99:dbbf35b96557	2001	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
Kojto	99:dbbf35b96557	2002	#else
Kojto	99:dbbf35b96557	2003	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
Kojto	99:dbbf35b96557	2004	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
Kojto	99:dbbf35b96557	2005	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
Kojto	99:dbbf35b96557	2006	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
Kojto	99:dbbf35b96557	2007	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
Kojto	99:dbbf35b96557	2008	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
Kojto	99:dbbf35b96557	2009	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
Kojto	99:dbbf35b96557	2010	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
Kojto	99:dbbf35b96557	2011	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
Kojto	99:dbbf35b96557	2012	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
Kojto	99:dbbf35b96557	2013	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
Kojto	99:dbbf35b96557	2014	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
Kojto	99:dbbf35b96557	2015	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
Kojto	99:dbbf35b96557	2016	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
Kojto	99:dbbf35b96557	2017	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
Kojto	99:dbbf35b96557	2018	#endif /* STM32F1 */
Kojto	99:dbbf35b96557	2019
Kojto	99:dbbf35b96557	2020	#define IS_ALARM IS_RTC_ALARM
Kojto	99:dbbf35b96557	2021	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
Kojto	99:dbbf35b96557	2022	#define IS_TAMPER IS_RTC_TAMPER
Kojto	99:dbbf35b96557	2023	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
Kojto	99:dbbf35b96557	2024	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
Kojto	99:dbbf35b96557	2025	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
Kojto	99:dbbf35b96557	2026	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
Kojto	99:dbbf35b96557	2027	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
Kojto	99:dbbf35b96557	2028	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
Kojto	99:dbbf35b96557	2029	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
Kojto	99:dbbf35b96557	2030	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
Kojto	99:dbbf35b96557	2031	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
Kojto	99:dbbf35b96557	2032	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
Kojto	99:dbbf35b96557	2033	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
Kojto	99:dbbf35b96557	2034
Kojto	99:dbbf35b96557	2035	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
Kojto	99:dbbf35b96557	2036	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
Kojto	99:dbbf35b96557	2037
Kojto	99:dbbf35b96557	2038	/**
Kojto	99:dbbf35b96557	2039	* @}
Kojto	99:dbbf35b96557	2040	*/
Kojto	99:dbbf35b96557	2041
Kojto	99:dbbf35b96557	2042	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2043	* @{
Kojto	99:dbbf35b96557	2044	*/
Kojto	99:dbbf35b96557	2045
Kojto	99:dbbf35b96557	2046	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
Kojto	99:dbbf35b96557	2047	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
Kojto	99:dbbf35b96557	2048
Kojto	99:dbbf35b96557	2049	/**
Kojto	99:dbbf35b96557	2050	* @}
Kojto	99:dbbf35b96557	2051	*/
Kojto	99:dbbf35b96557	2052
Kojto	99:dbbf35b96557	2053	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2054	* @{
Kojto	99:dbbf35b96557	2055	*/
Kojto	99:dbbf35b96557	2056
Kojto	99:dbbf35b96557	2057	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
Kojto	99:dbbf35b96557	2058	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
Kojto	99:dbbf35b96557	2059	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
Kojto	99:dbbf35b96557	2060	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
Kojto	99:dbbf35b96557	2061	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
Kojto	99:dbbf35b96557	2062	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
Kojto	99:dbbf35b96557	2063
Kojto	99:dbbf35b96557	2064	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto	99:dbbf35b96557	2065	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto	99:dbbf35b96557	2066
Kojto	99:dbbf35b96557	2067	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
Kojto	99:dbbf35b96557	2068
Kojto	99:dbbf35b96557	2069	#define SMARTCARD_WORDLENGTH_8B ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	2070	#define SMARTCARD_STOPBITS_1 ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	2071	#define SMARTCARD_STOPBITS_2 ((uint32_t)USART_CR2_STOP_1)
Kojto	99:dbbf35b96557	2072	#define SMARTCARD_PARITY_NONE ((uint32_t)0x00000000)
Kojto	99:dbbf35b96557	2073
Kojto	99:dbbf35b96557	2074
Kojto	99:dbbf35b96557	2075	/**
Kojto	99:dbbf35b96557	2076	* @}
Kojto	99:dbbf35b96557	2077	*/
Kojto	99:dbbf35b96557	2078
Kojto	99:dbbf35b96557	2079	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2080	* @{
Kojto	99:dbbf35b96557	2081	*/
Kojto	99:dbbf35b96557	2082	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
Kojto	99:dbbf35b96557	2083	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
Kojto	99:dbbf35b96557	2084	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
Kojto	99:dbbf35b96557	2085	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
Kojto	99:dbbf35b96557	2086	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
Kojto	99:dbbf35b96557	2087	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
Kojto	99:dbbf35b96557	2088	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
Kojto	99:dbbf35b96557	2089	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
Kojto	99:dbbf35b96557	2090	/**
Kojto	99:dbbf35b96557	2091	* @}
Kojto	99:dbbf35b96557	2092	*/
Kojto	99:dbbf35b96557	2093
Kojto	99:dbbf35b96557	2094	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2095	* @{
Kojto	99:dbbf35b96557	2096	*/
Kojto	99:dbbf35b96557	2097
Kojto	99:dbbf35b96557	2098	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
Kojto	99:dbbf35b96557	2099	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
Kojto	99:dbbf35b96557	2100	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
Kojto	99:dbbf35b96557	2101
Kojto	99:dbbf35b96557	2102	/**
Kojto	99:dbbf35b96557	2103	* @}
Kojto	99:dbbf35b96557	2104	*/
Kojto	99:dbbf35b96557	2105
Kojto	99:dbbf35b96557	2106	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2107	* @{
Kojto	99:dbbf35b96557	2108	*/
Kojto	99:dbbf35b96557	2109
Kojto	99:dbbf35b96557	2110	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto	99:dbbf35b96557	2111	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto	99:dbbf35b96557	2112	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto	99:dbbf35b96557	2113	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto	99:dbbf35b96557	2114
Kojto	99:dbbf35b96557	2115	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
Kojto	99:dbbf35b96557	2116
Kojto	99:dbbf35b96557	2117	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
Kojto	99:dbbf35b96557	2118	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
Kojto	99:dbbf35b96557	2119
Kojto	99:dbbf35b96557	2120	/**
Kojto	99:dbbf35b96557	2121	* @}
Kojto	99:dbbf35b96557	2122	*/
Kojto	99:dbbf35b96557	2123
Kojto	99:dbbf35b96557	2124
Kojto	99:dbbf35b96557	2125	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2126	* @{
Kojto	99:dbbf35b96557	2127	*/
Kojto	99:dbbf35b96557	2128
Kojto	99:dbbf35b96557	2129	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
Kojto	99:dbbf35b96557	2130	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
Kojto	99:dbbf35b96557	2131	#define __USART_ENABLE __HAL_USART_ENABLE
Kojto	99:dbbf35b96557	2132	#define __USART_DISABLE __HAL_USART_DISABLE
Kojto	99:dbbf35b96557	2133
Kojto	99:dbbf35b96557	2134	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto	99:dbbf35b96557	2135	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto	99:dbbf35b96557	2136
Kojto	99:dbbf35b96557	2137	/**
Kojto	99:dbbf35b96557	2138	* @}
Kojto	99:dbbf35b96557	2139	*/
Kojto	99:dbbf35b96557	2140
Kojto	99:dbbf35b96557	2141	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2142	* @{
Kojto	99:dbbf35b96557	2143	*/
Kojto	99:dbbf35b96557	2144	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
Kojto	99:dbbf35b96557	2145
Kojto	99:dbbf35b96557	2146	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
Kojto	99:dbbf35b96557	2147	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
Kojto	99:dbbf35b96557	2148	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto	99:dbbf35b96557	2149	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
Kojto	99:dbbf35b96557	2150
Kojto	99:dbbf35b96557	2151	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
Kojto	99:dbbf35b96557	2152	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
Kojto	99:dbbf35b96557	2153	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto	99:dbbf35b96557	2154	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
Kojto	99:dbbf35b96557	2155
Kojto	99:dbbf35b96557	2156	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
Kojto	99:dbbf35b96557	2157	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
Kojto	99:dbbf35b96557	2158	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
Kojto	99:dbbf35b96557	2159	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
Kojto	99:dbbf35b96557	2160	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto	99:dbbf35b96557	2161	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto	99:dbbf35b96557	2162	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto	99:dbbf35b96557	2163
Kojto	99:dbbf35b96557	2164	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
Kojto	99:dbbf35b96557	2165	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
Kojto	99:dbbf35b96557	2166	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
Kojto	99:dbbf35b96557	2167	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
Kojto	99:dbbf35b96557	2168	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto	99:dbbf35b96557	2169	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto	99:dbbf35b96557	2170	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto	99:dbbf35b96557	2171	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
Kojto	99:dbbf35b96557	2172
Kojto	99:dbbf35b96557	2173	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
Kojto	99:dbbf35b96557	2174	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
Kojto	99:dbbf35b96557	2175	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
Kojto	99:dbbf35b96557	2176	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
Kojto	99:dbbf35b96557	2177	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto	99:dbbf35b96557	2178	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto	99:dbbf35b96557	2179	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto	99:dbbf35b96557	2180	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
Kojto	99:dbbf35b96557	2181
Kojto	99:dbbf35b96557	2182	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
Kojto	99:dbbf35b96557	2183	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
Kojto	99:dbbf35b96557	2184
Kojto	99:dbbf35b96557	2185	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
Kojto	99:dbbf35b96557	2186	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
Kojto	99:dbbf35b96557	2187	/**
Kojto	99:dbbf35b96557	2188	* @}
Kojto	99:dbbf35b96557	2189	*/
Kojto	99:dbbf35b96557	2190
Kojto	99:dbbf35b96557	2191	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2192	* @{
Kojto	99:dbbf35b96557	2193	*/
Kojto	99:dbbf35b96557	2194	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
Kojto	99:dbbf35b96557	2195	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
Kojto	99:dbbf35b96557	2196
Kojto	99:dbbf35b96557	2197	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto	99:dbbf35b96557	2198	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
Kojto	99:dbbf35b96557	2199
Kojto	99:dbbf35b96557	2200	#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto	99:dbbf35b96557	2201
Kojto	99:dbbf35b96557	2202	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
Kojto	99:dbbf35b96557	2203	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
Kojto	99:dbbf35b96557	2204	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
Kojto	99:dbbf35b96557	2205	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
Kojto	99:dbbf35b96557	2206	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
Kojto	99:dbbf35b96557	2207	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
Kojto	99:dbbf35b96557	2208	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
Kojto	99:dbbf35b96557	2209	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
Kojto	99:dbbf35b96557	2210	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
Kojto	99:dbbf35b96557	2211	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
Kojto	99:dbbf35b96557	2212	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
Kojto	99:dbbf35b96557	2213	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
Kojto	99:dbbf35b96557	2214
Kojto	99:dbbf35b96557	2215	#define TIM_TS_ITR0 ((uint32_t)0x0000)
Kojto	99:dbbf35b96557	2216	#define TIM_TS_ITR1 ((uint32_t)0x0010)
Kojto	99:dbbf35b96557	2217	#define TIM_TS_ITR2 ((uint32_t)0x0020)
Kojto	99:dbbf35b96557	2218	#define TIM_TS_ITR3 ((uint32_t)0x0030)
Kojto	99:dbbf35b96557	2219	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
Kojto	99:dbbf35b96557	2220	((SELECTION) == TIM_TS_ITR1) \|\| \
Kojto	99:dbbf35b96557	2221	((SELECTION) == TIM_TS_ITR2) \|\| \
Kojto	99:dbbf35b96557	2222	((SELECTION) == TIM_TS_ITR3))
Kojto	99:dbbf35b96557	2223
Kojto	99:dbbf35b96557	2224	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
Kojto	99:dbbf35b96557	2225	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
Kojto	99:dbbf35b96557	2226	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
Kojto	99:dbbf35b96557	2227	((CHANNEL) == TIM_CHANNEL_2))
Kojto	99:dbbf35b96557	2228
Kojto	99:dbbf35b96557	2229	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
Kojto	99:dbbf35b96557	2230	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
Kojto	99:dbbf35b96557	2231
Kojto	99:dbbf35b96557	2232	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	2233	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
Kojto	99:dbbf35b96557	2234
Kojto	99:dbbf35b96557	2235	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
Kojto	99:dbbf35b96557	2236	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
Kojto	99:dbbf35b96557	2237
Kojto	99:dbbf35b96557	2238	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	2239	((STATE) == TIM_OUTPUTSTATE_ENABLE))
Kojto	99:dbbf35b96557	2240	/**
Kojto	99:dbbf35b96557	2241	* @}
Kojto	99:dbbf35b96557	2242	*/
Kojto	99:dbbf35b96557	2243
Kojto	99:dbbf35b96557	2244	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2245	* @{
Kojto	99:dbbf35b96557	2246	*/
Kojto	99:dbbf35b96557	2247
Kojto	99:dbbf35b96557	2248	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
Kojto	99:dbbf35b96557	2249	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
Kojto	99:dbbf35b96557	2250	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
Kojto	99:dbbf35b96557	2251	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
Kojto	99:dbbf35b96557	2252	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
Kojto	99:dbbf35b96557	2253	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
Kojto	99:dbbf35b96557	2254	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
Kojto	99:dbbf35b96557	2255
Kojto	99:dbbf35b96557	2256	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
Kojto	99:dbbf35b96557	2257	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
Kojto	99:dbbf35b96557	2258	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
Kojto	99:dbbf35b96557	2259	/**
Kojto	99:dbbf35b96557	2260	* @}
Kojto	99:dbbf35b96557	2261	*/
Kojto	99:dbbf35b96557	2262
Kojto	99:dbbf35b96557	2263	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2264	* @{
Kojto	99:dbbf35b96557	2265	*/
Kojto	99:dbbf35b96557	2266	#define __HAL_LTDC_LAYER LTDC_LAYER
Kojto	99:dbbf35b96557	2267	/**
Kojto	99:dbbf35b96557	2268	* @}
Kojto	99:dbbf35b96557	2269	*/
Kojto	99:dbbf35b96557	2270
Kojto	99:dbbf35b96557	2271	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2272	* @{
Kojto	99:dbbf35b96557	2273	*/
Kojto	99:dbbf35b96557	2274	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
Kojto	99:dbbf35b96557	2275	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
Kojto	99:dbbf35b96557	2276	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
Kojto	99:dbbf35b96557	2277	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
Kojto	99:dbbf35b96557	2278	#define SAI_STREOMODE SAI_STEREOMODE
Kojto	99:dbbf35b96557	2279	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
Kojto	99:dbbf35b96557	2280	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
Kojto	99:dbbf35b96557	2281	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
Kojto	99:dbbf35b96557	2282	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
Kojto	99:dbbf35b96557	2283	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
Kojto	99:dbbf35b96557	2284	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
Kojto	99:dbbf35b96557	2285	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
Kojto	99:dbbf35b96557	2286
Kojto	99:dbbf35b96557	2287	/**
Kojto	99:dbbf35b96557	2288	* @}
Kojto	99:dbbf35b96557	2289	*/
Kojto	99:dbbf35b96557	2290
Kojto	99:dbbf35b96557	2291
Kojto	99:dbbf35b96557	2292	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
Kojto	99:dbbf35b96557	2293	* @{
Kojto	99:dbbf35b96557	2294	*/
Kojto	99:dbbf35b96557	2295
Kojto	99:dbbf35b96557	2296	/**
Kojto	99:dbbf35b96557	2297	* @}
Kojto	99:dbbf35b96557	2298	*/
Kojto	99:dbbf35b96557	2299
Kojto	99:dbbf35b96557	2300	#ifdef __cplusplus
Kojto	99:dbbf35b96557	2301	}
Kojto	99:dbbf35b96557	2302	#endif
Kojto	99:dbbf35b96557	2303
Kojto	99:dbbf35b96557	2304	#endif /* ___STM32_HAL_LEGACY */
Kojto	99:dbbf35b96557	2305
Kojto	99:dbbf35b96557	2306	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
Kojto	99:dbbf35b96557	2307

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Type:	Library
Created:	04 Apr 2016
Imports:	4
Forks:	0
Commits:	122
Dependents:	4
Dependencies:	0
Followers:	1

The code in this repository is Apache licensed.

TARGET_NUCLEO_F401RE/stm32_hal_legacy.h@99:dbbf35b96557, 2015-05-13 (annotated)

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