Elijah Orr / mbed-renbed

Fork of the official mbed C/C SDK provides the software platform and libraries to build your applications for RenBED.

Dependents:   1-RenBuggyTimed RenBED_RGB RenBED_RGB_PWM RenBED_RGB

Fork of mbed by mbed official

TARGET_NUCLEO_F401RE/stm32_hal_legacy.h@106:ba1f97679dad, 2015-09-02 (annotated)

Committer:
Kojto
Date:
Wed Sep 02 14:17:43 2015 +0100
Revision:
106:ba1f97679dad
Parent:
99:dbbf35b96557
Child:
110:165afa46840b
Release 106  of the mbed library



Changes:

- new platform - Nucleo F446RE

- STM32F4 Cube driver update v2.3.2

- ST cmsis driver v2.3.2

- nordic bugfix gcc linker start address

- lpc11u68 - bugfix for serial ports

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /**
Kojto 99:dbbf35b96557 2 ******************************************************************************
Kojto 99:dbbf35b96557 3 * @file stm32_hal_legacy.h
Kojto 99:dbbf35b96557 4 * @author MCD Application Team
Kojto 106:ba1f97679dad 5 * @version V1.3.2
Kojto 106:ba1f97679dad 6 * @date 26-June-2015
Kojto 99:dbbf35b96557 7 * @brief This file contains aliases definition for the STM32Cube HAL constants
Kojto 99:dbbf35b96557 8 * macros and functions maintained for legacy purpose.
Kojto 99:dbbf35b96557 9 ******************************************************************************
Kojto 99:dbbf35b96557 10 * @attention
Kojto 99:dbbf35b96557 11 *
Kojto 99:dbbf35b96557 12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 99:dbbf35b96557 13 *
Kojto 99:dbbf35b96557 14 * Redistribution and use in source and binary forms, with or without modification,
Kojto 99:dbbf35b96557 15 * are permitted provided that the following conditions are met:
Kojto 99:dbbf35b96557 16 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 99:dbbf35b96557 17 * this list of conditions and the following disclaimer.
Kojto 99:dbbf35b96557 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 99:dbbf35b96557 19 * this list of conditions and the following disclaimer in the documentation
Kojto 99:dbbf35b96557 20 * and/or other materials provided with the distribution.
Kojto 99:dbbf35b96557 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 99:dbbf35b96557 22 * may be used to endorse or promote products derived from this software
Kojto 99:dbbf35b96557 23 * without specific prior written permission.
Kojto 99:dbbf35b96557 24 *
Kojto 99:dbbf35b96557 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 99:dbbf35b96557 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 99:dbbf35b96557 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 99:dbbf35b96557 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 99:dbbf35b96557 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 99:dbbf35b96557 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 99:dbbf35b96557 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 99:dbbf35b96557 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 106:ba1f97679dad 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 99:dbbf35b96557 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 99:dbbf35b96557 35 *
Kojto 99:dbbf35b96557 36 ******************************************************************************
Kojto 99:dbbf35b96557 37 */
Kojto 99:dbbf35b96557 38
Kojto 99:dbbf35b96557 39 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 99:dbbf35b96557 40 #ifndef __STM32_HAL_LEGACY
Kojto 99:dbbf35b96557 41 #define __STM32_HAL_LEGACY
Kojto 99:dbbf35b96557 42
Kojto 99:dbbf35b96557 43 #ifdef __cplusplus
Kojto 99:dbbf35b96557 44 extern "C" {
Kojto 99:dbbf35b96557 45 #endif
Kojto 99:dbbf35b96557 46
Kojto 99:dbbf35b96557 47 /* Includes ------------------------------------------------------------------*/
Kojto 99:dbbf35b96557 48 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 49 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 50
Kojto 99:dbbf35b96557 51 /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 52 * @{
Kojto 99:dbbf35b96557 53 */
Kojto 106:ba1f97679dad 54 #define AES_FLAG_RDERR CRYP_FLAG_RDERR
Kojto 106:ba1f97679dad 55 #define AES_FLAG_WRERR CRYP_FLAG_WRERR
Kojto 99:dbbf35b96557 56 #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
Kojto 99:dbbf35b96557 57 #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
Kojto 99:dbbf35b96557 58 #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
Kojto 99:dbbf35b96557 59
Kojto 99:dbbf35b96557 60 /**
Kojto 99:dbbf35b96557 61 * @}
Kojto 99:dbbf35b96557 62 */
Kojto 99:dbbf35b96557 63
Kojto 99:dbbf35b96557 64 /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 65 * @{
Kojto 99:dbbf35b96557 66 */
Kojto 99:dbbf35b96557 67 #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
Kojto 99:dbbf35b96557 68 #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
Kojto 99:dbbf35b96557 69 #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
Kojto 99:dbbf35b96557 70 #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
Kojto 99:dbbf35b96557 71 #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
Kojto 99:dbbf35b96557 72 #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
Kojto 99:dbbf35b96557 73 #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
Kojto 99:dbbf35b96557 74 #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
Kojto 99:dbbf35b96557 75 #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
Kojto 99:dbbf35b96557 76 #define REGULAR_GROUP ADC_REGULAR_GROUP
Kojto 99:dbbf35b96557 77 #define INJECTED_GROUP ADC_INJECTED_GROUP
Kojto 99:dbbf35b96557 78 #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
Kojto 99:dbbf35b96557 79 #define AWD_EVENT ADC_AWD_EVENT
Kojto 99:dbbf35b96557 80 #define AWD1_EVENT ADC_AWD1_EVENT
Kojto 99:dbbf35b96557 81 #define AWD2_EVENT ADC_AWD2_EVENT
Kojto 99:dbbf35b96557 82 #define AWD3_EVENT ADC_AWD3_EVENT
Kojto 99:dbbf35b96557 83 #define OVR_EVENT ADC_OVR_EVENT
Kojto 99:dbbf35b96557 84 #define JQOVF_EVENT ADC_JQOVF_EVENT
Kojto 99:dbbf35b96557 85 #define ALL_CHANNELS ADC_ALL_CHANNELS
Kojto 99:dbbf35b96557 86 #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
Kojto 99:dbbf35b96557 87 #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
Kojto 99:dbbf35b96557 88 #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
Kojto 99:dbbf35b96557 89 #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
Kojto 99:dbbf35b96557 90 #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
Kojto 99:dbbf35b96557 91 #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
Kojto 99:dbbf35b96557 92 #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
Kojto 99:dbbf35b96557 93 #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
Kojto 99:dbbf35b96557 94 #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
Kojto 99:dbbf35b96557 95 #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
Kojto 99:dbbf35b96557 96 #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
Kojto 99:dbbf35b96557 97 #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
Kojto 99:dbbf35b96557 98 #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
Kojto 99:dbbf35b96557 99 #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
Kojto 99:dbbf35b96557 100 #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
Kojto 99:dbbf35b96557 101 /**
Kojto 99:dbbf35b96557 102 * @}
Kojto 99:dbbf35b96557 103 */
Kojto 99:dbbf35b96557 104
Kojto 99:dbbf35b96557 105 /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 106 * @{
Kojto 99:dbbf35b96557 107 */
Kojto 99:dbbf35b96557 108
Kojto 99:dbbf35b96557 109 #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
Kojto 99:dbbf35b96557 110
Kojto 99:dbbf35b96557 111 /**
Kojto 99:dbbf35b96557 112 * @}
Kojto 99:dbbf35b96557 113 */
Kojto 99:dbbf35b96557 114
Kojto 99:dbbf35b96557 115 /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 116 * @{
Kojto 99:dbbf35b96557 117 */
Kojto 99:dbbf35b96557 118
Kojto 99:dbbf35b96557 119 #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
Kojto 99:dbbf35b96557 120 #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
Kojto 99:dbbf35b96557 121 #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
Kojto 99:dbbf35b96557 122 #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
Kojto 99:dbbf35b96557 123
Kojto 99:dbbf35b96557 124 /**
Kojto 99:dbbf35b96557 125 * @}
Kojto 99:dbbf35b96557 126 */
Kojto 99:dbbf35b96557 127
Kojto 99:dbbf35b96557 128 /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 129 * @{
Kojto 99:dbbf35b96557 130 */
Kojto 99:dbbf35b96557 131
Kojto 99:dbbf35b96557 132 #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
Kojto 99:dbbf35b96557 133 #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
Kojto 99:dbbf35b96557 134
Kojto 99:dbbf35b96557 135 /**
Kojto 99:dbbf35b96557 136 * @}
Kojto 99:dbbf35b96557 137 */
Kojto 99:dbbf35b96557 138
Kojto 99:dbbf35b96557 139 /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 140 * @{
Kojto 99:dbbf35b96557 141 */
Kojto 99:dbbf35b96557 142
Kojto 99:dbbf35b96557 143 #define DAC1_CHANNEL_1 DAC_CHANNEL_1
Kojto 99:dbbf35b96557 144 #define DAC1_CHANNEL_2 DAC_CHANNEL_2
Kojto 99:dbbf35b96557 145 #define DAC2_CHANNEL_1 DAC_CHANNEL_1
Kojto 99:dbbf35b96557 146 #define DAC_WAVE_NONE ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 147 #define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
Kojto 99:dbbf35b96557 148 #define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
Kojto 99:dbbf35b96557 149 #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
Kojto 99:dbbf35b96557 150 #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
Kojto 99:dbbf35b96557 151 #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
Kojto 99:dbbf35b96557 152
Kojto 99:dbbf35b96557 153 /**
Kojto 99:dbbf35b96557 154 * @}
Kojto 99:dbbf35b96557 155 */
Kojto 99:dbbf35b96557 156
Kojto 106:ba1f97679dad 157 /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
Kojto 106:ba1f97679dad 158 * @{
Kojto 106:ba1f97679dad 159 */
Kojto 106:ba1f97679dad 160 #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
Kojto 106:ba1f97679dad 161 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
Kojto 106:ba1f97679dad 162 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
Kojto 106:ba1f97679dad 163 #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
Kojto 106:ba1f97679dad 164 #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
Kojto 106:ba1f97679dad 165 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto 106:ba1f97679dad 166 #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
Kojto 106:ba1f97679dad 167 #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
Kojto 106:ba1f97679dad 168 #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
Kojto 106:ba1f97679dad 169 #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
Kojto 106:ba1f97679dad 170 #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
Kojto 106:ba1f97679dad 171 #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
Kojto 106:ba1f97679dad 172 #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
Kojto 106:ba1f97679dad 173 #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
Kojto 106:ba1f97679dad 174 #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
Kojto 106:ba1f97679dad 175
Kojto 106:ba1f97679dad 176 #define IS_HAL_REMAPDMA IS_DMA_REMAP
Kojto 106:ba1f97679dad 177 #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
Kojto 106:ba1f97679dad 178 #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
Kojto 106:ba1f97679dad 179
Kojto 106:ba1f97679dad 180
Kojto 106:ba1f97679dad 181
Kojto 106:ba1f97679dad 182 /**
Kojto 106:ba1f97679dad 183 * @}
Kojto 106:ba1f97679dad 184 */
Kojto 99:dbbf35b96557 185
Kojto 99:dbbf35b96557 186 /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 187 * @{
Kojto 99:dbbf35b96557 188 */
Kojto 99:dbbf35b96557 189
Kojto 99:dbbf35b96557 190 #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
Kojto 99:dbbf35b96557 191 #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto 99:dbbf35b96557 192 #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
Kojto 99:dbbf35b96557 193 #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
Kojto 99:dbbf35b96557 194 #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
Kojto 99:dbbf35b96557 195 #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
Kojto 99:dbbf35b96557 196 #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
Kojto 99:dbbf35b96557 197 #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
Kojto 99:dbbf35b96557 198 #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
Kojto 99:dbbf35b96557 199 #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
Kojto 99:dbbf35b96557 200 #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
Kojto 99:dbbf35b96557 201 #define OBEX_PCROP OPTIONBYTE_PCROP
Kojto 99:dbbf35b96557 202 #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
Kojto 99:dbbf35b96557 203 #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
Kojto 99:dbbf35b96557 204 #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
Kojto 99:dbbf35b96557 205 #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
Kojto 99:dbbf35b96557 206 #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
Kojto 99:dbbf35b96557 207 #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
Kojto 99:dbbf35b96557 208 #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
Kojto 99:dbbf35b96557 209 #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
Kojto 99:dbbf35b96557 210 #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
Kojto 99:dbbf35b96557 211 #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
Kojto 99:dbbf35b96557 212 #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
Kojto 99:dbbf35b96557 213 #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
Kojto 99:dbbf35b96557 214 #define PAGESIZE FLASH_PAGE_SIZE
Kojto 99:dbbf35b96557 215 #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
Kojto 99:dbbf35b96557 216 #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
Kojto 99:dbbf35b96557 217 #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
Kojto 99:dbbf35b96557 218 #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
Kojto 99:dbbf35b96557 219 #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
Kojto 99:dbbf35b96557 220 #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
Kojto 99:dbbf35b96557 221 #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
Kojto 99:dbbf35b96557 222 #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
Kojto 99:dbbf35b96557 223 #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
Kojto 99:dbbf35b96557 224 #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
Kojto 99:dbbf35b96557 225 #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
Kojto 99:dbbf35b96557 226 #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
Kojto 99:dbbf35b96557 227 #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
Kojto 99:dbbf35b96557 228 #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
Kojto 99:dbbf35b96557 229 #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
Kojto 99:dbbf35b96557 230 #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
Kojto 99:dbbf35b96557 231 #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
Kojto 99:dbbf35b96557 232 #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
Kojto 99:dbbf35b96557 233 #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
Kojto 99:dbbf35b96557 234 #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
Kojto 99:dbbf35b96557 235 #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
Kojto 99:dbbf35b96557 236 #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
Kojto 99:dbbf35b96557 237 #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
Kojto 99:dbbf35b96557 238 #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
Kojto 99:dbbf35b96557 239 #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
Kojto 99:dbbf35b96557 240 #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
Kojto 99:dbbf35b96557 241 #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
Kojto 99:dbbf35b96557 242 #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
Kojto 99:dbbf35b96557 243 #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
Kojto 99:dbbf35b96557 244 #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
Kojto 99:dbbf35b96557 245 #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
Kojto 99:dbbf35b96557 246 #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
Kojto 99:dbbf35b96557 247 #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
Kojto 99:dbbf35b96557 248 #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
Kojto 99:dbbf35b96557 249 #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
Kojto 99:dbbf35b96557 250 #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
Kojto 106:ba1f97679dad 251 #define OB_WDG_SW OB_IWDG_SW
Kojto 106:ba1f97679dad 252 #define OB_WDG_HW OB_IWDG_HW
Kojto 99:dbbf35b96557 253
Kojto 99:dbbf35b96557 254 /**
Kojto 99:dbbf35b96557 255 * @}
Kojto 99:dbbf35b96557 256 */
Kojto 99:dbbf35b96557 257
Kojto 99:dbbf35b96557 258 /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 259 * @{
Kojto 99:dbbf35b96557 260 */
Kojto 99:dbbf35b96557 261
Kojto 99:dbbf35b96557 262 #define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
Kojto 99:dbbf35b96557 263 #define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
Kojto 99:dbbf35b96557 264 #define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
Kojto 99:dbbf35b96557 265 #define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
Kojto 99:dbbf35b96557 266 #define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
Kojto 99:dbbf35b96557 267 #define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
Kojto 99:dbbf35b96557 268 #define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
Kojto 99:dbbf35b96557 269
Kojto 99:dbbf35b96557 270 /**
Kojto 99:dbbf35b96557 271 * @}
Kojto 99:dbbf35b96557 272 */
Kojto 99:dbbf35b96557 273
Kojto 99:dbbf35b96557 274
Kojto 106:ba1f97679dad 275 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
Kojto 106:ba1f97679dad 276 * @{
Kojto 106:ba1f97679dad 277 */
Kojto 106:ba1f97679dad 278 #if defined(STM32L4) || defined(STM32F7)
Kojto 106:ba1f97679dad 279 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
Kojto 106:ba1f97679dad 280 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
Kojto 106:ba1f97679dad 281 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
Kojto 106:ba1f97679dad 282 #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
Kojto 106:ba1f97679dad 283 #else
Kojto 106:ba1f97679dad 284 #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
Kojto 106:ba1f97679dad 285 #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
Kojto 106:ba1f97679dad 286 #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
Kojto 106:ba1f97679dad 287 #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
Kojto 106:ba1f97679dad 288 #endif
Kojto 106:ba1f97679dad 289 /**
Kojto 106:ba1f97679dad 290 * @}
Kojto 106:ba1f97679dad 291 */
Kojto 106:ba1f97679dad 292
Kojto 99:dbbf35b96557 293 /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 294 * @{
Kojto 99:dbbf35b96557 295 */
Kojto 99:dbbf35b96557 296
Kojto 99:dbbf35b96557 297 #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
Kojto 99:dbbf35b96557 298 #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
Kojto 99:dbbf35b96557 299 /**
Kojto 99:dbbf35b96557 300 * @}
Kojto 99:dbbf35b96557 301 */
Kojto 99:dbbf35b96557 302
Kojto 99:dbbf35b96557 303 /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 304 * @{
Kojto 99:dbbf35b96557 305 */
Kojto 99:dbbf35b96557 306 #define GET_GPIO_SOURCE GPIO_GET_INDEX
Kojto 99:dbbf35b96557 307 #define GET_GPIO_INDEX GPIO_GET_INDEX
Kojto 106:ba1f97679dad 308
Kojto 106:ba1f97679dad 309 #if defined(STM32F4)
Kojto 106:ba1f97679dad 310 #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
Kojto 106:ba1f97679dad 311 #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
Kojto 106:ba1f97679dad 312 #endif
Kojto 106:ba1f97679dad 313
Kojto 106:ba1f97679dad 314 #if defined(STM32F7)
Kojto 106:ba1f97679dad 315 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto 106:ba1f97679dad 316 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto 106:ba1f97679dad 317 #endif
Kojto 106:ba1f97679dad 318
Kojto 106:ba1f97679dad 319 #if defined(STM32L4)
Kojto 106:ba1f97679dad 320 #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
Kojto 106:ba1f97679dad 321 #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
Kojto 106:ba1f97679dad 322 #endif
Kojto 106:ba1f97679dad 323
Kojto 106:ba1f97679dad 324 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
Kojto 106:ba1f97679dad 325 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
Kojto 106:ba1f97679dad 326 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
Kojto 106:ba1f97679dad 327
Kojto 99:dbbf35b96557 328 /**
Kojto 99:dbbf35b96557 329 * @}
Kojto 99:dbbf35b96557 330 */
Kojto 99:dbbf35b96557 331
Kojto 106:ba1f97679dad 332 /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
Kojto 106:ba1f97679dad 333 * @{
Kojto 106:ba1f97679dad 334 */
Kojto 106:ba1f97679dad 335 #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
Kojto 106:ba1f97679dad 336 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
Kojto 106:ba1f97679dad 337 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
Kojto 106:ba1f97679dad 338 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
Kojto 106:ba1f97679dad 339 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
Kojto 106:ba1f97679dad 340 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
Kojto 106:ba1f97679dad 341 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
Kojto 106:ba1f97679dad 342 #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
Kojto 106:ba1f97679dad 343 #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
Kojto 106:ba1f97679dad 344 /**
Kojto 106:ba1f97679dad 345 * @}
Kojto 106:ba1f97679dad 346 */
Kojto 99:dbbf35b96557 347
Kojto 99:dbbf35b96557 348 /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 349 * @{
Kojto 99:dbbf35b96557 350 */
Kojto 99:dbbf35b96557 351 #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
Kojto 99:dbbf35b96557 352 #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
Kojto 99:dbbf35b96557 353 #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
Kojto 99:dbbf35b96557 354 #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
Kojto 99:dbbf35b96557 355 #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
Kojto 99:dbbf35b96557 356 #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
Kojto 99:dbbf35b96557 357 #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
Kojto 99:dbbf35b96557 358 #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
Kojto 99:dbbf35b96557 359 /**
Kojto 99:dbbf35b96557 360 * @}
Kojto 99:dbbf35b96557 361 */
Kojto 99:dbbf35b96557 362
Kojto 99:dbbf35b96557 363 /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 364 * @{
Kojto 99:dbbf35b96557 365 */
Kojto 99:dbbf35b96557 366 #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 367 #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 368
Kojto 99:dbbf35b96557 369 /**
Kojto 99:dbbf35b96557 370 * @}
Kojto 99:dbbf35b96557 371 */
Kojto 99:dbbf35b96557 372
Kojto 99:dbbf35b96557 373 /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 374 * @{
Kojto 99:dbbf35b96557 375 */
Kojto 99:dbbf35b96557 376 #define KR_KEY_RELOAD IWDG_KEY_RELOAD
Kojto 99:dbbf35b96557 377 #define KR_KEY_ENABLE IWDG_KEY_ENABLE
Kojto 99:dbbf35b96557 378 #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
Kojto 99:dbbf35b96557 379 #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
Kojto 99:dbbf35b96557 380 /**
Kojto 99:dbbf35b96557 381 * @}
Kojto 99:dbbf35b96557 382 */
Kojto 99:dbbf35b96557 383
Kojto 99:dbbf35b96557 384 /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 385 * @{
Kojto 99:dbbf35b96557 386 */
Kojto 99:dbbf35b96557 387
Kojto 99:dbbf35b96557 388 #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
Kojto 99:dbbf35b96557 389 #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
Kojto 99:dbbf35b96557 390 #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
Kojto 99:dbbf35b96557 391 #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
Kojto 99:dbbf35b96557 392
Kojto 99:dbbf35b96557 393 #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
Kojto 99:dbbf35b96557 394 #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
Kojto 99:dbbf35b96557 395 #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
Kojto 106:ba1f97679dad 396
Kojto 106:ba1f97679dad 397 #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
Kojto 106:ba1f97679dad 398 #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
Kojto 106:ba1f97679dad 399 #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
Kojto 106:ba1f97679dad 400 #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
Kojto 106:ba1f97679dad 401
Kojto 106:ba1f97679dad 402 /* The following 3 definition have also been present in a temporary version of lptim.h */
Kojto 106:ba1f97679dad 403 /* They need to be renamed also to the right name, just in case */
Kojto 106:ba1f97679dad 404 #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
Kojto 106:ba1f97679dad 405 #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
Kojto 106:ba1f97679dad 406 #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
Kojto 106:ba1f97679dad 407
Kojto 99:dbbf35b96557 408 /**
Kojto 99:dbbf35b96557 409 * @}
Kojto 99:dbbf35b96557 410 */
Kojto 99:dbbf35b96557 411
Kojto 99:dbbf35b96557 412 /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 413 * @{
Kojto 99:dbbf35b96557 414 */
Kojto 99:dbbf35b96557 415 #define NAND_AddressTypedef NAND_AddressTypeDef
Kojto 99:dbbf35b96557 416
Kojto 99:dbbf35b96557 417 #define __ARRAY_ADDRESS ARRAY_ADDRESS
Kojto 99:dbbf35b96557 418 #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
Kojto 99:dbbf35b96557 419 #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
Kojto 99:dbbf35b96557 420 #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
Kojto 99:dbbf35b96557 421 #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
Kojto 99:dbbf35b96557 422 /**
Kojto 99:dbbf35b96557 423 * @}
Kojto 99:dbbf35b96557 424 */
Kojto 99:dbbf35b96557 425
Kojto 99:dbbf35b96557 426 /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 427 * @{
Kojto 99:dbbf35b96557 428 */
Kojto 99:dbbf35b96557 429 #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
Kojto 99:dbbf35b96557 430 #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
Kojto 99:dbbf35b96557 431 #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
Kojto 99:dbbf35b96557 432 #define NOR_ERROR HAL_NOR_STATUS_ERROR
Kojto 99:dbbf35b96557 433 #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
Kojto 99:dbbf35b96557 434
Kojto 99:dbbf35b96557 435 #define __NOR_WRITE NOR_WRITE
Kojto 99:dbbf35b96557 436 #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
Kojto 99:dbbf35b96557 437 /**
Kojto 99:dbbf35b96557 438 * @}
Kojto 99:dbbf35b96557 439 */
Kojto 99:dbbf35b96557 440
Kojto 99:dbbf35b96557 441 /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 442 * @{
Kojto 99:dbbf35b96557 443 */
Kojto 99:dbbf35b96557 444
Kojto 99:dbbf35b96557 445 #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 446 #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 447 #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
Kojto 99:dbbf35b96557 448 #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
Kojto 99:dbbf35b96557 449
Kojto 99:dbbf35b96557 450 #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 451 #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 452 #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
Kojto 99:dbbf35b96557 453 #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
Kojto 99:dbbf35b96557 454
Kojto 99:dbbf35b96557 455 #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 456 #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 457
Kojto 99:dbbf35b96557 458 #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 459 #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 460
Kojto 99:dbbf35b96557 461 #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 462 #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 463
Kojto 99:dbbf35b96557 464 #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 465
Kojto 99:dbbf35b96557 466 #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
Kojto 99:dbbf35b96557 467 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
Kojto 99:dbbf35b96557 468 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
Kojto 99:dbbf35b96557 469
Kojto 99:dbbf35b96557 470 /**
Kojto 99:dbbf35b96557 471 * @}
Kojto 99:dbbf35b96557 472 */
Kojto 99:dbbf35b96557 473
Kojto 99:dbbf35b96557 474 /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 475 * @{
Kojto 99:dbbf35b96557 476 */
Kojto 99:dbbf35b96557 477 #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
Kojto 99:dbbf35b96557 478 /**
Kojto 99:dbbf35b96557 479 * @}
Kojto 99:dbbf35b96557 480 */
Kojto 99:dbbf35b96557 481
Kojto 99:dbbf35b96557 482 /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 483 * @{
Kojto 99:dbbf35b96557 484 */
Kojto 99:dbbf35b96557 485
Kojto 99:dbbf35b96557 486 /* Compact Flash-ATA registers description */
Kojto 99:dbbf35b96557 487 #define CF_DATA ATA_DATA
Kojto 99:dbbf35b96557 488 #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
Kojto 99:dbbf35b96557 489 #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
Kojto 99:dbbf35b96557 490 #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
Kojto 99:dbbf35b96557 491 #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
Kojto 99:dbbf35b96557 492 #define CF_CARD_HEAD ATA_CARD_HEAD
Kojto 99:dbbf35b96557 493 #define CF_STATUS_CMD ATA_STATUS_CMD
Kojto 99:dbbf35b96557 494 #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
Kojto 99:dbbf35b96557 495 #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
Kojto 99:dbbf35b96557 496
Kojto 99:dbbf35b96557 497 /* Compact Flash-ATA commands */
Kojto 99:dbbf35b96557 498 #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
Kojto 99:dbbf35b96557 499 #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
Kojto 99:dbbf35b96557 500 #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
Kojto 99:dbbf35b96557 501 #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
Kojto 99:dbbf35b96557 502
Kojto 99:dbbf35b96557 503 #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
Kojto 99:dbbf35b96557 504 #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
Kojto 99:dbbf35b96557 505 #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
Kojto 99:dbbf35b96557 506 #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
Kojto 99:dbbf35b96557 507 #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
Kojto 99:dbbf35b96557 508 /**
Kojto 99:dbbf35b96557 509 * @}
Kojto 99:dbbf35b96557 510 */
Kojto 99:dbbf35b96557 511
Kojto 99:dbbf35b96557 512 /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 513 * @{
Kojto 99:dbbf35b96557 514 */
Kojto 99:dbbf35b96557 515
Kojto 99:dbbf35b96557 516 #define FORMAT_BIN RTC_FORMAT_BIN
Kojto 99:dbbf35b96557 517 #define FORMAT_BCD RTC_FORMAT_BCD
Kojto 99:dbbf35b96557 518
Kojto 99:dbbf35b96557 519 #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
Kojto 99:dbbf35b96557 520 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto 99:dbbf35b96557 521 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto 99:dbbf35b96557 522 #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 99:dbbf35b96557 523 #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 99:dbbf35b96557 524
Kojto 106:ba1f97679dad 525 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 99:dbbf35b96557 526 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 106:ba1f97679dad 527 #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
Kojto 106:ba1f97679dad 528 #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
Kojto 106:ba1f97679dad 529 #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
Kojto 99:dbbf35b96557 530 #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
Kojto 106:ba1f97679dad 531 #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto 106:ba1f97679dad 532 #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
Kojto 106:ba1f97679dad 533
Kojto 106:ba1f97679dad 534 #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
Kojto 106:ba1f97679dad 535 #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
Kojto 106:ba1f97679dad 536 #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
Kojto 106:ba1f97679dad 537 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
Kojto 106:ba1f97679dad 538
Kojto 106:ba1f97679dad 539 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
Kojto 106:ba1f97679dad 540 #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
Kojto 106:ba1f97679dad 541 #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
Kojto 106:ba1f97679dad 542
Kojto 106:ba1f97679dad 543 #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
Kojto 106:ba1f97679dad 544 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
Kojto 106:ba1f97679dad 545 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
Kojto 99:dbbf35b96557 546
Kojto 99:dbbf35b96557 547 /**
Kojto 99:dbbf35b96557 548 * @}
Kojto 99:dbbf35b96557 549 */
Kojto 99:dbbf35b96557 550
Kojto 99:dbbf35b96557 551
Kojto 99:dbbf35b96557 552 /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 553 * @{
Kojto 99:dbbf35b96557 554 */
Kojto 99:dbbf35b96557 555 #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
Kojto 99:dbbf35b96557 556 #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
Kojto 99:dbbf35b96557 557
Kojto 99:dbbf35b96557 558 #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 559 #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 560 #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 561 #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 562
Kojto 99:dbbf35b96557 563 #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
Kojto 99:dbbf35b96557 564 #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
Kojto 99:dbbf35b96557 565
Kojto 99:dbbf35b96557 566 #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
Kojto 99:dbbf35b96557 567 #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
Kojto 99:dbbf35b96557 568 /**
Kojto 99:dbbf35b96557 569 * @}
Kojto 99:dbbf35b96557 570 */
Kojto 99:dbbf35b96557 571
Kojto 99:dbbf35b96557 572
Kojto 99:dbbf35b96557 573 /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 574 * @{
Kojto 99:dbbf35b96557 575 */
Kojto 99:dbbf35b96557 576 #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
Kojto 99:dbbf35b96557 577 #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
Kojto 99:dbbf35b96557 578 #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
Kojto 99:dbbf35b96557 579 #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
Kojto 99:dbbf35b96557 580 #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
Kojto 99:dbbf35b96557 581 #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
Kojto 99:dbbf35b96557 582 #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
Kojto 99:dbbf35b96557 583 #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
Kojto 106:ba1f97679dad 584 #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
Kojto 106:ba1f97679dad 585 #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
Kojto 99:dbbf35b96557 586 #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
Kojto 99:dbbf35b96557 587 /**
Kojto 99:dbbf35b96557 588 * @}
Kojto 99:dbbf35b96557 589 */
Kojto 99:dbbf35b96557 590
Kojto 99:dbbf35b96557 591 /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 592 * @{
Kojto 99:dbbf35b96557 593 */
Kojto 99:dbbf35b96557 594 #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
Kojto 99:dbbf35b96557 595 #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
Kojto 99:dbbf35b96557 596
Kojto 99:dbbf35b96557 597 #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
Kojto 99:dbbf35b96557 598 #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
Kojto 99:dbbf35b96557 599
Kojto 99:dbbf35b96557 600 #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
Kojto 99:dbbf35b96557 601 #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
Kojto 99:dbbf35b96557 602
Kojto 99:dbbf35b96557 603 /**
Kojto 99:dbbf35b96557 604 * @}
Kojto 99:dbbf35b96557 605 */
Kojto 99:dbbf35b96557 606
Kojto 99:dbbf35b96557 607 /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 608 * @{
Kojto 99:dbbf35b96557 609 */
Kojto 99:dbbf35b96557 610 #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
Kojto 99:dbbf35b96557 611 #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
Kojto 99:dbbf35b96557 612
Kojto 99:dbbf35b96557 613 #define TIM_DMABase_CR1 TIM_DMABASE_CR1
Kojto 99:dbbf35b96557 614 #define TIM_DMABase_CR2 TIM_DMABASE_CR2
Kojto 99:dbbf35b96557 615 #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
Kojto 99:dbbf35b96557 616 #define TIM_DMABase_DIER TIM_DMABASE_DIER
Kojto 99:dbbf35b96557 617 #define TIM_DMABase_SR TIM_DMABASE_SR
Kojto 99:dbbf35b96557 618 #define TIM_DMABase_EGR TIM_DMABASE_EGR
Kojto 99:dbbf35b96557 619 #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
Kojto 99:dbbf35b96557 620 #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
Kojto 99:dbbf35b96557 621 #define TIM_DMABase_CCER TIM_DMABASE_CCER
Kojto 99:dbbf35b96557 622 #define TIM_DMABase_CNT TIM_DMABASE_CNT
Kojto 99:dbbf35b96557 623 #define TIM_DMABase_PSC TIM_DMABASE_PSC
Kojto 99:dbbf35b96557 624 #define TIM_DMABase_ARR TIM_DMABASE_ARR
Kojto 99:dbbf35b96557 625 #define TIM_DMABase_RCR TIM_DMABASE_RCR
Kojto 99:dbbf35b96557 626 #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
Kojto 99:dbbf35b96557 627 #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
Kojto 99:dbbf35b96557 628 #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
Kojto 99:dbbf35b96557 629 #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
Kojto 99:dbbf35b96557 630 #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
Kojto 99:dbbf35b96557 631 #define TIM_DMABase_DCR TIM_DMABASE_DCR
Kojto 99:dbbf35b96557 632 #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
Kojto 99:dbbf35b96557 633 #define TIM_DMABase_OR1 TIM_DMABASE_OR1
Kojto 99:dbbf35b96557 634 #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
Kojto 99:dbbf35b96557 635 #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
Kojto 99:dbbf35b96557 636 #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
Kojto 99:dbbf35b96557 637 #define TIM_DMABase_OR2 TIM_DMABASE_OR2
Kojto 99:dbbf35b96557 638 #define TIM_DMABase_OR3 TIM_DMABASE_OR3
Kojto 99:dbbf35b96557 639 #define TIM_DMABase_OR TIM_DMABASE_OR
Kojto 99:dbbf35b96557 640
Kojto 99:dbbf35b96557 641 #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
Kojto 99:dbbf35b96557 642 #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
Kojto 99:dbbf35b96557 643 #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
Kojto 99:dbbf35b96557 644 #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
Kojto 99:dbbf35b96557 645 #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
Kojto 99:dbbf35b96557 646 #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
Kojto 99:dbbf35b96557 647 #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
Kojto 99:dbbf35b96557 648 #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
Kojto 99:dbbf35b96557 649 #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
Kojto 99:dbbf35b96557 650
Kojto 99:dbbf35b96557 651 #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
Kojto 99:dbbf35b96557 652 #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
Kojto 99:dbbf35b96557 653 #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
Kojto 99:dbbf35b96557 654 #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
Kojto 99:dbbf35b96557 655 #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
Kojto 99:dbbf35b96557 656 #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
Kojto 99:dbbf35b96557 657 #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
Kojto 99:dbbf35b96557 658 #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
Kojto 99:dbbf35b96557 659 #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
Kojto 99:dbbf35b96557 660 #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
Kojto 99:dbbf35b96557 661 #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
Kojto 99:dbbf35b96557 662 #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
Kojto 99:dbbf35b96557 663 #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
Kojto 99:dbbf35b96557 664 #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
Kojto 99:dbbf35b96557 665 #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
Kojto 99:dbbf35b96557 666 #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
Kojto 99:dbbf35b96557 667 #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
Kojto 99:dbbf35b96557 668 #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
Kojto 99:dbbf35b96557 669
Kojto 99:dbbf35b96557 670 /**
Kojto 99:dbbf35b96557 671 * @}
Kojto 99:dbbf35b96557 672 */
Kojto 99:dbbf35b96557 673
Kojto 99:dbbf35b96557 674 /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 675 * @{
Kojto 99:dbbf35b96557 676 */
Kojto 99:dbbf35b96557 677 #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
Kojto 99:dbbf35b96557 678 #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
Kojto 99:dbbf35b96557 679 /**
Kojto 99:dbbf35b96557 680 * @}
Kojto 99:dbbf35b96557 681 */
Kojto 99:dbbf35b96557 682
Kojto 99:dbbf35b96557 683 /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 684 * @{
Kojto 99:dbbf35b96557 685 */
Kojto 99:dbbf35b96557 686 #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 687 #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 688 #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 689 #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 690
Kojto 99:dbbf35b96557 691 #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
Kojto 99:dbbf35b96557 692 #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
Kojto 99:dbbf35b96557 693
Kojto 99:dbbf35b96557 694 #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
Kojto 99:dbbf35b96557 695 #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
Kojto 99:dbbf35b96557 696 #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
Kojto 99:dbbf35b96557 697 #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
Kojto 99:dbbf35b96557 698
Kojto 99:dbbf35b96557 699 #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
Kojto 99:dbbf35b96557 700 #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
Kojto 99:dbbf35b96557 701 #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
Kojto 99:dbbf35b96557 702 #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
Kojto 99:dbbf35b96557 703
Kojto 99:dbbf35b96557 704 #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
Kojto 99:dbbf35b96557 705 #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
Kojto 99:dbbf35b96557 706
Kojto 99:dbbf35b96557 707 /**
Kojto 99:dbbf35b96557 708 * @}
Kojto 99:dbbf35b96557 709 */
Kojto 99:dbbf35b96557 710
Kojto 99:dbbf35b96557 711
Kojto 99:dbbf35b96557 712 /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 713 * @{
Kojto 99:dbbf35b96557 714 */
Kojto 99:dbbf35b96557 715
Kojto 99:dbbf35b96557 716 #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
Kojto 99:dbbf35b96557 717 #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
Kojto 99:dbbf35b96557 718
Kojto 99:dbbf35b96557 719 #define USARTNACK_ENABLED USART_NACK_ENABLE
Kojto 99:dbbf35b96557 720 #define USARTNACK_DISABLED USART_NACK_DISABLE
Kojto 99:dbbf35b96557 721 /**
Kojto 99:dbbf35b96557 722 * @}
Kojto 99:dbbf35b96557 723 */
Kojto 99:dbbf35b96557 724
Kojto 99:dbbf35b96557 725 /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 726 * @{
Kojto 99:dbbf35b96557 727 */
Kojto 99:dbbf35b96557 728 #define CFR_BASE WWDG_CFR_BASE
Kojto 99:dbbf35b96557 729
Kojto 99:dbbf35b96557 730 /**
Kojto 99:dbbf35b96557 731 * @}
Kojto 99:dbbf35b96557 732 */
Kojto 99:dbbf35b96557 733
Kojto 99:dbbf35b96557 734 /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 735 * @{
Kojto 99:dbbf35b96557 736 */
Kojto 99:dbbf35b96557 737 #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
Kojto 99:dbbf35b96557 738 #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
Kojto 99:dbbf35b96557 739 #define CAN_IT_RQCP0 CAN_IT_TME
Kojto 99:dbbf35b96557 740 #define CAN_IT_RQCP1 CAN_IT_TME
Kojto 99:dbbf35b96557 741 #define CAN_IT_RQCP2 CAN_IT_TME
Kojto 99:dbbf35b96557 742 #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto 99:dbbf35b96557 743 #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
Kojto 99:dbbf35b96557 744 #define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
Kojto 99:dbbf35b96557 745 #define CAN_TXSTATUS_OK ((uint8_t)0x01)
Kojto 99:dbbf35b96557 746 #define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
Kojto 99:dbbf35b96557 747
Kojto 99:dbbf35b96557 748 /**
Kojto 99:dbbf35b96557 749 * @}
Kojto 99:dbbf35b96557 750 */
Kojto 99:dbbf35b96557 751
Kojto 99:dbbf35b96557 752 /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 753 * @{
Kojto 99:dbbf35b96557 754 */
Kojto 99:dbbf35b96557 755
Kojto 99:dbbf35b96557 756 #define VLAN_TAG ETH_VLAN_TAG
Kojto 99:dbbf35b96557 757 #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
Kojto 99:dbbf35b96557 758 #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
Kojto 99:dbbf35b96557 759 #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
Kojto 99:dbbf35b96557 760 #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
Kojto 99:dbbf35b96557 761 #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
Kojto 99:dbbf35b96557 762 #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
Kojto 99:dbbf35b96557 763 #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
Kojto 99:dbbf35b96557 764
Kojto 99:dbbf35b96557 765 #define ETH_MMCCR ((uint32_t)0x00000100)
Kojto 99:dbbf35b96557 766 #define ETH_MMCRIR ((uint32_t)0x00000104)
Kojto 99:dbbf35b96557 767 #define ETH_MMCTIR ((uint32_t)0x00000108)
Kojto 99:dbbf35b96557 768 #define ETH_MMCRIMR ((uint32_t)0x0000010C)
Kojto 99:dbbf35b96557 769 #define ETH_MMCTIMR ((uint32_t)0x00000110)
Kojto 99:dbbf35b96557 770 #define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
Kojto 99:dbbf35b96557 771 #define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
Kojto 99:dbbf35b96557 772 #define ETH_MMCTGFCR ((uint32_t)0x00000168)
Kojto 99:dbbf35b96557 773 #define ETH_MMCRFCECR ((uint32_t)0x00000194)
Kojto 99:dbbf35b96557 774 #define ETH_MMCRFAECR ((uint32_t)0x00000198)
Kojto 99:dbbf35b96557 775 #define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
Kojto 99:dbbf35b96557 776
Kojto 99:dbbf35b96557 777 /**
Kojto 99:dbbf35b96557 778 * @}
Kojto 99:dbbf35b96557 779 */
Kojto 99:dbbf35b96557 780
Kojto 99:dbbf35b96557 781 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
Kojto 99:dbbf35b96557 782 * @{
Kojto 99:dbbf35b96557 783 */
Kojto 99:dbbf35b96557 784
Kojto 99:dbbf35b96557 785 /**
Kojto 99:dbbf35b96557 786 * @}
Kojto 99:dbbf35b96557 787 */
Kojto 99:dbbf35b96557 788
Kojto 99:dbbf35b96557 789 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 790
Kojto 99:dbbf35b96557 791 /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 792 * @{
Kojto 99:dbbf35b96557 793 */
Kojto 99:dbbf35b96557 794 #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
Kojto 99:dbbf35b96557 795 /**
Kojto 99:dbbf35b96557 796 * @}
Kojto 99:dbbf35b96557 797 */
Kojto 99:dbbf35b96557 798
Kojto 99:dbbf35b96557 799 /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 800 * @{
Kojto 99:dbbf35b96557 801 */
Kojto 99:dbbf35b96557 802
Kojto 99:dbbf35b96557 803 #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
Kojto 99:dbbf35b96557 804 #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
Kojto 99:dbbf35b96557 805 #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
Kojto 99:dbbf35b96557 806 #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
Kojto 99:dbbf35b96557 807
Kojto 99:dbbf35b96557 808 /*HASH Algorithm Selection*/
Kojto 99:dbbf35b96557 809
Kojto 99:dbbf35b96557 810 #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
Kojto 99:dbbf35b96557 811 #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
Kojto 99:dbbf35b96557 812 #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
Kojto 99:dbbf35b96557 813 #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
Kojto 99:dbbf35b96557 814
Kojto 99:dbbf35b96557 815 #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
Kojto 99:dbbf35b96557 816 #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
Kojto 99:dbbf35b96557 817
Kojto 99:dbbf35b96557 818 #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
Kojto 99:dbbf35b96557 819 #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
Kojto 99:dbbf35b96557 820 /**
Kojto 99:dbbf35b96557 821 * @}
Kojto 99:dbbf35b96557 822 */
Kojto 99:dbbf35b96557 823
Kojto 99:dbbf35b96557 824 /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 825 * @{
Kojto 99:dbbf35b96557 826 */
Kojto 99:dbbf35b96557 827 #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
Kojto 99:dbbf35b96557 828 #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
Kojto 99:dbbf35b96557 829 #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
Kojto 99:dbbf35b96557 830 #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
Kojto 99:dbbf35b96557 831 #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
Kojto 99:dbbf35b96557 832 #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
Kojto 99:dbbf35b96557 833 #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
Kojto 99:dbbf35b96557 834 #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
Kojto 99:dbbf35b96557 835 #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
Kojto 99:dbbf35b96557 836 #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
Kojto 99:dbbf35b96557 837 #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
Kojto 99:dbbf35b96557 838 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
Kojto 99:dbbf35b96557 839 /**
Kojto 99:dbbf35b96557 840 * @}
Kojto 99:dbbf35b96557 841 */
Kojto 99:dbbf35b96557 842
Kojto 99:dbbf35b96557 843 /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 844 * @{
Kojto 99:dbbf35b96557 845 */
Kojto 99:dbbf35b96557 846 #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
Kojto 99:dbbf35b96557 847 #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
Kojto 99:dbbf35b96557 848 #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
Kojto 99:dbbf35b96557 849 #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
Kojto 99:dbbf35b96557 850 #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
Kojto 99:dbbf35b96557 851 #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
Kojto 99:dbbf35b96557 852 #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
Kojto 99:dbbf35b96557 853
Kojto 99:dbbf35b96557 854 /**
Kojto 99:dbbf35b96557 855 * @}
Kojto 99:dbbf35b96557 856 */
Kojto 99:dbbf35b96557 857
Kojto 99:dbbf35b96557 858 /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 859 * @{
Kojto 99:dbbf35b96557 860 */
Kojto 99:dbbf35b96557 861 #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
Kojto 99:dbbf35b96557 862 #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
Kojto 99:dbbf35b96557 863
Kojto 99:dbbf35b96557 864 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
Kojto 99:dbbf35b96557 865 /**
Kojto 99:dbbf35b96557 866 * @}
Kojto 99:dbbf35b96557 867 */
Kojto 99:dbbf35b96557 868
Kojto 99:dbbf35b96557 869 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
Kojto 99:dbbf35b96557 870 * @{
Kojto 99:dbbf35b96557 871 */
Kojto 99:dbbf35b96557 872 #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
Kojto 99:dbbf35b96557 873 #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
Kojto 99:dbbf35b96557 874 #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
Kojto 99:dbbf35b96557 875 #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
Kojto 99:dbbf35b96557 876 #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
Kojto 99:dbbf35b96557 877 #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
Kojto 99:dbbf35b96557 878 #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
Kojto 99:dbbf35b96557 879 #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
Kojto 99:dbbf35b96557 880 #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
Kojto 99:dbbf35b96557 881 #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
Kojto 99:dbbf35b96557 882 #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
Kojto 99:dbbf35b96557 883 #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
Kojto 99:dbbf35b96557 884 #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
Kojto 99:dbbf35b96557 885 #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
Kojto 99:dbbf35b96557 886 #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
Kojto 99:dbbf35b96557 887 #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
Kojto 99:dbbf35b96557 888
Kojto 99:dbbf35b96557 889 #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
Kojto 99:dbbf35b96557 890 #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
Kojto 99:dbbf35b96557 891 #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
Kojto 99:dbbf35b96557 892 #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
Kojto 99:dbbf35b96557 893 #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
Kojto 99:dbbf35b96557 894 #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
Kojto 99:dbbf35b96557 895 #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
Kojto 99:dbbf35b96557 896
Kojto 99:dbbf35b96557 897 #define CR_OFFSET_BB PWR_CR_OFFSET_BB
Kojto 99:dbbf35b96557 898 #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
Kojto 99:dbbf35b96557 899
Kojto 99:dbbf35b96557 900 #define DBP_BitNumber DBP_BIT_NUMBER
Kojto 99:dbbf35b96557 901 #define PVDE_BitNumber PVDE_BIT_NUMBER
Kojto 99:dbbf35b96557 902 #define PMODE_BitNumber PMODE_BIT_NUMBER
Kojto 99:dbbf35b96557 903 #define EWUP_BitNumber EWUP_BIT_NUMBER
Kojto 99:dbbf35b96557 904 #define FPDS_BitNumber FPDS_BIT_NUMBER
Kojto 99:dbbf35b96557 905 #define ODEN_BitNumber ODEN_BIT_NUMBER
Kojto 99:dbbf35b96557 906 #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
Kojto 99:dbbf35b96557 907 #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
Kojto 99:dbbf35b96557 908 #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
Kojto 99:dbbf35b96557 909 #define BRE_BitNumber BRE_BIT_NUMBER
Kojto 99:dbbf35b96557 910
Kojto 99:dbbf35b96557 911 #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
Kojto 106:ba1f97679dad 912
Kojto 99:dbbf35b96557 913 /**
Kojto 99:dbbf35b96557 914 * @}
Kojto 99:dbbf35b96557 915 */
Kojto 99:dbbf35b96557 916
Kojto 99:dbbf35b96557 917 /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 918 * @{
Kojto 99:dbbf35b96557 919 */
Kojto 99:dbbf35b96557 920 #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
Kojto 99:dbbf35b96557 921 #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
Kojto 99:dbbf35b96557 922 #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
Kojto 99:dbbf35b96557 923 /**
Kojto 99:dbbf35b96557 924 * @}
Kojto 99:dbbf35b96557 925 */
Kojto 99:dbbf35b96557 926
Kojto 99:dbbf35b96557 927 /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 928 * @{
Kojto 99:dbbf35b96557 929 */
Kojto 99:dbbf35b96557 930 #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
Kojto 99:dbbf35b96557 931 /**
Kojto 99:dbbf35b96557 932 * @}
Kojto 99:dbbf35b96557 933 */
Kojto 99:dbbf35b96557 934
Kojto 99:dbbf35b96557 935 /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 936 * @{
Kojto 99:dbbf35b96557 937 */
Kojto 99:dbbf35b96557 938 #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
Kojto 99:dbbf35b96557 939 #define HAL_TIM_DMAError TIM_DMAError
Kojto 99:dbbf35b96557 940 #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
Kojto 99:dbbf35b96557 941 #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
Kojto 99:dbbf35b96557 942 /**
Kojto 99:dbbf35b96557 943 * @}
Kojto 99:dbbf35b96557 944 */
Kojto 99:dbbf35b96557 945
Kojto 99:dbbf35b96557 946 /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 947 * @{
Kojto 99:dbbf35b96557 948 */
Kojto 99:dbbf35b96557 949 #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
Kojto 99:dbbf35b96557 950 /**
Kojto 99:dbbf35b96557 951 * @}
Kojto 99:dbbf35b96557 952 */
Kojto 106:ba1f97679dad 953
Kojto 106:ba1f97679dad 954 /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
Kojto 106:ba1f97679dad 955 * @{
Kojto 106:ba1f97679dad 956 */
Kojto 106:ba1f97679dad 957 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
Kojto 106:ba1f97679dad 958 /**
Kojto 106:ba1f97679dad 959 * @}
Kojto 106:ba1f97679dad 960 */
Kojto 99:dbbf35b96557 961
Kojto 99:dbbf35b96557 962
Kojto 99:dbbf35b96557 963 /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
Kojto 99:dbbf35b96557 964 * @{
Kojto 99:dbbf35b96557 965 */
Kojto 99:dbbf35b96557 966
Kojto 99:dbbf35b96557 967 /**
Kojto 99:dbbf35b96557 968 * @}
Kojto 99:dbbf35b96557 969 */
Kojto 99:dbbf35b96557 970
Kojto 99:dbbf35b96557 971 /* Exported macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 972
Kojto 99:dbbf35b96557 973 /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 974 * @{
Kojto 99:dbbf35b96557 975 */
Kojto 99:dbbf35b96557 976 #define AES_IT_CC CRYP_IT_CC
Kojto 99:dbbf35b96557 977 #define AES_IT_ERR CRYP_IT_ERR
Kojto 99:dbbf35b96557 978 #define AES_FLAG_CCF CRYP_FLAG_CCF
Kojto 99:dbbf35b96557 979 /**
Kojto 99:dbbf35b96557 980 * @}
Kojto 99:dbbf35b96557 981 */
Kojto 99:dbbf35b96557 982
Kojto 99:dbbf35b96557 983 /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 984 * @{
Kojto 99:dbbf35b96557 985 */
Kojto 99:dbbf35b96557 986 #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
Kojto 99:dbbf35b96557 987 #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
Kojto 99:dbbf35b96557 988 #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
Kojto 99:dbbf35b96557 989 #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
Kojto 99:dbbf35b96557 990 #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
Kojto 99:dbbf35b96557 991 #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
Kojto 99:dbbf35b96557 992 #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
Kojto 99:dbbf35b96557 993 #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
Kojto 99:dbbf35b96557 994 #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
Kojto 99:dbbf35b96557 995 #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
Kojto 99:dbbf35b96557 996 #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
Kojto 99:dbbf35b96557 997 #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
Kojto 99:dbbf35b96557 998 #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
Kojto 99:dbbf35b96557 999
Kojto 99:dbbf35b96557 1000 #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
Kojto 99:dbbf35b96557 1001 #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
Kojto 99:dbbf35b96557 1002 #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
Kojto 99:dbbf35b96557 1003 #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
Kojto 99:dbbf35b96557 1004 #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
Kojto 99:dbbf35b96557 1005
Kojto 99:dbbf35b96557 1006 /**
Kojto 99:dbbf35b96557 1007 * @}
Kojto 99:dbbf35b96557 1008 */
Kojto 99:dbbf35b96557 1009
Kojto 99:dbbf35b96557 1010
Kojto 99:dbbf35b96557 1011 /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1012 * @{
Kojto 99:dbbf35b96557 1013 */
Kojto 99:dbbf35b96557 1014 #define __ADC_ENABLE __HAL_ADC_ENABLE
Kojto 99:dbbf35b96557 1015 #define __ADC_DISABLE __HAL_ADC_DISABLE
Kojto 99:dbbf35b96557 1016 #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
Kojto 99:dbbf35b96557 1017 #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
Kojto 99:dbbf35b96557 1018 #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
Kojto 99:dbbf35b96557 1019 #define __ADC_IS_ENABLED ADC_IS_ENABLE
Kojto 99:dbbf35b96557 1020 #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
Kojto 99:dbbf35b96557 1021 #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
Kojto 99:dbbf35b96557 1022 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
Kojto 99:dbbf35b96557 1023 #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
Kojto 99:dbbf35b96557 1024 #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
Kojto 99:dbbf35b96557 1025 #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
Kojto 99:dbbf35b96557 1026 #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
Kojto 99:dbbf35b96557 1027
Kojto 99:dbbf35b96557 1028 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto 99:dbbf35b96557 1029 #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
Kojto 99:dbbf35b96557 1030 #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
Kojto 99:dbbf35b96557 1031 #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
Kojto 99:dbbf35b96557 1032 #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
Kojto 99:dbbf35b96557 1033 #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
Kojto 99:dbbf35b96557 1034 #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
Kojto 99:dbbf35b96557 1035 #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
Kojto 99:dbbf35b96557 1036 #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
Kojto 99:dbbf35b96557 1037 #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
Kojto 99:dbbf35b96557 1038 #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
Kojto 99:dbbf35b96557 1039 #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
Kojto 99:dbbf35b96557 1040 #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
Kojto 99:dbbf35b96557 1041 #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
Kojto 99:dbbf35b96557 1042 #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
Kojto 99:dbbf35b96557 1043 #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
Kojto 99:dbbf35b96557 1044 #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
Kojto 99:dbbf35b96557 1045 #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
Kojto 99:dbbf35b96557 1046 #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
Kojto 99:dbbf35b96557 1047 #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
Kojto 99:dbbf35b96557 1048
Kojto 99:dbbf35b96557 1049 #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
Kojto 99:dbbf35b96557 1050 #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
Kojto 99:dbbf35b96557 1051 #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
Kojto 99:dbbf35b96557 1052 #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
Kojto 99:dbbf35b96557 1053 #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
Kojto 99:dbbf35b96557 1054 #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto 99:dbbf35b96557 1055 #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
Kojto 99:dbbf35b96557 1056 #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
Kojto 99:dbbf35b96557 1057 #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
Kojto 99:dbbf35b96557 1058 #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
Kojto 99:dbbf35b96557 1059
Kojto 99:dbbf35b96557 1060 #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
Kojto 99:dbbf35b96557 1061 #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
Kojto 99:dbbf35b96557 1062 #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
Kojto 99:dbbf35b96557 1063 #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
Kojto 99:dbbf35b96557 1064 #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
Kojto 99:dbbf35b96557 1065 #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
Kojto 99:dbbf35b96557 1066 #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
Kojto 99:dbbf35b96557 1067 #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
Kojto 99:dbbf35b96557 1068
Kojto 99:dbbf35b96557 1069 #define __HAL_ADC_SQR1 ADC_SQR1
Kojto 99:dbbf35b96557 1070 #define __HAL_ADC_SMPR1 ADC_SMPR1
Kojto 99:dbbf35b96557 1071 #define __HAL_ADC_SMPR2 ADC_SMPR2
Kojto 99:dbbf35b96557 1072 #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
Kojto 99:dbbf35b96557 1073 #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
Kojto 99:dbbf35b96557 1074 #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
Kojto 99:dbbf35b96557 1075 #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
Kojto 99:dbbf35b96557 1076 #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
Kojto 99:dbbf35b96557 1077 #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
Kojto 99:dbbf35b96557 1078 #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
Kojto 99:dbbf35b96557 1079 #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
Kojto 99:dbbf35b96557 1080 #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
Kojto 99:dbbf35b96557 1081 #define __HAL_ADC_JSQR ADC_JSQR
Kojto 99:dbbf35b96557 1082
Kojto 99:dbbf35b96557 1083 #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
Kojto 99:dbbf35b96557 1084 #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
Kojto 99:dbbf35b96557 1085 #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
Kojto 99:dbbf35b96557 1086 #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
Kojto 99:dbbf35b96557 1087 #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
Kojto 99:dbbf35b96557 1088 #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
Kojto 99:dbbf35b96557 1089 #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
Kojto 99:dbbf35b96557 1090 #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
Kojto 99:dbbf35b96557 1091
Kojto 99:dbbf35b96557 1092 /**
Kojto 99:dbbf35b96557 1093 * @}
Kojto 99:dbbf35b96557 1094 */
Kojto 99:dbbf35b96557 1095
Kojto 99:dbbf35b96557 1096 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1097 * @{
Kojto 99:dbbf35b96557 1098 */
Kojto 99:dbbf35b96557 1099 #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
Kojto 99:dbbf35b96557 1100 #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
Kojto 99:dbbf35b96557 1101 #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
Kojto 99:dbbf35b96557 1102 #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
Kojto 99:dbbf35b96557 1103
Kojto 99:dbbf35b96557 1104 /**
Kojto 99:dbbf35b96557 1105 * @}
Kojto 99:dbbf35b96557 1106 */
Kojto 99:dbbf35b96557 1107
Kojto 99:dbbf35b96557 1108 /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1109 * @{
Kojto 99:dbbf35b96557 1110 */
Kojto 99:dbbf35b96557 1111 #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
Kojto 99:dbbf35b96557 1112 #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
Kojto 99:dbbf35b96557 1113 #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
Kojto 99:dbbf35b96557 1114 #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
Kojto 99:dbbf35b96557 1115 #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
Kojto 99:dbbf35b96557 1116 #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
Kojto 99:dbbf35b96557 1117 #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
Kojto 99:dbbf35b96557 1118 #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
Kojto 99:dbbf35b96557 1119 #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
Kojto 99:dbbf35b96557 1120 #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
Kojto 99:dbbf35b96557 1121 #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
Kojto 99:dbbf35b96557 1122 #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
Kojto 99:dbbf35b96557 1123 #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
Kojto 99:dbbf35b96557 1124 #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
Kojto 99:dbbf35b96557 1125 #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
Kojto 99:dbbf35b96557 1126 #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
Kojto 99:dbbf35b96557 1127
Kojto 99:dbbf35b96557 1128 #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
Kojto 99:dbbf35b96557 1129 #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
Kojto 99:dbbf35b96557 1130 #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
Kojto 99:dbbf35b96557 1131 #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
Kojto 99:dbbf35b96557 1132 #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
Kojto 99:dbbf35b96557 1133 #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
Kojto 99:dbbf35b96557 1134 #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
Kojto 99:dbbf35b96557 1135 #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
Kojto 99:dbbf35b96557 1136 #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
Kojto 99:dbbf35b96557 1137 #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
Kojto 99:dbbf35b96557 1138 #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
Kojto 99:dbbf35b96557 1139 #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
Kojto 99:dbbf35b96557 1140 #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
Kojto 99:dbbf35b96557 1141 #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
Kojto 99:dbbf35b96557 1142
Kojto 99:dbbf35b96557 1143
Kojto 99:dbbf35b96557 1144 #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
Kojto 99:dbbf35b96557 1145 #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
Kojto 99:dbbf35b96557 1146 #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
Kojto 99:dbbf35b96557 1147 #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
Kojto 99:dbbf35b96557 1148 #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
Kojto 99:dbbf35b96557 1149 #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
Kojto 99:dbbf35b96557 1150 #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
Kojto 99:dbbf35b96557 1151 #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
Kojto 99:dbbf35b96557 1152 #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
Kojto 99:dbbf35b96557 1153 #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
Kojto 99:dbbf35b96557 1154 #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
Kojto 99:dbbf35b96557 1155 #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
Kojto 99:dbbf35b96557 1156 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
Kojto 99:dbbf35b96557 1157 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
Kojto 99:dbbf35b96557 1158 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
Kojto 99:dbbf35b96557 1159 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
Kojto 99:dbbf35b96557 1160 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
Kojto 99:dbbf35b96557 1161 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
Kojto 99:dbbf35b96557 1162 #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
Kojto 99:dbbf35b96557 1163 #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
Kojto 99:dbbf35b96557 1164 #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
Kojto 99:dbbf35b96557 1165 #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
Kojto 99:dbbf35b96557 1166 #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
Kojto 99:dbbf35b96557 1167 #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
Kojto 99:dbbf35b96557 1168
Kojto 99:dbbf35b96557 1169 /**
Kojto 99:dbbf35b96557 1170 * @}
Kojto 99:dbbf35b96557 1171 */
Kojto 99:dbbf35b96557 1172
Kojto 99:dbbf35b96557 1173 /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1174 * @{
Kojto 99:dbbf35b96557 1175 */
Kojto 99:dbbf35b96557 1176
Kojto 99:dbbf35b96557 1177 #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 99:dbbf35b96557 1178 __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
Kojto 99:dbbf35b96557 1179 #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
Kojto 99:dbbf35b96557 1180 __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
Kojto 99:dbbf35b96557 1181 #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 99:dbbf35b96557 1182 __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
Kojto 99:dbbf35b96557 1183 #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
Kojto 99:dbbf35b96557 1184 __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
Kojto 99:dbbf35b96557 1185 #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
Kojto 99:dbbf35b96557 1186 __HAL_COMP_COMP2_EXTI_ENABLE_IT())
Kojto 99:dbbf35b96557 1187 #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
Kojto 99:dbbf35b96557 1188 __HAL_COMP_COMP2_EXTI_DISABLE_IT())
Kojto 99:dbbf35b96557 1189 #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
Kojto 99:dbbf35b96557 1190 __HAL_COMP_COMP2_EXTI_GET_FLAG())
Kojto 99:dbbf35b96557 1191 #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
Kojto 99:dbbf35b96557 1192 __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
Kojto 99:dbbf35b96557 1193 #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
Kojto 99:dbbf35b96557 1194
Kojto 99:dbbf35b96557 1195 /**
Kojto 99:dbbf35b96557 1196 * @}
Kojto 99:dbbf35b96557 1197 */
Kojto 99:dbbf35b96557 1198
Kojto 99:dbbf35b96557 1199 /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1200 * @{
Kojto 99:dbbf35b96557 1201 */
Kojto 99:dbbf35b96557 1202
Kojto 99:dbbf35b96557 1203 #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
Kojto 99:dbbf35b96557 1204 ((WAVE) == DAC_WAVE_NOISE)|| \
Kojto 99:dbbf35b96557 1205 ((WAVE) == DAC_WAVE_TRIANGLE))
Kojto 99:dbbf35b96557 1206
Kojto 99:dbbf35b96557 1207 /**
Kojto 99:dbbf35b96557 1208 * @}
Kojto 99:dbbf35b96557 1209 */
Kojto 99:dbbf35b96557 1210
Kojto 99:dbbf35b96557 1211 /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1212 * @{
Kojto 99:dbbf35b96557 1213 */
Kojto 99:dbbf35b96557 1214
Kojto 99:dbbf35b96557 1215 #define IS_WRPAREA IS_OB_WRPAREA
Kojto 99:dbbf35b96557 1216 #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
Kojto 99:dbbf35b96557 1217 #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
Kojto 99:dbbf35b96557 1218 #define IS_TYPEERASE IS_FLASH_TYPEERASE
Kojto 106:ba1f97679dad 1219 #define IS_NBSECTORS IS_FLASH_NBSECTORS
Kojto 106:ba1f97679dad 1220 #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
Kojto 99:dbbf35b96557 1221
Kojto 99:dbbf35b96557 1222 /**
Kojto 99:dbbf35b96557 1223 * @}
Kojto 99:dbbf35b96557 1224 */
Kojto 99:dbbf35b96557 1225
Kojto 99:dbbf35b96557 1226 /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1227 * @{
Kojto 99:dbbf35b96557 1228 */
Kojto 99:dbbf35b96557 1229
Kojto 99:dbbf35b96557 1230 #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
Kojto 99:dbbf35b96557 1231 #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
Kojto 99:dbbf35b96557 1232 #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
Kojto 99:dbbf35b96557 1233 #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
Kojto 99:dbbf35b96557 1234 #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
Kojto 99:dbbf35b96557 1235 #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
Kojto 99:dbbf35b96557 1236 #define __HAL_I2C_SPEED I2C_SPEED
Kojto 99:dbbf35b96557 1237 #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
Kojto 99:dbbf35b96557 1238 #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
Kojto 99:dbbf35b96557 1239 #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
Kojto 99:dbbf35b96557 1240 #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
Kojto 99:dbbf35b96557 1241 #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
Kojto 99:dbbf35b96557 1242 #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
Kojto 99:dbbf35b96557 1243 #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
Kojto 99:dbbf35b96557 1244 #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
Kojto 99:dbbf35b96557 1245 /**
Kojto 99:dbbf35b96557 1246 * @}
Kojto 99:dbbf35b96557 1247 */
Kojto 99:dbbf35b96557 1248
Kojto 99:dbbf35b96557 1249 /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1250 * @{
Kojto 99:dbbf35b96557 1251 */
Kojto 99:dbbf35b96557 1252
Kojto 99:dbbf35b96557 1253 #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
Kojto 99:dbbf35b96557 1254 #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
Kojto 99:dbbf35b96557 1255
Kojto 99:dbbf35b96557 1256 /**
Kojto 99:dbbf35b96557 1257 * @}
Kojto 99:dbbf35b96557 1258 */
Kojto 99:dbbf35b96557 1259
Kojto 99:dbbf35b96557 1260 /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1261 * @{
Kojto 99:dbbf35b96557 1262 */
Kojto 99:dbbf35b96557 1263
Kojto 99:dbbf35b96557 1264 #define __IRDA_DISABLE __HAL_IRDA_DISABLE
Kojto 99:dbbf35b96557 1265 #define __IRDA_ENABLE __HAL_IRDA_ENABLE
Kojto 99:dbbf35b96557 1266
Kojto 99:dbbf35b96557 1267 #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 1268 #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto 99:dbbf35b96557 1269 #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 1270 #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
Kojto 99:dbbf35b96557 1271
Kojto 99:dbbf35b96557 1272 #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
Kojto 99:dbbf35b96557 1273
Kojto 99:dbbf35b96557 1274
Kojto 99:dbbf35b96557 1275 /**
Kojto 99:dbbf35b96557 1276 * @}
Kojto 99:dbbf35b96557 1277 */
Kojto 99:dbbf35b96557 1278
Kojto 99:dbbf35b96557 1279
Kojto 99:dbbf35b96557 1280 /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1281 * @{
Kojto 99:dbbf35b96557 1282 */
Kojto 99:dbbf35b96557 1283 #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
Kojto 99:dbbf35b96557 1284 #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
Kojto 99:dbbf35b96557 1285 /**
Kojto 99:dbbf35b96557 1286 * @}
Kojto 99:dbbf35b96557 1287 */
Kojto 99:dbbf35b96557 1288
Kojto 99:dbbf35b96557 1289
Kojto 99:dbbf35b96557 1290 /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1291 * @{
Kojto 99:dbbf35b96557 1292 */
Kojto 99:dbbf35b96557 1293
Kojto 99:dbbf35b96557 1294 #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
Kojto 99:dbbf35b96557 1295 #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
Kojto 99:dbbf35b96557 1296 #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
Kojto 99:dbbf35b96557 1297
Kojto 99:dbbf35b96557 1298 /**
Kojto 99:dbbf35b96557 1299 * @}
Kojto 99:dbbf35b96557 1300 */
Kojto 99:dbbf35b96557 1301
Kojto 99:dbbf35b96557 1302
Kojto 99:dbbf35b96557 1303 /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1304 * @{
Kojto 99:dbbf35b96557 1305 */
Kojto 99:dbbf35b96557 1306 #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
Kojto 99:dbbf35b96557 1307 #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
Kojto 99:dbbf35b96557 1308 #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
Kojto 99:dbbf35b96557 1309 #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
Kojto 99:dbbf35b96557 1310 #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
Kojto 99:dbbf35b96557 1311 #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
Kojto 99:dbbf35b96557 1312 #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
Kojto 99:dbbf35b96557 1313 #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
Kojto 99:dbbf35b96557 1314 #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
Kojto 99:dbbf35b96557 1315 #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
Kojto 99:dbbf35b96557 1316 #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
Kojto 99:dbbf35b96557 1317 #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
Kojto 99:dbbf35b96557 1318 #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
Kojto 99:dbbf35b96557 1319
Kojto 99:dbbf35b96557 1320 /**
Kojto 99:dbbf35b96557 1321 * @}
Kojto 99:dbbf35b96557 1322 */
Kojto 99:dbbf35b96557 1323
Kojto 99:dbbf35b96557 1324
Kojto 99:dbbf35b96557 1325 /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 1326 * @{
Kojto 99:dbbf35b96557 1327 */
Kojto 99:dbbf35b96557 1328 #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto 99:dbbf35b96557 1329 #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto 99:dbbf35b96557 1330 #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1331 #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1332 #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto 99:dbbf35b96557 1333 #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 1334 #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
Kojto 99:dbbf35b96557 1335 #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
Kojto 99:dbbf35b96557 1336 #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
Kojto 99:dbbf35b96557 1337 #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
Kojto 99:dbbf35b96557 1338 #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
Kojto 99:dbbf35b96557 1339 #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
Kojto 99:dbbf35b96557 1340 #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
Kojto 99:dbbf35b96557 1341 #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
Kojto 99:dbbf35b96557 1342 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
Kojto 99:dbbf35b96557 1343 #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
Kojto 99:dbbf35b96557 1344 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()
Kojto 99:dbbf35b96557 1345 #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
Kojto 99:dbbf35b96557 1346 #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
Kojto 99:dbbf35b96557 1347 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1348 #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1349 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
Kojto 99:dbbf35b96557 1350 #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 1351 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1352 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 1353 #define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4()
Kojto 99:dbbf35b96557 1354 #define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4()
Kojto 99:dbbf35b96557 1355 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
Kojto 99:dbbf35b96557 1356 #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
Kojto 99:dbbf35b96557 1357 #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
Kojto 99:dbbf35b96557 1358 #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
Kojto 99:dbbf35b96557 1359 #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1360 #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 1361 #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
Kojto 99:dbbf35b96557 1362 #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
Kojto 99:dbbf35b96557 1363
Kojto 99:dbbf35b96557 1364 #if defined (STM32F4)
Kojto 99:dbbf35b96557 1365 #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
Kojto 99:dbbf35b96557 1366 #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
Kojto 99:dbbf35b96557 1367 #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
Kojto 99:dbbf35b96557 1368 #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
Kojto 99:dbbf35b96557 1369 #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
Kojto 99:dbbf35b96557 1370 #else
Kojto 99:dbbf35b96557 1371 #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 1372 #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 1373 #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 1374 #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
Kojto 99:dbbf35b96557 1375 #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
Kojto 99:dbbf35b96557 1376 #endif /* STM32F4 */
Kojto 99:dbbf35b96557 1377 /**
Kojto 99:dbbf35b96557 1378 * @}
Kojto 99:dbbf35b96557 1379 */
Kojto 99:dbbf35b96557 1380
Kojto 99:dbbf35b96557 1381
Kojto 99:dbbf35b96557 1382 /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
Kojto 99:dbbf35b96557 1383 * @{
Kojto 99:dbbf35b96557 1384 */
Kojto 99:dbbf35b96557 1385
Kojto 99:dbbf35b96557 1386 #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
Kojto 99:dbbf35b96557 1387 #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
Kojto 99:dbbf35b96557 1388
Kojto 99:dbbf35b96557 1389 #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
Kojto 99:dbbf35b96557 1390 #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
Kojto 99:dbbf35b96557 1391
Kojto 99:dbbf35b96557 1392 #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
Kojto 99:dbbf35b96557 1393 #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
Kojto 99:dbbf35b96557 1394 #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1395 #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1396 #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
Kojto 99:dbbf35b96557 1397 #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
Kojto 99:dbbf35b96557 1398 #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
Kojto 99:dbbf35b96557 1399 #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
Kojto 99:dbbf35b96557 1400 #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
Kojto 99:dbbf35b96557 1401 #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
Kojto 99:dbbf35b96557 1402 #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1403 #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1404 #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
Kojto 99:dbbf35b96557 1405 #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
Kojto 99:dbbf35b96557 1406 #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
Kojto 99:dbbf35b96557 1407 #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
Kojto 99:dbbf35b96557 1408 #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
Kojto 99:dbbf35b96557 1409 #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
Kojto 99:dbbf35b96557 1410 #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
Kojto 99:dbbf35b96557 1411 #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
Kojto 99:dbbf35b96557 1412 #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
Kojto 99:dbbf35b96557 1413 #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
Kojto 99:dbbf35b96557 1414 #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1415 #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1416 #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
Kojto 99:dbbf35b96557 1417 #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
Kojto 99:dbbf35b96557 1418 #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1419 #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1420 #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
Kojto 99:dbbf35b96557 1421 #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
Kojto 99:dbbf35b96557 1422 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto 99:dbbf35b96557 1423 #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
Kojto 99:dbbf35b96557 1424 #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
Kojto 99:dbbf35b96557 1425 #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
Kojto 99:dbbf35b96557 1426 #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
Kojto 99:dbbf35b96557 1427 #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
Kojto 99:dbbf35b96557 1428 #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
Kojto 99:dbbf35b96557 1429 #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
Kojto 99:dbbf35b96557 1430 #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
Kojto 99:dbbf35b96557 1431 #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
Kojto 99:dbbf35b96557 1432 #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
Kojto 99:dbbf35b96557 1433 #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
Kojto 99:dbbf35b96557 1434 #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
Kojto 99:dbbf35b96557 1435 #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
Kojto 99:dbbf35b96557 1436 #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
Kojto 99:dbbf35b96557 1437 #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
Kojto 99:dbbf35b96557 1438 #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
Kojto 99:dbbf35b96557 1439 #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
Kojto 99:dbbf35b96557 1440 #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
Kojto 99:dbbf35b96557 1441 #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
Kojto 99:dbbf35b96557 1442 #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
Kojto 99:dbbf35b96557 1443 #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
Kojto 99:dbbf35b96557 1444 #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto 99:dbbf35b96557 1445 #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto 99:dbbf35b96557 1446 #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1447 #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1448 #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto 99:dbbf35b96557 1449 #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto 99:dbbf35b96557 1450 #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
Kojto 99:dbbf35b96557 1451 #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
Kojto 99:dbbf35b96557 1452 #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
Kojto 99:dbbf35b96557 1453 #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
Kojto 99:dbbf35b96557 1454 #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
Kojto 99:dbbf35b96557 1455 #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
Kojto 99:dbbf35b96557 1456 #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
Kojto 99:dbbf35b96557 1457 #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
Kojto 99:dbbf35b96557 1458 #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
Kojto 99:dbbf35b96557 1459 #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
Kojto 99:dbbf35b96557 1460 #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
Kojto 99:dbbf35b96557 1461 #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
Kojto 99:dbbf35b96557 1462 #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
Kojto 99:dbbf35b96557 1463 #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
Kojto 99:dbbf35b96557 1464 #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1465 #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1466 #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
Kojto 99:dbbf35b96557 1467 #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
Kojto 99:dbbf35b96557 1468 #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
Kojto 99:dbbf35b96557 1469 #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
Kojto 99:dbbf35b96557 1470 #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1471 #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1472 #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
Kojto 99:dbbf35b96557 1473 #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
Kojto 99:dbbf35b96557 1474 #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
Kojto 99:dbbf35b96557 1475 #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
Kojto 99:dbbf35b96557 1476 #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
Kojto 99:dbbf35b96557 1477 #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
Kojto 99:dbbf35b96557 1478 #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
Kojto 99:dbbf35b96557 1479 #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
Kojto 99:dbbf35b96557 1480 #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1481 #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1482 #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
Kojto 99:dbbf35b96557 1483 #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
Kojto 99:dbbf35b96557 1484 #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
Kojto 99:dbbf35b96557 1485 #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
Kojto 99:dbbf35b96557 1486 #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
Kojto 99:dbbf35b96557 1487 #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
Kojto 99:dbbf35b96557 1488 #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
Kojto 99:dbbf35b96557 1489 #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
Kojto 99:dbbf35b96557 1490 #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1491 #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1492 #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
Kojto 99:dbbf35b96557 1493 #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
Kojto 99:dbbf35b96557 1494 #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
Kojto 99:dbbf35b96557 1495 #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
Kojto 99:dbbf35b96557 1496 #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1497 #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1498 #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
Kojto 99:dbbf35b96557 1499 #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
Kojto 99:dbbf35b96557 1500 #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
Kojto 99:dbbf35b96557 1501 #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
Kojto 99:dbbf35b96557 1502 #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1503 #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1504 #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
Kojto 99:dbbf35b96557 1505 #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
Kojto 99:dbbf35b96557 1506 #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
Kojto 99:dbbf35b96557 1507 #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
Kojto 99:dbbf35b96557 1508 #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
Kojto 99:dbbf35b96557 1509 #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
Kojto 99:dbbf35b96557 1510 #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
Kojto 99:dbbf35b96557 1511 #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
Kojto 99:dbbf35b96557 1512 #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
Kojto 99:dbbf35b96557 1513 #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
Kojto 99:dbbf35b96557 1514 #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
Kojto 99:dbbf35b96557 1515 #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
Kojto 99:dbbf35b96557 1516 #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
Kojto 99:dbbf35b96557 1517 #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
Kojto 99:dbbf35b96557 1518 #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1519 #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1520 #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
Kojto 99:dbbf35b96557 1521 #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
Kojto 99:dbbf35b96557 1522 #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
Kojto 99:dbbf35b96557 1523 #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
Kojto 99:dbbf35b96557 1524 #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
Kojto 99:dbbf35b96557 1525 #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
Kojto 99:dbbf35b96557 1526 #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1527 #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1528 #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
Kojto 99:dbbf35b96557 1529 #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
Kojto 99:dbbf35b96557 1530 #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1531 #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1532 #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
Kojto 99:dbbf35b96557 1533 #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
Kojto 99:dbbf35b96557 1534 #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
Kojto 99:dbbf35b96557 1535 #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
Kojto 99:dbbf35b96557 1536 #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
Kojto 99:dbbf35b96557 1537 #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
Kojto 99:dbbf35b96557 1538 #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1539 #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1540 #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
Kojto 99:dbbf35b96557 1541 #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
Kojto 99:dbbf35b96557 1542 #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
Kojto 99:dbbf35b96557 1543 #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
Kojto 99:dbbf35b96557 1544 #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1545 #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1546 #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
Kojto 99:dbbf35b96557 1547 #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
Kojto 99:dbbf35b96557 1548 #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
Kojto 99:dbbf35b96557 1549 #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
Kojto 99:dbbf35b96557 1550 #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1551 #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1552 #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
Kojto 99:dbbf35b96557 1553 #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
Kojto 99:dbbf35b96557 1554 #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
Kojto 99:dbbf35b96557 1555 #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
Kojto 99:dbbf35b96557 1556 #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1557 #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1558 #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
Kojto 99:dbbf35b96557 1559 #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
Kojto 99:dbbf35b96557 1560 #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
Kojto 99:dbbf35b96557 1561 #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
Kojto 99:dbbf35b96557 1562 #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1563 #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1564 #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
Kojto 99:dbbf35b96557 1565 #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
Kojto 99:dbbf35b96557 1566 #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
Kojto 99:dbbf35b96557 1567 #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
Kojto 99:dbbf35b96557 1568 #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1569 #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1570 #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
Kojto 99:dbbf35b96557 1571 #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
Kojto 99:dbbf35b96557 1572 #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
Kojto 99:dbbf35b96557 1573 #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
Kojto 99:dbbf35b96557 1574 #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1575 #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1576 #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
Kojto 99:dbbf35b96557 1577 #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
Kojto 99:dbbf35b96557 1578 #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
Kojto 99:dbbf35b96557 1579 #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
Kojto 99:dbbf35b96557 1580 #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1581 #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1582 #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
Kojto 99:dbbf35b96557 1583 #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
Kojto 99:dbbf35b96557 1584 #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
Kojto 99:dbbf35b96557 1585 #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
Kojto 99:dbbf35b96557 1586 #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1587 #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1588 #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
Kojto 99:dbbf35b96557 1589 #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
Kojto 99:dbbf35b96557 1590 #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
Kojto 99:dbbf35b96557 1591 #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
Kojto 99:dbbf35b96557 1592 #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1593 #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1594 #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
Kojto 99:dbbf35b96557 1595 #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
Kojto 99:dbbf35b96557 1596 #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
Kojto 99:dbbf35b96557 1597 #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
Kojto 99:dbbf35b96557 1598 #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1599 #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1600 #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
Kojto 99:dbbf35b96557 1601 #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
Kojto 99:dbbf35b96557 1602 #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
Kojto 99:dbbf35b96557 1603 #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
Kojto 99:dbbf35b96557 1604 #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1605 #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1606 #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
Kojto 99:dbbf35b96557 1607 #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
Kojto 99:dbbf35b96557 1608 #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
Kojto 99:dbbf35b96557 1609 #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
Kojto 99:dbbf35b96557 1610 #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1611 #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1612 #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
Kojto 99:dbbf35b96557 1613 #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
Kojto 99:dbbf35b96557 1614 #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
Kojto 99:dbbf35b96557 1615 #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
Kojto 99:dbbf35b96557 1616 #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1617 #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1618 #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
Kojto 99:dbbf35b96557 1619 #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
Kojto 99:dbbf35b96557 1620 #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
Kojto 99:dbbf35b96557 1621 #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
Kojto 99:dbbf35b96557 1622 #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1623 #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1624 #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
Kojto 99:dbbf35b96557 1625 #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
Kojto 99:dbbf35b96557 1626 #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
Kojto 99:dbbf35b96557 1627 #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
Kojto 99:dbbf35b96557 1628 #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1629 #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1630 #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
Kojto 99:dbbf35b96557 1631 #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
Kojto 99:dbbf35b96557 1632 #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
Kojto 99:dbbf35b96557 1633 #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
Kojto 99:dbbf35b96557 1634 #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1635 #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1636 #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
Kojto 99:dbbf35b96557 1637 #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
Kojto 99:dbbf35b96557 1638 #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
Kojto 99:dbbf35b96557 1639 #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
Kojto 99:dbbf35b96557 1640 #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1641 #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1642 #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
Kojto 99:dbbf35b96557 1643 #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
Kojto 99:dbbf35b96557 1644 #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
Kojto 99:dbbf35b96557 1645 #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
Kojto 99:dbbf35b96557 1646 #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1647 #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1648 #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
Kojto 99:dbbf35b96557 1649 #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
Kojto 99:dbbf35b96557 1650 #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
Kojto 99:dbbf35b96557 1651 #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
Kojto 99:dbbf35b96557 1652 #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1653 #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1654 #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
Kojto 99:dbbf35b96557 1655 #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
Kojto 99:dbbf35b96557 1656 #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
Kojto 99:dbbf35b96557 1657 #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
Kojto 99:dbbf35b96557 1658 #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1659 #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1660 #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
Kojto 99:dbbf35b96557 1661 #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
Kojto 99:dbbf35b96557 1662 #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
Kojto 99:dbbf35b96557 1663 #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
Kojto 99:dbbf35b96557 1664 #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1665 #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1666 #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
Kojto 99:dbbf35b96557 1667 #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
Kojto 99:dbbf35b96557 1668 #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto 99:dbbf35b96557 1669 #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto 99:dbbf35b96557 1670 #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
Kojto 99:dbbf35b96557 1671 #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
Kojto 99:dbbf35b96557 1672 #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1673 #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1674 #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
Kojto 99:dbbf35b96557 1675 #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
Kojto 99:dbbf35b96557 1676 #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
Kojto 99:dbbf35b96557 1677 #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
Kojto 99:dbbf35b96557 1678 #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1679 #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1680 #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
Kojto 99:dbbf35b96557 1681 #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
Kojto 99:dbbf35b96557 1682 #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
Kojto 99:dbbf35b96557 1683 #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
Kojto 99:dbbf35b96557 1684 #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1685 #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1686 #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
Kojto 99:dbbf35b96557 1687 #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
Kojto 99:dbbf35b96557 1688 #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
Kojto 99:dbbf35b96557 1689 #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
Kojto 99:dbbf35b96557 1690 #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1691 #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1692 #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
Kojto 99:dbbf35b96557 1693 #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
Kojto 99:dbbf35b96557 1694 #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
Kojto 99:dbbf35b96557 1695 #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
Kojto 99:dbbf35b96557 1696 #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1697 #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1698 #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1699 #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1700 #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
Kojto 99:dbbf35b96557 1701 #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
Kojto 99:dbbf35b96557 1702 #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1703 #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1704 #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
Kojto 99:dbbf35b96557 1705 #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
Kojto 99:dbbf35b96557 1706 #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
Kojto 99:dbbf35b96557 1707 #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
Kojto 99:dbbf35b96557 1708 #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1709 #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1710 #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
Kojto 99:dbbf35b96557 1711 #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
Kojto 99:dbbf35b96557 1712 #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
Kojto 99:dbbf35b96557 1713 #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
Kojto 99:dbbf35b96557 1714 #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1715 #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1716 #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
Kojto 99:dbbf35b96557 1717 #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
Kojto 99:dbbf35b96557 1718 #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
Kojto 99:dbbf35b96557 1719 #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
Kojto 99:dbbf35b96557 1720 #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
Kojto 99:dbbf35b96557 1721 #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
Kojto 99:dbbf35b96557 1722 #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
Kojto 99:dbbf35b96557 1723 #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
Kojto 99:dbbf35b96557 1724 #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
Kojto 99:dbbf35b96557 1725 #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
Kojto 99:dbbf35b96557 1726 #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
Kojto 99:dbbf35b96557 1727 #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
Kojto 99:dbbf35b96557 1728 #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
Kojto 99:dbbf35b96557 1729 #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
Kojto 99:dbbf35b96557 1730 #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
Kojto 99:dbbf35b96557 1731 #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
Kojto 99:dbbf35b96557 1732 #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
Kojto 99:dbbf35b96557 1733 #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
Kojto 99:dbbf35b96557 1734 #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
Kojto 99:dbbf35b96557 1735 #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
Kojto 99:dbbf35b96557 1736 #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
Kojto 99:dbbf35b96557 1737 #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
Kojto 99:dbbf35b96557 1738 #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
Kojto 99:dbbf35b96557 1739 #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
Kojto 99:dbbf35b96557 1740 #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1741 #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1742 #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
Kojto 99:dbbf35b96557 1743 #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
Kojto 99:dbbf35b96557 1744 #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
Kojto 99:dbbf35b96557 1745 #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
Kojto 99:dbbf35b96557 1746 #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1747 #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1748 #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
Kojto 99:dbbf35b96557 1749 #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
Kojto 99:dbbf35b96557 1750 #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
Kojto 99:dbbf35b96557 1751 #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
Kojto 99:dbbf35b96557 1752 #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1753 #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1754 #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
Kojto 99:dbbf35b96557 1755 #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
Kojto 99:dbbf35b96557 1756 #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
Kojto 99:dbbf35b96557 1757 #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
Kojto 99:dbbf35b96557 1758 #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1759 #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1760 #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
Kojto 99:dbbf35b96557 1761 #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
Kojto 99:dbbf35b96557 1762 #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
Kojto 99:dbbf35b96557 1763 #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
Kojto 99:dbbf35b96557 1764 #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1765 #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1766 #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
Kojto 99:dbbf35b96557 1767 #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
Kojto 99:dbbf35b96557 1768 #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
Kojto 99:dbbf35b96557 1769 #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
Kojto 99:dbbf35b96557 1770 #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1771 #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1772 #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
Kojto 99:dbbf35b96557 1773 #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
Kojto 99:dbbf35b96557 1774 #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
Kojto 99:dbbf35b96557 1775 #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
Kojto 99:dbbf35b96557 1776 #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1777 #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1778 #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
Kojto 99:dbbf35b96557 1779 #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
Kojto 99:dbbf35b96557 1780 #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
Kojto 99:dbbf35b96557 1781 #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
Kojto 99:dbbf35b96557 1782 #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1783 #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1784 #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
Kojto 99:dbbf35b96557 1785 #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
Kojto 99:dbbf35b96557 1786 #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
Kojto 99:dbbf35b96557 1787 #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
Kojto 99:dbbf35b96557 1788 #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1789 #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1790 #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
Kojto 99:dbbf35b96557 1791 #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
Kojto 99:dbbf35b96557 1792 #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
Kojto 99:dbbf35b96557 1793 #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
Kojto 99:dbbf35b96557 1794 #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1795 #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1796 #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
Kojto 99:dbbf35b96557 1797 #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
Kojto 99:dbbf35b96557 1798 #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
Kojto 99:dbbf35b96557 1799 #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
Kojto 99:dbbf35b96557 1800 #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
Kojto 99:dbbf35b96557 1801 #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
Kojto 99:dbbf35b96557 1802 #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
Kojto 99:dbbf35b96557 1803 #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
Kojto 99:dbbf35b96557 1804 #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1805 #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1806 #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
Kojto 99:dbbf35b96557 1807 #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
Kojto 99:dbbf35b96557 1808 #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
Kojto 99:dbbf35b96557 1809 #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
Kojto 99:dbbf35b96557 1810 #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1811 #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1812 #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
Kojto 99:dbbf35b96557 1813 #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
Kojto 99:dbbf35b96557 1814 #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
Kojto 99:dbbf35b96557 1815 #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
Kojto 99:dbbf35b96557 1816 #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1817 #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1818 #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
Kojto 99:dbbf35b96557 1819 #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
Kojto 99:dbbf35b96557 1820 #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
Kojto 99:dbbf35b96557 1821 #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
Kojto 99:dbbf35b96557 1822 #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1823 #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1824 #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
Kojto 99:dbbf35b96557 1825 #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
Kojto 99:dbbf35b96557 1826 #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
Kojto 99:dbbf35b96557 1827 #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
Kojto 99:dbbf35b96557 1828 #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1829 #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1830 #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
Kojto 99:dbbf35b96557 1831 #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
Kojto 99:dbbf35b96557 1832 #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
Kojto 99:dbbf35b96557 1833 #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
Kojto 99:dbbf35b96557 1834 #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1835 #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1836 #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
Kojto 99:dbbf35b96557 1837 #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
Kojto 99:dbbf35b96557 1838 #define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
Kojto 99:dbbf35b96557 1839 #define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
Kojto 99:dbbf35b96557 1840 #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1841 #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1842 #define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
Kojto 99:dbbf35b96557 1843 #define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
Kojto 99:dbbf35b96557 1844 #define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
Kojto 99:dbbf35b96557 1845 #define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
Kojto 99:dbbf35b96557 1846 #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1847 #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1848 #define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
Kojto 99:dbbf35b96557 1849 #define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
Kojto 99:dbbf35b96557 1850 #define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
Kojto 99:dbbf35b96557 1851 #define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
Kojto 99:dbbf35b96557 1852 #define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
Kojto 99:dbbf35b96557 1853 #define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
Kojto 99:dbbf35b96557 1854 #define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
Kojto 99:dbbf35b96557 1855 #define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
Kojto 99:dbbf35b96557 1856 #define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
Kojto 99:dbbf35b96557 1857 #define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
Kojto 99:dbbf35b96557 1858 #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
Kojto 99:dbbf35b96557 1859 #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
Kojto 99:dbbf35b96557 1860 #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
Kojto 99:dbbf35b96557 1861 #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1862 #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1863 #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
Kojto 99:dbbf35b96557 1864 #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
Kojto 99:dbbf35b96557 1865 #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
Kojto 99:dbbf35b96557 1866 #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
Kojto 99:dbbf35b96557 1867 #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
Kojto 99:dbbf35b96557 1868 #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1869 #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1870 #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
Kojto 99:dbbf35b96557 1871 #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
Kojto 99:dbbf35b96557 1872 #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
Kojto 99:dbbf35b96557 1873 #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
Kojto 99:dbbf35b96557 1874 #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
Kojto 99:dbbf35b96557 1875 #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
Kojto 99:dbbf35b96557 1876 #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1877 #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1878 #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
Kojto 99:dbbf35b96557 1879 #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
Kojto 99:dbbf35b96557 1880 #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
Kojto 99:dbbf35b96557 1881 #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
Kojto 99:dbbf35b96557 1882 #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1883 #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1884 #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
Kojto 99:dbbf35b96557 1885 #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
Kojto 99:dbbf35b96557 1886 #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1887 #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1888 #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
Kojto 99:dbbf35b96557 1889 #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
Kojto 99:dbbf35b96557 1890 #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
Kojto 99:dbbf35b96557 1891 #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
Kojto 99:dbbf35b96557 1892
Kojto 99:dbbf35b96557 1893 #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto 99:dbbf35b96557 1894 #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto 99:dbbf35b96557 1895 #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1896 #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1897 #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
Kojto 99:dbbf35b96557 1898 #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
Kojto 99:dbbf35b96557 1899 #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
Kojto 99:dbbf35b96557 1900 #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
Kojto 99:dbbf35b96557 1901 #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1902 #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1903 #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1904 #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1905 #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1906 #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1907 #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1908 #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1909 #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
Kojto 99:dbbf35b96557 1910 #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
Kojto 99:dbbf35b96557 1911 #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
Kojto 99:dbbf35b96557 1912 #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
Kojto 99:dbbf35b96557 1913 #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
Kojto 99:dbbf35b96557 1914 #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1915 #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1916 #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
Kojto 99:dbbf35b96557 1917 #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
Kojto 99:dbbf35b96557 1918 #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
Kojto 99:dbbf35b96557 1919 #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
Kojto 99:dbbf35b96557 1920 #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
Kojto 99:dbbf35b96557 1921 #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1922 #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1923 #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
Kojto 99:dbbf35b96557 1924 #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
Kojto 99:dbbf35b96557 1925 #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
Kojto 99:dbbf35b96557 1926 #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
Kojto 99:dbbf35b96557 1927 #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1928 #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1929 #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
Kojto 99:dbbf35b96557 1930 #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
Kojto 99:dbbf35b96557 1931 #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
Kojto 99:dbbf35b96557 1932 #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
Kojto 99:dbbf35b96557 1933 #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1934 #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1935 #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1936 #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1937 #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1938 #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1939 #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1940 #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1941 #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1942 #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1943 #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1944 #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1945 #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1946 #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
Kojto 99:dbbf35b96557 1947 #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
Kojto 99:dbbf35b96557 1948 #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1949 #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1950 #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
Kojto 99:dbbf35b96557 1951 #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
Kojto 99:dbbf35b96557 1952 #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
Kojto 99:dbbf35b96557 1953 #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
Kojto 99:dbbf35b96557 1954 #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
Kojto 99:dbbf35b96557 1955 #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
Kojto 99:dbbf35b96557 1956 #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1957 #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1958 #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
Kojto 99:dbbf35b96557 1959 #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
Kojto 99:dbbf35b96557 1960 #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
Kojto 99:dbbf35b96557 1961 #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
Kojto 99:dbbf35b96557 1962 #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1963 #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1964 #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
Kojto 99:dbbf35b96557 1965 #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
Kojto 99:dbbf35b96557 1966 #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
Kojto 99:dbbf35b96557 1967 #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
Kojto 99:dbbf35b96557 1968 #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1969 #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1970 #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
Kojto 99:dbbf35b96557 1971 #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
Kojto 99:dbbf35b96557 1972 #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
Kojto 99:dbbf35b96557 1973 #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
Kojto 99:dbbf35b96557 1974 #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1975 #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1976 #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
Kojto 99:dbbf35b96557 1977 #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
Kojto 99:dbbf35b96557 1978 #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
Kojto 99:dbbf35b96557 1979 #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1980 #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1981 #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
Kojto 99:dbbf35b96557 1982 #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
Kojto 99:dbbf35b96557 1983 #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
Kojto 99:dbbf35b96557 1984 #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
Kojto 99:dbbf35b96557 1985 #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
Kojto 99:dbbf35b96557 1986 #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
Kojto 99:dbbf35b96557 1987 #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1988 #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1989 #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
Kojto 99:dbbf35b96557 1990 #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
Kojto 99:dbbf35b96557 1991 #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
Kojto 99:dbbf35b96557 1992 #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
Kojto 99:dbbf35b96557 1993 #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 1994 #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 1995 #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
Kojto 99:dbbf35b96557 1996 #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
Kojto 99:dbbf35b96557 1997 #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
Kojto 99:dbbf35b96557 1998 #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
Kojto 99:dbbf35b96557 1999 #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2000 #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2001 #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2002 #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2003 #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto 99:dbbf35b96557 2004 #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto 99:dbbf35b96557 2005 #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2006 #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2007 #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2008 #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
Kojto 106:ba1f97679dad 2009 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
Kojto 106:ba1f97679dad 2010 #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
Kojto 99:dbbf35b96557 2011 #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
Kojto 99:dbbf35b96557 2012 #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
Kojto 99:dbbf35b96557 2013 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
Kojto 106:ba1f97679dad 2014 #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
Kojto 106:ba1f97679dad 2015 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
Kojto 106:ba1f97679dad 2016 #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
Kojto 99:dbbf35b96557 2017 #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
Kojto 99:dbbf35b96557 2018 #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2019 #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2020 #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2021 #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2022 #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2023 #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2024 #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2025 #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2026 #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2027 #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
Kojto 99:dbbf35b96557 2028 #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
Kojto 99:dbbf35b96557 2029 #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2030 #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2031 #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto 99:dbbf35b96557 2032 #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto 99:dbbf35b96557 2033 #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2034 #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2035 #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
Kojto 99:dbbf35b96557 2036 #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
Kojto 99:dbbf35b96557 2037 #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
Kojto 99:dbbf35b96557 2038 #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
Kojto 99:dbbf35b96557 2039 #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
Kojto 99:dbbf35b96557 2040 #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
Kojto 99:dbbf35b96557 2041
Kojto 99:dbbf35b96557 2042 /* alias define maintained for legacy */
Kojto 99:dbbf35b96557 2043 #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
Kojto 99:dbbf35b96557 2044 #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
Kojto 99:dbbf35b96557 2045
Kojto 106:ba1f97679dad 2046 #if defined(STM32F4)
Kojto 106:ba1f97679dad 2047 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto 106:ba1f97679dad 2048 #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
Kojto 106:ba1f97679dad 2049 #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
Kojto 106:ba1f97679dad 2050 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
Kojto 106:ba1f97679dad 2051 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
Kojto 106:ba1f97679dad 2052 #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
Kojto 106:ba1f97679dad 2053 #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
Kojto 106:ba1f97679dad 2054 #define Sdmmc1ClockSelection SdioClockSelection
Kojto 106:ba1f97679dad 2055 #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
Kojto 106:ba1f97679dad 2056 #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
Kojto 106:ba1f97679dad 2057 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
Kojto 106:ba1f97679dad 2058 #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
Kojto 106:ba1f97679dad 2059 #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
Kojto 106:ba1f97679dad 2060 #endif
Kojto 106:ba1f97679dad 2061
Kojto 106:ba1f97679dad 2062 #if defined(STM32F7) || defined(STM32L4)
Kojto 106:ba1f97679dad 2063 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
Kojto 106:ba1f97679dad 2064 #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
Kojto 106:ba1f97679dad 2065 #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
Kojto 106:ba1f97679dad 2066 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
Kojto 106:ba1f97679dad 2067 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
Kojto 106:ba1f97679dad 2068 #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
Kojto 106:ba1f97679dad 2069 #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
Kojto 106:ba1f97679dad 2070 #define SdioClockSelection Sdmmc1ClockSelection
Kojto 106:ba1f97679dad 2071 #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
Kojto 106:ba1f97679dad 2072 #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
Kojto 106:ba1f97679dad 2073 #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
Kojto 106:ba1f97679dad 2074 #endif
Kojto 106:ba1f97679dad 2075
Kojto 106:ba1f97679dad 2076 #if defined(STM32F7)
Kojto 106:ba1f97679dad 2077 #define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
Kojto 106:ba1f97679dad 2078 #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
Kojto 106:ba1f97679dad 2079 #endif
Kojto 106:ba1f97679dad 2080
Kojto 99:dbbf35b96557 2081 #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
Kojto 99:dbbf35b96557 2082 #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
Kojto 99:dbbf35b96557 2083
Kojto 99:dbbf35b96557 2084 #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
Kojto 99:dbbf35b96557 2085
Kojto 99:dbbf35b96557 2086 #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
Kojto 99:dbbf35b96557 2087 #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
Kojto 99:dbbf35b96557 2088 #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
Kojto 99:dbbf35b96557 2089 #define IS_RCC_HCLK_DIV IS_RCC_PCLK
Kojto 99:dbbf35b96557 2090
Kojto 99:dbbf35b96557 2091 #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
Kojto 99:dbbf35b96557 2092 #define RCC_MCO_NODIV RCC_MCODIV_1
Kojto 99:dbbf35b96557 2093 #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
Kojto 99:dbbf35b96557 2094
Kojto 99:dbbf35b96557 2095 #define HSION_BitNumber RCC_HSION_BIT_NUMBER
Kojto 99:dbbf35b96557 2096 #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
Kojto 99:dbbf35b96557 2097 #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
Kojto 99:dbbf35b96557 2098 #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
Kojto 99:dbbf35b96557 2099 #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
Kojto 99:dbbf35b96557 2100 #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
Kojto 99:dbbf35b96557 2101 #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
Kojto 99:dbbf35b96557 2102 #define LSION_BitNumber RCC_LSION_BIT_NUMBER
Kojto 99:dbbf35b96557 2103 #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
Kojto 99:dbbf35b96557 2104 #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
Kojto 99:dbbf35b96557 2105
Kojto 99:dbbf35b96557 2106 #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
Kojto 99:dbbf35b96557 2107 #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
Kojto 99:dbbf35b96557 2108 #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
Kojto 99:dbbf35b96557 2109 #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
Kojto 99:dbbf35b96557 2110 #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
Kojto 99:dbbf35b96557 2111 #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
Kojto 99:dbbf35b96557 2112
Kojto 99:dbbf35b96557 2113 #define CR_HSION_BB RCC_CR_HSION_BB
Kojto 99:dbbf35b96557 2114 #define CR_CSSON_BB RCC_CR_CSSON_BB
Kojto 99:dbbf35b96557 2115 #define CR_PLLON_BB RCC_CR_PLLON_BB
Kojto 99:dbbf35b96557 2116 #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
Kojto 99:dbbf35b96557 2117 #define CR_MSION_BB RCC_CR_MSION_BB
Kojto 99:dbbf35b96557 2118 #define CSR_LSION_BB RCC_CSR_LSION_BB
Kojto 99:dbbf35b96557 2119 #define CSR_LSEON_BB RCC_CSR_LSEON_BB
Kojto 99:dbbf35b96557 2120 #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
Kojto 99:dbbf35b96557 2121 #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
Kojto 99:dbbf35b96557 2122 #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
Kojto 99:dbbf35b96557 2123 #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
Kojto 99:dbbf35b96557 2124 #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
Kojto 99:dbbf35b96557 2125 #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
Kojto 99:dbbf35b96557 2126 #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
Kojto 99:dbbf35b96557 2127 #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
Kojto 99:dbbf35b96557 2128
Kojto 99:dbbf35b96557 2129 /**
Kojto 99:dbbf35b96557 2130 * @}
Kojto 99:dbbf35b96557 2131 */
Kojto 99:dbbf35b96557 2132
Kojto 99:dbbf35b96557 2133 /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2134 * @{
Kojto 99:dbbf35b96557 2135 */
Kojto 99:dbbf35b96557 2136 #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
Kojto 99:dbbf35b96557 2137
Kojto 99:dbbf35b96557 2138 /**
Kojto 99:dbbf35b96557 2139 * @}
Kojto 99:dbbf35b96557 2140 */
Kojto 99:dbbf35b96557 2141
Kojto 99:dbbf35b96557 2142 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2143 * @{
Kojto 99:dbbf35b96557 2144 */
Kojto 99:dbbf35b96557 2145
Kojto 99:dbbf35b96557 2146 #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 2147 #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 2148 #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
Kojto 106:ba1f97679dad 2149
Kojto 99:dbbf35b96557 2150 #if defined (STM32F1)
Kojto 99:dbbf35b96557 2151 #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
Kojto 99:dbbf35b96557 2152
Kojto 99:dbbf35b96557 2153 #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
Kojto 99:dbbf35b96557 2154
Kojto 99:dbbf35b96557 2155 #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
Kojto 99:dbbf35b96557 2156
Kojto 99:dbbf35b96557 2157 #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
Kojto 99:dbbf35b96557 2158
Kojto 99:dbbf35b96557 2159 #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
Kojto 99:dbbf35b96557 2160 #else
Kojto 99:dbbf35b96557 2161 #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
Kojto 99:dbbf35b96557 2162 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
Kojto 99:dbbf35b96557 2163 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
Kojto 99:dbbf35b96557 2164 #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
Kojto 99:dbbf35b96557 2165 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
Kojto 99:dbbf35b96557 2166 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
Kojto 99:dbbf35b96557 2167 #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
Kojto 99:dbbf35b96557 2168 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
Kojto 99:dbbf35b96557 2169 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
Kojto 99:dbbf35b96557 2170 #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
Kojto 99:dbbf35b96557 2171 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
Kojto 99:dbbf35b96557 2172 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
Kojto 99:dbbf35b96557 2173 #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
Kojto 99:dbbf35b96557 2174 (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
Kojto 99:dbbf35b96557 2175 __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
Kojto 99:dbbf35b96557 2176 #endif /* STM32F1 */
Kojto 99:dbbf35b96557 2177
Kojto 99:dbbf35b96557 2178 #define IS_ALARM IS_RTC_ALARM
Kojto 99:dbbf35b96557 2179 #define IS_ALARM_MASK IS_RTC_ALARM_MASK
Kojto 99:dbbf35b96557 2180 #define IS_TAMPER IS_RTC_TAMPER
Kojto 99:dbbf35b96557 2181 #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
Kojto 99:dbbf35b96557 2182 #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
Kojto 99:dbbf35b96557 2183 #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
Kojto 99:dbbf35b96557 2184 #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
Kojto 99:dbbf35b96557 2185 #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
Kojto 99:dbbf35b96557 2186 #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
Kojto 99:dbbf35b96557 2187 #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
Kojto 99:dbbf35b96557 2188 #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
Kojto 99:dbbf35b96557 2189 #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
Kojto 99:dbbf35b96557 2190 #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
Kojto 99:dbbf35b96557 2191 #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
Kojto 99:dbbf35b96557 2192
Kojto 99:dbbf35b96557 2193 #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
Kojto 99:dbbf35b96557 2194 #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
Kojto 99:dbbf35b96557 2195
Kojto 99:dbbf35b96557 2196 /**
Kojto 99:dbbf35b96557 2197 * @}
Kojto 99:dbbf35b96557 2198 */
Kojto 99:dbbf35b96557 2199
Kojto 99:dbbf35b96557 2200 /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2201 * @{
Kojto 99:dbbf35b96557 2202 */
Kojto 99:dbbf35b96557 2203
Kojto 99:dbbf35b96557 2204 #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
Kojto 99:dbbf35b96557 2205 #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
Kojto 106:ba1f97679dad 2206
Kojto 106:ba1f97679dad 2207 #if defined(STM32F4)
Kojto 106:ba1f97679dad 2208 #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
Kojto 106:ba1f97679dad 2209 #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
Kojto 106:ba1f97679dad 2210 #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
Kojto 106:ba1f97679dad 2211 #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
Kojto 106:ba1f97679dad 2212 #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
Kojto 106:ba1f97679dad 2213 #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
Kojto 106:ba1f97679dad 2214 #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
Kojto 106:ba1f97679dad 2215 #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
Kojto 106:ba1f97679dad 2216 #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
Kojto 106:ba1f97679dad 2217 #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
Kojto 106:ba1f97679dad 2218 #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
Kojto 106:ba1f97679dad 2219 #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
Kojto 106:ba1f97679dad 2220 #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
Kojto 106:ba1f97679dad 2221 #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
Kojto 106:ba1f97679dad 2222 #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
Kojto 106:ba1f97679dad 2223 #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
Kojto 106:ba1f97679dad 2224 #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
Kojto 106:ba1f97679dad 2225 #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
Kojto 106:ba1f97679dad 2226 #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
Kojto 106:ba1f97679dad 2227 #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
Kojto 106:ba1f97679dad 2228 /* alias CMSIS */
Kojto 106:ba1f97679dad 2229 #define SDMMC1_IRQn SDIO_IRQn
Kojto 106:ba1f97679dad 2230 #define SDMMC1_IRQHandler SDIO_IRQHandler
Kojto 106:ba1f97679dad 2231 #endif
Kojto 106:ba1f97679dad 2232
Kojto 106:ba1f97679dad 2233 #if defined(STM32F7) || defined(STM32L4)
Kojto 106:ba1f97679dad 2234 #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
Kojto 106:ba1f97679dad 2235 #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
Kojto 106:ba1f97679dad 2236 #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
Kojto 106:ba1f97679dad 2237 #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
Kojto 106:ba1f97679dad 2238 #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
Kojto 106:ba1f97679dad 2239 #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
Kojto 106:ba1f97679dad 2240 #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
Kojto 106:ba1f97679dad 2241 #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
Kojto 106:ba1f97679dad 2242 #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
Kojto 106:ba1f97679dad 2243 #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
Kojto 106:ba1f97679dad 2244 #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
Kojto 106:ba1f97679dad 2245 #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
Kojto 106:ba1f97679dad 2246 #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
Kojto 106:ba1f97679dad 2247 #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
Kojto 106:ba1f97679dad 2248 #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
Kojto 106:ba1f97679dad 2249 #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
Kojto 106:ba1f97679dad 2250 #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
Kojto 106:ba1f97679dad 2251 #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
Kojto 106:ba1f97679dad 2252 #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
Kojto 106:ba1f97679dad 2253 #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
Kojto 106:ba1f97679dad 2254 /* alias CMSIS for compatibilities */
Kojto 106:ba1f97679dad 2255 #define SDIO_IRQn SDMMC1_IRQn
Kojto 106:ba1f97679dad 2256 #define SDIO_IRQHandler SDMMC1_IRQHandler
Kojto 106:ba1f97679dad 2257 #endif
Kojto 99:dbbf35b96557 2258 /**
Kojto 99:dbbf35b96557 2259 * @}
Kojto 99:dbbf35b96557 2260 */
Kojto 99:dbbf35b96557 2261
Kojto 99:dbbf35b96557 2262 /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2263 * @{
Kojto 99:dbbf35b96557 2264 */
Kojto 99:dbbf35b96557 2265
Kojto 99:dbbf35b96557 2266 #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
Kojto 99:dbbf35b96557 2267 #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
Kojto 99:dbbf35b96557 2268 #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
Kojto 99:dbbf35b96557 2269 #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
Kojto 99:dbbf35b96557 2270 #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
Kojto 99:dbbf35b96557 2271 #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
Kojto 99:dbbf35b96557 2272
Kojto 99:dbbf35b96557 2273 #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2274 #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2275
Kojto 106:ba1f97679dad 2276 #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
Kojto 99:dbbf35b96557 2277
Kojto 99:dbbf35b96557 2278 /**
Kojto 99:dbbf35b96557 2279 * @}
Kojto 99:dbbf35b96557 2280 */
Kojto 99:dbbf35b96557 2281
Kojto 99:dbbf35b96557 2282 /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2283 * @{
Kojto 99:dbbf35b96557 2284 */
Kojto 99:dbbf35b96557 2285 #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
Kojto 99:dbbf35b96557 2286 #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
Kojto 99:dbbf35b96557 2287 #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
Kojto 99:dbbf35b96557 2288 #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
Kojto 99:dbbf35b96557 2289 #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
Kojto 99:dbbf35b96557 2290 #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
Kojto 99:dbbf35b96557 2291 #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
Kojto 99:dbbf35b96557 2292 #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
Kojto 99:dbbf35b96557 2293 /**
Kojto 99:dbbf35b96557 2294 * @}
Kojto 99:dbbf35b96557 2295 */
Kojto 99:dbbf35b96557 2296
Kojto 99:dbbf35b96557 2297 /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2298 * @{
Kojto 99:dbbf35b96557 2299 */
Kojto 99:dbbf35b96557 2300
Kojto 99:dbbf35b96557 2301 #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
Kojto 99:dbbf35b96557 2302 #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
Kojto 99:dbbf35b96557 2303 #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
Kojto 99:dbbf35b96557 2304
Kojto 99:dbbf35b96557 2305 /**
Kojto 99:dbbf35b96557 2306 * @}
Kojto 99:dbbf35b96557 2307 */
Kojto 99:dbbf35b96557 2308
Kojto 99:dbbf35b96557 2309 /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2310 * @{
Kojto 99:dbbf35b96557 2311 */
Kojto 99:dbbf35b96557 2312
Kojto 99:dbbf35b96557 2313 #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2314 #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto 99:dbbf35b96557 2315 #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2316 #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
Kojto 99:dbbf35b96557 2317
Kojto 99:dbbf35b96557 2318 #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
Kojto 99:dbbf35b96557 2319
Kojto 99:dbbf35b96557 2320 #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
Kojto 99:dbbf35b96557 2321 #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
Kojto 99:dbbf35b96557 2322
Kojto 99:dbbf35b96557 2323 /**
Kojto 99:dbbf35b96557 2324 * @}
Kojto 99:dbbf35b96557 2325 */
Kojto 99:dbbf35b96557 2326
Kojto 99:dbbf35b96557 2327
Kojto 99:dbbf35b96557 2328 /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2329 * @{
Kojto 99:dbbf35b96557 2330 */
Kojto 99:dbbf35b96557 2331
Kojto 99:dbbf35b96557 2332 #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
Kojto 99:dbbf35b96557 2333 #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
Kojto 99:dbbf35b96557 2334 #define __USART_ENABLE __HAL_USART_ENABLE
Kojto 99:dbbf35b96557 2335 #define __USART_DISABLE __HAL_USART_DISABLE
Kojto 99:dbbf35b96557 2336
Kojto 99:dbbf35b96557 2337 #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2338 #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
Kojto 99:dbbf35b96557 2339
Kojto 99:dbbf35b96557 2340 /**
Kojto 99:dbbf35b96557 2341 * @}
Kojto 99:dbbf35b96557 2342 */
Kojto 99:dbbf35b96557 2343
Kojto 99:dbbf35b96557 2344 /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2345 * @{
Kojto 99:dbbf35b96557 2346 */
Kojto 99:dbbf35b96557 2347 #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
Kojto 99:dbbf35b96557 2348
Kojto 99:dbbf35b96557 2349 #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
Kojto 99:dbbf35b96557 2350 #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
Kojto 99:dbbf35b96557 2351 #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto 99:dbbf35b96557 2352 #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
Kojto 99:dbbf35b96557 2353
Kojto 99:dbbf35b96557 2354 #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
Kojto 99:dbbf35b96557 2355 #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
Kojto 99:dbbf35b96557 2356 #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
Kojto 99:dbbf35b96557 2357 #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
Kojto 99:dbbf35b96557 2358
Kojto 99:dbbf35b96557 2359 #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 2360 #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 2361 #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
Kojto 99:dbbf35b96557 2362 #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 2363 #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 2364 #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 2365 #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 99:dbbf35b96557 2366
Kojto 99:dbbf35b96557 2367 #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 2368 #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 2369 #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
Kojto 99:dbbf35b96557 2370 #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 2371 #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 2372 #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 2373 #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 99:dbbf35b96557 2374 #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
Kojto 99:dbbf35b96557 2375
Kojto 99:dbbf35b96557 2376 #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 2377 #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 2378 #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
Kojto 99:dbbf35b96557 2379 #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 2380 #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
Kojto 99:dbbf35b96557 2381 #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
Kojto 99:dbbf35b96557 2382 #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
Kojto 99:dbbf35b96557 2383 #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
Kojto 99:dbbf35b96557 2384
Kojto 99:dbbf35b96557 2385 #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
Kojto 99:dbbf35b96557 2386 #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
Kojto 99:dbbf35b96557 2387
Kojto 99:dbbf35b96557 2388 #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
Kojto 99:dbbf35b96557 2389 #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
Kojto 99:dbbf35b96557 2390 /**
Kojto 99:dbbf35b96557 2391 * @}
Kojto 99:dbbf35b96557 2392 */
Kojto 99:dbbf35b96557 2393
Kojto 99:dbbf35b96557 2394 /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2395 * @{
Kojto 99:dbbf35b96557 2396 */
Kojto 99:dbbf35b96557 2397 #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
Kojto 99:dbbf35b96557 2398 #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
Kojto 99:dbbf35b96557 2399
Kojto 99:dbbf35b96557 2400 #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto 99:dbbf35b96557 2401 #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
Kojto 99:dbbf35b96557 2402
Kojto 99:dbbf35b96557 2403 #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
Kojto 99:dbbf35b96557 2404
Kojto 99:dbbf35b96557 2405 #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
Kojto 99:dbbf35b96557 2406 #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
Kojto 99:dbbf35b96557 2407 #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
Kojto 99:dbbf35b96557 2408 #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
Kojto 99:dbbf35b96557 2409 #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
Kojto 99:dbbf35b96557 2410 #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
Kojto 99:dbbf35b96557 2411 #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
Kojto 99:dbbf35b96557 2412 #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
Kojto 99:dbbf35b96557 2413 #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
Kojto 99:dbbf35b96557 2414 #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
Kojto 99:dbbf35b96557 2415 #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
Kojto 99:dbbf35b96557 2416 #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
Kojto 99:dbbf35b96557 2417
Kojto 99:dbbf35b96557 2418 #define TIM_TS_ITR0 ((uint32_t)0x0000)
Kojto 99:dbbf35b96557 2419 #define TIM_TS_ITR1 ((uint32_t)0x0010)
Kojto 99:dbbf35b96557 2420 #define TIM_TS_ITR2 ((uint32_t)0x0020)
Kojto 99:dbbf35b96557 2421 #define TIM_TS_ITR3 ((uint32_t)0x0030)
Kojto 99:dbbf35b96557 2422 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
Kojto 99:dbbf35b96557 2423 ((SELECTION) == TIM_TS_ITR1) || \
Kojto 99:dbbf35b96557 2424 ((SELECTION) == TIM_TS_ITR2) || \
Kojto 99:dbbf35b96557 2425 ((SELECTION) == TIM_TS_ITR3))
Kojto 99:dbbf35b96557 2426
Kojto 99:dbbf35b96557 2427 #define TIM_CHANNEL_1 ((uint32_t)0x0000)
Kojto 99:dbbf35b96557 2428 #define TIM_CHANNEL_2 ((uint32_t)0x0004)
Kojto 99:dbbf35b96557 2429 #define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 99:dbbf35b96557 2430 ((CHANNEL) == TIM_CHANNEL_2))
Kojto 99:dbbf35b96557 2431
Kojto 99:dbbf35b96557 2432 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
Kojto 99:dbbf35b96557 2433 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
Kojto 99:dbbf35b96557 2434
Kojto 99:dbbf35b96557 2435 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
Kojto 99:dbbf35b96557 2436 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
Kojto 99:dbbf35b96557 2437
Kojto 99:dbbf35b96557 2438 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
Kojto 99:dbbf35b96557 2439 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
Kojto 99:dbbf35b96557 2440
Kojto 99:dbbf35b96557 2441 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
Kojto 99:dbbf35b96557 2442 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
Kojto 99:dbbf35b96557 2443 /**
Kojto 99:dbbf35b96557 2444 * @}
Kojto 99:dbbf35b96557 2445 */
Kojto 99:dbbf35b96557 2446
Kojto 99:dbbf35b96557 2447 /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2448 * @{
Kojto 99:dbbf35b96557 2449 */
Kojto 99:dbbf35b96557 2450
Kojto 99:dbbf35b96557 2451 #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
Kojto 99:dbbf35b96557 2452 #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
Kojto 99:dbbf35b96557 2453 #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
Kojto 99:dbbf35b96557 2454 #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
Kojto 99:dbbf35b96557 2455 #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
Kojto 99:dbbf35b96557 2456 #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
Kojto 99:dbbf35b96557 2457 #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
Kojto 99:dbbf35b96557 2458
Kojto 99:dbbf35b96557 2459 #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
Kojto 99:dbbf35b96557 2460 #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
Kojto 99:dbbf35b96557 2461 #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
Kojto 99:dbbf35b96557 2462 /**
Kojto 99:dbbf35b96557 2463 * @}
Kojto 99:dbbf35b96557 2464 */
Kojto 99:dbbf35b96557 2465
Kojto 99:dbbf35b96557 2466 /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2467 * @{
Kojto 99:dbbf35b96557 2468 */
Kojto 99:dbbf35b96557 2469 #define __HAL_LTDC_LAYER LTDC_LAYER
Kojto 99:dbbf35b96557 2470 /**
Kojto 99:dbbf35b96557 2471 * @}
Kojto 99:dbbf35b96557 2472 */
Kojto 99:dbbf35b96557 2473
Kojto 99:dbbf35b96557 2474 /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2475 * @{
Kojto 99:dbbf35b96557 2476 */
Kojto 99:dbbf35b96557 2477 #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
Kojto 99:dbbf35b96557 2478 #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
Kojto 99:dbbf35b96557 2479 #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
Kojto 99:dbbf35b96557 2480 #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
Kojto 99:dbbf35b96557 2481 #define SAI_STREOMODE SAI_STEREOMODE
Kojto 99:dbbf35b96557 2482 #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
Kojto 99:dbbf35b96557 2483 #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
Kojto 99:dbbf35b96557 2484 #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
Kojto 99:dbbf35b96557 2485 #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
Kojto 99:dbbf35b96557 2486 #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
Kojto 99:dbbf35b96557 2487 #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
Kojto 99:dbbf35b96557 2488 #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
Kojto 99:dbbf35b96557 2489
Kojto 99:dbbf35b96557 2490 /**
Kojto 99:dbbf35b96557 2491 * @}
Kojto 99:dbbf35b96557 2492 */
Kojto 99:dbbf35b96557 2493
Kojto 99:dbbf35b96557 2494
Kojto 99:dbbf35b96557 2495 /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
Kojto 99:dbbf35b96557 2496 * @{
Kojto 99:dbbf35b96557 2497 */
Kojto 99:dbbf35b96557 2498
Kojto 99:dbbf35b96557 2499 /**
Kojto 99:dbbf35b96557 2500 * @}
Kojto 99:dbbf35b96557 2501 */
Kojto 99:dbbf35b96557 2502
Kojto 99:dbbf35b96557 2503 #ifdef __cplusplus
Kojto 99:dbbf35b96557 2504 }
Kojto 99:dbbf35b96557 2505 #endif
Kojto 99:dbbf35b96557 2506
Kojto 99:dbbf35b96557 2507 #endif /* ___STM32_HAL_LEGACY */
Kojto 99:dbbf35b96557 2508
Kojto 99:dbbf35b96557 2509 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 99:dbbf35b96557 2510