erkin yucel / mbed-os

mbed os with nrf51 internal bandgap enabled to read battery level

Dependents:   BLE_file_test BLE_Blink ExternalEncoder

targets/TARGET_NUVOTON/TARGET_M451/i2c_api.c@0:f269e3021894, 2016-10-23 (annotated)

Committer:
elessair
Date:
Sun Oct 23 15:10:02 2016 +0000
Revision:
0:f269e3021894
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
elessair 0:f269e3021894 1 /* mbed Microcontroller Library
elessair 0:f269e3021894 2 * Copyright (c) 2015-2016 Nuvoton
elessair 0:f269e3021894 3 *
elessair 0:f269e3021894 4 * Licensed under the Apache License, Version 2.0 (the "License");
elessair 0:f269e3021894 5 * you may not use this file except in compliance with the License.
elessair 0:f269e3021894 6 * You may obtain a copy of the License at
elessair 0:f269e3021894 7 *
elessair 0:f269e3021894 8 * http://www.apache.org/licenses/LICENSE-2.0
elessair 0:f269e3021894 9 *
elessair 0:f269e3021894 10 * Unless required by applicable law or agreed to in writing, software
elessair 0:f269e3021894 11 * distributed under the License is distributed on an "AS IS" BASIS,
elessair 0:f269e3021894 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
elessair 0:f269e3021894 13 * See the License for the specific language governing permissions and
elessair 0:f269e3021894 14 * limitations under the License.
elessair 0:f269e3021894 15 */
elessair 0:f269e3021894 16
elessair 0:f269e3021894 17 #include "i2c_api.h"
elessair 0:f269e3021894 18
elessair 0:f269e3021894 19 #if DEVICE_I2C
elessair 0:f269e3021894 20
elessair 0:f269e3021894 21 #include "cmsis.h"
elessair 0:f269e3021894 22 #include "pinmap.h"
elessair 0:f269e3021894 23 #include "PeripheralPins.h"
elessair 0:f269e3021894 24 #include "nu_modutil.h"
elessair 0:f269e3021894 25 #include "nu_miscutil.h"
elessair 0:f269e3021894 26 #include "nu_bitutil.h"
elessair 0:f269e3021894 27 #include "critical.h"
elessair 0:f269e3021894 28
elessair 0:f269e3021894 29 #define NU_I2C_DEBUG 0
elessair 0:f269e3021894 30
elessair 0:f269e3021894 31 #if NU_I2C_DEBUG
elessair 0:f269e3021894 32 struct i2c_s MY_I2C;
elessair 0:f269e3021894 33 struct i2c_s MY_I2C_2;
elessair 0:f269e3021894 34 char MY_I2C_STATUS[64];
elessair 0:f269e3021894 35 int MY_I2C_STATUS_POS = 0;
elessair 0:f269e3021894 36 uint32_t MY_I2C_TIMEOUT;
elessair 0:f269e3021894 37 uint32_t MY_I2C_ELAPSED;
elessair 0:f269e3021894 38 uint32_t MY_I2C_T1;
elessair 0:f269e3021894 39 uint32_t MY_I2C_T2;
elessair 0:f269e3021894 40 #endif
elessair 0:f269e3021894 41
elessair 0:f269e3021894 42 struct nu_i2c_var {
elessair 0:f269e3021894 43 i2c_t * obj;
elessair 0:f269e3021894 44 void (*vec)(void);
elessair 0:f269e3021894 45 };
elessair 0:f269e3021894 46
elessair 0:f269e3021894 47 static void i2c0_vec(void);
elessair 0:f269e3021894 48 static void i2c1_vec(void);
elessair 0:f269e3021894 49 static void i2c_irq(i2c_t *obj);
elessair 0:f269e3021894 50 static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl);
elessair 0:f269e3021894 51
elessair 0:f269e3021894 52 static struct nu_i2c_var i2c0_var = {
elessair 0:f269e3021894 53 .obj = NULL,
elessair 0:f269e3021894 54 .vec = i2c0_vec,
elessair 0:f269e3021894 55 };
elessair 0:f269e3021894 56 static struct nu_i2c_var i2c1_var = {
elessair 0:f269e3021894 57 .obj = NULL,
elessair 0:f269e3021894 58 .vec = i2c1_vec,
elessair 0:f269e3021894 59 };
elessair 0:f269e3021894 60
elessair 0:f269e3021894 61 static uint32_t i2c_modinit_mask = 0;
elessair 0:f269e3021894 62
elessair 0:f269e3021894 63 static const struct nu_modinit_s i2c_modinit_tab[] = {
elessair 0:f269e3021894 64 {I2C_0, I2C0_MODULE, 0, 0, I2C0_RST, I2C0_IRQn, &i2c0_var},
elessair 0:f269e3021894 65 {I2C_1, I2C1_MODULE, 0, 0, I2C1_RST, I2C1_IRQn, &i2c1_var},
elessair 0:f269e3021894 66
elessair 0:f269e3021894 67 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
elessair 0:f269e3021894 68 };
elessair 0:f269e3021894 69
elessair 0:f269e3021894 70 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata);
elessair 0:f269e3021894 71 static int i2c_do_write(i2c_t *obj, char data, int naklastdata);
elessair 0:f269e3021894 72 static int i2c_do_read(i2c_t *obj, char *data, int naklastdata);
elessair 0:f269e3021894 73 static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync);
elessair 0:f269e3021894 74 #define NU_I2C_TIMEOUT_STAT_INT 500000
elessair 0:f269e3021894 75 #define NU_I2C_TIMEOUT_STOP 500000
elessair 0:f269e3021894 76 static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout);
elessair 0:f269e3021894 77 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout);
elessair 0:f269e3021894 78 //static int i2c_is_stat_int(i2c_t *obj);
elessair 0:f269e3021894 79 //static int i2c_is_stop_det(i2c_t *obj);
elessair 0:f269e3021894 80 static int i2c_is_trsn_done(i2c_t *obj);
elessair 0:f269e3021894 81 static int i2c_is_tran_started(i2c_t *obj);
elessair 0:f269e3021894 82 static int i2c_addr2data(int address, int read);
elessair 0:f269e3021894 83 #if DEVICE_I2CSLAVE
elessair 0:f269e3021894 84 // Convert mbed address to BSP address.
elessair 0:f269e3021894 85 static int i2c_addr2bspaddr(int address);
elessair 0:f269e3021894 86 #endif // #if DEVICE_I2CSLAVE
elessair 0:f269e3021894 87 static void i2c_enable_int(i2c_t *obj);
elessair 0:f269e3021894 88 static void i2c_disable_int(i2c_t *obj);
elessair 0:f269e3021894 89 static int i2c_set_int(i2c_t *obj, int inten);
elessair 0:f269e3021894 90
elessair 0:f269e3021894 91
elessair 0:f269e3021894 92 #if DEVICE_I2C_ASYNCH
elessair 0:f269e3021894 93 static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length);
elessair 0:f269e3021894 94 static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable);
elessair 0:f269e3021894 95 static void i2c_rollback_vector_interrupt(i2c_t *obj);
elessair 0:f269e3021894 96 #endif
elessair 0:f269e3021894 97
elessair 0:f269e3021894 98 #define TRANCTRL_STARTED (1)
elessair 0:f269e3021894 99 #define TRANCTRL_NAKLASTDATA (1 << 1)
elessair 0:f269e3021894 100
elessair 0:f269e3021894 101 uint32_t us_ticker_read(void);
elessair 0:f269e3021894 102
elessair 0:f269e3021894 103 void i2c_init(i2c_t *obj, PinName sda, PinName scl)
elessair 0:f269e3021894 104 {
elessair 0:f269e3021894 105 uint32_t i2c_sda = pinmap_peripheral(sda, PinMap_I2C_SDA);
elessair 0:f269e3021894 106 uint32_t i2c_scl = pinmap_peripheral(scl, PinMap_I2C_SCL);
elessair 0:f269e3021894 107 obj->i2c.i2c = (I2CName) pinmap_merge(i2c_sda, i2c_scl);
elessair 0:f269e3021894 108 MBED_ASSERT((int)obj->i2c.i2c != NC);
elessair 0:f269e3021894 109
elessair 0:f269e3021894 110 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 111 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 112 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
elessair 0:f269e3021894 113
elessair 0:f269e3021894 114 // Reset this module
elessair 0:f269e3021894 115 SYS_ResetModule(modinit->rsetidx);
elessair 0:f269e3021894 116
elessair 0:f269e3021894 117 // Enable IP clock
elessair 0:f269e3021894 118 CLK_EnableModuleClock(modinit->clkidx);
elessair 0:f269e3021894 119
elessair 0:f269e3021894 120 pinmap_pinout(sda, PinMap_I2C_SDA);
elessair 0:f269e3021894 121 pinmap_pinout(scl, PinMap_I2C_SCL);
elessair 0:f269e3021894 122
elessair 0:f269e3021894 123 #if DEVICE_I2C_ASYNCH
elessair 0:f269e3021894 124 obj->i2c.dma_usage = DMA_USAGE_NEVER;
elessair 0:f269e3021894 125 obj->i2c.event = 0;
elessair 0:f269e3021894 126 obj->i2c.stop = 0;
elessair 0:f269e3021894 127 obj->i2c.address = 0;
elessair 0:f269e3021894 128 #endif
elessair 0:f269e3021894 129
elessair 0:f269e3021894 130 // NOTE: Setting I2C bus clock to 100 KHz is required. See I2C::I2C in common/I2C.cpp.
elessair 0:f269e3021894 131 I2C_Open((I2C_T *) NU_MODBASE(obj->i2c.i2c), 100000);
elessair 0:f269e3021894 132 // NOTE: INTEN bit and FSM control bits (STA, STO, SI, AA) are packed in one register CTL. We cannot control interrupt through
elessair 0:f269e3021894 133 // INTEN bit without impacting FSM control bits. Use NVIC_EnableIRQ/NVIC_DisableIRQ instead for interrupt control.
elessair 0:f269e3021894 134 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 135 i2c_base->CTL |= (I2C_CTL_INTEN_Msk | I2C_CTL_I2CEN_Msk);
elessair 0:f269e3021894 136
elessair 0:f269e3021894 137 // Enable sync-moce vector interrupt.
elessair 0:f269e3021894 138 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
elessair 0:f269e3021894 139 var->obj = obj;
elessair 0:f269e3021894 140 obj->i2c.tran_ctrl = 0;
elessair 0:f269e3021894 141 obj->i2c.stop = 0;
elessair 0:f269e3021894 142 i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
elessair 0:f269e3021894 143
elessair 0:f269e3021894 144 // Mark this module to be inited.
elessair 0:f269e3021894 145 int i = modinit - i2c_modinit_tab;
elessair 0:f269e3021894 146 i2c_modinit_mask |= 1 << i;
elessair 0:f269e3021894 147 }
elessair 0:f269e3021894 148
elessair 0:f269e3021894 149 int i2c_start(i2c_t *obj)
elessair 0:f269e3021894 150 {
elessair 0:f269e3021894 151 return i2c_do_trsn(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk, 1);
elessair 0:f269e3021894 152 }
elessair 0:f269e3021894 153
elessair 0:f269e3021894 154 int i2c_stop(i2c_t *obj)
elessair 0:f269e3021894 155 {
elessair 0:f269e3021894 156 return i2c_do_trsn(obj, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk, 1);
elessair 0:f269e3021894 157 }
elessair 0:f269e3021894 158
elessair 0:f269e3021894 159 void i2c_frequency(i2c_t *obj, int hz)
elessair 0:f269e3021894 160 {
elessair 0:f269e3021894 161 I2C_SetBusClockFreq((I2C_T *) NU_MODBASE(obj->i2c.i2c), hz);
elessair 0:f269e3021894 162 }
elessair 0:f269e3021894 163
elessair 0:f269e3021894 164 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
elessair 0:f269e3021894 165 {
elessair 0:f269e3021894 166 if (i2c_start(obj)) {
elessair 0:f269e3021894 167 i2c_stop(obj);
elessair 0:f269e3021894 168 return I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 169 }
elessair 0:f269e3021894 170
elessair 0:f269e3021894 171 if (i2c_do_write(obj, i2c_addr2data(address, 1), 0)) {
elessair 0:f269e3021894 172 i2c_stop(obj);
elessair 0:f269e3021894 173 return I2C_ERROR_NO_SLAVE;
elessair 0:f269e3021894 174 }
elessair 0:f269e3021894 175
elessair 0:f269e3021894 176 // Read in bytes
elessair 0:f269e3021894 177 length = i2c_do_tran(obj, data, length, 1, 1);
elessair 0:f269e3021894 178
elessair 0:f269e3021894 179 // If not repeated start, send stop.
elessair 0:f269e3021894 180 if (stop) {
elessair 0:f269e3021894 181 i2c_stop(obj);
elessair 0:f269e3021894 182 }
elessair 0:f269e3021894 183
elessair 0:f269e3021894 184 return length;
elessair 0:f269e3021894 185 }
elessair 0:f269e3021894 186
elessair 0:f269e3021894 187 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
elessair 0:f269e3021894 188 {
elessair 0:f269e3021894 189 if (i2c_start(obj)) {
elessair 0:f269e3021894 190 i2c_stop(obj);
elessair 0:f269e3021894 191 return I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 192 }
elessair 0:f269e3021894 193
elessair 0:f269e3021894 194 if (i2c_do_write(obj, i2c_addr2data(address, 0), 0)) {
elessair 0:f269e3021894 195 i2c_stop(obj);
elessair 0:f269e3021894 196 return I2C_ERROR_NO_SLAVE;
elessair 0:f269e3021894 197 }
elessair 0:f269e3021894 198
elessair 0:f269e3021894 199 // Write out bytes
elessair 0:f269e3021894 200 length = i2c_do_tran(obj, (char *) data, length, 0, 1);
elessair 0:f269e3021894 201
elessair 0:f269e3021894 202 if (stop) {
elessair 0:f269e3021894 203 i2c_stop(obj);
elessair 0:f269e3021894 204 }
elessair 0:f269e3021894 205
elessair 0:f269e3021894 206 return length;
elessair 0:f269e3021894 207 }
elessair 0:f269e3021894 208
elessair 0:f269e3021894 209 void i2c_reset(i2c_t *obj)
elessair 0:f269e3021894 210 {
elessair 0:f269e3021894 211 i2c_stop(obj);
elessair 0:f269e3021894 212 }
elessair 0:f269e3021894 213
elessair 0:f269e3021894 214 int i2c_byte_read(i2c_t *obj, int last)
elessair 0:f269e3021894 215 {
elessair 0:f269e3021894 216 char data = 0;
elessair 0:f269e3021894 217
elessair 0:f269e3021894 218 i2c_do_read(obj, &data, last);
elessair 0:f269e3021894 219 return data;
elessair 0:f269e3021894 220 }
elessair 0:f269e3021894 221
elessair 0:f269e3021894 222 int i2c_byte_write(i2c_t *obj, int data)
elessair 0:f269e3021894 223 {
elessair 0:f269e3021894 224 return i2c_do_write(obj, (data & 0xFF), 0);
elessair 0:f269e3021894 225 }
elessair 0:f269e3021894 226
elessair 0:f269e3021894 227 #if DEVICE_I2CSLAVE
elessair 0:f269e3021894 228
elessair 0:f269e3021894 229 // See I2CSlave.h
elessair 0:f269e3021894 230 #define NoData 0 // the slave has not been addressed
elessair 0:f269e3021894 231 #define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
elessair 0:f269e3021894 232 #define WriteGeneral 2 // the master is writing to all slave
elessair 0:f269e3021894 233 #define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
elessair 0:f269e3021894 234
elessair 0:f269e3021894 235 void i2c_slave_mode(i2c_t *obj, int enable_slave)
elessair 0:f269e3021894 236 {
elessair 0:f269e3021894 237 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 238
elessair 0:f269e3021894 239 i2c_disable_int(obj);
elessair 0:f269e3021894 240
elessair 0:f269e3021894 241 obj->i2c.slaveaddr_state = NoData;
elessair 0:f269e3021894 242
elessair 0:f269e3021894 243 // Switch to not addressed mode
elessair 0:f269e3021894 244 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 245
elessair 0:f269e3021894 246 i2c_enable_int(obj);
elessair 0:f269e3021894 247 }
elessair 0:f269e3021894 248
elessair 0:f269e3021894 249 int i2c_slave_receive(i2c_t *obj)
elessair 0:f269e3021894 250 {
elessair 0:f269e3021894 251 int slaveaddr_state;
elessair 0:f269e3021894 252
elessair 0:f269e3021894 253 i2c_disable_int(obj);
elessair 0:f269e3021894 254 slaveaddr_state = obj->i2c.slaveaddr_state;
elessair 0:f269e3021894 255 i2c_enable_int(obj);
elessair 0:f269e3021894 256
elessair 0:f269e3021894 257 return slaveaddr_state;
elessair 0:f269e3021894 258 }
elessair 0:f269e3021894 259
elessair 0:f269e3021894 260 int i2c_slave_read(i2c_t *obj, char *data, int length)
elessair 0:f269e3021894 261 {
elessair 0:f269e3021894 262 return i2c_do_tran(obj, data, length, 1, 1);
elessair 0:f269e3021894 263 }
elessair 0:f269e3021894 264
elessair 0:f269e3021894 265 int i2c_slave_write(i2c_t *obj, const char *data, int length)
elessair 0:f269e3021894 266 {
elessair 0:f269e3021894 267 return i2c_do_tran(obj, (char *) data, length, 0, 1);
elessair 0:f269e3021894 268 }
elessair 0:f269e3021894 269
elessair 0:f269e3021894 270 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
elessair 0:f269e3021894 271 {
elessair 0:f269e3021894 272 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 273
elessair 0:f269e3021894 274 i2c_disable_int(obj);
elessair 0:f269e3021894 275
elessair 0:f269e3021894 276 I2C_SetSlaveAddr(i2c_base, 0, i2c_addr2bspaddr(address), I2C_GCMODE_ENABLE);
elessair 0:f269e3021894 277
elessair 0:f269e3021894 278 i2c_enable_int(obj);
elessair 0:f269e3021894 279 }
elessair 0:f269e3021894 280
elessair 0:f269e3021894 281 static int i2c_addr2bspaddr(int address)
elessair 0:f269e3021894 282 {
elessair 0:f269e3021894 283 return (address >> 1);
elessair 0:f269e3021894 284 }
elessair 0:f269e3021894 285
elessair 0:f269e3021894 286 #endif // #if DEVICE_I2CSLAVE
elessair 0:f269e3021894 287
elessair 0:f269e3021894 288 static void i2c_enable_int(i2c_t *obj)
elessair 0:f269e3021894 289 {
elessair 0:f269e3021894 290 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 291
elessair 0:f269e3021894 292 core_util_critical_section_enter();
elessair 0:f269e3021894 293
elessair 0:f269e3021894 294 // Enable I2C interrupt
elessair 0:f269e3021894 295 NVIC_EnableIRQ(modinit->irq_n);
elessair 0:f269e3021894 296 obj->i2c.inten = 1;
elessair 0:f269e3021894 297
elessair 0:f269e3021894 298 core_util_critical_section_exit();
elessair 0:f269e3021894 299 }
elessair 0:f269e3021894 300
elessair 0:f269e3021894 301 static void i2c_disable_int(i2c_t *obj)
elessair 0:f269e3021894 302 {
elessair 0:f269e3021894 303 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 304
elessair 0:f269e3021894 305 core_util_critical_section_enter();
elessair 0:f269e3021894 306
elessair 0:f269e3021894 307 // Disable I2C interrupt
elessair 0:f269e3021894 308 NVIC_DisableIRQ(modinit->irq_n);
elessair 0:f269e3021894 309 obj->i2c.inten = 0;
elessair 0:f269e3021894 310
elessair 0:f269e3021894 311 core_util_critical_section_exit();
elessair 0:f269e3021894 312 }
elessair 0:f269e3021894 313
elessair 0:f269e3021894 314 static int i2c_set_int(i2c_t *obj, int inten)
elessair 0:f269e3021894 315 {
elessair 0:f269e3021894 316 int inten_back;
elessair 0:f269e3021894 317
elessair 0:f269e3021894 318 core_util_critical_section_enter();
elessair 0:f269e3021894 319
elessair 0:f269e3021894 320 inten_back = obj->i2c.inten;
elessair 0:f269e3021894 321
elessair 0:f269e3021894 322 core_util_critical_section_exit();
elessair 0:f269e3021894 323
elessair 0:f269e3021894 324 if (inten) {
elessair 0:f269e3021894 325 i2c_enable_int(obj);
elessair 0:f269e3021894 326 }
elessair 0:f269e3021894 327 else {
elessair 0:f269e3021894 328 i2c_disable_int(obj);
elessair 0:f269e3021894 329 }
elessair 0:f269e3021894 330
elessair 0:f269e3021894 331 return inten_back;
elessair 0:f269e3021894 332 }
elessair 0:f269e3021894 333
elessair 0:f269e3021894 334 int i2c_allow_powerdown(void)
elessair 0:f269e3021894 335 {
elessair 0:f269e3021894 336 uint32_t modinit_mask = i2c_modinit_mask;
elessair 0:f269e3021894 337 while (modinit_mask) {
elessair 0:f269e3021894 338 int i2c_idx = nu_ctz(modinit_mask);
elessair 0:f269e3021894 339 const struct nu_modinit_s *modinit = i2c_modinit_tab + i2c_idx;
elessair 0:f269e3021894 340 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
elessair 0:f269e3021894 341 if (var->obj) {
elessair 0:f269e3021894 342 // Disallow entering power-down mode if I2C transfer is enabled.
elessair 0:f269e3021894 343 if (i2c_active(var->obj)) {
elessair 0:f269e3021894 344 return 0;
elessair 0:f269e3021894 345 }
elessair 0:f269e3021894 346 }
elessair 0:f269e3021894 347 modinit_mask &= ~(1 << i2c_idx);
elessair 0:f269e3021894 348 }
elessair 0:f269e3021894 349
elessair 0:f269e3021894 350 return 1;
elessair 0:f269e3021894 351 }
elessair 0:f269e3021894 352
elessair 0:f269e3021894 353 static int i2c_do_tran(i2c_t *obj, char *buf, int length, int read, int naklastdata)
elessair 0:f269e3021894 354 {
elessair 0:f269e3021894 355 int tran_len = 0;
elessair 0:f269e3021894 356
elessair 0:f269e3021894 357 i2c_disable_int(obj);
elessair 0:f269e3021894 358 obj->i2c.tran_ctrl = naklastdata ? (TRANCTRL_STARTED | TRANCTRL_NAKLASTDATA) : TRANCTRL_STARTED;
elessair 0:f269e3021894 359 obj->i2c.tran_beg = buf;
elessair 0:f269e3021894 360 obj->i2c.tran_pos = buf;
elessair 0:f269e3021894 361 obj->i2c.tran_end = buf + length;
elessair 0:f269e3021894 362 i2c_enable_int(obj);
elessair 0:f269e3021894 363
elessair 0:f269e3021894 364 if (i2c_poll_tran_heatbeat_timeout(obj, NU_I2C_TIMEOUT_STAT_INT)) {
elessair 0:f269e3021894 365 #if NU_I2C_DEBUG
elessair 0:f269e3021894 366 MY_I2C_2 = obj->i2c;
elessair 0:f269e3021894 367 while (1);
elessair 0:f269e3021894 368 #endif
elessair 0:f269e3021894 369 }
elessair 0:f269e3021894 370 else {
elessair 0:f269e3021894 371 i2c_disable_int(obj);
elessair 0:f269e3021894 372 obj->i2c.tran_ctrl = 0;
elessair 0:f269e3021894 373 tran_len = obj->i2c.tran_pos - obj->i2c.tran_beg;
elessair 0:f269e3021894 374 obj->i2c.tran_beg = NULL;
elessair 0:f269e3021894 375 obj->i2c.tran_pos = NULL;
elessair 0:f269e3021894 376 obj->i2c.tran_end = NULL;
elessair 0:f269e3021894 377 i2c_enable_int(obj);
elessair 0:f269e3021894 378 }
elessair 0:f269e3021894 379
elessair 0:f269e3021894 380 return tran_len;
elessair 0:f269e3021894 381 }
elessair 0:f269e3021894 382
elessair 0:f269e3021894 383 static int i2c_do_write(i2c_t *obj, char data, int naklastdata)
elessair 0:f269e3021894 384 {
elessair 0:f269e3021894 385 char data_[1];
elessair 0:f269e3021894 386 data_[0] = data;
elessair 0:f269e3021894 387 return i2c_do_tran(obj, data_, 1, 0, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 388 }
elessair 0:f269e3021894 389
elessair 0:f269e3021894 390 static int i2c_do_read(i2c_t *obj, char *data, int naklastdata)
elessair 0:f269e3021894 391 {
elessair 0:f269e3021894 392 return i2c_do_tran(obj, data, 1, 1, naklastdata) == 1 ? 0 : I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 393 }
elessair 0:f269e3021894 394
elessair 0:f269e3021894 395 static int i2c_do_trsn(i2c_t *obj, uint32_t i2c_ctl, int sync)
elessair 0:f269e3021894 396 {
elessair 0:f269e3021894 397 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 398 int err = 0;
elessair 0:f269e3021894 399
elessair 0:f269e3021894 400 i2c_disable_int(obj);
elessair 0:f269e3021894 401
elessair 0:f269e3021894 402 if (i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
elessair 0:f269e3021894 403 err = I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 404 #if NU_I2C_DEBUG
elessair 0:f269e3021894 405 MY_I2C_2 = obj->i2c;
elessair 0:f269e3021894 406 while (1);
elessair 0:f269e3021894 407 #endif
elessair 0:f269e3021894 408 }
elessair 0:f269e3021894 409 else {
elessair 0:f269e3021894 410 #if 1
elessair 0:f269e3021894 411 // NOTE: Avoid duplicate Start/Stop. Otherwise, we may meet strange error.
elessair 0:f269e3021894 412 uint32_t status = I2C_GET_STATUS(i2c_base);
elessair 0:f269e3021894 413
elessair 0:f269e3021894 414 switch (status) {
elessair 0:f269e3021894 415 case 0x08: // Start
elessair 0:f269e3021894 416 case 0x10: // Master Repeat Start
elessair 0:f269e3021894 417 if (i2c_ctl & I2C_CTL_STA_Msk) {
elessair 0:f269e3021894 418 return 0;
elessair 0:f269e3021894 419 }
elessair 0:f269e3021894 420 else {
elessair 0:f269e3021894 421 break;
elessair 0:f269e3021894 422 }
elessair 0:f269e3021894 423 case 0xF8: // Bus Released
elessair 0:f269e3021894 424 if (i2c_ctl & (I2C_CTL_STA_Msk | I2C_CTL_STO_Msk) == I2C_CTL_STO_Msk) {
elessair 0:f269e3021894 425 return 0;
elessair 0:f269e3021894 426 }
elessair 0:f269e3021894 427 else {
elessair 0:f269e3021894 428 break;
elessair 0:f269e3021894 429 }
elessair 0:f269e3021894 430 }
elessair 0:f269e3021894 431 #endif
elessair 0:f269e3021894 432 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 433 if (sync && i2c_poll_status_timeout(obj, i2c_is_trsn_done, NU_I2C_TIMEOUT_STAT_INT)) {
elessair 0:f269e3021894 434 err = I2C_ERROR_BUS_BUSY;
elessair 0:f269e3021894 435 #if NU_I2C_DEBUG
elessair 0:f269e3021894 436 MY_I2C_2 = obj->i2c;
elessair 0:f269e3021894 437 while (1);
elessair 0:f269e3021894 438 #endif
elessair 0:f269e3021894 439 }
elessair 0:f269e3021894 440 }
elessair 0:f269e3021894 441
elessair 0:f269e3021894 442 i2c_enable_int(obj);
elessair 0:f269e3021894 443
elessair 0:f269e3021894 444 return err;
elessair 0:f269e3021894 445 }
elessair 0:f269e3021894 446
elessair 0:f269e3021894 447 static int i2c_poll_status_timeout(i2c_t *obj, int (*is_status)(i2c_t *obj), uint32_t timeout)
elessair 0:f269e3021894 448 {
elessair 0:f269e3021894 449 uint32_t t1, t2, elapsed = 0;
elessair 0:f269e3021894 450 int status_assert = 0;
elessair 0:f269e3021894 451
elessair 0:f269e3021894 452 t1 = us_ticker_read();
elessair 0:f269e3021894 453 while (1) {
elessair 0:f269e3021894 454 status_assert = is_status(obj);
elessair 0:f269e3021894 455 if (status_assert) {
elessair 0:f269e3021894 456 break;
elessair 0:f269e3021894 457 }
elessair 0:f269e3021894 458
elessair 0:f269e3021894 459 t2 = us_ticker_read();
elessair 0:f269e3021894 460 elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
elessair 0:f269e3021894 461 if (elapsed >= timeout) {
elessair 0:f269e3021894 462 #if NU_I2C_DEBUG
elessair 0:f269e3021894 463 MY_I2C_T1 = t1;
elessair 0:f269e3021894 464 MY_I2C_T2 = t2;
elessair 0:f269e3021894 465 MY_I2C_ELAPSED = elapsed;
elessair 0:f269e3021894 466 MY_I2C_TIMEOUT = timeout;
elessair 0:f269e3021894 467 MY_I2C_2 = obj->i2c;
elessair 0:f269e3021894 468 while (1);
elessair 0:f269e3021894 469 #endif
elessair 0:f269e3021894 470 break;
elessair 0:f269e3021894 471 }
elessair 0:f269e3021894 472 }
elessair 0:f269e3021894 473
elessair 0:f269e3021894 474 return (elapsed >= timeout);
elessair 0:f269e3021894 475 }
elessair 0:f269e3021894 476
elessair 0:f269e3021894 477 static int i2c_poll_tran_heatbeat_timeout(i2c_t *obj, uint32_t timeout)
elessair 0:f269e3021894 478 {
elessair 0:f269e3021894 479 uint32_t t1, t2, elapsed = 0;
elessair 0:f269e3021894 480 int tran_started;
elessair 0:f269e3021894 481 char *tran_pos = NULL;
elessair 0:f269e3021894 482 char *tran_pos2 = NULL;
elessair 0:f269e3021894 483
elessair 0:f269e3021894 484 i2c_disable_int(obj);
elessair 0:f269e3021894 485 tran_pos = obj->i2c.tran_pos;
elessair 0:f269e3021894 486 i2c_enable_int(obj);
elessair 0:f269e3021894 487 t1 = us_ticker_read();
elessair 0:f269e3021894 488 while (1) {
elessair 0:f269e3021894 489 i2c_disable_int(obj);
elessair 0:f269e3021894 490 tran_started = i2c_is_tran_started(obj);
elessair 0:f269e3021894 491 i2c_enable_int(obj);
elessair 0:f269e3021894 492 if (! tran_started) { // Transfer completed or stopped
elessair 0:f269e3021894 493 break;
elessair 0:f269e3021894 494 }
elessair 0:f269e3021894 495
elessair 0:f269e3021894 496 i2c_disable_int(obj);
elessair 0:f269e3021894 497 tran_pos2 = obj->i2c.tran_pos;
elessair 0:f269e3021894 498 i2c_enable_int(obj);
elessair 0:f269e3021894 499 t2 = us_ticker_read();
elessair 0:f269e3021894 500 if (tran_pos2 != tran_pos) { // Transfer on-going
elessair 0:f269e3021894 501 t1 = t2;
elessair 0:f269e3021894 502 tran_pos = tran_pos2;
elessair 0:f269e3021894 503 continue;
elessair 0:f269e3021894 504 }
elessair 0:f269e3021894 505
elessair 0:f269e3021894 506 elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t) t2 + 0xFFFFFFFF - t1 + 1);
elessair 0:f269e3021894 507 if (elapsed >= timeout) { // Transfer idle
elessair 0:f269e3021894 508 #if NU_I2C_DEBUG
elessair 0:f269e3021894 509 MY_I2C = obj->i2c;
elessair 0:f269e3021894 510 MY_I2C_T1 = t1;
elessair 0:f269e3021894 511 MY_I2C_T2 = t2;
elessair 0:f269e3021894 512 MY_I2C_ELAPSED = elapsed;
elessair 0:f269e3021894 513 MY_I2C_TIMEOUT = timeout;
elessair 0:f269e3021894 514 MY_I2C_2 = obj->i2c;
elessair 0:f269e3021894 515 while (1);
elessair 0:f269e3021894 516 #endif
elessair 0:f269e3021894 517 break;
elessair 0:f269e3021894 518 }
elessair 0:f269e3021894 519 }
elessair 0:f269e3021894 520
elessair 0:f269e3021894 521 return (elapsed >= timeout);
elessair 0:f269e3021894 522 }
elessair 0:f269e3021894 523
elessair 0:f269e3021894 524 #if 0
elessair 0:f269e3021894 525 static int i2c_is_stat_int(i2c_t *obj)
elessair 0:f269e3021894 526 {
elessair 0:f269e3021894 527 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 528
elessair 0:f269e3021894 529 return !! (i2c_base->CTL & I2C_CTL_SI_Msk);
elessair 0:f269e3021894 530 }
elessair 0:f269e3021894 531
elessair 0:f269e3021894 532 static int i2c_is_stop_det(i2c_t *obj)
elessair 0:f269e3021894 533 {
elessair 0:f269e3021894 534 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 535
elessair 0:f269e3021894 536 return ! (i2c_base->CTL & I2C_CTL_STO_Msk);
elessair 0:f269e3021894 537 }
elessair 0:f269e3021894 538 #endif
elessair 0:f269e3021894 539
elessair 0:f269e3021894 540 static int i2c_is_trsn_done(i2c_t *obj)
elessair 0:f269e3021894 541 {
elessair 0:f269e3021894 542 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 543 int i2c_int;
elessair 0:f269e3021894 544 uint32_t status;
elessair 0:f269e3021894 545 int inten_back;
elessair 0:f269e3021894 546
elessair 0:f269e3021894 547 inten_back = i2c_set_int(obj, 0);
elessair 0:f269e3021894 548 i2c_int = !! (i2c_base->CTL & I2C_CTL_SI_Msk);
elessair 0:f269e3021894 549 status = I2C_GET_STATUS(i2c_base);
elessair 0:f269e3021894 550 i2c_set_int(obj, inten_back);
elessair 0:f269e3021894 551
elessair 0:f269e3021894 552 return (i2c_int || status == 0xF8);
elessair 0:f269e3021894 553 }
elessair 0:f269e3021894 554
elessair 0:f269e3021894 555 static int i2c_is_tran_started(i2c_t *obj)
elessair 0:f269e3021894 556 {
elessair 0:f269e3021894 557 int started;
elessair 0:f269e3021894 558 int inten_back;
elessair 0:f269e3021894 559
elessair 0:f269e3021894 560 inten_back = i2c_set_int(obj, 0);
elessair 0:f269e3021894 561 started = !! (obj->i2c.tran_ctrl & TRANCTRL_STARTED);
elessair 0:f269e3021894 562 i2c_set_int(obj, inten_back);
elessair 0:f269e3021894 563
elessair 0:f269e3021894 564 return started;
elessair 0:f269e3021894 565 }
elessair 0:f269e3021894 566
elessair 0:f269e3021894 567 static int i2c_addr2data(int address, int read)
elessair 0:f269e3021894 568 {
elessair 0:f269e3021894 569 return read ? (address | 1) : (address & 0xFE);
elessair 0:f269e3021894 570 }
elessair 0:f269e3021894 571
elessair 0:f269e3021894 572 static void i2c0_vec(void)
elessair 0:f269e3021894 573 {
elessair 0:f269e3021894 574 i2c_irq(i2c0_var.obj);
elessair 0:f269e3021894 575 }
elessair 0:f269e3021894 576 static void i2c1_vec(void)
elessair 0:f269e3021894 577 {
elessair 0:f269e3021894 578 i2c_irq(i2c1_var.obj);
elessair 0:f269e3021894 579 }
elessair 0:f269e3021894 580
elessair 0:f269e3021894 581 static void i2c_irq(i2c_t *obj)
elessair 0:f269e3021894 582 {
elessair 0:f269e3021894 583 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 584 uint32_t status;
elessair 0:f269e3021894 585
elessair 0:f269e3021894 586 if (I2C_GET_TIMEOUT_FLAG(i2c_base)) {
elessair 0:f269e3021894 587 I2C_ClearTimeoutFlag(i2c_base);
elessair 0:f269e3021894 588 return;
elessair 0:f269e3021894 589 }
elessair 0:f269e3021894 590
elessair 0:f269e3021894 591 status = I2C_GET_STATUS(i2c_base);
elessair 0:f269e3021894 592 #if NU_I2C_DEBUG
elessair 0:f269e3021894 593 if (MY_I2C_STATUS_POS < (sizeof (MY_I2C_STATUS) / sizeof (MY_I2C_STATUS[0]))) {
elessair 0:f269e3021894 594 MY_I2C_STATUS[MY_I2C_STATUS_POS ++] = status;
elessair 0:f269e3021894 595 }
elessair 0:f269e3021894 596 else {
elessair 0:f269e3021894 597 memset(MY_I2C_STATUS, 0x00, sizeof (MY_I2C_STATUS));
elessair 0:f269e3021894 598 MY_I2C_STATUS_POS = 0;
elessair 0:f269e3021894 599 }
elessair 0:f269e3021894 600 #endif
elessair 0:f269e3021894 601
elessair 0:f269e3021894 602 switch (status) {
elessair 0:f269e3021894 603 // Master Transmit
elessair 0:f269e3021894 604 case 0x28: // Master Transmit Data ACK
elessair 0:f269e3021894 605 case 0x18: // Master Transmit Address ACK
elessair 0:f269e3021894 606 case 0x08: // Start
elessair 0:f269e3021894 607 case 0x10: // Master Repeat Start
elessair 0:f269e3021894 608 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
elessair 0:f269e3021894 609 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
elessair 0:f269e3021894 610 I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
elessair 0:f269e3021894 611 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 612 }
elessair 0:f269e3021894 613 else {
elessair 0:f269e3021894 614 if (status == 0x18) {
elessair 0:f269e3021894 615 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
elessair 0:f269e3021894 616 i2c_disable_int(obj);
elessair 0:f269e3021894 617 break;
elessair 0:f269e3021894 618 }
elessair 0:f269e3021894 619 // Go Master Repeat Start
elessair 0:f269e3021894 620 i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 621 }
elessair 0:f269e3021894 622 }
elessair 0:f269e3021894 623 else {
elessair 0:f269e3021894 624 i2c_disable_int(obj);
elessair 0:f269e3021894 625 }
elessair 0:f269e3021894 626 break;
elessair 0:f269e3021894 627 case 0x30: // Master Transmit Data NACK
elessair 0:f269e3021894 628 case 0x20: // Master Transmit Address NACK
elessair 0:f269e3021894 629 // Go Master Repeat Start
elessair 0:f269e3021894 630 i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 631 break;
elessair 0:f269e3021894 632 case 0x38: // Master Arbitration Lost
elessair 0:f269e3021894 633 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 634 break;
elessair 0:f269e3021894 635
elessair 0:f269e3021894 636 case 0x48: // Master Receive Address NACK
elessair 0:f269e3021894 637 // Go Master Repeat Start
elessair 0:f269e3021894 638 i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 639 break;
elessair 0:f269e3021894 640 case 0x40: // Master Receive Address ACK
elessair 0:f269e3021894 641 case 0x50: // Master Receive Data ACK
elessair 0:f269e3021894 642 case 0x58: // Master Receive Data NACK
elessair 0:f269e3021894 643 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
elessair 0:f269e3021894 644 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
elessair 0:f269e3021894 645 if (status == 0x50 || status == 0x58) {
elessair 0:f269e3021894 646 *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
elessair 0:f269e3021894 647 }
elessair 0:f269e3021894 648
elessair 0:f269e3021894 649 if (status == 0x58) {
elessair 0:f269e3021894 650 #if NU_I2C_DEBUG
elessair 0:f269e3021894 651 if (obj->i2c.tran_pos != obj->i2c.tran_end) {
elessair 0:f269e3021894 652 MY_I2C = obj->i2c;
elessair 0:f269e3021894 653 while (1);
elessair 0:f269e3021894 654 }
elessair 0:f269e3021894 655 #endif
elessair 0:f269e3021894 656 // Go Master Repeat Start
elessair 0:f269e3021894 657 i2c_fsm_reset(obj, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 658 }
elessair 0:f269e3021894 659 else {
elessair 0:f269e3021894 660 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
elessair 0:f269e3021894 661 if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
elessair 0:f269e3021894 662 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
elessair 0:f269e3021894 663 // Last data
elessair 0:f269e3021894 664 i2c_ctl &= ~I2C_CTL_AA_Msk;
elessair 0:f269e3021894 665 }
elessair 0:f269e3021894 666 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 667 }
elessair 0:f269e3021894 668 }
elessair 0:f269e3021894 669 else {
elessair 0:f269e3021894 670 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
elessair 0:f269e3021894 671 i2c_disable_int(obj);
elessair 0:f269e3021894 672 break;
elessair 0:f269e3021894 673 }
elessair 0:f269e3021894 674 }
elessair 0:f269e3021894 675 else {
elessair 0:f269e3021894 676 i2c_disable_int(obj);
elessair 0:f269e3021894 677 }
elessair 0:f269e3021894 678 break;
elessair 0:f269e3021894 679
elessair 0:f269e3021894 680 //case 0x00: // Bus error
elessair 0:f269e3021894 681
elessair 0:f269e3021894 682 // Slave Transmit
elessair 0:f269e3021894 683 case 0xB8: // Slave Transmit Data ACK
elessair 0:f269e3021894 684 case 0xA8: // Slave Transmit Address ACK
elessair 0:f269e3021894 685 case 0xB0: // Slave Transmit Arbitration Lost
elessair 0:f269e3021894 686 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
elessair 0:f269e3021894 687 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
elessair 0:f269e3021894 688 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
elessair 0:f269e3021894 689
elessair 0:f269e3021894 690 I2C_SET_DATA(i2c_base, *obj->i2c.tran_pos ++);
elessair 0:f269e3021894 691 if (obj->i2c.tran_pos == obj->i2c.tran_end &&
elessair 0:f269e3021894 692 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
elessair 0:f269e3021894 693 // Last data
elessair 0:f269e3021894 694 i2c_ctl &= ~I2C_CTL_AA_Msk;
elessair 0:f269e3021894 695 }
elessair 0:f269e3021894 696 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 697 }
elessair 0:f269e3021894 698 else {
elessair 0:f269e3021894 699 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
elessair 0:f269e3021894 700 i2c_disable_int(obj);
elessair 0:f269e3021894 701 break;
elessair 0:f269e3021894 702 }
elessair 0:f269e3021894 703 }
elessair 0:f269e3021894 704 else {
elessair 0:f269e3021894 705 i2c_disable_int(obj);
elessair 0:f269e3021894 706 }
elessair 0:f269e3021894 707 obj->i2c.slaveaddr_state = ReadAddressed;
elessair 0:f269e3021894 708 break;
elessair 0:f269e3021894 709 //case 0xA0: // Slave Transmit Repeat Start or Stop
elessair 0:f269e3021894 710 case 0xC0: // Slave Transmit Data NACK
elessair 0:f269e3021894 711 case 0xC8: // Slave Transmit Last Data ACK
elessair 0:f269e3021894 712 obj->i2c.slaveaddr_state = NoData;
elessair 0:f269e3021894 713 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 714 break;
elessair 0:f269e3021894 715
elessair 0:f269e3021894 716 // Slave Receive
elessair 0:f269e3021894 717 case 0x80: // Slave Receive Data ACK
elessair 0:f269e3021894 718 case 0x88: // Slave Receive Data NACK
elessair 0:f269e3021894 719 case 0x60: // Slave Receive Address ACK
elessair 0:f269e3021894 720 case 0x68: // Slave Receive Arbitration Lost
elessair 0:f269e3021894 721 obj->i2c.slaveaddr_state = WriteAddressed;
elessair 0:f269e3021894 722 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
elessair 0:f269e3021894 723 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
elessair 0:f269e3021894 724 if (status == 0x80 || status == 0x88) {
elessair 0:f269e3021894 725 *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
elessair 0:f269e3021894 726 }
elessair 0:f269e3021894 727
elessair 0:f269e3021894 728 if (status == 0x88) {
elessair 0:f269e3021894 729 #if NU_I2C_DEBUG
elessair 0:f269e3021894 730 if (obj->i2c.tran_pos != obj->i2c.tran_end) {
elessair 0:f269e3021894 731 MY_I2C = obj->i2c;
elessair 0:f269e3021894 732 while (1);
elessair 0:f269e3021894 733 }
elessair 0:f269e3021894 734 #endif
elessair 0:f269e3021894 735 obj->i2c.slaveaddr_state = NoData;
elessair 0:f269e3021894 736 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 737 }
elessair 0:f269e3021894 738 else {
elessair 0:f269e3021894 739 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
elessair 0:f269e3021894 740 if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
elessair 0:f269e3021894 741 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
elessair 0:f269e3021894 742 // Last data
elessair 0:f269e3021894 743 i2c_ctl &= ~I2C_CTL_AA_Msk;
elessair 0:f269e3021894 744 }
elessair 0:f269e3021894 745 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 746 }
elessair 0:f269e3021894 747 }
elessair 0:f269e3021894 748 else {
elessair 0:f269e3021894 749 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
elessair 0:f269e3021894 750 i2c_disable_int(obj);
elessair 0:f269e3021894 751 break;
elessair 0:f269e3021894 752 }
elessair 0:f269e3021894 753 }
elessair 0:f269e3021894 754 else {
elessair 0:f269e3021894 755 i2c_disable_int(obj);
elessair 0:f269e3021894 756 }
elessair 0:f269e3021894 757 break;
elessair 0:f269e3021894 758 //case 0xA0: // Slave Receive Repeat Start or Stop
elessair 0:f269e3021894 759
elessair 0:f269e3021894 760 // GC mode
elessair 0:f269e3021894 761 //case 0xA0: // GC mode Repeat Start or Stop
elessair 0:f269e3021894 762 case 0x90: // GC mode Data ACK
elessair 0:f269e3021894 763 case 0x98: // GC mode Data NACK
elessair 0:f269e3021894 764 case 0x70: // GC mode Address ACK
elessair 0:f269e3021894 765 case 0x78: // GC mode Arbitration Lost
elessair 0:f269e3021894 766 obj->i2c.slaveaddr_state = WriteAddressed;
elessair 0:f269e3021894 767 if ((obj->i2c.tran_ctrl & TRANCTRL_STARTED) && obj->i2c.tran_pos) {
elessair 0:f269e3021894 768 if (obj->i2c.tran_pos < obj->i2c.tran_end) {
elessair 0:f269e3021894 769 if (status == 0x90 || status == 0x98) {
elessair 0:f269e3021894 770 *obj->i2c.tran_pos ++ = I2C_GET_DATA(i2c_base);
elessair 0:f269e3021894 771 }
elessair 0:f269e3021894 772
elessair 0:f269e3021894 773 if (status == 0x98) {
elessair 0:f269e3021894 774 #if NU_I2C_DEBUG
elessair 0:f269e3021894 775 if (obj->i2c.tran_pos != obj->i2c.tran_end) {
elessair 0:f269e3021894 776 MY_I2C = obj->i2c;
elessair 0:f269e3021894 777 while (1);
elessair 0:f269e3021894 778 }
elessair 0:f269e3021894 779 #endif
elessair 0:f269e3021894 780 obj->i2c.slaveaddr_state = NoData;
elessair 0:f269e3021894 781 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 782 }
elessair 0:f269e3021894 783 else {
elessair 0:f269e3021894 784 uint32_t i2c_ctl = I2C_CTL_SI_Msk | I2C_CTL_AA_Msk;
elessair 0:f269e3021894 785 if ((obj->i2c.tran_end - obj->i2c.tran_pos) == 1 &&
elessair 0:f269e3021894 786 obj->i2c.tran_ctrl & TRANCTRL_NAKLASTDATA) {
elessair 0:f269e3021894 787 // Last data
elessair 0:f269e3021894 788 i2c_ctl &= ~I2C_CTL_AA_Msk;
elessair 0:f269e3021894 789 }
elessair 0:f269e3021894 790 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 791 }
elessair 0:f269e3021894 792 }
elessair 0:f269e3021894 793 else {
elessair 0:f269e3021894 794 obj->i2c.tran_ctrl &= ~TRANCTRL_STARTED;
elessair 0:f269e3021894 795 i2c_disable_int(obj);
elessair 0:f269e3021894 796 break;
elessair 0:f269e3021894 797 }
elessair 0:f269e3021894 798 }
elessair 0:f269e3021894 799 else {
elessair 0:f269e3021894 800 i2c_disable_int(obj);
elessair 0:f269e3021894 801 }
elessair 0:f269e3021894 802 break;
elessair 0:f269e3021894 803
elessair 0:f269e3021894 804 case 0xF8: // Bus Released
elessair 0:f269e3021894 805 break;
elessair 0:f269e3021894 806
elessair 0:f269e3021894 807 default:
elessair 0:f269e3021894 808 i2c_fsm_reset(obj, I2C_CTL_SI_Msk | I2C_CTL_AA_Msk);
elessair 0:f269e3021894 809 }
elessair 0:f269e3021894 810 }
elessair 0:f269e3021894 811
elessair 0:f269e3021894 812 static void i2c_fsm_reset(i2c_t *obj, uint32_t i2c_ctl)
elessair 0:f269e3021894 813 {
elessair 0:f269e3021894 814 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 815
elessair 0:f269e3021894 816 obj->i2c.stop = 0;
elessair 0:f269e3021894 817
elessair 0:f269e3021894 818 obj->i2c.tran_ctrl = 0;
elessair 0:f269e3021894 819
elessair 0:f269e3021894 820 I2C_SET_CONTROL_REG(i2c_base, i2c_ctl);
elessair 0:f269e3021894 821 obj->i2c.slaveaddr_state = NoData;
elessair 0:f269e3021894 822 }
elessair 0:f269e3021894 823
elessair 0:f269e3021894 824 #if DEVICE_I2C_ASYNCH
elessair 0:f269e3021894 825
elessair 0:f269e3021894 826 void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint)
elessair 0:f269e3021894 827 {
elessair 0:f269e3021894 828 // NOTE: M451 I2C only supports 7-bit slave address. The mbed I2C address passed in is shifted left by 1 bit (7-bit addr << 1).
elessair 0:f269e3021894 829 MBED_ASSERT((address & 0xFFFFFF00) == 0);
elessair 0:f269e3021894 830
elessair 0:f269e3021894 831 // NOTE: First transmit and then receive.
elessair 0:f269e3021894 832
elessair 0:f269e3021894 833 (void) hint;
elessair 0:f269e3021894 834 obj->i2c.dma_usage = DMA_USAGE_NEVER;
elessair 0:f269e3021894 835 obj->i2c.stop = stop;
elessair 0:f269e3021894 836 obj->i2c.address = address;
elessair 0:f269e3021894 837 obj->i2c.event = event;
elessair 0:f269e3021894 838 i2c_buffer_set(obj, tx, tx_length, rx, rx_length);
elessair 0:f269e3021894 839
elessair 0:f269e3021894 840 //I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 841
elessair 0:f269e3021894 842 i2c_enable_vector_interrupt(obj, handler, 1);
elessair 0:f269e3021894 843 i2c_start(obj);
elessair 0:f269e3021894 844 }
elessair 0:f269e3021894 845
elessair 0:f269e3021894 846 uint32_t i2c_irq_handler_asynch(i2c_t *obj)
elessair 0:f269e3021894 847 {
elessair 0:f269e3021894 848 int event = 0;
elessair 0:f269e3021894 849
elessair 0:f269e3021894 850 I2C_T *i2c_base = (I2C_T *) NU_MODBASE(obj->i2c.i2c);
elessair 0:f269e3021894 851 uint32_t status = I2C_GET_STATUS(i2c_base);
elessair 0:f269e3021894 852 switch (status) {
elessair 0:f269e3021894 853 case 0x08: // Start
elessair 0:f269e3021894 854 case 0x10: {// Master Repeat Start
elessair 0:f269e3021894 855 if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
elessair 0:f269e3021894 856 I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 0)));
elessair 0:f269e3021894 857 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
elessair 0:f269e3021894 858 }
elessair 0:f269e3021894 859 else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
elessair 0:f269e3021894 860 I2C_SET_DATA(i2c_base, (i2c_addr2data(obj->i2c.address, 1)));
elessair 0:f269e3021894 861 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
elessair 0:f269e3021894 862 }
elessair 0:f269e3021894 863 else {
elessair 0:f269e3021894 864 event = I2C_EVENT_TRANSFER_COMPLETE;
elessair 0:f269e3021894 865 if (obj->i2c.stop) {
elessair 0:f269e3021894 866 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 867 }
elessair 0:f269e3021894 868 }
elessair 0:f269e3021894 869 break;
elessair 0:f269e3021894 870 }
elessair 0:f269e3021894 871
elessair 0:f269e3021894 872 case 0x18: // Master Transmit Address ACK
elessair 0:f269e3021894 873 case 0x28: // Master Transmit Data ACK
elessair 0:f269e3021894 874 if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
elessair 0:f269e3021894 875 uint8_t *tx = (uint8_t *)obj->tx_buff.buffer;
elessair 0:f269e3021894 876 I2C_SET_DATA(i2c_base, tx[obj->tx_buff.pos ++]);
elessair 0:f269e3021894 877 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk);
elessair 0:f269e3021894 878 }
elessair 0:f269e3021894 879 else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
elessair 0:f269e3021894 880 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 881 }
elessair 0:f269e3021894 882 else {
elessair 0:f269e3021894 883 event = I2C_EVENT_TRANSFER_COMPLETE;
elessair 0:f269e3021894 884 if (obj->i2c.stop) {
elessair 0:f269e3021894 885 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 886 }
elessair 0:f269e3021894 887 }
elessair 0:f269e3021894 888 break;
elessair 0:f269e3021894 889
elessair 0:f269e3021894 890 case 0x20: // Master Transmit Address NACK
elessair 0:f269e3021894 891 event = I2C_EVENT_ERROR_NO_SLAVE;
elessair 0:f269e3021894 892 if (obj->i2c.stop) {
elessair 0:f269e3021894 893 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 894 }
elessair 0:f269e3021894 895 break;
elessair 0:f269e3021894 896
elessair 0:f269e3021894 897 case 0x30: // Master Transmit Data NACK
elessair 0:f269e3021894 898 if (obj->tx_buff.buffer && obj->tx_buff.pos < obj->tx_buff.length) {
elessair 0:f269e3021894 899 event = I2C_EVENT_TRANSFER_EARLY_NACK;
elessair 0:f269e3021894 900 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 901 }
elessair 0:f269e3021894 902 else if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
elessair 0:f269e3021894 903 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 904 }
elessair 0:f269e3021894 905 else {
elessair 0:f269e3021894 906 event = I2C_EVENT_TRANSFER_COMPLETE;
elessair 0:f269e3021894 907 if (obj->i2c.stop) {
elessair 0:f269e3021894 908 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 909 }
elessair 0:f269e3021894 910 }
elessair 0:f269e3021894 911 break;
elessair 0:f269e3021894 912
elessair 0:f269e3021894 913 case 0x38: // Master Arbitration Lost
elessair 0:f269e3021894 914 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk); // Enter not addressed SLV mode
elessair 0:f269e3021894 915 event = I2C_EVENT_ERROR;
elessair 0:f269e3021894 916 break;
elessair 0:f269e3021894 917
elessair 0:f269e3021894 918 case 0x50: // Master Receive Data ACK
elessair 0:f269e3021894 919 if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
elessair 0:f269e3021894 920 uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
elessair 0:f269e3021894 921 rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
elessair 0:f269e3021894 922 }
elessair 0:f269e3021894 923 case 0x40: // Master Receive Address ACK
elessair 0:f269e3021894 924 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_SI_Msk | ((obj->rx_buff.pos != obj->rx_buff.length - 1) ? I2C_CTL_AA_Msk : 0));
elessair 0:f269e3021894 925 break;
elessair 0:f269e3021894 926
elessair 0:f269e3021894 927 case 0x48: // Master Receive Address NACK
elessair 0:f269e3021894 928 event = I2C_EVENT_ERROR_NO_SLAVE;
elessair 0:f269e3021894 929 if (obj->i2c.stop) {
elessair 0:f269e3021894 930 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 931 }
elessair 0:f269e3021894 932 break;
elessair 0:f269e3021894 933
elessair 0:f269e3021894 934 case 0x58: // Master Receive Data NACK
elessair 0:f269e3021894 935 if (obj->rx_buff.buffer && obj->rx_buff.pos < obj->rx_buff.length) {
elessair 0:f269e3021894 936 uint8_t *rx = (uint8_t *) obj->rx_buff.buffer;
elessair 0:f269e3021894 937 rx[obj->rx_buff.pos ++] = I2C_GET_DATA(((I2C_T *) NU_MODBASE(obj->i2c.i2c)));
elessair 0:f269e3021894 938 }
elessair 0:f269e3021894 939 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STA_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 940 break;
elessair 0:f269e3021894 941
elessair 0:f269e3021894 942 case 0x00: // Bus error
elessair 0:f269e3021894 943 event = I2C_EVENT_ERROR;
elessair 0:f269e3021894 944 i2c_reset(obj);
elessair 0:f269e3021894 945 break;
elessair 0:f269e3021894 946
elessair 0:f269e3021894 947 default:
elessair 0:f269e3021894 948 event = I2C_EVENT_ERROR;
elessair 0:f269e3021894 949 if (obj->i2c.stop) {
elessair 0:f269e3021894 950 I2C_SET_CONTROL_REG(i2c_base, I2C_CTL_STO_Msk | I2C_CTL_SI_Msk);
elessair 0:f269e3021894 951 }
elessair 0:f269e3021894 952 }
elessair 0:f269e3021894 953
elessair 0:f269e3021894 954 if (event) {
elessair 0:f269e3021894 955 i2c_rollback_vector_interrupt(obj);
elessair 0:f269e3021894 956 }
elessair 0:f269e3021894 957
elessair 0:f269e3021894 958 return (event & obj->i2c.event);
elessair 0:f269e3021894 959 }
elessair 0:f269e3021894 960
elessair 0:f269e3021894 961 uint8_t i2c_active(i2c_t *obj)
elessair 0:f269e3021894 962 {
elessair 0:f269e3021894 963 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 964 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 965 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
elessair 0:f269e3021894 966
elessair 0:f269e3021894 967 // Vector will be changed for async transfer. Use it to judge if async transfer is on-going.
elessair 0:f269e3021894 968 uint32_t vec = NVIC_GetVector(modinit->irq_n);
elessair 0:f269e3021894 969 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
elessair 0:f269e3021894 970 return (vec && vec != (uint32_t) var->vec);
elessair 0:f269e3021894 971 }
elessair 0:f269e3021894 972
elessair 0:f269e3021894 973 void i2c_abort_asynch(i2c_t *obj)
elessair 0:f269e3021894 974 {
elessair 0:f269e3021894 975 i2c_rollback_vector_interrupt(obj);
elessair 0:f269e3021894 976 i2c_stop(obj);
elessair 0:f269e3021894 977 }
elessair 0:f269e3021894 978
elessair 0:f269e3021894 979 static void i2c_buffer_set(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length)
elessair 0:f269e3021894 980 {
elessair 0:f269e3021894 981 obj->tx_buff.buffer = (void *) tx;
elessair 0:f269e3021894 982 obj->tx_buff.length = tx_length;
elessair 0:f269e3021894 983 obj->tx_buff.pos = 0;
elessair 0:f269e3021894 984 obj->rx_buff.buffer = rx;
elessair 0:f269e3021894 985 obj->rx_buff.length = rx_length;
elessair 0:f269e3021894 986 obj->rx_buff.pos = 0;
elessair 0:f269e3021894 987 }
elessair 0:f269e3021894 988
elessair 0:f269e3021894 989 static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable)
elessair 0:f269e3021894 990 {
elessair 0:f269e3021894 991 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 992 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 993 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
elessair 0:f269e3021894 994
elessair 0:f269e3021894 995 if (enable) {
elessair 0:f269e3021894 996 NVIC_SetVector(modinit->irq_n, handler);
elessair 0:f269e3021894 997 i2c_enable_int(obj);
elessair 0:f269e3021894 998 }
elessair 0:f269e3021894 999 else {
elessair 0:f269e3021894 1000 i2c_disable_int(obj);
elessair 0:f269e3021894 1001 }
elessair 0:f269e3021894 1002
elessair 0:f269e3021894 1003 }
elessair 0:f269e3021894 1004
elessair 0:f269e3021894 1005 static void i2c_rollback_vector_interrupt(i2c_t *obj)
elessair 0:f269e3021894 1006 {
elessair 0:f269e3021894 1007 const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
elessair 0:f269e3021894 1008 MBED_ASSERT(modinit != NULL);
elessair 0:f269e3021894 1009 MBED_ASSERT(modinit->modname == obj->i2c.i2c);
elessair 0:f269e3021894 1010
elessair 0:f269e3021894 1011 struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
elessair 0:f269e3021894 1012 i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);
elessair 0:f269e3021894 1013 }
elessair 0:f269e3021894 1014
elessair 0:f269e3021894 1015 #endif
elessair 0:f269e3021894 1016
elessair 0:f269e3021894 1017 #endif