L VD / MAX113XX_Pixi

Library for the MAX11300

MAX113XX_Pixi.h@12:8054ee101bad, 2017-05-09 (annotated)

Committer:
j3
Date:
Tue May 09 19:04:38 2017 +0000
Revision:
12:8054ee101bad
Parent:
10:6efe114ef882
Child:
13:546dd29b1c7a
fixed error in config array and other updates

Who changed what in which revision?

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j3 7:8669a53acd0d 1 /**********************************************************************
j3 7:8669a53acd0d 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
j3 7:8669a53acd0d 3 *
j3 7:8669a53acd0d 4 * Permission is hereby granted, free of charge, to any person obtaining a
j3 7:8669a53acd0d 5 * copy of this software and associated documentation files (the "Software"),
j3 7:8669a53acd0d 6 * to deal in the Software without restriction, including without limitation
j3 7:8669a53acd0d 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
j3 7:8669a53acd0d 8 * and/or sell copies of the Software, and to permit persons to whom the
j3 7:8669a53acd0d 9 * Software is furnished to do so, subject to the following conditions:
j3 7:8669a53acd0d 10 *
j3 7:8669a53acd0d 11 * The above copyright notice and this permission notice shall be included
j3 7:8669a53acd0d 12 * in all copies or substantial portions of the Software.
j3 7:8669a53acd0d 13 *
j3 7:8669a53acd0d 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
j3 7:8669a53acd0d 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
j3 7:8669a53acd0d 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
j3 7:8669a53acd0d 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
j3 7:8669a53acd0d 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
j3 7:8669a53acd0d 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
j3 7:8669a53acd0d 20 * OTHER DEALINGS IN THE SOFTWARE.
j3 7:8669a53acd0d 21 *
j3 7:8669a53acd0d 22 * Except as contained in this notice, the name of Maxim Integrated
j3 7:8669a53acd0d 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
j3 7:8669a53acd0d 24 * Products, Inc. Branding Policy.
j3 7:8669a53acd0d 25 *
j3 7:8669a53acd0d 26 * The mere transfer of this software does not imply any licenses
j3 7:8669a53acd0d 27 * of trade secrets, proprietary technology, copyrights, patents,
j3 7:8669a53acd0d 28 * trademarks, maskwork rights, or any other form of intellectual
j3 7:8669a53acd0d 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
j3 7:8669a53acd0d 30 * ownership rights.
j3 7:8669a53acd0d 31 **********************************************************************/
j3 7:8669a53acd0d 32
j3 7:8669a53acd0d 33
j3 7:8669a53acd0d 34 #ifndef _MAX113XX_PIXI_H_
j3 7:8669a53acd0d 35 #define _MAX113XX_PIXI_H_
j3 7:8669a53acd0d 36
j3 9:094df3de3616 37
j3 7:8669a53acd0d 38 #include "mbed.h"
j3 12:8054ee101bad 39 #include "MAX11300Hex.h"
j3 9:094df3de3616 40
j3 7:8669a53acd0d 41
j3 7:8669a53acd0d 42 /**
j3 8:4291f7e54863 43 @brief MAX113XX - PIXI, 20/12-Port Programmable Mixed-Signal I/O with
j3 7:8669a53acd0d 44 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
j3 7:8669a53acd0d 45
j3 8:4291f7e54863 46 The MAX113XX family integrates a PIXI™, 12-bit, multichannel, analog-to-digital
j3 7:8669a53acd0d 47 converter (ADC) and a 12-bit, multichannel, buffered digital-to-analog
j3 8:4291f7e54863 48 converter (DAC) in a single integrated circuit (IC). These devices offers
j3 8:4291f7e54863 49 20/12 mixed-signal high-voltage, bipolar ports, which are configurable as an
j3 7:8669a53acd0d 50 ADC analog input, a DAC analog output, a general-purpose input port (GPI),
j3 7:8669a53acd0d 51 a general-purpose output port (GPO), or an analog switch terminal.
j3 7:8669a53acd0d 52 One internal and two external temperature sensors track junction and
j3 7:8669a53acd0d 53 environmental temperature, respectively. Adjacent pairs of ports are
j3 7:8669a53acd0d 54 configurable as a logic-level translator for open-drain devices or an
j3 7:8669a53acd0d 55 analog switch.
j3 7:8669a53acd0d 56
j3 7:8669a53acd0d 57 Use configuration software found at
j3 7:8669a53acd0d 58 https://www.maximintegrated.com/en/products/analog/data-converters/analog-to-digital-converters/MAX11300.html/tb_tab2
j3 9:094df3de3616 59 to generate MAX113XXHex.h file
j3 7:8669a53acd0d 60 */
j3 7:8669a53acd0d 61 class MAX113XX_Pixi
j3 7:8669a53acd0d 62 {
j3 7:8669a53acd0d 63 public:
j3 7:8669a53acd0d 64
j3 10:6efe114ef882 65 ///Pixi devices
j3 9:094df3de3616 66 enum Device_e
j3 9:094df3de3616 67 {
j3 9:094df3de3616 68 MAX11300 = 0,
j3 9:094df3de3616 69 MAX11301,
j3 9:094df3de3616 70 MAX11311,
j3 9:094df3de3616 71 MAX11312
j3 9:094df3de3616 72 };
j3 9:094df3de3616 73
j3 9:094df3de3616 74 ///MAX113XX Ports
j3 9:094df3de3616 75 enum Ports_e
j3 7:8669a53acd0d 76 {
j3 7:8669a53acd0d 77 PORT0,
j3 7:8669a53acd0d 78 PORT1,
j3 7:8669a53acd0d 79 PORT2,
j3 7:8669a53acd0d 80 PORT3,
j3 7:8669a53acd0d 81 PORT4,
j3 7:8669a53acd0d 82 PORT5,
j3 7:8669a53acd0d 83 PORT6,
j3 7:8669a53acd0d 84 PORT7,
j3 7:8669a53acd0d 85 PORT8,
j3 7:8669a53acd0d 86 PORT9,
j3 7:8669a53acd0d 87 PORT10,
j3 7:8669a53acd0d 88 PORT11,
j3 7:8669a53acd0d 89 PORT12,
j3 7:8669a53acd0d 90 PORT13,
j3 7:8669a53acd0d 91 PORT14,
j3 7:8669a53acd0d 92 PORT15,
j3 7:8669a53acd0d 93 PORT16,
j3 7:8669a53acd0d 94 PORT17,
j3 7:8669a53acd0d 95 PORT18,
j3 7:8669a53acd0d 96 PORT19
j3 7:8669a53acd0d 97 };
j3 7:8669a53acd0d 98
j3 9:094df3de3616 99 ///MAX113XX Port Modes
j3 9:094df3de3616 100 enum PortModes_e
j3 7:8669a53acd0d 101 {
j3 7:8669a53acd0d 102 ///HIGH_Z
j3 7:8669a53acd0d 103 MODE_0,
j3 7:8669a53acd0d 104 ///Digital input with programmable threshold, GPI
j3 7:8669a53acd0d 105 MODE_1,
j3 7:8669a53acd0d 106 ///Bidirectional level translator terminal
j3 7:8669a53acd0d 107 MODE_2,
j3 7:8669a53acd0d 108 ///Register-driven digital output with DAC-controlled level, GPO
j3 7:8669a53acd0d 109 MODE_3,
j3 7:8669a53acd0d 110 ///Unidirectional path output with DAC-controlled level, GPO
j3 7:8669a53acd0d 111 MODE_4,
j3 7:8669a53acd0d 112 ///Analog output for DAC
j3 7:8669a53acd0d 113 MODE_5,
j3 7:8669a53acd0d 114 ///Analog output for DAC with ADC monitoring
j3 7:8669a53acd0d 115 MODE_6,
j3 7:8669a53acd0d 116 ///Positive analog input to single-ended ADC
j3 7:8669a53acd0d 117 MODE_7,
j3 7:8669a53acd0d 118 ///Positive analog input to differential ADC
j3 7:8669a53acd0d 119 MODE_8,
j3 7:8669a53acd0d 120 ///Negative analog input to differential ADC
j3 7:8669a53acd0d 121 MODE_9,
j3 7:8669a53acd0d 122 ///Analog output for DAC and negative analog input to differential ADC
j3 7:8669a53acd0d 123 MODE_10,
j3 7:8669a53acd0d 124 ///Terminal to GPI-controlled analog switch
j3 7:8669a53acd0d 125 MODE_11,
j3 7:8669a53acd0d 126 ///Terminal to register-controlled analog switch
j3 7:8669a53acd0d 127 MODE_12
j3 7:8669a53acd0d 128 };
j3 7:8669a53acd0d 129
j3 10:6efe114ef882 130 ///Command results
j3 7:8669a53acd0d 131 enum CmdResult_e
j3 7:8669a53acd0d 132 {
j3 7:8669a53acd0d 133 ///Failed operation
j3 7:8669a53acd0d 134 OpFailure,
j3 7:8669a53acd0d 135 ///Successful operation
j3 7:8669a53acd0d 136 Success
j3 7:8669a53acd0d 137 };
j3 7:8669a53acd0d 138
j3 9:094df3de3616 139 MAX113XX_Pixi(Device_e device, PinName cnvt);
j3 7:8669a53acd0d 140
j3 12:8054ee101bad 141 ///@brief Read single ended ADC configured port
j3 12:8054ee101bad 142 ///@param[in] port - single ended ADC configured port
j3 12:8054ee101bad 143 ///@param[out] data - contents of ADC data register
j3 12:8054ee101bad 144 ///@return Result of operation
j3 12:8054ee101bad 145 CmdResult_e singleEndedADCRead(Ports_e port, uint16_t &data);
j3 12:8054ee101bad 146
j3 12:8054ee101bad 147 ///@brief Read differential ADC configured port
j3 12:8054ee101bad 148 ///@param[in] posPort - positive port
j3 12:8054ee101bad 149 ///@param[in] negPort - negative Port
j3 12:8054ee101bad 150 ///@param[out] data - contents of ADC data register
j3 12:8054ee101bad 151 ///@return Result of operation
j3 12:8054ee101bad 152 CmdResult_e differentialADCRead(Ports_e posPort, Ports_e negPort,
j3 12:8054ee101bad 153 uint16_t &data);
j3 12:8054ee101bad 154
j3 12:8054ee101bad 155 ///@brief Write DAC configured port
j3 12:8054ee101bad 156 ///@param[in] port - DAC configured port
j3 12:8054ee101bad 157 ///@param[in] data - value to be written to DAC data register
j3 12:8054ee101bad 158 ///@return Result of operation
j3 12:8054ee101bad 159 CmdResult_e dacWrite(Ports_e port, const uint16_t data);
j3 7:8669a53acd0d 160
j3 7:8669a53acd0d 161 ///@brief Reads gpi configured port
j3 7:8669a53acd0d 162 ///@param[in] port - gpi congigured port to be read
j3 7:8669a53acd0d 163 ///@param[out] state - lsb of state matches port state
j3 7:8669a53acd0d 164 ///@return Result of operation
j3 9:094df3de3616 165 CmdResult_e gpioRead(Ports_e port, uint8_t &state);
j3 7:8669a53acd0d 166
j3 12:8054ee101bad 167 ///@brief Writes gpo configured port with lsb of state
j3 12:8054ee101bad 168 ///@param[in] port - gpo congigured port to be written
j3 12:8054ee101bad 169 ///@param[in] state - lsb of state is written to port
j3 12:8054ee101bad 170 ///@return Result of operation
j3 12:8054ee101bad 171 CmdResult_e gpioWrite(Ports_e port, const uint8_t state);
j3 7:8669a53acd0d 172
j3 12:8054ee101bad 173 ///@brief Sets the state of a software controlled analog switch
j3 12:8054ee101bad 174 ///@param[in] portA - One side of analog switch
j3 12:8054ee101bad 175 ///@param[in] portB - The ther side of the analog switch
j3 12:8054ee101bad 176 ///@param[in] state - True for closed, false for open
j3 12:8054ee101bad 177 ///@return Result of operation
j3 12:8054ee101bad 178 CmdResult_e setAnalogSwitchState(Ports_e portA, Ports_e portB, bool state);
j3 7:8669a53acd0d 179
j3 10:6efe114ef882 180 ///@brief Dumps pixi memory to provided Serial object
j3 10:6efe114ef882 181 ///@param[in] ser - output device
j3 10:6efe114ef882 182 ///@return None
j3 12:8054ee101bad 183 void dumpMemory(Serial &ser);
j3 7:8669a53acd0d 184
j3 7:8669a53acd0d 185 protected:
j3 7:8669a53acd0d 186
j3 9:094df3de3616 187 Device_e m_device;
j3 7:8669a53acd0d 188 DigitalOut m_cnvt;
j3 7:8669a53acd0d 189
j3 7:8669a53acd0d 190 ///@brief Writes given register with data
j3 7:8669a53acd0d 191 ///@param[in] reg - register to be written
j3 7:8669a53acd0d 192 ///@param[in] data - data to write
j3 7:8669a53acd0d 193 ///@return none
j3 9:094df3de3616 194 virtual void writeRegister(uint8_t reg, const uint16_t data) = 0;
j3 7:8669a53acd0d 195
j3 7:8669a53acd0d 196 ///@brief Reads given register
j3 7:8669a53acd0d 197 ///@param[in] reg - register to read
j3 7:8669a53acd0d 198 ///@return contents of register
j3 9:094df3de3616 199 virtual uint16_t readRegister(uint8_t reg) = 0;
j3 7:8669a53acd0d 200
j3 7:8669a53acd0d 201 ///@brief Writes a block of data starting at given register
j3 7:8669a53acd0d 202 ///@param[in] reg - register to start writing at
j3 7:8669a53acd0d 203 ///@param[in] data - pointer to data buffer
j3 7:8669a53acd0d 204 ///@param[in] num_reg - number of registers to be written
j3 7:8669a53acd0d 205 ///@return none
j3 9:094df3de3616 206 virtual void blockWrite(uint8_t reg, const uint16_t *data,
j3 9:094df3de3616 207 const uint8_t num_reg) = 0;
j3 7:8669a53acd0d 208
j3 7:8669a53acd0d 209 ///@brief Reads a block of data starting at given register
j3 7:8669a53acd0d 210 ///@param[in] reg - register to start reading at
j3 7:8669a53acd0d 211 ///@param[in] data - pointer to data buffer
j3 7:8669a53acd0d 212 ///@param[in] num_reg - number of registers to be read
j3 7:8669a53acd0d 213 ///@return none
j3 9:094df3de3616 214 virtual void blockRead(uint8_t reg, uint16_t *data,
j3 9:094df3de3616 215 const uint8_t num_reg) = 0;
j3 7:8669a53acd0d 216 };
j3 7:8669a53acd0d 217
j3 7:8669a53acd0d 218
j3 7:8669a53acd0d 219 /**
j3 7:8669a53acd0d 220 @brief SPI Declaration for MAX113XX parts
j3 7:8669a53acd0d 221 */
j3 7:8669a53acd0d 222 class MAX113XX_SPI: public MAX113XX_Pixi
j3 7:8669a53acd0d 223 {
j3 7:8669a53acd0d 224
j3 7:8669a53acd0d 225 public:
j3 7:8669a53acd0d 226
j3 7:8669a53acd0d 227 ///@brief MAX113XX_SPI Constructor
j3 7:8669a53acd0d 228 ///@param[in] spiBus - reference to SPI bus for this device
j3 7:8669a53acd0d 229 ///@param[in] cs - pin to be used for chip select
j3 10:6efe114ef882 230 ///@param[in] device - pixi device; MAX11300, MAX11301,...
j3 7:8669a53acd0d 231 ///@param[in] cnvrt - pin to be used for convert
j3 9:094df3de3616 232 MAX113XX_SPI(SPI & spiBus, PinName cs, MAX113XX_Pixi::Device_e device,
j3 9:094df3de3616 233 PinName cnvt);
j3 7:8669a53acd0d 234
j3 7:8669a53acd0d 235 ///@brief MAX113XX_SPI Destructor
j3 7:8669a53acd0d 236 ~MAX113XX_SPI();
j3 7:8669a53acd0d 237
j3 7:8669a53acd0d 238 private:
j3 7:8669a53acd0d 239
j3 7:8669a53acd0d 240 SPI & m_spiBus;
j3 7:8669a53acd0d 241 DigitalOut m_cs;
j3 7:8669a53acd0d 242
j3 9:094df3de3616 243 virtual void writeRegister(uint8_t reg, const uint16_t data);
j3 7:8669a53acd0d 244
j3 9:094df3de3616 245 virtual uint16_t readRegister(uint8_t reg);
j3 7:8669a53acd0d 246
j3 9:094df3de3616 247 virtual void blockWrite(uint8_t reg, const uint16_t *data,
j3 7:8669a53acd0d 248 const uint8_t num_reg);
j3 7:8669a53acd0d 249
j3 9:094df3de3616 250 virtual void blockRead(uint8_t reg, uint16_t *data, const uint8_t num_reg);
j3 7:8669a53acd0d 251 };
j3 7:8669a53acd0d 252
j3 7:8669a53acd0d 253
j3 7:8669a53acd0d 254 /**
j3 7:8669a53acd0d 255 @brief I2C Declaration for MAX113XX parts
j3 7:8669a53acd0d 256 */
j3 7:8669a53acd0d 257 class MAX113XX_I2C: public MAX113XX_Pixi
j3 7:8669a53acd0d 258 {
j3 7:8669a53acd0d 259
j3 7:8669a53acd0d 260 public:
j3 7:8669a53acd0d 261
j3 7:8669a53acd0d 262 ///@brief MAX113XX_I2C Constructor
j3 7:8669a53acd0d 263 ///@param[in] i2cBus - reference to I2C bus for this device
j3 10:6efe114ef882 264 ///@param[in] device - pixi device; MAX11300, MAX11301,...
j3 7:8669a53acd0d 265 ///@param[in] cnvrt - pin to be used for convert
j3 9:094df3de3616 266 MAX113XX_I2C(I2C &i2cBus, MAX113XX_Pixi::Device_e device, PinName cnvt);
j3 7:8669a53acd0d 267
j3 7:8669a53acd0d 268 ///@brief MAX113XX_I2C Destructor
j3 7:8669a53acd0d 269 ~MAX113XX_I2C();
j3 7:8669a53acd0d 270
j3 7:8669a53acd0d 271 private:
j3 7:8669a53acd0d 272
j3 7:8669a53acd0d 273 I2C &m_i2cBus;
j3 7:8669a53acd0d 274
j3 9:094df3de3616 275 virtual void writeRegister(uint8_t reg, const uint16_t data);
j3 7:8669a53acd0d 276
j3 9:094df3de3616 277 virtual uint16_t readRegister(uint8_t reg);
j3 7:8669a53acd0d 278
j3 9:094df3de3616 279 virtual void blockWrite(uint8_t reg, const uint16_t *data,
j3 7:8669a53acd0d 280 const uint8_t num_reg);
j3 7:8669a53acd0d 281
j3 9:094df3de3616 282 virtual void blockRead(uint8_t reg, uint16_t *data, const uint8_t num_reg);
j3 7:8669a53acd0d 283 };
j3 7:8669a53acd0d 284
j3 7:8669a53acd0d 285
j3 7:8669a53acd0d 286 #endif /* _MAX113XX_PIXI_H_ */