Doubea Pierre / Mbed 2 deprecated HW3

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Dependencies:   SDFileSystem TextLCD mbed-rtos mbed wave_player FATFileSystem

mbed-rtos/rtx/rt_HAL_CM.h@0:67dbd54e60d4, 2013-11-13 (annotated)

Committer:
doubster
Date:
Wed Nov 13 20:00:28 2013 +0000
Revision:
0:67dbd54e60d4
Lab Checkoff

Who changed what in which revision?

UserRevisionLine numberNew contents of line
doubster 0:67dbd54e60d4 1 /*----------------------------------------------------------------------------
doubster 0:67dbd54e60d4 2 * RL-ARM - RTX
doubster 0:67dbd54e60d4 3 *----------------------------------------------------------------------------
doubster 0:67dbd54e60d4 4 * Name: RT_HAL_CM.H
doubster 0:67dbd54e60d4 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
doubster 0:67dbd54e60d4 6 * Rev.: V4.60
doubster 0:67dbd54e60d4 7 *----------------------------------------------------------------------------
doubster 0:67dbd54e60d4 8 *
doubster 0:67dbd54e60d4 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
doubster 0:67dbd54e60d4 10 * All rights reserved.
doubster 0:67dbd54e60d4 11 * Redistribution and use in source and binary forms, with or without
doubster 0:67dbd54e60d4 12 * modification, are permitted provided that the following conditions are met:
doubster 0:67dbd54e60d4 13 * - Redistributions of source code must retain the above copyright
doubster 0:67dbd54e60d4 14 * notice, this list of conditions and the following disclaimer.
doubster 0:67dbd54e60d4 15 * - Redistributions in binary form must reproduce the above copyright
doubster 0:67dbd54e60d4 16 * notice, this list of conditions and the following disclaimer in the
doubster 0:67dbd54e60d4 17 * documentation and/or other materials provided with the distribution.
doubster 0:67dbd54e60d4 18 * - Neither the name of ARM nor the names of its contributors may be used
doubster 0:67dbd54e60d4 19 * to endorse or promote products derived from this software without
doubster 0:67dbd54e60d4 20 * specific prior written permission.
doubster 0:67dbd54e60d4 21 *
doubster 0:67dbd54e60d4 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
doubster 0:67dbd54e60d4 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
doubster 0:67dbd54e60d4 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
doubster 0:67dbd54e60d4 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
doubster 0:67dbd54e60d4 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
doubster 0:67dbd54e60d4 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
doubster 0:67dbd54e60d4 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
doubster 0:67dbd54e60d4 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
doubster 0:67dbd54e60d4 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
doubster 0:67dbd54e60d4 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
doubster 0:67dbd54e60d4 32 * POSSIBILITY OF SUCH DAMAGE.
doubster 0:67dbd54e60d4 33 *---------------------------------------------------------------------------*/
doubster 0:67dbd54e60d4 34
doubster 0:67dbd54e60d4 35 /* Definitions */
doubster 0:67dbd54e60d4 36 #define INITIAL_xPSR 0x01000000
doubster 0:67dbd54e60d4 37 #define DEMCR_TRCENA 0x01000000
doubster 0:67dbd54e60d4 38 #define ITM_ITMENA 0x00000001
doubster 0:67dbd54e60d4 39 #define MAGIC_WORD 0xE25A2EA5
doubster 0:67dbd54e60d4 40
doubster 0:67dbd54e60d4 41 #if defined (__CC_ARM) /* ARM Compiler */
doubster 0:67dbd54e60d4 42
doubster 0:67dbd54e60d4 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
doubster 0:67dbd54e60d4 44 #define __USE_EXCLUSIVE_ACCESS
doubster 0:67dbd54e60d4 45 #else
doubster 0:67dbd54e60d4 46 #undef __USE_EXCLUSIVE_ACCESS
doubster 0:67dbd54e60d4 47 #endif
doubster 0:67dbd54e60d4 48
doubster 0:67dbd54e60d4 49 #elif defined (__GNUC__) /* GNU Compiler */
doubster 0:67dbd54e60d4 50
doubster 0:67dbd54e60d4 51 #undef __USE_EXCLUSIVE_ACCESS
doubster 0:67dbd54e60d4 52
doubster 0:67dbd54e60d4 53 #if defined (__CORTEX_M0)
doubster 0:67dbd54e60d4 54 #define __TARGET_ARCH_6S_M 1
doubster 0:67dbd54e60d4 55 #else
doubster 0:67dbd54e60d4 56 #define __TARGET_ARCH_6S_M 0
doubster 0:67dbd54e60d4 57 #endif
doubster 0:67dbd54e60d4 58
doubster 0:67dbd54e60d4 59 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
doubster 0:67dbd54e60d4 60 #define __TARGET_FPU_VFP 1
doubster 0:67dbd54e60d4 61 #else
doubster 0:67dbd54e60d4 62 #define __TARGET_FPU_VFP 0
doubster 0:67dbd54e60d4 63 #endif
doubster 0:67dbd54e60d4 64
doubster 0:67dbd54e60d4 65 #define __inline inline
doubster 0:67dbd54e60d4 66 #define __weak __attribute__((weak))
doubster 0:67dbd54e60d4 67
doubster 0:67dbd54e60d4 68 #ifndef __CMSIS_GENERIC
doubster 0:67dbd54e60d4 69
doubster 0:67dbd54e60d4 70 __attribute__((always_inline)) static inline void __enable_irq(void)
doubster 0:67dbd54e60d4 71 {
doubster 0:67dbd54e60d4 72 __asm volatile ("cpsie i");
doubster 0:67dbd54e60d4 73 }
doubster 0:67dbd54e60d4 74
doubster 0:67dbd54e60d4 75 __attribute__((always_inline)) static inline U32 __disable_irq(void)
doubster 0:67dbd54e60d4 76 {
doubster 0:67dbd54e60d4 77 U32 result;
doubster 0:67dbd54e60d4 78
doubster 0:67dbd54e60d4 79 __asm volatile ("mrs %0, primask" : "=r" (result));
doubster 0:67dbd54e60d4 80 __asm volatile ("cpsid i");
doubster 0:67dbd54e60d4 81 return(result & 1);
doubster 0:67dbd54e60d4 82 }
doubster 0:67dbd54e60d4 83
doubster 0:67dbd54e60d4 84 #endif
doubster 0:67dbd54e60d4 85
doubster 0:67dbd54e60d4 86 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
doubster 0:67dbd54e60d4 87 {
doubster 0:67dbd54e60d4 88 U8 result;
doubster 0:67dbd54e60d4 89
doubster 0:67dbd54e60d4 90 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
doubster 0:67dbd54e60d4 91 return(result);
doubster 0:67dbd54e60d4 92 }
doubster 0:67dbd54e60d4 93
doubster 0:67dbd54e60d4 94 #elif defined (__ICCARM__) /* IAR Compiler */
doubster 0:67dbd54e60d4 95
doubster 0:67dbd54e60d4 96 #undef __USE_EXCLUSIVE_ACCESS
doubster 0:67dbd54e60d4 97
doubster 0:67dbd54e60d4 98 #if (__CORE__ == __ARM6M__)
doubster 0:67dbd54e60d4 99 #define __TARGET_ARCH_6S_M 1
doubster 0:67dbd54e60d4 100 #else
doubster 0:67dbd54e60d4 101 #define __TARGET_ARCH_6S_M 0
doubster 0:67dbd54e60d4 102 #endif
doubster 0:67dbd54e60d4 103
doubster 0:67dbd54e60d4 104 #if defined __ARMVFP__
doubster 0:67dbd54e60d4 105 #define __TARGET_FPU_VFP 1
doubster 0:67dbd54e60d4 106 #else
doubster 0:67dbd54e60d4 107 #define __TARGET_FPU_VFP 0
doubster 0:67dbd54e60d4 108 #endif
doubster 0:67dbd54e60d4 109
doubster 0:67dbd54e60d4 110 #define __inline inline
doubster 0:67dbd54e60d4 111
doubster 0:67dbd54e60d4 112 #ifndef __CMSIS_GENERIC
doubster 0:67dbd54e60d4 113
doubster 0:67dbd54e60d4 114 static inline void __enable_irq(void)
doubster 0:67dbd54e60d4 115 {
doubster 0:67dbd54e60d4 116 __asm volatile ("cpsie i");
doubster 0:67dbd54e60d4 117 }
doubster 0:67dbd54e60d4 118
doubster 0:67dbd54e60d4 119 static inline U32 __disable_irq(void)
doubster 0:67dbd54e60d4 120 {
doubster 0:67dbd54e60d4 121 U32 result;
doubster 0:67dbd54e60d4 122
doubster 0:67dbd54e60d4 123 __asm volatile ("mrs %0, primask" : "=r" (result));
doubster 0:67dbd54e60d4 124 __asm volatile ("cpsid i");
doubster 0:67dbd54e60d4 125 return(result & 1);
doubster 0:67dbd54e60d4 126 }
doubster 0:67dbd54e60d4 127
doubster 0:67dbd54e60d4 128 #endif
doubster 0:67dbd54e60d4 129
doubster 0:67dbd54e60d4 130 static inline U8 __clz(U32 value)
doubster 0:67dbd54e60d4 131 {
doubster 0:67dbd54e60d4 132 U8 result;
doubster 0:67dbd54e60d4 133
doubster 0:67dbd54e60d4 134 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
doubster 0:67dbd54e60d4 135 return(result);
doubster 0:67dbd54e60d4 136 }
doubster 0:67dbd54e60d4 137
doubster 0:67dbd54e60d4 138 #endif
doubster 0:67dbd54e60d4 139
doubster 0:67dbd54e60d4 140 /* NVIC registers */
doubster 0:67dbd54e60d4 141 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
doubster 0:67dbd54e60d4 142 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
doubster 0:67dbd54e60d4 143 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
doubster 0:67dbd54e60d4 144 #define NVIC_ISER ((volatile U32 *)0xE000E100)
doubster 0:67dbd54e60d4 145 #define NVIC_ICER ((volatile U32 *)0xE000E180)
doubster 0:67dbd54e60d4 146 #if (__TARGET_ARCH_6S_M)
doubster 0:67dbd54e60d4 147 #define NVIC_IP ((volatile U32 *)0xE000E400)
doubster 0:67dbd54e60d4 148 #else
doubster 0:67dbd54e60d4 149 #define NVIC_IP ((volatile U8 *)0xE000E400)
doubster 0:67dbd54e60d4 150 #endif
doubster 0:67dbd54e60d4 151 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
doubster 0:67dbd54e60d4 152 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
doubster 0:67dbd54e60d4 153 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
doubster 0:67dbd54e60d4 154 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
doubster 0:67dbd54e60d4 155
doubster 0:67dbd54e60d4 156 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
doubster 0:67dbd54e60d4 157 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
doubster 0:67dbd54e60d4 158 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
doubster 0:67dbd54e60d4 159 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
doubster 0:67dbd54e60d4 160 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
doubster 0:67dbd54e60d4 161 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
doubster 0:67dbd54e60d4 162
doubster 0:67dbd54e60d4 163 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
doubster 0:67dbd54e60d4 164 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
doubster 0:67dbd54e60d4 165 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
doubster 0:67dbd54e60d4 166 #if (__TARGET_ARCH_6S_M)
doubster 0:67dbd54e60d4 167 #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
doubster 0:67dbd54e60d4 168 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
doubster 0:67dbd54e60d4 169 #else
doubster 0:67dbd54e60d4 170 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
doubster 0:67dbd54e60d4 171 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
doubster 0:67dbd54e60d4 172 #endif
doubster 0:67dbd54e60d4 173 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
doubster 0:67dbd54e60d4 174 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
doubster 0:67dbd54e60d4 175
doubster 0:67dbd54e60d4 176 /* Core Debug registers */
doubster 0:67dbd54e60d4 177 #define DEMCR (*((volatile U32 *)0xE000EDFC))
doubster 0:67dbd54e60d4 178
doubster 0:67dbd54e60d4 179 /* ITM registers */
doubster 0:67dbd54e60d4 180 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
doubster 0:67dbd54e60d4 181 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
doubster 0:67dbd54e60d4 182 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
doubster 0:67dbd54e60d4 183 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
doubster 0:67dbd54e60d4 184 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
doubster 0:67dbd54e60d4 185 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
doubster 0:67dbd54e60d4 186
doubster 0:67dbd54e60d4 187 /* Variables */
doubster 0:67dbd54e60d4 188 extern BIT dbg_msg;
doubster 0:67dbd54e60d4 189
doubster 0:67dbd54e60d4 190 /* Functions */
doubster 0:67dbd54e60d4 191 #ifdef __USE_EXCLUSIVE_ACCESS
doubster 0:67dbd54e60d4 192 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
doubster 0:67dbd54e60d4 193 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
doubster 0:67dbd54e60d4 194 #else
doubster 0:67dbd54e60d4 195 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
doubster 0:67dbd54e60d4 196 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
doubster 0:67dbd54e60d4 197 #endif
doubster 0:67dbd54e60d4 198
doubster 0:67dbd54e60d4 199 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
doubster 0:67dbd54e60d4 200 U32 cnt,c2;
doubster 0:67dbd54e60d4 201 #ifdef __USE_EXCLUSIVE_ACCESS
doubster 0:67dbd54e60d4 202 do {
doubster 0:67dbd54e60d4 203 if ((cnt = __ldrex(count)) == size) {
doubster 0:67dbd54e60d4 204 __clrex();
doubster 0:67dbd54e60d4 205 return (cnt); }
doubster 0:67dbd54e60d4 206 } while (__strex(cnt+1, count));
doubster 0:67dbd54e60d4 207 do {
doubster 0:67dbd54e60d4 208 c2 = (cnt = __ldrex(first)) + 1;
doubster 0:67dbd54e60d4 209 if (c2 == size) c2 = 0;
doubster 0:67dbd54e60d4 210 } while (__strex(c2, first));
doubster 0:67dbd54e60d4 211 #else
doubster 0:67dbd54e60d4 212 __disable_irq();
doubster 0:67dbd54e60d4 213 if ((cnt = *count) < size) {
doubster 0:67dbd54e60d4 214 *count = cnt+1;
doubster 0:67dbd54e60d4 215 c2 = (cnt = *first) + 1;
doubster 0:67dbd54e60d4 216 if (c2 == size) c2 = 0;
doubster 0:67dbd54e60d4 217 *first = c2;
doubster 0:67dbd54e60d4 218 }
doubster 0:67dbd54e60d4 219 __enable_irq ();
doubster 0:67dbd54e60d4 220 #endif
doubster 0:67dbd54e60d4 221 return (cnt);
doubster 0:67dbd54e60d4 222 }
doubster 0:67dbd54e60d4 223
doubster 0:67dbd54e60d4 224 __inline static void rt_systick_init (void) {
doubster 0:67dbd54e60d4 225 NVIC_ST_RELOAD = os_trv;
doubster 0:67dbd54e60d4 226 NVIC_ST_CURRENT = 0;
doubster 0:67dbd54e60d4 227 NVIC_ST_CTRL = 0x0007;
doubster 0:67dbd54e60d4 228 NVIC_SYS_PRI3 |= 0xFF000000;
doubster 0:67dbd54e60d4 229 }
doubster 0:67dbd54e60d4 230
doubster 0:67dbd54e60d4 231 __inline static void rt_svc_init (void) {
doubster 0:67dbd54e60d4 232 #if !(__TARGET_ARCH_6S_M)
doubster 0:67dbd54e60d4 233 int sh,prigroup;
doubster 0:67dbd54e60d4 234 #endif
doubster 0:67dbd54e60d4 235 NVIC_SYS_PRI3 |= 0x00FF0000;
doubster 0:67dbd54e60d4 236 #if (__TARGET_ARCH_6S_M)
doubster 0:67dbd54e60d4 237 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
doubster 0:67dbd54e60d4 238 #else
doubster 0:67dbd54e60d4 239 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
doubster 0:67dbd54e60d4 240 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
doubster 0:67dbd54e60d4 241 if (prigroup >= sh) {
doubster 0:67dbd54e60d4 242 sh = prigroup + 1;
doubster 0:67dbd54e60d4 243 }
doubster 0:67dbd54e60d4 244 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
doubster 0:67dbd54e60d4 245 #endif
doubster 0:67dbd54e60d4 246 }
doubster 0:67dbd54e60d4 247
doubster 0:67dbd54e60d4 248 extern void rt_set_PSP (U32 stack);
doubster 0:67dbd54e60d4 249 extern U32 rt_get_PSP (void);
doubster 0:67dbd54e60d4 250 extern void os_set_env (void);
doubster 0:67dbd54e60d4 251 extern void *_alloc_box (void *box_mem);
doubster 0:67dbd54e60d4 252 extern int _free_box (void *box_mem, void *box);
doubster 0:67dbd54e60d4 253
doubster 0:67dbd54e60d4 254 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
doubster 0:67dbd54e60d4 255 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
doubster 0:67dbd54e60d4 256 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
doubster 0:67dbd54e60d4 257
doubster 0:67dbd54e60d4 258 extern void dbg_init (void);
doubster 0:67dbd54e60d4 259 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
doubster 0:67dbd54e60d4 260 extern void dbg_task_switch (U32 task_id);
doubster 0:67dbd54e60d4 261
doubster 0:67dbd54e60d4 262 #ifdef DBG_MSG
doubster 0:67dbd54e60d4 263 #define DBG_INIT() dbg_init()
doubster 0:67dbd54e60d4 264 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
doubster 0:67dbd54e60d4 265 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
doubster 0:67dbd54e60d4 266 dbg_task_switch(task_id)
doubster 0:67dbd54e60d4 267 #else
doubster 0:67dbd54e60d4 268 #define DBG_INIT()
doubster 0:67dbd54e60d4 269 #define DBG_TASK_NOTIFY(p_tcb,create)
doubster 0:67dbd54e60d4 270 #define DBG_TASK_SWITCH(task_id)
doubster 0:67dbd54e60d4 271 #endif
doubster 0:67dbd54e60d4 272
doubster 0:67dbd54e60d4 273 /*----------------------------------------------------------------------------
doubster 0:67dbd54e60d4 274 * end of file
doubster 0:67dbd54e60d4 275 *---------------------------------------------------------------------------*/
doubster 0:67dbd54e60d4 276
doubster 0:67dbd54e60d4 277