Donatien Garnier
LwIP with PPP & Ethernet integration
This is the mbed port of the LwIP stack: http://savannah.nongnu.org/projects/lwip/
It includes contributed content from NXP's port for LPCxxxx devices: http://www.lpcware.com/content/project/lightweight-ip-lwip-networking-stack
Licence
LwIP is licenced under the BSD licence:
Copyright (c) 2001-2004 Swedish Institute of Computer Science. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. The name of the author may not be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Diff: arch/lpc_phy_dp83848.c
- Revision:
- 2:1a87f74b8e3b
- Parent:
- 0:8e01dca41002
--- a/arch/lpc_phy_dp83848.c Thu May 24 16:49:41 2012 +0000
+++ b/arch/lpc_phy_dp83848.c Fri May 25 08:56:35 2012 +0000
@@ -1,11 +1,11 @@
/**********************************************************************
-* $Id$ lpc_phy_dp83848.c 2011-11-20
+* $Id$ lpc_phy_dp83848.c 2011-11-20
*//**
-* @file lpc_phy_dp83848.c
-* @brief DP83848C PHY status and control.
-* @version 1.0
-* @date 20 Nov. 2011
-* @author NXP MCU SW Application Team
+* @file lpc_phy_dp83848.c
+* @brief DP83848C PHY status and control.
+* @version 1.0
+* @date 20 Nov. 2011
+* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
@@ -24,13 +24,16 @@
**********************************************************************/
#include "lwip/opt.h"
+
+#if NET_ETHERNET
+
#include "lwip/err.h"
-#include "lwip/snmp.h"
+#include "lwip/snmp.h"
#include "lpc_emac_config.h"
#include "lpc_phy.h"
#include "sys_arch.h"
-/** @defgroup dp83848_phy PHY status and control for the DP83848.
+/** @defgroup dp83848_phy PHY status and control for the DP83848.
* @ingroup lwip_phy
*
* Various functions for controlling and monitoring the status of the
@@ -86,12 +89,12 @@
#define DP8_PHYID1_OUI 0x2000 /**< Expected PHY ID1 */
#define DP8_PHYID2_OUI 0x5c90 /**< Expected PHY ID2 */
-/** \brief PHY status structure used to indicate current status of PHY.
- */
+/** \brief PHY status structure used to indicate current status of PHY.
+ */
typedef struct {
- u32_t phy_speed_100mbs:1; /**< 10/100 MBS connection speed flag. */
- u32_t phy_full_duplex:1; /**< Half/full duplex connection speed flag. */
- u32_t phy_link_active:1; /**< Phy link active flag. */
+ u32_t phy_speed_100mbs:1; /**< 10/100 MBS connection speed flag. */
+ u32_t phy_full_duplex:1; /**< Half/full duplex connection speed flag. */
+ u32_t phy_link_active:1; /**< Phy link active flag. */
} PHY_STATUS_TYPE;
/** \brief PHY update flags */
@@ -115,65 +118,65 @@
*/
static s32_t lpc_update_phy_sts(struct netif *netif, u32_t linksts)
{
- s32_t changed = 0;
+ s32_t changed = 0;
- /* Update link active status */
- if (linksts & DP8_VALID_LINK)
- physts.phy_link_active = 1;
- else
- physts.phy_link_active = 0;
+ /* Update link active status */
+ if (linksts & DP8_VALID_LINK)
+ physts.phy_link_active = 1;
+ else
+ physts.phy_link_active = 0;
- /* Full or half duplex */
- if (linksts & DP8_FULLDUPLEX)
- physts.phy_full_duplex = 1;
- else
- physts.phy_full_duplex = 0;
-
- /* Configure 100MBit/10MBit mode. */
- if (linksts & DP8_SPEED10MBPS)
- physts.phy_speed_100mbs = 0;
- else
- physts.phy_speed_100mbs = 1;
+ /* Full or half duplex */
+ if (linksts & DP8_FULLDUPLEX)
+ physts.phy_full_duplex = 1;
+ else
+ physts.phy_full_duplex = 0;
- if (physts.phy_speed_100mbs != olddphysts.phy_speed_100mbs) {
- changed = 1;
- if (physts.phy_speed_100mbs) {
- /* 100MBit mode. */
- lpc_emac_set_speed(1);
+ /* Configure 100MBit/10MBit mode. */
+ if (linksts & DP8_SPEED10MBPS)
+ physts.phy_speed_100mbs = 0;
+ else
+ physts.phy_speed_100mbs = 1;
+
+ if (physts.phy_speed_100mbs != olddphysts.phy_speed_100mbs) {
+ changed = 1;
+ if (physts.phy_speed_100mbs) {
+ /* 100MBit mode. */
+ lpc_emac_set_speed(1);
- NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100000000);
- }
- else {
- /* 10MBit mode. */
- lpc_emac_set_speed(0);
-
- NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
- }
+ NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100000000);
+ }
+ else {
+ /* 10MBit mode. */
+ lpc_emac_set_speed(0);
- olddphysts.phy_speed_100mbs = physts.phy_speed_100mbs;
- }
+ NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
+ }
+
+ olddphysts.phy_speed_100mbs = physts.phy_speed_100mbs;
+ }
- if (physts.phy_full_duplex != olddphysts.phy_full_duplex) {
- changed = 1;
- if (physts.phy_full_duplex)
- lpc_emac_set_duplex(1);
- else
- lpc_emac_set_duplex(0);
+ if (physts.phy_full_duplex != olddphysts.phy_full_duplex) {
+ changed = 1;
+ if (physts.phy_full_duplex)
+ lpc_emac_set_duplex(1);
+ else
+ lpc_emac_set_duplex(0);
- olddphysts.phy_full_duplex = physts.phy_full_duplex;
- }
+ olddphysts.phy_full_duplex = physts.phy_full_duplex;
+ }
- if (physts.phy_link_active != olddphysts.phy_link_active) {
- changed = 1;
- if (physts.phy_link_active)
- netif_set_link_up(netif);
- else
- netif_set_link_down(netif);
+ if (physts.phy_link_active != olddphysts.phy_link_active) {
+ changed = 1;
+ if (physts.phy_link_active)
+ netif_set_link_up(netif);
+ else
+ netif_set_link_down(netif);
- olddphysts.phy_link_active = physts.phy_link_active;
- }
+ olddphysts.phy_link_active = physts.phy_link_active;
+ }
- return changed;
+ return changed;
}
/** \brief Initialize the DP83848 PHY.
@@ -188,81 +191,83 @@
*/
err_t lpc_phy_init(struct netif *netif)
{
- u32_t tmp;
- s32_t i;
+ u32_t tmp;
+ s32_t i;
- physts.phy_speed_100mbs = olddphysts.phy_speed_100mbs = 2;
- physts.phy_full_duplex = olddphysts.phy_full_duplex = 2;
- physts.phy_link_active = olddphysts.phy_link_active = 2;
- phyustate = 0;
+ physts.phy_speed_100mbs = olddphysts.phy_speed_100mbs = 2;
+ physts.phy_full_duplex = olddphysts.phy_full_duplex = 2;
+ physts.phy_link_active = olddphysts.phy_link_active = 2;
+ phyustate = 0;
- /* Only first read and write are checked for failure */
- /* Put the DP83848C in reset mode and wait for completion */
- if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != 0)
- return ERR_TIMEOUT;
- i = 400;
- while (i > 0) {
- osDelay(1); /* 1 ms */
- if (lpc_mii_read(DP8_BMCR_REG, &tmp) != 0)
- return ERR_TIMEOUT;
-
- if (!(tmp & (DP8_RESET | DP8_POWER_DOWN)))
- i = -1;
- else
- i--;
- }
- /* Timeout? */
- if (i == 0)
- return ERR_TIMEOUT;
-
- /* Setup link based on configuration options */
+ /* Only first read and write are checked for failure */
+ /* Put the DP83848C in reset mode and wait for completion */
+ if (lpc_mii_write(DP8_BMCR_REG, DP8_RESET) != 0)
+ return ERR_TIMEOUT;
+ i = 400;
+ while (i > 0) {
+ osDelay(1); /* 1 ms */
+ if (lpc_mii_read(DP8_BMCR_REG, &tmp) != 0)
+ return ERR_TIMEOUT;
+
+ if (!(tmp & (DP8_RESET | DP8_POWER_DOWN)))
+ i = -1;
+ else
+ i--;
+ }
+ /* Timeout? */
+ if (i == 0)
+ return ERR_TIMEOUT;
+
+ /* Setup link based on configuration options */
#if PHY_USE_AUTONEG==1
- tmp = DP8_AUTONEG;
+ tmp = DP8_AUTONEG;
#else
- tmp = 0;
+ tmp = 0;
#endif
#if PHY_USE_100MBS==1
- tmp |= DP8_SPEED_SELECT;
+ tmp |= DP8_SPEED_SELECT;
#endif
#if PHY_USE_FULL_DUPLEX==1
- tmp |= DP8_DUPLEX_MODE;
+ tmp |= DP8_DUPLEX_MODE;
#endif
- lpc_mii_write(DP8_BMCR_REG, tmp);
+ lpc_mii_write(DP8_BMCR_REG, tmp);
- /* The link is not set active at this point, but will be detected
+ /* The link is not set active at this point, but will be detected
later */
- return ERR_OK;
+ return ERR_OK;
}
/* Phy status update state machine */
s32_t lpc_phy_sts_sm(struct netif *netif)
{
- s32_t changed = 0;
+ s32_t changed = 0;
- switch (phyustate) {
- default:
- case 0:
- /* Read BMSR to clear faults */
- lpc_mii_read_noblock(DP8_PHY_STAT_REG);
- phyustate = 1;
- break;
+ switch (phyustate) {
+ default:
+ case 0:
+ /* Read BMSR to clear faults */
+ lpc_mii_read_noblock(DP8_PHY_STAT_REG);
+ phyustate = 1;
+ break;
- case 1:
- /* Wait for read status state */
- if (!lpc_mii_is_busy()) {
- /* Update PHY status */
- changed = lpc_update_phy_sts(netif, lpc_mii_read_data());
- phyustate = 0;
- }
- break;
- }
+ case 1:
+ /* Wait for read status state */
+ if (!lpc_mii_is_busy()) {
+ /* Update PHY status */
+ changed = lpc_update_phy_sts(netif, lpc_mii_read_data());
+ phyustate = 0;
+ }
+ break;
+ }
- return changed;
+ return changed;
}
-/**
- * @}
+#endif
+
+/**
+ * @}
*/
/* --------------------------------- End Of File ------------------------------ */
