Daiki Kato / mbed-os-lychee

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targets/TARGET_RENESAS/TARGET_RZA1XX/serial_api.c@0:f782d9c66c49, 2018-02-02 (annotated)

Committer:
dkato
Date:
Fri Feb 02 05:42:23 2018 +0000
Revision:
0:f782d9c66c49
mbed-os for GR-LYCHEE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:f782d9c66c49 1 /* mbed Microcontroller Library
dkato 0:f782d9c66c49 2 * Copyright (c) 2006-2015 ARM Limited
dkato 0:f782d9c66c49 3 *
dkato 0:f782d9c66c49 4 * Licensed under the Apache License, Version 2.0 (the "License");
dkato 0:f782d9c66c49 5 * you may not use this file except in compliance with the License.
dkato 0:f782d9c66c49 6 * You may obtain a copy of the License at
dkato 0:f782d9c66c49 7 *
dkato 0:f782d9c66c49 8 * http://www.apache.org/licenses/LICENSE-2.0
dkato 0:f782d9c66c49 9 *
dkato 0:f782d9c66c49 10 * Unless required by applicable law or agreed to in writing, software
dkato 0:f782d9c66c49 11 * distributed under the License is distributed on an "AS IS" BASIS,
dkato 0:f782d9c66c49 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
dkato 0:f782d9c66c49 13 * See the License for the specific language governing permissions and
dkato 0:f782d9c66c49 14 * limitations under the License.
dkato 0:f782d9c66c49 15 */
dkato 0:f782d9c66c49 16 // math.h required for floating point operations for baud rate calculation
dkato 0:f782d9c66c49 17 #include "mbed_assert.h"
dkato 0:f782d9c66c49 18 #include <math.h>
dkato 0:f782d9c66c49 19 #include <string.h>
dkato 0:f782d9c66c49 20 #include <stdlib.h>
dkato 0:f782d9c66c49 21
dkato 0:f782d9c66c49 22 #include "serial_api.h"
dkato 0:f782d9c66c49 23 #include "cmsis.h"
dkato 0:f782d9c66c49 24 #include "PeripheralPins.h"
dkato 0:f782d9c66c49 25 #include "gpio_api.h"
dkato 0:f782d9c66c49 26 #include "RZ_A1_Init.h"
dkato 0:f782d9c66c49 27
dkato 0:f782d9c66c49 28 #include "iodefine.h"
dkato 0:f782d9c66c49 29 #include "mbed_drv_cfg.h"
dkato 0:f782d9c66c49 30
dkato 0:f782d9c66c49 31 /******************************************************************************
dkato 0:f782d9c66c49 32 * INITIALIZATION
dkato 0:f782d9c66c49 33 ******************************************************************************/
dkato 0:f782d9c66c49 34 #if defined(TARGET_RZA1H)
dkato 0:f782d9c66c49 35 #define UART_NUM 8
dkato 0:f782d9c66c49 36 #else
dkato 0:f782d9c66c49 37 #define UART_NUM 5
dkato 0:f782d9c66c49 38 #endif
dkato 0:f782d9c66c49 39 #define IRQ_NUM 4
dkato 0:f782d9c66c49 40
dkato 0:f782d9c66c49 41 static void uart0_tx_irq(void);
dkato 0:f782d9c66c49 42 static void uart0_rx_irq(void);
dkato 0:f782d9c66c49 43 static void uart0_er_irq(void);
dkato 0:f782d9c66c49 44 static void uart1_tx_irq(void);
dkato 0:f782d9c66c49 45 static void uart1_rx_irq(void);
dkato 0:f782d9c66c49 46 static void uart1_er_irq(void);
dkato 0:f782d9c66c49 47 static void uart2_tx_irq(void);
dkato 0:f782d9c66c49 48 static void uart2_rx_irq(void);
dkato 0:f782d9c66c49 49 static void uart2_er_irq(void);
dkato 0:f782d9c66c49 50 static void uart3_tx_irq(void);
dkato 0:f782d9c66c49 51 static void uart3_rx_irq(void);
dkato 0:f782d9c66c49 52 static void uart3_er_irq(void);
dkato 0:f782d9c66c49 53 static void uart4_tx_irq(void);
dkato 0:f782d9c66c49 54 static void uart4_rx_irq(void);
dkato 0:f782d9c66c49 55 static void uart4_er_irq(void);
dkato 0:f782d9c66c49 56 #if defined(TARGET_RZA1H)
dkato 0:f782d9c66c49 57 static void uart5_tx_irq(void);
dkato 0:f782d9c66c49 58 static void uart5_rx_irq(void);
dkato 0:f782d9c66c49 59 static void uart5_er_irq(void);
dkato 0:f782d9c66c49 60 static void uart6_tx_irq(void);
dkato 0:f782d9c66c49 61 static void uart6_rx_irq(void);
dkato 0:f782d9c66c49 62 static void uart6_er_irq(void);
dkato 0:f782d9c66c49 63 static void uart7_tx_irq(void);
dkato 0:f782d9c66c49 64 static void uart7_rx_irq(void);
dkato 0:f782d9c66c49 65 static void uart7_er_irq(void);
dkato 0:f782d9c66c49 66 #endif
dkato 0:f782d9c66c49 67
dkato 0:f782d9c66c49 68 static void serial_put_done(serial_t *obj);
dkato 0:f782d9c66c49 69 static uint8_t serial_available_buffer(serial_t *obj);
dkato 0:f782d9c66c49 70 static void serial_irq_err_set(serial_t *obj, uint32_t enable);
dkato 0:f782d9c66c49 71
dkato 0:f782d9c66c49 72 static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
dkato 0:f782d9c66c49 73 static uart_irq_handler irq_handler;
dkato 0:f782d9c66c49 74
dkato 0:f782d9c66c49 75 int stdio_uart_inited = 0;
dkato 0:f782d9c66c49 76 serial_t stdio_uart;
dkato 0:f782d9c66c49 77
dkato 0:f782d9c66c49 78 struct serial_global_data_s {
dkato 0:f782d9c66c49 79 uint32_t serial_irq_id;
dkato 0:f782d9c66c49 80 gpio_t sw_rts, sw_cts;
dkato 0:f782d9c66c49 81 serial_t *tranferring_obj, *receiving_obj;
dkato 0:f782d9c66c49 82 uint32_t async_tx_callback, async_rx_callback;
dkato 0:f782d9c66c49 83 int event, wanted_rx_events;
dkato 0:f782d9c66c49 84 };
dkato 0:f782d9c66c49 85
dkato 0:f782d9c66c49 86 static struct serial_global_data_s uart_data[UART_NUM];
dkato 0:f782d9c66c49 87
dkato 0:f782d9c66c49 88 static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
dkato 0:f782d9c66c49 89 {SCIFRXI0_IRQn, SCIFTXI0_IRQn, SCIFBRI0_IRQn, SCIFERI0_IRQn},
dkato 0:f782d9c66c49 90 {SCIFRXI1_IRQn, SCIFTXI1_IRQn, SCIFBRI1_IRQn, SCIFERI1_IRQn},
dkato 0:f782d9c66c49 91 {SCIFRXI2_IRQn, SCIFTXI2_IRQn, SCIFBRI2_IRQn, SCIFERI2_IRQn},
dkato 0:f782d9c66c49 92 {SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn},
dkato 0:f782d9c66c49 93 {SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn},
dkato 0:f782d9c66c49 94 #if defined(TARGET_RZA1H)
dkato 0:f782d9c66c49 95 {SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn},
dkato 0:f782d9c66c49 96 {SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn},
dkato 0:f782d9c66c49 97 {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn},
dkato 0:f782d9c66c49 98 #endif
dkato 0:f782d9c66c49 99 };
dkato 0:f782d9c66c49 100
dkato 0:f782d9c66c49 101 static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
dkato 0:f782d9c66c49 102 {uart0_rx_irq, uart0_tx_irq, uart0_er_irq, uart0_er_irq},
dkato 0:f782d9c66c49 103 {uart1_rx_irq, uart1_tx_irq, uart1_er_irq, uart1_er_irq},
dkato 0:f782d9c66c49 104 {uart2_rx_irq, uart2_tx_irq, uart2_er_irq, uart2_er_irq},
dkato 0:f782d9c66c49 105 {uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq},
dkato 0:f782d9c66c49 106 {uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq},
dkato 0:f782d9c66c49 107 #if defined(TARGET_RZA1H)
dkato 0:f782d9c66c49 108 {uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq},
dkato 0:f782d9c66c49 109 {uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq},
dkato 0:f782d9c66c49 110 {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq},
dkato 0:f782d9c66c49 111 #endif
dkato 0:f782d9c66c49 112 };
dkato 0:f782d9c66c49 113
dkato 0:f782d9c66c49 114 static __IO uint16_t *SCSCR_MATCH[] = {
dkato 0:f782d9c66c49 115 &SCSCR_0,
dkato 0:f782d9c66c49 116 &SCSCR_1,
dkato 0:f782d9c66c49 117 &SCSCR_2,
dkato 0:f782d9c66c49 118 &SCSCR_3,
dkato 0:f782d9c66c49 119 &SCSCR_4,
dkato 0:f782d9c66c49 120 #if defined(TARGET_RZA1H)
dkato 0:f782d9c66c49 121 &SCSCR_5,
dkato 0:f782d9c66c49 122 &SCSCR_6,
dkato 0:f782d9c66c49 123 &SCSCR_7,
dkato 0:f782d9c66c49 124 #endif
dkato 0:f782d9c66c49 125 };
dkato 0:f782d9c66c49 126
dkato 0:f782d9c66c49 127 static __IO uint16_t *SCFSR_MATCH[] = {
dkato 0:f782d9c66c49 128 &SCFSR_0,
dkato 0:f782d9c66c49 129 &SCFSR_1,
dkato 0:f782d9c66c49 130 &SCFSR_2,
dkato 0:f782d9c66c49 131 &SCFSR_3,
dkato 0:f782d9c66c49 132 &SCFSR_4,
dkato 0:f782d9c66c49 133 #if defined(TARGET_RZA1H)
dkato 0:f782d9c66c49 134 &SCFSR_5,
dkato 0:f782d9c66c49 135 &SCFSR_6,
dkato 0:f782d9c66c49 136 &SCFSR_7,
dkato 0:f782d9c66c49 137 #endif
dkato 0:f782d9c66c49 138 };
dkato 0:f782d9c66c49 139
dkato 0:f782d9c66c49 140
dkato 0:f782d9c66c49 141 void serial_init(serial_t *obj, PinName tx, PinName rx) {
dkato 0:f782d9c66c49 142 volatile uint8_t dummy ;
dkato 0:f782d9c66c49 143 int is_stdio_uart = 0;
dkato 0:f782d9c66c49 144 // determine the UART to use
dkato 0:f782d9c66c49 145 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
dkato 0:f782d9c66c49 146 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
dkato 0:f782d9c66c49 147 uint32_t uart = pinmap_merge(uart_tx, uart_rx);
dkato 0:f782d9c66c49 148
dkato 0:f782d9c66c49 149 MBED_ASSERT((int)uart != NC);
dkato 0:f782d9c66c49 150
dkato 0:f782d9c66c49 151 obj->serial.uart = (struct st_scif *)SCIF[uart];
dkato 0:f782d9c66c49 152 // enable power
dkato 0:f782d9c66c49 153 CPG.STBCR4 &= ~(1 << (7 - uart));
dkato 0:f782d9c66c49 154 dummy = CPG.STBCR4;
dkato 0:f782d9c66c49 155
dkato 0:f782d9c66c49 156 /* ==== SCIF initial setting ==== */
dkato 0:f782d9c66c49 157 /* ---- Serial control register (SCSCR) setting ---- */
dkato 0:f782d9c66c49 158 /* B'00 : Internal CLK */
dkato 0:f782d9c66c49 159 obj->serial.uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */
dkato 0:f782d9c66c49 160
dkato 0:f782d9c66c49 161 /* ---- FIFO control register (SCFCR) setting ---- */
dkato 0:f782d9c66c49 162 /* Transmit FIFO reset & Receive FIFO data register reset */
dkato 0:f782d9c66c49 163 obj->serial.uart->SCFCR = 0x0006u;
dkato 0:f782d9c66c49 164
dkato 0:f782d9c66c49 165 /* ---- Serial status register (SCFSR) setting ---- */
dkato 0:f782d9c66c49 166 dummy = obj->serial.uart->SCFSR;
dkato 0:f782d9c66c49 167 obj->serial.uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */
dkato 0:f782d9c66c49 168
dkato 0:f782d9c66c49 169 /* ---- Line status register (SCLSR) setting ---- */
dkato 0:f782d9c66c49 170 /* ORER bit clear */
dkato 0:f782d9c66c49 171 obj->serial.uart->SCLSR = 0;
dkato 0:f782d9c66c49 172
dkato 0:f782d9c66c49 173 /* ---- Serial extension mode register (SCEMR) setting ----
dkato 0:f782d9c66c49 174 b7 BGDM - Baud rate generator double-speed mode : Normal mode
dkato 0:f782d9c66c49 175 b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */
dkato 0:f782d9c66c49 176 obj->serial.uart->SCEMR = 0x0000u;
dkato 0:f782d9c66c49 177
dkato 0:f782d9c66c49 178 /* ---- Bit rate register (SCBRR) setting ---- */
dkato 0:f782d9c66c49 179 serial_baud (obj, 9600);
dkato 0:f782d9c66c49 180 serial_format(obj, 8, ParityNone, 1);
dkato 0:f782d9c66c49 181
dkato 0:f782d9c66c49 182 /* ---- FIFO control register (SCFCR) setting ---- */
dkato 0:f782d9c66c49 183 obj->serial.uart->SCFCR = 0x0030u;
dkato 0:f782d9c66c49 184
dkato 0:f782d9c66c49 185 /* ---- Serial port register (SCSPTR) setting ----
dkato 0:f782d9c66c49 186 b1 SPB2IO - Serial port break output : disabled
dkato 0:f782d9c66c49 187 b0 SPB2DT - Serial port break data : High-level */
dkato 0:f782d9c66c49 188 obj->serial.uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1
dkato 0:f782d9c66c49 189
dkato 0:f782d9c66c49 190 /* ---- Line status register (SCLSR) setting ----
dkato 0:f782d9c66c49 191 b0 ORER - Overrun error detect : clear */
dkato 0:f782d9c66c49 192
dkato 0:f782d9c66c49 193 if (obj->serial.uart->SCLSR & 0x0001) {
dkato 0:f782d9c66c49 194 obj->serial.uart->SCLSR = 0u; // ORER clear
dkato 0:f782d9c66c49 195 }
dkato 0:f782d9c66c49 196
dkato 0:f782d9c66c49 197 // pinout the chosen uart
dkato 0:f782d9c66c49 198 pinmap_pinout(tx, PinMap_UART_TX);
dkato 0:f782d9c66c49 199 pinmap_pinout(rx, PinMap_UART_RX);
dkato 0:f782d9c66c49 200
dkato 0:f782d9c66c49 201 obj->serial.index = uart;
dkato 0:f782d9c66c49 202
dkato 0:f782d9c66c49 203 uart_data[obj->serial.index].sw_rts.pin = NC;
dkato 0:f782d9c66c49 204 uart_data[obj->serial.index].sw_cts.pin = NC;
dkato 0:f782d9c66c49 205
dkato 0:f782d9c66c49 206 /* ---- Serial control register (SCSCR) setting ---- */
dkato 0:f782d9c66c49 207 /* Setting the TE and RE bits enables the TxD and RxD pins to be used. */
dkato 0:f782d9c66c49 208 obj->serial.uart->SCSCR = 0x0070;
dkato 0:f782d9c66c49 209
dkato 0:f782d9c66c49 210 is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
dkato 0:f782d9c66c49 211
dkato 0:f782d9c66c49 212 if (is_stdio_uart) {
dkato 0:f782d9c66c49 213 stdio_uart_inited = 1;
dkato 0:f782d9c66c49 214 memcpy(&stdio_uart, obj, sizeof(serial_t));
dkato 0:f782d9c66c49 215 }
dkato 0:f782d9c66c49 216 }
dkato 0:f782d9c66c49 217
dkato 0:f782d9c66c49 218 void serial_free(serial_t *obj) {
dkato 0:f782d9c66c49 219 uart_data[obj->serial.index].serial_irq_id = 0;
dkato 0:f782d9c66c49 220 }
dkato 0:f782d9c66c49 221
dkato 0:f782d9c66c49 222 // serial_baud
dkato 0:f782d9c66c49 223 // set the baud rate, taking in to account the current SystemFrequency
dkato 0:f782d9c66c49 224 void serial_baud(serial_t *obj, int baudrate) {
dkato 0:f782d9c66c49 225 uint32_t pclk_base;
dkato 0:f782d9c66c49 226 uint32_t bgdm = 1;
dkato 0:f782d9c66c49 227 uint32_t cks = 0;
dkato 0:f782d9c66c49 228 uint32_t DL;
dkato 0:f782d9c66c49 229
dkato 0:f782d9c66c49 230 if (RZ_A1_IsClockMode0() == false) {
dkato 0:f782d9c66c49 231 pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
dkato 0:f782d9c66c49 232 } else {
dkato 0:f782d9c66c49 233 pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
dkato 0:f782d9c66c49 234 }
dkato 0:f782d9c66c49 235
dkato 0:f782d9c66c49 236 if (baudrate > (int)(pclk_base / 0x800)) {
dkato 0:f782d9c66c49 237 obj->serial.uart->SCSMR &= ~0x0003;
dkato 0:f782d9c66c49 238 obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1
dkato 0:f782d9c66c49 239 DL = (pclk_base + (4 * baudrate)) / (8 * baudrate); // Rounding
dkato 0:f782d9c66c49 240 if (DL > 0) {
dkato 0:f782d9c66c49 241 DL--;
dkato 0:f782d9c66c49 242 }
dkato 0:f782d9c66c49 243 obj->serial.uart->SCBRR = (uint8_t)DL;
dkato 0:f782d9c66c49 244 } else if (baudrate < (int)(pclk_base / 0x80000)) {
dkato 0:f782d9c66c49 245 obj->serial.uart->SCSMR |= 0x0003;
dkato 0:f782d9c66c49 246 obj->serial.uart->SCEMR = 0x0000;
dkato 0:f782d9c66c49 247 obj->serial.uart->SCBRR = 0xFFu;
dkato 0:f782d9c66c49 248 } else {
dkato 0:f782d9c66c49 249 DL = (pclk_base + (8 * baudrate)) / (16 * baudrate); // Rounding
dkato 0:f782d9c66c49 250 while (DL > 256) {
dkato 0:f782d9c66c49 251 DL >>= 1;
dkato 0:f782d9c66c49 252 if (bgdm == 1) {
dkato 0:f782d9c66c49 253 bgdm = 0;
dkato 0:f782d9c66c49 254 } else {
dkato 0:f782d9c66c49 255 bgdm = 1;
dkato 0:f782d9c66c49 256 cks++;
dkato 0:f782d9c66c49 257 }
dkato 0:f782d9c66c49 258 }
dkato 0:f782d9c66c49 259 obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0003) | (uint8_t)cks;
dkato 0:f782d9c66c49 260 obj->serial.uart->SCEMR = (uint8_t)(bgdm << 7);
dkato 0:f782d9c66c49 261 obj->serial.uart->SCBRR = (uint8_t)(DL - 1);
dkato 0:f782d9c66c49 262 }
dkato 0:f782d9c66c49 263 }
dkato 0:f782d9c66c49 264
dkato 0:f782d9c66c49 265 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
dkato 0:f782d9c66c49 266 int parity_enable;
dkato 0:f782d9c66c49 267 int parity_select;
dkato 0:f782d9c66c49 268
dkato 0:f782d9c66c49 269 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
dkato 0:f782d9c66c49 270 MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits
dkato 0:f782d9c66c49 271 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
dkato 0:f782d9c66c49 272 (parity == ParityForced1) || (parity == ParityForced0));
dkato 0:f782d9c66c49 273
dkato 0:f782d9c66c49 274 stop_bits = (stop_bits == 1)? 0:
dkato 0:f782d9c66c49 275 (stop_bits == 2)? 1:
dkato 0:f782d9c66c49 276 0; // must not to be
dkato 0:f782d9c66c49 277
dkato 0:f782d9c66c49 278 data_bits = (data_bits == 8)? 0:
dkato 0:f782d9c66c49 279 (data_bits == 7)? 1:
dkato 0:f782d9c66c49 280 0; // must not to be
dkato 0:f782d9c66c49 281
dkato 0:f782d9c66c49 282 switch (parity) {
dkato 0:f782d9c66c49 283 case ParityNone:
dkato 0:f782d9c66c49 284 parity_enable = 0;
dkato 0:f782d9c66c49 285 parity_select = 0;
dkato 0:f782d9c66c49 286 break;
dkato 0:f782d9c66c49 287 case ParityOdd:
dkato 0:f782d9c66c49 288 parity_enable = 1;
dkato 0:f782d9c66c49 289 parity_select = 1;
dkato 0:f782d9c66c49 290 break;
dkato 0:f782d9c66c49 291 case ParityEven:
dkato 0:f782d9c66c49 292 parity_enable = 1;
dkato 0:f782d9c66c49 293 parity_select = 0;
dkato 0:f782d9c66c49 294 break;
dkato 0:f782d9c66c49 295 case ParityForced1:
dkato 0:f782d9c66c49 296 case ParityForced0:
dkato 0:f782d9c66c49 297 default:
dkato 0:f782d9c66c49 298 parity_enable = 0;
dkato 0:f782d9c66c49 299 parity_select = 0;
dkato 0:f782d9c66c49 300 break;
dkato 0:f782d9c66c49 301 }
dkato 0:f782d9c66c49 302
dkato 0:f782d9c66c49 303 obj->serial.uart->SCSMR = data_bits << 6
dkato 0:f782d9c66c49 304 | parity_enable << 5
dkato 0:f782d9c66c49 305 | parity_select << 4
dkato 0:f782d9c66c49 306 | stop_bits << 3;
dkato 0:f782d9c66c49 307 }
dkato 0:f782d9c66c49 308
dkato 0:f782d9c66c49 309 /******************************************************************************
dkato 0:f782d9c66c49 310 * INTERRUPTS HANDLING
dkato 0:f782d9c66c49 311 ******************************************************************************/
dkato 0:f782d9c66c49 312
dkato 0:f782d9c66c49 313 static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
dkato 0:f782d9c66c49 314 __IO uint16_t *dmy_rd_scscr;
dkato 0:f782d9c66c49 315 __IO uint16_t *dmy_rd_scfsr;
dkato 0:f782d9c66c49 316 serial_t *obj;
dkato 0:f782d9c66c49 317 int i;
dkato 0:f782d9c66c49 318
dkato 0:f782d9c66c49 319 dmy_rd_scscr = SCSCR_MATCH[index];
dkato 0:f782d9c66c49 320 *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0
dkato 0:f782d9c66c49 321 dmy_rd_scfsr = SCFSR_MATCH[index];
dkato 0:f782d9c66c49 322 *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Set TEND
dkato 0:f782d9c66c49 323
dkato 0:f782d9c66c49 324 obj = uart_data[index].tranferring_obj;
dkato 0:f782d9c66c49 325 if (obj) {
dkato 0:f782d9c66c49 326 i = obj->tx_buff.length - obj->tx_buff.pos;
dkato 0:f782d9c66c49 327 if (0 < i) {
dkato 0:f782d9c66c49 328 if (serial_available_buffer(obj) < i) {
dkato 0:f782d9c66c49 329 i = serial_available_buffer(obj);
dkato 0:f782d9c66c49 330 }
dkato 0:f782d9c66c49 331 do {
dkato 0:f782d9c66c49 332 uint8_t c = *(uint8_t *)obj->tx_buff.buffer;
dkato 0:f782d9c66c49 333 obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
dkato 0:f782d9c66c49 334 ++obj->tx_buff.pos;
dkato 0:f782d9c66c49 335 obj->serial.uart->SCFTDR = c;
dkato 0:f782d9c66c49 336 } while (--i);
dkato 0:f782d9c66c49 337 serial_put_done(obj);
dkato 0:f782d9c66c49 338 } else {
dkato 0:f782d9c66c49 339 uart_data[index].tranferring_obj = NULL;
dkato 0:f782d9c66c49 340 uart_data[index].event = SERIAL_EVENT_TX_COMPLETE;
dkato 0:f782d9c66c49 341 ((void (*)())uart_data[index].async_tx_callback)();
dkato 0:f782d9c66c49 342 }
dkato 0:f782d9c66c49 343 }
dkato 0:f782d9c66c49 344
dkato 0:f782d9c66c49 345 irq_handler(uart_data[index].serial_irq_id, TxIrq);
dkato 0:f782d9c66c49 346 }
dkato 0:f782d9c66c49 347
dkato 0:f782d9c66c49 348 static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
dkato 0:f782d9c66c49 349 __IO uint16_t *dmy_rd_scscr;
dkato 0:f782d9c66c49 350 __IO uint16_t *dmy_rd_scfsr;
dkato 0:f782d9c66c49 351 serial_t *obj;
dkato 0:f782d9c66c49 352 int c;
dkato 0:f782d9c66c49 353
dkato 0:f782d9c66c49 354 dmy_rd_scscr = SCSCR_MATCH[index];
dkato 0:f782d9c66c49 355 *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0
dkato 0:f782d9c66c49 356 dmy_rd_scfsr = SCFSR_MATCH[index];
dkato 0:f782d9c66c49 357 *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR
dkato 0:f782d9c66c49 358
dkato 0:f782d9c66c49 359 obj = uart_data[index].receiving_obj;
dkato 0:f782d9c66c49 360 if (obj) {
dkato 0:f782d9c66c49 361 if (obj->serial.uart->SCLSR & 1) {
dkato 0:f782d9c66c49 362 if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_OVERRUN_ERROR) {
dkato 0:f782d9c66c49 363 serial_rx_abort_asynch(obj);
dkato 0:f782d9c66c49 364 uart_data[index].event = SERIAL_EVENT_RX_OVERRUN_ERROR;
dkato 0:f782d9c66c49 365 ((void (*)())uart_data[index].async_rx_callback)();
dkato 0:f782d9c66c49 366 }
dkato 0:f782d9c66c49 367 return;
dkato 0:f782d9c66c49 368 }
dkato 0:f782d9c66c49 369 c = serial_getc(obj);
dkato 0:f782d9c66c49 370 if (c != -1) {
dkato 0:f782d9c66c49 371 ((uint8_t *)obj->rx_buff.buffer)[obj->rx_buff.pos] = c;
dkato 0:f782d9c66c49 372 ++obj->rx_buff.pos;
dkato 0:f782d9c66c49 373 if (c == obj->char_match && ! obj->char_found) {
dkato 0:f782d9c66c49 374 obj->char_found = 1;
dkato 0:f782d9c66c49 375 if (obj->rx_buff.pos == obj->rx_buff.length) {
dkato 0:f782d9c66c49 376 if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) {
dkato 0:f782d9c66c49 377 uart_data[index].event = SERIAL_EVENT_RX_COMPLETE;
dkato 0:f782d9c66c49 378 }
dkato 0:f782d9c66c49 379 }
dkato 0:f782d9c66c49 380 if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_CHARACTER_MATCH) {
dkato 0:f782d9c66c49 381 uart_data[index].event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
dkato 0:f782d9c66c49 382 }
dkato 0:f782d9c66c49 383 if (uart_data[index].event) {
dkato 0:f782d9c66c49 384 uart_data[index].receiving_obj = NULL;
dkato 0:f782d9c66c49 385 ((void (*)())uart_data[index].async_rx_callback)();
dkato 0:f782d9c66c49 386 }
dkato 0:f782d9c66c49 387 } else if (obj->rx_buff.pos == obj->rx_buff.length) {
dkato 0:f782d9c66c49 388 uart_data[index].receiving_obj = NULL;
dkato 0:f782d9c66c49 389 if (uart_data[index].wanted_rx_events & SERIAL_EVENT_RX_COMPLETE) {
dkato 0:f782d9c66c49 390 uart_data[index].event = SERIAL_EVENT_RX_COMPLETE;
dkato 0:f782d9c66c49 391 ((void (*)())uart_data[index].async_rx_callback)();
dkato 0:f782d9c66c49 392 }
dkato 0:f782d9c66c49 393 }
dkato 0:f782d9c66c49 394 } else {
dkato 0:f782d9c66c49 395 serial_rx_abort_asynch(obj);
dkato 0:f782d9c66c49 396 if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) {
dkato 0:f782d9c66c49 397 uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR;
dkato 0:f782d9c66c49 398 if (obj->serial.uart->SCFSR & 1 << 2) {
dkato 0:f782d9c66c49 399 uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR;
dkato 0:f782d9c66c49 400 } else if (obj->serial.uart->SCFSR & 1 << 3) {
dkato 0:f782d9c66c49 401 uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR;
dkato 0:f782d9c66c49 402 }
dkato 0:f782d9c66c49 403 ((void (*)())uart_data[index].async_rx_callback)();
dkato 0:f782d9c66c49 404 }
dkato 0:f782d9c66c49 405 return;
dkato 0:f782d9c66c49 406 }
dkato 0:f782d9c66c49 407 }
dkato 0:f782d9c66c49 408
dkato 0:f782d9c66c49 409 irq_handler(uart_data[index].serial_irq_id, RxIrq);
dkato 0:f782d9c66c49 410 }
dkato 0:f782d9c66c49 411
dkato 0:f782d9c66c49 412 static void uart_err_irq(IRQn_Type irq_num, uint32_t index) {
dkato 0:f782d9c66c49 413 serial_t *obj = uart_data[index].receiving_obj;
dkato 0:f782d9c66c49 414 int was_masked, err_read;
dkato 0:f782d9c66c49 415
dkato 0:f782d9c66c49 416 if (obj) {
dkato 0:f782d9c66c49 417 serial_irq_err_set(obj, 0);
dkato 0:f782d9c66c49 418 if (uart_data[index].wanted_rx_events & (SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR)) {
dkato 0:f782d9c66c49 419 uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR | SERIAL_EVENT_RX_FRAMING_ERROR;
dkato 0:f782d9c66c49 420 if (obj->serial.uart->SCFSR & 1 << 2) {
dkato 0:f782d9c66c49 421 uart_data[index].event = SERIAL_EVENT_RX_PARITY_ERROR;
dkato 0:f782d9c66c49 422 } else if (obj->serial.uart->SCFSR & 1 << 3) {
dkato 0:f782d9c66c49 423 uart_data[index].event = SERIAL_EVENT_RX_FRAMING_ERROR;
dkato 0:f782d9c66c49 424 }
dkato 0:f782d9c66c49 425 ((void (*)())uart_data[index].async_rx_callback)();
dkato 0:f782d9c66c49 426 }
dkato 0:f782d9c66c49 427 serial_rx_abort_asynch(obj);
dkato 0:f782d9c66c49 428
dkato 0:f782d9c66c49 429 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 430 was_masked = __disable_irq_iar();
dkato 0:f782d9c66c49 431 #else
dkato 0:f782d9c66c49 432 was_masked = __disable_irq();
dkato 0:f782d9c66c49 433 #endif /* __ICCARM__ */
dkato 0:f782d9c66c49 434 if (obj->serial.uart->SCFSR & 0x93) {
dkato 0:f782d9c66c49 435 err_read = obj->serial.uart->SCFSR;
dkato 0:f782d9c66c49 436 obj->serial.uart->SCFSR = (err_read & ~0x93);
dkato 0:f782d9c66c49 437 }
dkato 0:f782d9c66c49 438 if (obj->serial.uart->SCLSR & 1) {
dkato 0:f782d9c66c49 439 obj->serial.uart->SCLSR = 0;
dkato 0:f782d9c66c49 440 }
dkato 0:f782d9c66c49 441 if (!was_masked) {
dkato 0:f782d9c66c49 442 __enable_irq();
dkato 0:f782d9c66c49 443 }
dkato 0:f782d9c66c49 444 }
dkato 0:f782d9c66c49 445 }
dkato 0:f782d9c66c49 446
dkato 0:f782d9c66c49 447 static void uart0_tx_irq(void) {
dkato 0:f782d9c66c49 448 uart_tx_irq(SCIFTXI0_IRQn, 0);
dkato 0:f782d9c66c49 449 }
dkato 0:f782d9c66c49 450 static void uart0_rx_irq(void) {
dkato 0:f782d9c66c49 451 uart_rx_irq(SCIFRXI0_IRQn, 0);
dkato 0:f782d9c66c49 452 }
dkato 0:f782d9c66c49 453 static void uart0_er_irq(void) {
dkato 0:f782d9c66c49 454 uart_err_irq(SCIFERI0_IRQn, 0);
dkato 0:f782d9c66c49 455 }
dkato 0:f782d9c66c49 456
dkato 0:f782d9c66c49 457 static void uart1_tx_irq(void) {
dkato 0:f782d9c66c49 458 uart_tx_irq(SCIFTXI1_IRQn, 1);
dkato 0:f782d9c66c49 459 }
dkato 0:f782d9c66c49 460 static void uart1_rx_irq(void) {
dkato 0:f782d9c66c49 461 uart_rx_irq(SCIFRXI1_IRQn, 1);
dkato 0:f782d9c66c49 462 }
dkato 0:f782d9c66c49 463 static void uart1_er_irq(void) {
dkato 0:f782d9c66c49 464 uart_err_irq(SCIFERI1_IRQn, 1);
dkato 0:f782d9c66c49 465 }
dkato 0:f782d9c66c49 466
dkato 0:f782d9c66c49 467 static void uart2_tx_irq(void) {
dkato 0:f782d9c66c49 468 uart_tx_irq(SCIFTXI2_IRQn, 2);
dkato 0:f782d9c66c49 469 }
dkato 0:f782d9c66c49 470 static void uart2_rx_irq(void) {
dkato 0:f782d9c66c49 471 uart_rx_irq(SCIFRXI2_IRQn, 2);
dkato 0:f782d9c66c49 472 }
dkato 0:f782d9c66c49 473 static void uart2_er_irq(void) {
dkato 0:f782d9c66c49 474 uart_err_irq(SCIFERI2_IRQn, 2);
dkato 0:f782d9c66c49 475 }
dkato 0:f782d9c66c49 476
dkato 0:f782d9c66c49 477 static void uart3_tx_irq(void) {
dkato 0:f782d9c66c49 478 uart_tx_irq(SCIFTXI3_IRQn, 3);
dkato 0:f782d9c66c49 479 }
dkato 0:f782d9c66c49 480 static void uart3_rx_irq(void) {
dkato 0:f782d9c66c49 481 uart_rx_irq(SCIFRXI3_IRQn, 3);
dkato 0:f782d9c66c49 482 }
dkato 0:f782d9c66c49 483 static void uart3_er_irq(void) {
dkato 0:f782d9c66c49 484 uart_err_irq(SCIFERI3_IRQn, 3);
dkato 0:f782d9c66c49 485 }
dkato 0:f782d9c66c49 486
dkato 0:f782d9c66c49 487 static void uart4_tx_irq(void) {
dkato 0:f782d9c66c49 488 uart_tx_irq(SCIFTXI4_IRQn, 4);
dkato 0:f782d9c66c49 489 }
dkato 0:f782d9c66c49 490 static void uart4_rx_irq(void) {
dkato 0:f782d9c66c49 491 uart_rx_irq(SCIFRXI4_IRQn, 4);
dkato 0:f782d9c66c49 492 }
dkato 0:f782d9c66c49 493 static void uart4_er_irq(void) {
dkato 0:f782d9c66c49 494 uart_err_irq(SCIFERI4_IRQn, 4);
dkato 0:f782d9c66c49 495 }
dkato 0:f782d9c66c49 496
dkato 0:f782d9c66c49 497 #if defined(TARGET_RZA1H)
dkato 0:f782d9c66c49 498 static void uart5_tx_irq(void) {
dkato 0:f782d9c66c49 499 uart_tx_irq(SCIFTXI5_IRQn, 5);
dkato 0:f782d9c66c49 500 }
dkato 0:f782d9c66c49 501 static void uart5_rx_irq(void) {
dkato 0:f782d9c66c49 502 uart_rx_irq(SCIFRXI5_IRQn, 5);
dkato 0:f782d9c66c49 503 }
dkato 0:f782d9c66c49 504 static void uart5_er_irq(void) {
dkato 0:f782d9c66c49 505 uart_err_irq(SCIFERI5_IRQn, 5);
dkato 0:f782d9c66c49 506 }
dkato 0:f782d9c66c49 507
dkato 0:f782d9c66c49 508 static void uart6_tx_irq(void) {
dkato 0:f782d9c66c49 509 uart_tx_irq(SCIFTXI6_IRQn, 6);
dkato 0:f782d9c66c49 510 }
dkato 0:f782d9c66c49 511 static void uart6_rx_irq(void) {
dkato 0:f782d9c66c49 512 uart_rx_irq(SCIFRXI6_IRQn, 6);
dkato 0:f782d9c66c49 513 }
dkato 0:f782d9c66c49 514 static void uart6_er_irq(void) {
dkato 0:f782d9c66c49 515 uart_err_irq(SCIFERI6_IRQn, 6);
dkato 0:f782d9c66c49 516 }
dkato 0:f782d9c66c49 517
dkato 0:f782d9c66c49 518 static void uart7_tx_irq(void) {
dkato 0:f782d9c66c49 519 uart_tx_irq(SCIFTXI7_IRQn, 7);
dkato 0:f782d9c66c49 520 }
dkato 0:f782d9c66c49 521 static void uart7_rx_irq(void) {
dkato 0:f782d9c66c49 522 uart_rx_irq(SCIFRXI7_IRQn, 7);
dkato 0:f782d9c66c49 523 }
dkato 0:f782d9c66c49 524 static void uart7_er_irq(void) {
dkato 0:f782d9c66c49 525 uart_err_irq(SCIFERI7_IRQn, 7);
dkato 0:f782d9c66c49 526 }
dkato 0:f782d9c66c49 527 #endif
dkato 0:f782d9c66c49 528
dkato 0:f782d9c66c49 529 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
dkato 0:f782d9c66c49 530 irq_handler = handler;
dkato 0:f782d9c66c49 531 uart_data[obj->serial.index].serial_irq_id = id;
dkato 0:f782d9c66c49 532 }
dkato 0:f782d9c66c49 533
dkato 0:f782d9c66c49 534 static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enable)
dkato 0:f782d9c66c49 535 {
dkato 0:f782d9c66c49 536 if (enable) {
dkato 0:f782d9c66c49 537 InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
dkato 0:f782d9c66c49 538 GIC_SetPriority(IRQn, 5);
dkato 0:f782d9c66c49 539 GIC_EnableIRQ(IRQn);
dkato 0:f782d9c66c49 540 } else {
dkato 0:f782d9c66c49 541 GIC_DisableIRQ(IRQn);
dkato 0:f782d9c66c49 542 }
dkato 0:f782d9c66c49 543 }
dkato 0:f782d9c66c49 544
dkato 0:f782d9c66c49 545 static void serial_irq_err_set(serial_t *obj, uint32_t enable)
dkato 0:f782d9c66c49 546 {
dkato 0:f782d9c66c49 547 serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable);
dkato 0:f782d9c66c49 548 serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable);
dkato 0:f782d9c66c49 549 }
dkato 0:f782d9c66c49 550
dkato 0:f782d9c66c49 551 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
dkato 0:f782d9c66c49 552 IRQn_Type IRQn;
dkato 0:f782d9c66c49 553 IRQHandler handler;
dkato 0:f782d9c66c49 554
dkato 0:f782d9c66c49 555 IRQn = irq_set_tbl[obj->serial.index][irq];
dkato 0:f782d9c66c49 556 handler = hander_set_tbl[obj->serial.index][irq];
dkato 0:f782d9c66c49 557
dkato 0:f782d9c66c49 558 if ((obj->serial.index >= 0) && (obj->serial.index <= 7)) {
dkato 0:f782d9c66c49 559 serial_irq_set_irq(IRQn, handler, enable);
dkato 0:f782d9c66c49 560 }
dkato 0:f782d9c66c49 561 }
dkato 0:f782d9c66c49 562
dkato 0:f782d9c66c49 563 /******************************************************************************
dkato 0:f782d9c66c49 564 * READ/WRITE
dkato 0:f782d9c66c49 565 ******************************************************************************/
dkato 0:f782d9c66c49 566 int serial_getc(serial_t *obj) {
dkato 0:f782d9c66c49 567 uint16_t err_read;
dkato 0:f782d9c66c49 568 int data;
dkato 0:f782d9c66c49 569 int was_masked;
dkato 0:f782d9c66c49 570
dkato 0:f782d9c66c49 571 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 572 was_masked = __disable_irq_iar();
dkato 0:f782d9c66c49 573 #else
dkato 0:f782d9c66c49 574 was_masked = __disable_irq();
dkato 0:f782d9c66c49 575 #endif /* __ICCARM__ */
dkato 0:f782d9c66c49 576 if (obj->serial.uart->SCFSR & 0x93) {
dkato 0:f782d9c66c49 577 err_read = obj->serial.uart->SCFSR;
dkato 0:f782d9c66c49 578 obj->serial.uart->SCFSR = (err_read & ~0x93);
dkato 0:f782d9c66c49 579 }
dkato 0:f782d9c66c49 580 obj->serial.uart->SCSCR |= 0x0040; // Set RIE
dkato 0:f782d9c66c49 581 if (!was_masked) {
dkato 0:f782d9c66c49 582 __enable_irq();
dkato 0:f782d9c66c49 583 }
dkato 0:f782d9c66c49 584
dkato 0:f782d9c66c49 585 if (obj->serial.uart->SCLSR & 0x0001) {
dkato 0:f782d9c66c49 586 obj->serial.uart->SCLSR = 0u; // ORER clear
dkato 0:f782d9c66c49 587 }
dkato 0:f782d9c66c49 588
dkato 0:f782d9c66c49 589 while (!serial_readable(obj));
dkato 0:f782d9c66c49 590 data = obj->serial.uart->SCFRDR & 0xff;
dkato 0:f782d9c66c49 591
dkato 0:f782d9c66c49 592 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 593 was_masked = __disable_irq_iar();
dkato 0:f782d9c66c49 594 #else
dkato 0:f782d9c66c49 595 was_masked = __disable_irq();
dkato 0:f782d9c66c49 596 #endif /* __ICCARM__ */
dkato 0:f782d9c66c49 597 err_read = obj->serial.uart->SCFSR;
dkato 0:f782d9c66c49 598 obj->serial.uart->SCFSR = (err_read & 0xfffD); // Clear RDF
dkato 0:f782d9c66c49 599 if (!was_masked) {
dkato 0:f782d9c66c49 600 __enable_irq();
dkato 0:f782d9c66c49 601 }
dkato 0:f782d9c66c49 602
dkato 0:f782d9c66c49 603 if (err_read & 0x80) {
dkato 0:f782d9c66c49 604 data = -1; //err
dkato 0:f782d9c66c49 605 }
dkato 0:f782d9c66c49 606 return data;
dkato 0:f782d9c66c49 607 }
dkato 0:f782d9c66c49 608
dkato 0:f782d9c66c49 609 void serial_putc(serial_t *obj, int c) {
dkato 0:f782d9c66c49 610 while (!serial_writable(obj));
dkato 0:f782d9c66c49 611 obj->serial.uart->SCFTDR = c;
dkato 0:f782d9c66c49 612 serial_put_done(obj);
dkato 0:f782d9c66c49 613 }
dkato 0:f782d9c66c49 614
dkato 0:f782d9c66c49 615 static void serial_put_done(serial_t *obj)
dkato 0:f782d9c66c49 616 {
dkato 0:f782d9c66c49 617 int was_masked;
dkato 0:f782d9c66c49 618 volatile uint16_t dummy_read;
dkato 0:f782d9c66c49 619
dkato 0:f782d9c66c49 620 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 621 was_masked = __disable_irq_iar();
dkato 0:f782d9c66c49 622 #else
dkato 0:f782d9c66c49 623 was_masked = __disable_irq();
dkato 0:f782d9c66c49 624 #endif /* __ICCARM__ */
dkato 0:f782d9c66c49 625 dummy_read = obj->serial.uart->SCFSR;
dkato 0:f782d9c66c49 626 obj->serial.uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE
dkato 0:f782d9c66c49 627 obj->serial.uart->SCSCR |= 0x0080; // Set TIE
dkato 0:f782d9c66c49 628 if (!was_masked) {
dkato 0:f782d9c66c49 629 __enable_irq();
dkato 0:f782d9c66c49 630 }
dkato 0:f782d9c66c49 631 }
dkato 0:f782d9c66c49 632
dkato 0:f782d9c66c49 633 int serial_readable(serial_t *obj) {
dkato 0:f782d9c66c49 634 return ((obj->serial.uart->SCFSR & 0x02) != 0); // RDF
dkato 0:f782d9c66c49 635 }
dkato 0:f782d9c66c49 636
dkato 0:f782d9c66c49 637 int serial_writable(serial_t *obj) {
dkato 0:f782d9c66c49 638 return ((obj->serial.uart->SCFSR & 0x20) != 0); // TDFE
dkato 0:f782d9c66c49 639 }
dkato 0:f782d9c66c49 640
dkato 0:f782d9c66c49 641 void serial_clear(serial_t *obj) {
dkato 0:f782d9c66c49 642 int was_masked;
dkato 0:f782d9c66c49 643 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 644 was_masked = __disable_irq_iar();
dkato 0:f782d9c66c49 645 #else
dkato 0:f782d9c66c49 646 was_masked = __disable_irq();
dkato 0:f782d9c66c49 647 #endif /* __ICCARM__ */
dkato 0:f782d9c66c49 648
dkato 0:f782d9c66c49 649 obj->serial.uart->SCFCR |= 0x0006u; // TFRST = 1, RFRST = 1
dkato 0:f782d9c66c49 650 obj->serial.uart->SCFCR &= ~0x0006u; // TFRST = 0, RFRST = 0
dkato 0:f782d9c66c49 651 obj->serial.uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0
dkato 0:f782d9c66c49 652
dkato 0:f782d9c66c49 653 if (!was_masked) {
dkato 0:f782d9c66c49 654 __enable_irq();
dkato 0:f782d9c66c49 655 }
dkato 0:f782d9c66c49 656 }
dkato 0:f782d9c66c49 657
dkato 0:f782d9c66c49 658 void serial_pinout_tx(PinName tx) {
dkato 0:f782d9c66c49 659 pinmap_pinout(tx, PinMap_UART_TX);
dkato 0:f782d9c66c49 660 }
dkato 0:f782d9c66c49 661
dkato 0:f782d9c66c49 662 void serial_break_set(serial_t *obj) {
dkato 0:f782d9c66c49 663 int was_masked;
dkato 0:f782d9c66c49 664 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 665 was_masked = __disable_irq_iar();
dkato 0:f782d9c66c49 666 #else
dkato 0:f782d9c66c49 667 was_masked = __disable_irq();
dkato 0:f782d9c66c49 668 #endif /* __ICCARM__ */
dkato 0:f782d9c66c49 669 // TxD Output(L)
dkato 0:f782d9c66c49 670 obj->serial.uart->SCSPTR &= ~0x0001u; // SPB2DT = 0
dkato 0:f782d9c66c49 671 obj->serial.uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable)
dkato 0:f782d9c66c49 672 if (!was_masked) {
dkato 0:f782d9c66c49 673 __enable_irq();
dkato 0:f782d9c66c49 674 }
dkato 0:f782d9c66c49 675 }
dkato 0:f782d9c66c49 676
dkato 0:f782d9c66c49 677 void serial_break_clear(serial_t *obj) {
dkato 0:f782d9c66c49 678 int was_masked;
dkato 0:f782d9c66c49 679 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 680 was_masked = __disable_irq_iar();
dkato 0:f782d9c66c49 681 #else
dkato 0:f782d9c66c49 682 was_masked = __disable_irq();
dkato 0:f782d9c66c49 683 #endif /* __ICCARM__ */
dkato 0:f782d9c66c49 684 obj->serial.uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
dkato 0:f782d9c66c49 685 obj->serial.uart->SCSPTR |= 0x0001u; // SPB2DT = 1
dkato 0:f782d9c66c49 686 if (!was_masked) {
dkato 0:f782d9c66c49 687 __enable_irq();
dkato 0:f782d9c66c49 688 }
dkato 0:f782d9c66c49 689 }
dkato 0:f782d9c66c49 690
dkato 0:f782d9c66c49 691 #if DEVICE_SERIAL_FC
dkato 0:f782d9c66c49 692 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
dkato 0:f782d9c66c49 693 // determine the UART to use
dkato 0:f782d9c66c49 694 int was_masked;
dkato 0:f782d9c66c49 695
dkato 0:f782d9c66c49 696 if (type == FlowControlRTSCTS) {
dkato 0:f782d9c66c49 697 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 698 was_masked = __disable_irq_iar();
dkato 0:f782d9c66c49 699 #else
dkato 0:f782d9c66c49 700 was_masked = __disable_irq();
dkato 0:f782d9c66c49 701 #endif /* __ICCARM__ */
dkato 0:f782d9c66c49 702 obj->serial.uart->SCFCR |= 0x0008u; // CTS/RTS enable
dkato 0:f782d9c66c49 703 if (!was_masked) {
dkato 0:f782d9c66c49 704 __enable_irq();
dkato 0:f782d9c66c49 705 }
dkato 0:f782d9c66c49 706 pinmap_pinout(rxflow, PinMap_UART_RTS);
dkato 0:f782d9c66c49 707 pinmap_pinout(txflow, PinMap_UART_CTS);
dkato 0:f782d9c66c49 708 } else {
dkato 0:f782d9c66c49 709 #if defined ( __ICCARM__ )
dkato 0:f782d9c66c49 710 was_masked = __disable_irq_iar();
dkato 0:f782d9c66c49 711 #else
dkato 0:f782d9c66c49 712 was_masked = __disable_irq();
dkato 0:f782d9c66c49 713 #endif /* __ICCARM__ */
dkato 0:f782d9c66c49 714 obj->serial.uart->SCFCR &= ~0x0008u; // CTS/RTS diable
dkato 0:f782d9c66c49 715 if (!was_masked) {
dkato 0:f782d9c66c49 716 __enable_irq();
dkato 0:f782d9c66c49 717 }
dkato 0:f782d9c66c49 718 }
dkato 0:f782d9c66c49 719 }
dkato 0:f782d9c66c49 720 #endif
dkato 0:f782d9c66c49 721
dkato 0:f782d9c66c49 722 static uint8_t serial_available_buffer(serial_t *obj)
dkato 0:f782d9c66c49 723 {
dkato 0:f782d9c66c49 724 return 1;
dkato 0:f782d9c66c49 725 /* Faster but unstable way */
dkato 0:f782d9c66c49 726 /*
dkato 0:f782d9c66c49 727 uint16_t ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F);
dkato 0:f782d9c66c49 728 while (ret == 0) {
dkato 0:f782d9c66c49 729 ret = 16 - ((obj->serial.uart->SCFDR >> 8) & 0x1F);
dkato 0:f782d9c66c49 730 }
dkato 0:f782d9c66c49 731 MBED_ASSERT(0 < ret && ret <= 16);
dkato 0:f782d9c66c49 732 return ret;
dkato 0:f782d9c66c49 733 */
dkato 0:f782d9c66c49 734 }
dkato 0:f782d9c66c49 735
dkato 0:f782d9c66c49 736 #if DEVICE_SERIAL_ASYNCH
dkato 0:f782d9c66c49 737
dkato 0:f782d9c66c49 738 /******************************************************************************
dkato 0:f782d9c66c49 739 * ASYNCHRONOUS HAL
dkato 0:f782d9c66c49 740 ******************************************************************************/
dkato 0:f782d9c66c49 741
dkato 0:f782d9c66c49 742 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
dkato 0:f782d9c66c49 743 {
dkato 0:f782d9c66c49 744 int i;
dkato 0:f782d9c66c49 745 buffer_t *buf = &obj->tx_buff;
dkato 0:f782d9c66c49 746 struct serial_global_data_s *data = uart_data + obj->serial.index;
dkato 0:f782d9c66c49 747
dkato 0:f782d9c66c49 748 if (tx_length == 0) {
dkato 0:f782d9c66c49 749 return 0;
dkato 0:f782d9c66c49 750 }
dkato 0:f782d9c66c49 751
dkato 0:f782d9c66c49 752 buf->buffer = (void *)tx;
dkato 0:f782d9c66c49 753 buf->length = tx_length * tx_width / 8;
dkato 0:f782d9c66c49 754 buf->pos = 0;
dkato 0:f782d9c66c49 755 buf->width = tx_width;
dkato 0:f782d9c66c49 756 data->tranferring_obj = obj;
dkato 0:f782d9c66c49 757 data->async_tx_callback = handler;
dkato 0:f782d9c66c49 758 serial_irq_set(obj, TxIrq, 1);
dkato 0:f782d9c66c49 759
dkato 0:f782d9c66c49 760 while (!serial_writable(obj));
dkato 0:f782d9c66c49 761 i = buf->length;
dkato 0:f782d9c66c49 762 if (serial_available_buffer(obj) < i) {
dkato 0:f782d9c66c49 763 i = serial_available_buffer(obj);
dkato 0:f782d9c66c49 764 }
dkato 0:f782d9c66c49 765 do {
dkato 0:f782d9c66c49 766 uint8_t c = *(uint8_t *)buf->buffer;
dkato 0:f782d9c66c49 767 obj->tx_buff.buffer = (uint8_t *)obj->tx_buff.buffer + 1;
dkato 0:f782d9c66c49 768 ++buf->pos;
dkato 0:f782d9c66c49 769 obj->serial.uart->SCFTDR = c;
dkato 0:f782d9c66c49 770 } while (--i);
dkato 0:f782d9c66c49 771 serial_put_done(obj);
dkato 0:f782d9c66c49 772
dkato 0:f782d9c66c49 773 return buf->length;
dkato 0:f782d9c66c49 774 }
dkato 0:f782d9c66c49 775
dkato 0:f782d9c66c49 776 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
dkato 0:f782d9c66c49 777 {
dkato 0:f782d9c66c49 778 buffer_t *buf = &obj->rx_buff;
dkato 0:f782d9c66c49 779 struct serial_global_data_s *data = uart_data + obj->serial.index;
dkato 0:f782d9c66c49 780
dkato 0:f782d9c66c49 781 if (rx_length == 0) {
dkato 0:f782d9c66c49 782 return;
dkato 0:f782d9c66c49 783 }
dkato 0:f782d9c66c49 784
dkato 0:f782d9c66c49 785 buf->buffer = rx;
dkato 0:f782d9c66c49 786 buf->length = rx_length * rx_width / 8;
dkato 0:f782d9c66c49 787 buf->pos = 0;
dkato 0:f782d9c66c49 788 buf->width = rx_width;
dkato 0:f782d9c66c49 789 obj->char_match = char_match;
dkato 0:f782d9c66c49 790 obj->char_found = 0;
dkato 0:f782d9c66c49 791 data->receiving_obj = obj;
dkato 0:f782d9c66c49 792 data->async_rx_callback = handler;
dkato 0:f782d9c66c49 793 data->event = 0;
dkato 0:f782d9c66c49 794 data->wanted_rx_events = event;
dkato 0:f782d9c66c49 795
dkato 0:f782d9c66c49 796 serial_irq_set(obj, RxIrq, 1);
dkato 0:f782d9c66c49 797 serial_irq_err_set(obj, 1);
dkato 0:f782d9c66c49 798 }
dkato 0:f782d9c66c49 799
dkato 0:f782d9c66c49 800 uint8_t serial_tx_active(serial_t *obj)
dkato 0:f782d9c66c49 801 {
dkato 0:f782d9c66c49 802 return uart_data[obj->serial.index].tranferring_obj != NULL;
dkato 0:f782d9c66c49 803 }
dkato 0:f782d9c66c49 804
dkato 0:f782d9c66c49 805 uint8_t serial_rx_active(serial_t *obj)
dkato 0:f782d9c66c49 806 {
dkato 0:f782d9c66c49 807 return uart_data[obj->serial.index].receiving_obj != NULL;
dkato 0:f782d9c66c49 808 }
dkato 0:f782d9c66c49 809
dkato 0:f782d9c66c49 810 int serial_irq_handler_asynch(serial_t *obj)
dkato 0:f782d9c66c49 811 {
dkato 0:f782d9c66c49 812 return uart_data[obj->serial.index].event;
dkato 0:f782d9c66c49 813 }
dkato 0:f782d9c66c49 814
dkato 0:f782d9c66c49 815 void serial_tx_abort_asynch(serial_t *obj)
dkato 0:f782d9c66c49 816 {
dkato 0:f782d9c66c49 817 uart_data[obj->serial.index].tranferring_obj = NULL;
dkato 0:f782d9c66c49 818 obj->serial.uart->SCFCR |= 1 << 2;
dkato 0:f782d9c66c49 819 obj->serial.uart->SCFCR &= ~(1 << 2);
dkato 0:f782d9c66c49 820 }
dkato 0:f782d9c66c49 821
dkato 0:f782d9c66c49 822 void serial_rx_abort_asynch(serial_t *obj)
dkato 0:f782d9c66c49 823 {
dkato 0:f782d9c66c49 824 uart_data[obj->serial.index].receiving_obj = NULL;
dkato 0:f782d9c66c49 825 obj->serial.uart->SCFCR |= 1 << 1;
dkato 0:f782d9c66c49 826 obj->serial.uart->SCFCR &= ~(1 << 1);
dkato 0:f782d9c66c49 827 }
dkato 0:f782d9c66c49 828
dkato 0:f782d9c66c49 829 #endif