Daiki Kato / mbed-os-lychee

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targets/TARGET_RENESAS/TARGET_RZA1XX/common/gic.h@0:f782d9c66c49, 2018-02-02 (annotated)

Committer:
dkato
Date:
Fri Feb 02 05:42:23 2018 +0000
Revision:
0:f782d9c66c49
mbed-os for GR-LYCHEE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:f782d9c66c49 1 /**************************************************************************//**
dkato 0:f782d9c66c49 2 * @file gic.h
dkato 0:f782d9c66c49 3 * @brief Implementation of GIC functions declared in CMSIS Cortex-A9 Core Peripheral Access Layer Header File
dkato 0:f782d9c66c49 4 * @version
dkato 0:f782d9c66c49 5 * @date 29 August 2013
dkato 0:f782d9c66c49 6 *
dkato 0:f782d9c66c49 7 * @note
dkato 0:f782d9c66c49 8 *
dkato 0:f782d9c66c49 9 ******************************************************************************/
dkato 0:f782d9c66c49 10 /* Copyright (c) 2011 - 2013 ARM LIMITED
dkato 0:f782d9c66c49 11
dkato 0:f782d9c66c49 12 All rights reserved.
dkato 0:f782d9c66c49 13 Redistribution and use in source and binary forms, with or without
dkato 0:f782d9c66c49 14 modification, are permitted provided that the following conditions are met:
dkato 0:f782d9c66c49 15 - Redistributions of source code must retain the above copyright
dkato 0:f782d9c66c49 16 notice, this list of conditions and the following disclaimer.
dkato 0:f782d9c66c49 17 - Redistributions in binary form must reproduce the above copyright
dkato 0:f782d9c66c49 18 notice, this list of conditions and the following disclaimer in the
dkato 0:f782d9c66c49 19 documentation and/or other materials provided with the distribution.
dkato 0:f782d9c66c49 20 - Neither the name of ARM nor the names of its contributors may be used
dkato 0:f782d9c66c49 21 to endorse or promote products derived from this software without
dkato 0:f782d9c66c49 22 specific prior written permission.
dkato 0:f782d9c66c49 23 *
dkato 0:f782d9c66c49 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
dkato 0:f782d9c66c49 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
dkato 0:f782d9c66c49 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
dkato 0:f782d9c66c49 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
dkato 0:f782d9c66c49 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
dkato 0:f782d9c66c49 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
dkato 0:f782d9c66c49 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
dkato 0:f782d9c66c49 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
dkato 0:f782d9c66c49 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
dkato 0:f782d9c66c49 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
dkato 0:f782d9c66c49 34 POSSIBILITY OF SUCH DAMAGE.
dkato 0:f782d9c66c49 35 ---------------------------------------------------------------------------*/
dkato 0:f782d9c66c49 36
dkato 0:f782d9c66c49 37 #ifndef GIC_H_
dkato 0:f782d9c66c49 38 #define GIC_H_
dkato 0:f782d9c66c49 39
dkato 0:f782d9c66c49 40 /* IO definitions (access restrictions to peripheral registers) */
dkato 0:f782d9c66c49 41 /**
dkato 0:f782d9c66c49 42 */
dkato 0:f782d9c66c49 43 #ifdef __cplusplus
dkato 0:f782d9c66c49 44 #define __I volatile /*!< Defines 'read only' permissions */
dkato 0:f782d9c66c49 45 #else
dkato 0:f782d9c66c49 46 #define __I volatile const /*!< Defines 'read only' permissions */
dkato 0:f782d9c66c49 47 #endif
dkato 0:f782d9c66c49 48 #define __O volatile /*!< Defines 'write only' permissions */
dkato 0:f782d9c66c49 49 #define __IO volatile /*!< Defines 'read / write' permissions */
dkato 0:f782d9c66c49 50
dkato 0:f782d9c66c49 51 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
dkato 0:f782d9c66c49 52 */
dkato 0:f782d9c66c49 53 typedef struct
dkato 0:f782d9c66c49 54 {
dkato 0:f782d9c66c49 55 __IO uint32_t ICDDCR;
dkato 0:f782d9c66c49 56 __I uint32_t ICDICTR;
dkato 0:f782d9c66c49 57 __I uint32_t ICDIIDR;
dkato 0:f782d9c66c49 58 uint32_t RESERVED0[29];
dkato 0:f782d9c66c49 59 __IO uint32_t ICDISR[32];
dkato 0:f782d9c66c49 60 __IO uint32_t ICDISER[32];
dkato 0:f782d9c66c49 61 __IO uint32_t ICDICER[32];
dkato 0:f782d9c66c49 62 __IO uint32_t ICDISPR[32];
dkato 0:f782d9c66c49 63 __IO uint32_t ICDICPR[32];
dkato 0:f782d9c66c49 64 __I uint32_t ICDABR[32];
dkato 0:f782d9c66c49 65 uint32_t RESERVED1[32];
dkato 0:f782d9c66c49 66 __IO uint32_t ICDIPR[256];
dkato 0:f782d9c66c49 67 __IO uint32_t ICDIPTR[256];
dkato 0:f782d9c66c49 68 __IO uint32_t ICDICFR[64];
dkato 0:f782d9c66c49 69 uint32_t RESERVED2[128];
dkato 0:f782d9c66c49 70 __IO uint32_t ICDSGIR;
dkato 0:f782d9c66c49 71 } GICDistributor_Type;
dkato 0:f782d9c66c49 72
dkato 0:f782d9c66c49 73 /** \brief Structure type to access the Controller Interface (GICC)
dkato 0:f782d9c66c49 74 */
dkato 0:f782d9c66c49 75 typedef struct
dkato 0:f782d9c66c49 76 {
dkato 0:f782d9c66c49 77 __IO uint32_t ICCICR; // +0x000 - RW - CPU Interface Control Register
dkato 0:f782d9c66c49 78 __IO uint32_t ICCPMR; // +0x004 - RW - Interrupt Priority Mask Register
dkato 0:f782d9c66c49 79 __IO uint32_t ICCBPR; // +0x008 - RW - Binary Point Register
dkato 0:f782d9c66c49 80 __I uint32_t ICCIAR; // +0x00C - RO - Interrupt Acknowledge Register
dkato 0:f782d9c66c49 81 __IO uint32_t ICCEOIR; // +0x010 - WO - End of Interrupt Register
dkato 0:f782d9c66c49 82 __I uint32_t ICCRPR; // +0x014 - RO - Running Priority Register
dkato 0:f782d9c66c49 83 __I uint32_t ICCHPIR; // +0x018 - RO - Highest Pending Interrupt Register
dkato 0:f782d9c66c49 84 __IO uint32_t ICCABPR; // +0x01C - RW - Aliased Binary Point Register
dkato 0:f782d9c66c49 85
dkato 0:f782d9c66c49 86 uint32_t RESERVED[55];
dkato 0:f782d9c66c49 87
dkato 0:f782d9c66c49 88 __I uint32_t ICCIIDR; // +0x0FC - RO - CPU Interface Identification Register
dkato 0:f782d9c66c49 89 } GICInterface_Type;
dkato 0:f782d9c66c49 90
dkato 0:f782d9c66c49 91 /*@} end of GICD */
dkato 0:f782d9c66c49 92
dkato 0:f782d9c66c49 93 /* ########################## GIC functions #################################### */
dkato 0:f782d9c66c49 94 /** \brief Functions that manage interrupts via the GIC.
dkato 0:f782d9c66c49 95 @{
dkato 0:f782d9c66c49 96 */
dkato 0:f782d9c66c49 97
dkato 0:f782d9c66c49 98 /** \brief Enable DistributorGICInterface->ICCICR |= 1; //enable interface
dkato 0:f782d9c66c49 99
dkato 0:f782d9c66c49 100 Enables the forwarding of pending interrupts to the CPU interfaces.
dkato 0:f782d9c66c49 101
dkato 0:f782d9c66c49 102 */
dkato 0:f782d9c66c49 103 void GIC_EnableDistributor(void);
dkato 0:f782d9c66c49 104
dkato 0:f782d9c66c49 105 /** \brief Disable Distributor
dkato 0:f782d9c66c49 106
dkato 0:f782d9c66c49 107 Disables the forwarding of pending interrupts to the CPU interfaces.
dkato 0:f782d9c66c49 108
dkato 0:f782d9c66c49 109 */
dkato 0:f782d9c66c49 110 void GIC_DisableDistributor(void);
dkato 0:f782d9c66c49 111
dkato 0:f782d9c66c49 112 /** \brief Provides information about the configuration of the GIC.
dkato 0:f782d9c66c49 113 Provides information about the configuration of the GIC.
dkato 0:f782d9c66c49 114 - whether the GIC implements the Security Extensions
dkato 0:f782d9c66c49 115 - the maximum number of interrupt IDs that the GIC supports
dkato 0:f782d9c66c49 116 - the number of CPU interfaces implemented
dkato 0:f782d9c66c49 117 - if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).
dkato 0:f782d9c66c49 118
dkato 0:f782d9c66c49 119 \return Distributor Information.
dkato 0:f782d9c66c49 120 */
dkato 0:f782d9c66c49 121 uint32_t GIC_DistributorInfo(void);
dkato 0:f782d9c66c49 122
dkato 0:f782d9c66c49 123 /** \brief Distributor Implementer Identification Register.
dkato 0:f782d9c66c49 124
dkato 0:f782d9c66c49 125 Distributor Implementer Identification Register
dkato 0:f782d9c66c49 126
dkato 0:f782d9c66c49 127 \return Implementer Information.
dkato 0:f782d9c66c49 128 */
dkato 0:f782d9c66c49 129 uint32_t GIC_DistributorImplementer(void);
dkato 0:f782d9c66c49 130
dkato 0:f782d9c66c49 131 /** \brief Set list of processors that the interrupt is sent to if it is asserted.
dkato 0:f782d9c66c49 132
dkato 0:f782d9c66c49 133 The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
dkato 0:f782d9c66c49 134 This field stores the list of processors that the interrupt is sent to if it is asserted.
dkato 0:f782d9c66c49 135
dkato 0:f782d9c66c49 136 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 137 \param [in] target CPU target
dkato 0:f782d9c66c49 138 */
dkato 0:f782d9c66c49 139 void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target);
dkato 0:f782d9c66c49 140
dkato 0:f782d9c66c49 141 /** \brief Get list of processors that the interrupt is sent to if it is asserted.
dkato 0:f782d9c66c49 142
dkato 0:f782d9c66c49 143 The ICDIPTRs provide an 8-bit CPU targets field for each interrupt supported by the GIC.
dkato 0:f782d9c66c49 144 This field stores the list of processors that the interrupt is sent to if it is asserted.
dkato 0:f782d9c66c49 145
dkato 0:f782d9c66c49 146 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 147 \param [in] target CPU target
dkato 0:f782d9c66c49 148 */
dkato 0:f782d9c66c49 149 uint32_t GIC_GetTarget(IRQn_Type IRQn);
dkato 0:f782d9c66c49 150
dkato 0:f782d9c66c49 151 /** \brief Enable Interface
dkato 0:f782d9c66c49 152
dkato 0:f782d9c66c49 153 Enables the signalling of interrupts to the target processors.
dkato 0:f782d9c66c49 154
dkato 0:f782d9c66c49 155 */
dkato 0:f782d9c66c49 156 void GIC_EnableInterface(void);
dkato 0:f782d9c66c49 157
dkato 0:f782d9c66c49 158 /** \brief Disable Interface
dkato 0:f782d9c66c49 159
dkato 0:f782d9c66c49 160 Disables the signalling of interrupts to the target processors.
dkato 0:f782d9c66c49 161
dkato 0:f782d9c66c49 162 */
dkato 0:f782d9c66c49 163 void GIC_DisableInterface(void);
dkato 0:f782d9c66c49 164
dkato 0:f782d9c66c49 165 /** \brief Acknowledge Interrupt
dkato 0:f782d9c66c49 166
dkato 0:f782d9c66c49 167 The function acknowledges the highest priority pending interrupt and returns its IRQ number.
dkato 0:f782d9c66c49 168
dkato 0:f782d9c66c49 169 \return Interrupt number
dkato 0:f782d9c66c49 170 */
dkato 0:f782d9c66c49 171 IRQn_Type GIC_AcknowledgePending(void);
dkato 0:f782d9c66c49 172
dkato 0:f782d9c66c49 173 /** \brief End Interrupt
dkato 0:f782d9c66c49 174
dkato 0:f782d9c66c49 175 The function writes the end of interrupt register, indicating that handling of the interrupt is complete.
dkato 0:f782d9c66c49 176
dkato 0:f782d9c66c49 177 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 178 */
dkato 0:f782d9c66c49 179 void GIC_EndInterrupt(IRQn_Type IRQn);
dkato 0:f782d9c66c49 180
dkato 0:f782d9c66c49 181
dkato 0:f782d9c66c49 182 /** \brief Enable Interrupt
dkato 0:f782d9c66c49 183
dkato 0:f782d9c66c49 184 Set-enable bit for each interrupt supported by the GIC.
dkato 0:f782d9c66c49 185
dkato 0:f782d9c66c49 186 \param [in] IRQn External interrupt number.
dkato 0:f782d9c66c49 187 */
dkato 0:f782d9c66c49 188 void GIC_EnableIRQ(IRQn_Type IRQn);
dkato 0:f782d9c66c49 189
dkato 0:f782d9c66c49 190 /** \brief Disable Interrupt
dkato 0:f782d9c66c49 191
dkato 0:f782d9c66c49 192 Clear-enable bit for each interrupt supported by the GIC.
dkato 0:f782d9c66c49 193
dkato 0:f782d9c66c49 194 \param [in] IRQn Number of the external interrupt to disable
dkato 0:f782d9c66c49 195 */
dkato 0:f782d9c66c49 196 void GIC_DisableIRQ(IRQn_Type IRQn);
dkato 0:f782d9c66c49 197
dkato 0:f782d9c66c49 198 /** \brief Set Pending Interrupt
dkato 0:f782d9c66c49 199
dkato 0:f782d9c66c49 200 Set-pending bit for each interrupt supported by the GIC.
dkato 0:f782d9c66c49 201
dkato 0:f782d9c66c49 202 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 203 */
dkato 0:f782d9c66c49 204 void GIC_SetPendingIRQ(IRQn_Type IRQn);
dkato 0:f782d9c66c49 205
dkato 0:f782d9c66c49 206 /** \brief Clear Pending Interrupt
dkato 0:f782d9c66c49 207
dkato 0:f782d9c66c49 208 Clear-pending bit for each interrupt supported by the GIC
dkato 0:f782d9c66c49 209
dkato 0:f782d9c66c49 210 \param [in] IRQn Number of the interrupt for clear pending
dkato 0:f782d9c66c49 211 */
dkato 0:f782d9c66c49 212 void GIC_ClearPendingIRQ(IRQn_Type IRQn);
dkato 0:f782d9c66c49 213
dkato 0:f782d9c66c49 214 /** \brief Int_config field for each interrupt supported by the GIC.
dkato 0:f782d9c66c49 215
dkato 0:f782d9c66c49 216 This field identifies whether the corresponding interrupt is:
dkato 0:f782d9c66c49 217 (1) edge-triggered or (0) level-sensitive
dkato 0:f782d9c66c49 218 (1) 1-N model or (0) N-N model
dkato 0:f782d9c66c49 219
dkato 0:f782d9c66c49 220 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 221 \param [in] edge_level (1) edge-triggered or (0) level-sensitive
dkato 0:f782d9c66c49 222 \param [in] model (1) 1-N model or (0) N-N model
dkato 0:f782d9c66c49 223 */
dkato 0:f782d9c66c49 224 void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model);
dkato 0:f782d9c66c49 225
dkato 0:f782d9c66c49 226
dkato 0:f782d9c66c49 227 /** \brief Set Interrupt Priority
dkato 0:f782d9c66c49 228
dkato 0:f782d9c66c49 229 The function sets the priority of an interrupt.
dkato 0:f782d9c66c49 230
dkato 0:f782d9c66c49 231 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 232 \param [in] priority Priority to set.
dkato 0:f782d9c66c49 233 */
dkato 0:f782d9c66c49 234 void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
dkato 0:f782d9c66c49 235
dkato 0:f782d9c66c49 236 /** \brief Get Interrupt Priority
dkato 0:f782d9c66c49 237
dkato 0:f782d9c66c49 238 The function reads the priority of an interrupt.
dkato 0:f782d9c66c49 239
dkato 0:f782d9c66c49 240 \param [in] IRQn Interrupt number.
dkato 0:f782d9c66c49 241 \return Interrupt Priority.
dkato 0:f782d9c66c49 242 */
dkato 0:f782d9c66c49 243 uint32_t GIC_GetPriority(IRQn_Type IRQn);
dkato 0:f782d9c66c49 244
dkato 0:f782d9c66c49 245 /** \brief CPU Interface Priority Mask Register
dkato 0:f782d9c66c49 246
dkato 0:f782d9c66c49 247 The priority mask level for the CPU interface. If the priority of an interrupt is higher than the
dkato 0:f782d9c66c49 248 value indicated by this field, the interface signals the interrupt to the processor.
dkato 0:f782d9c66c49 249
dkato 0:f782d9c66c49 250 \param [in] Mask.
dkato 0:f782d9c66c49 251 */
dkato 0:f782d9c66c49 252 void GIC_InterfacePriorityMask(uint32_t priority);
dkato 0:f782d9c66c49 253
dkato 0:f782d9c66c49 254 /** \brief Set the binary point.
dkato 0:f782d9c66c49 255
dkato 0:f782d9c66c49 256 Set the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
dkato 0:f782d9c66c49 257
dkato 0:f782d9c66c49 258 \param [in] Mask.
dkato 0:f782d9c66c49 259 */
dkato 0:f782d9c66c49 260 void GIC_SetBinaryPoint(uint32_t binary_point);
dkato 0:f782d9c66c49 261
dkato 0:f782d9c66c49 262 /** \brief Get the binary point.
dkato 0:f782d9c66c49 263
dkato 0:f782d9c66c49 264 Get the point at which the priority value fields split into two parts, the group priority field and the subpriority field.
dkato 0:f782d9c66c49 265
dkato 0:f782d9c66c49 266 \return Binary point.
dkato 0:f782d9c66c49 267 */
dkato 0:f782d9c66c49 268 uint32_t GIC_GetBinaryPoint(uint32_t binary_point);
dkato 0:f782d9c66c49 269
dkato 0:f782d9c66c49 270 /** \brief Get Interrupt state.
dkato 0:f782d9c66c49 271
dkato 0:f782d9c66c49 272 Get the interrupt state, whether pending and/or active
dkato 0:f782d9c66c49 273
dkato 0:f782d9c66c49 274 \return 0 - inactive, 1 - pending, 2 - active, 3 - pending and active
dkato 0:f782d9c66c49 275 */
dkato 0:f782d9c66c49 276 uint32_t GIC_GetIRQStatus(IRQn_Type IRQn);
dkato 0:f782d9c66c49 277
dkato 0:f782d9c66c49 278 /** \brief Send Software Generated interrupt
dkato 0:f782d9c66c49 279
dkato 0:f782d9c66c49 280 Provides an interrupt priority filter. Only interrupts with higher priority than the value in this register can be signalled to the processor.
dkato 0:f782d9c66c49 281 GIC_InterfacePriorityMask
dkato 0:f782d9c66c49 282 \param [in] IRQn The Interrupt ID of the SGI.
dkato 0:f782d9c66c49 283 \param [in] target_list CPUTargetList
dkato 0:f782d9c66c49 284 \param [in] filter_list TargetListFilter
dkato 0:f782d9c66c49 285 */
dkato 0:f782d9c66c49 286 void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list);
dkato 0:f782d9c66c49 287
dkato 0:f782d9c66c49 288 /** \brief API call to initialise the interrupt distributor
dkato 0:f782d9c66c49 289
dkato 0:f782d9c66c49 290 API call to initialise the interrupt distributor
dkato 0:f782d9c66c49 291
dkato 0:f782d9c66c49 292 */
dkato 0:f782d9c66c49 293 void GIC_DistInit(void);
dkato 0:f782d9c66c49 294
dkato 0:f782d9c66c49 295 /** \brief API call to initialise the CPU interface
dkato 0:f782d9c66c49 296
dkato 0:f782d9c66c49 297 API call to initialise the CPU interface
dkato 0:f782d9c66c49 298
dkato 0:f782d9c66c49 299 */
dkato 0:f782d9c66c49 300 void GIC_CPUInterfaceInit(void);
dkato 0:f782d9c66c49 301
dkato 0:f782d9c66c49 302 /** \brief API call to set the Interrupt Configuration Registers
dkato 0:f782d9c66c49 303
dkato 0:f782d9c66c49 304 API call to initialise the Interrupt Configuration Registers
dkato 0:f782d9c66c49 305
dkato 0:f782d9c66c49 306 */
dkato 0:f782d9c66c49 307 void GIC_SetICDICFR (const uint32_t *ICDICFRn);
dkato 0:f782d9c66c49 308
dkato 0:f782d9c66c49 309 /** \brief API call to Enable the GIC
dkato 0:f782d9c66c49 310
dkato 0:f782d9c66c49 311 API call to Enable the GIC
dkato 0:f782d9c66c49 312
dkato 0:f782d9c66c49 313 */
dkato 0:f782d9c66c49 314 void GIC_Enable(void);
dkato 0:f782d9c66c49 315
dkato 0:f782d9c66c49 316 #endif /* GIC_H_ */