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mbed-os for GR-LYCHEE

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cmsis/core_cm7.h@0:f782d9c66c49, 2018-02-02 (annotated)

Committer:: dkato
Date:: Fri Feb 02 05:42:23 2018 +0000
Revision:: 0:f782d9c66c49

mbed-os for GR-LYCHEE

Who changed what in which revision?

User	Revision	Line number	New contents of line
dkato	0:f782d9c66c49	1	/************************************************************************//
dkato	0:f782d9c66c49	2	* @file core_cm7.h
dkato	0:f782d9c66c49	3	* @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File
dkato	0:f782d9c66c49	4	* @version V4.10
dkato	0:f782d9c66c49	5	* @date 18. March 2015
dkato	0:f782d9c66c49	6	*
dkato	0:f782d9c66c49	7	* @note
dkato	0:f782d9c66c49	8	*
dkato	0:f782d9c66c49	9	******************************************************************************/
dkato	0:f782d9c66c49	10	/* Copyright (c) 2009 - 2015 ARM LIMITED
dkato	0:f782d9c66c49	11
dkato	0:f782d9c66c49	12	All rights reserved.
dkato	0:f782d9c66c49	13	Redistribution and use in source and binary forms, with or without
dkato	0:f782d9c66c49	14	modification, are permitted provided that the following conditions are met:
dkato	0:f782d9c66c49	15	- Redistributions of source code must retain the above copyright
dkato	0:f782d9c66c49	16	notice, this list of conditions and the following disclaimer.
dkato	0:f782d9c66c49	17	- Redistributions in binary form must reproduce the above copyright
dkato	0:f782d9c66c49	18	notice, this list of conditions and the following disclaimer in the
dkato	0:f782d9c66c49	19	documentation and/or other materials provided with the distribution.
dkato	0:f782d9c66c49	20	- Neither the name of ARM nor the names of its contributors may be used
dkato	0:f782d9c66c49	21	to endorse or promote products derived from this software without
dkato	0:f782d9c66c49	22	specific prior written permission.
dkato	0:f782d9c66c49	23	*
dkato	0:f782d9c66c49	24	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
dkato	0:f782d9c66c49	25	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
dkato	0:f782d9c66c49	26	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
dkato	0:f782d9c66c49	27	ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
dkato	0:f782d9c66c49	28	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
dkato	0:f782d9c66c49	29	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
dkato	0:f782d9c66c49	30	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
dkato	0:f782d9c66c49	31	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
dkato	0:f782d9c66c49	32	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
dkato	0:f782d9c66c49	33	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
dkato	0:f782d9c66c49	34	POSSIBILITY OF SUCH DAMAGE.
dkato	0:f782d9c66c49	35	---------------------------------------------------------------------------*/
dkato	0:f782d9c66c49	36
dkato	0:f782d9c66c49	37
dkato	0:f782d9c66c49	38	#if defined ( __ICCARM__ )
dkato	0:f782d9c66c49	39	#pragma system_include /* treat file as system include file for MISRA check */
dkato	0:f782d9c66c49	40	#endif
dkato	0:f782d9c66c49	41
dkato	0:f782d9c66c49	42	#ifndef __CORE_CM7_H_GENERIC
dkato	0:f782d9c66c49	43	#define __CORE_CM7_H_GENERIC
dkato	0:f782d9c66c49	44
dkato	0:f782d9c66c49	45	#ifdef __cplusplus
dkato	0:f782d9c66c49	46	extern "C" {
dkato	0:f782d9c66c49	47	#endif
dkato	0:f782d9c66c49	48
dkato	0:f782d9c66c49	49	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
dkato	0:f782d9c66c49	50	CMSIS violates the following MISRA-C:2004 rules:
dkato	0:f782d9c66c49	51
dkato	0:f782d9c66c49	52	\li Required Rule 8.5, object/function definition in header file.<br>
dkato	0:f782d9c66c49	53	Function definitions in header files are used to allow 'inlining'.
dkato	0:f782d9c66c49	54
dkato	0:f782d9c66c49	55	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
dkato	0:f782d9c66c49	56	Unions are used for effective representation of core registers.
dkato	0:f782d9c66c49	57
dkato	0:f782d9c66c49	58	\li Advisory Rule 19.7, Function-like macro defined.<br>
dkato	0:f782d9c66c49	59	Function-like macros are used to allow more efficient code.
dkato	0:f782d9c66c49	60	*/
dkato	0:f782d9c66c49	61
dkato	0:f782d9c66c49	62
dkato	0:f782d9c66c49	63	/*******************************************************************************
dkato	0:f782d9c66c49	64	* CMSIS definitions
dkato	0:f782d9c66c49	65	******************************************************************************/
dkato	0:f782d9c66c49	66	/** \ingroup Cortex_M7
dkato	0:f782d9c66c49	67	@{
dkato	0:f782d9c66c49	68	*/
dkato	0:f782d9c66c49	69
dkato	0:f782d9c66c49	70	/* CMSIS CM7 definitions */
dkato	0:f782d9c66c49	71	#define __CM7_CMSIS_VERSION_MAIN (0x04) /!< [31:16] CMSIS HAL main version /
dkato	0:f782d9c66c49	72	#define __CM7_CMSIS_VERSION_SUB (0x00) /!< [15:0] CMSIS HAL sub version /
dkato	0:f782d9c66c49	73	#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) \| \
dkato	0:f782d9c66c49	74	__CM7_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
dkato	0:f782d9c66c49	75
dkato	0:f782d9c66c49	76	#define __CORTEX_M (0x07) /!< Cortex-M Core /
dkato	0:f782d9c66c49	77
dkato	0:f782d9c66c49	78
dkato	0:f782d9c66c49	79	#if defined ( __CC_ARM )
dkato	0:f782d9c66c49	80	#define __ASM __asm /!< asm keyword for ARM Compiler /
dkato	0:f782d9c66c49	81	#define __INLINE __inline /!< inline keyword for ARM Compiler /
dkato	0:f782d9c66c49	82	#define __STATIC_INLINE static __inline
dkato	0:f782d9c66c49	83
dkato	0:f782d9c66c49	84	#elif defined ( __GNUC__ )
dkato	0:f782d9c66c49	85	#define __ASM __asm /!< asm keyword for GNU Compiler /
dkato	0:f782d9c66c49	86	#define __INLINE inline /!< inline keyword for GNU Compiler /
dkato	0:f782d9c66c49	87	#define __STATIC_INLINE static inline
dkato	0:f782d9c66c49	88
dkato	0:f782d9c66c49	89	#elif defined ( __ICCARM__ )
dkato	0:f782d9c66c49	90	#define __ASM __asm /!< asm keyword for IAR Compiler /
dkato	0:f782d9c66c49	91	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
dkato	0:f782d9c66c49	92	#define __STATIC_INLINE static inline
dkato	0:f782d9c66c49	93
dkato	0:f782d9c66c49	94	#elif defined ( __TMS470__ )
dkato	0:f782d9c66c49	95	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
dkato	0:f782d9c66c49	96	#define __STATIC_INLINE static inline
dkato	0:f782d9c66c49	97
dkato	0:f782d9c66c49	98	#elif defined ( __TASKING__ )
dkato	0:f782d9c66c49	99	#define __ASM __asm /!< asm keyword for TASKING Compiler /
dkato	0:f782d9c66c49	100	#define __INLINE inline /!< inline keyword for TASKING Compiler /
dkato	0:f782d9c66c49	101	#define __STATIC_INLINE static inline
dkato	0:f782d9c66c49	102
dkato	0:f782d9c66c49	103	#elif defined ( __CSMC__ )
dkato	0:f782d9c66c49	104	#define __packed
dkato	0:f782d9c66c49	105	#define __ASM _asm /!< asm keyword for COSMIC Compiler /
dkato	0:f782d9c66c49	106	#define __INLINE inline /use -pc99 on compile line !< inline keyword for COSMIC Compiler /
dkato	0:f782d9c66c49	107	#define __STATIC_INLINE static inline
dkato	0:f782d9c66c49	108
dkato	0:f782d9c66c49	109	#endif
dkato	0:f782d9c66c49	110
dkato	0:f782d9c66c49	111	/** __FPU_USED indicates whether an FPU is used or not.
dkato	0:f782d9c66c49	112	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
dkato	0:f782d9c66c49	113	*/
dkato	0:f782d9c66c49	114	#if defined ( __CC_ARM )
dkato	0:f782d9c66c49	115	#if defined __TARGET_FPU_VFP
dkato	0:f782d9c66c49	116	#if (__FPU_PRESENT == 1)
dkato	0:f782d9c66c49	117	#define __FPU_USED 1
dkato	0:f782d9c66c49	118	#else
dkato	0:f782d9c66c49	119	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato	0:f782d9c66c49	120	#define __FPU_USED 0
dkato	0:f782d9c66c49	121	#endif
dkato	0:f782d9c66c49	122	#else
dkato	0:f782d9c66c49	123	#define __FPU_USED 0
dkato	0:f782d9c66c49	124	#endif
dkato	0:f782d9c66c49	125
dkato	0:f782d9c66c49	126	#elif defined ( __GNUC__ )
dkato	0:f782d9c66c49	127	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
dkato	0:f782d9c66c49	128	#if (__FPU_PRESENT == 1)
dkato	0:f782d9c66c49	129	#define __FPU_USED 1
dkato	0:f782d9c66c49	130	#else
dkato	0:f782d9c66c49	131	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato	0:f782d9c66c49	132	#define __FPU_USED 0
dkato	0:f782d9c66c49	133	#endif
dkato	0:f782d9c66c49	134	#else
dkato	0:f782d9c66c49	135	#define __FPU_USED 0
dkato	0:f782d9c66c49	136	#endif
dkato	0:f782d9c66c49	137
dkato	0:f782d9c66c49	138	#elif defined ( __ICCARM__ )
dkato	0:f782d9c66c49	139	#if defined __ARMVFP__
dkato	0:f782d9c66c49	140	#if (__FPU_PRESENT == 1)
dkato	0:f782d9c66c49	141	#define __FPU_USED 1
dkato	0:f782d9c66c49	142	#else
dkato	0:f782d9c66c49	143	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato	0:f782d9c66c49	144	#define __FPU_USED 0
dkato	0:f782d9c66c49	145	#endif
dkato	0:f782d9c66c49	146	#else
dkato	0:f782d9c66c49	147	#define __FPU_USED 0
dkato	0:f782d9c66c49	148	#endif
dkato	0:f782d9c66c49	149
dkato	0:f782d9c66c49	150	#elif defined ( __TMS470__ )
dkato	0:f782d9c66c49	151	#if defined __TI_VFP_SUPPORT__
dkato	0:f782d9c66c49	152	#if (__FPU_PRESENT == 1)
dkato	0:f782d9c66c49	153	#define __FPU_USED 1
dkato	0:f782d9c66c49	154	#else
dkato	0:f782d9c66c49	155	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato	0:f782d9c66c49	156	#define __FPU_USED 0
dkato	0:f782d9c66c49	157	#endif
dkato	0:f782d9c66c49	158	#else
dkato	0:f782d9c66c49	159	#define __FPU_USED 0
dkato	0:f782d9c66c49	160	#endif
dkato	0:f782d9c66c49	161
dkato	0:f782d9c66c49	162	#elif defined ( __TASKING__ )
dkato	0:f782d9c66c49	163	#if defined __FPU_VFP__
dkato	0:f782d9c66c49	164	#if (__FPU_PRESENT == 1)
dkato	0:f782d9c66c49	165	#define __FPU_USED 1
dkato	0:f782d9c66c49	166	#else
dkato	0:f782d9c66c49	167	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato	0:f782d9c66c49	168	#define __FPU_USED 0
dkato	0:f782d9c66c49	169	#endif
dkato	0:f782d9c66c49	170	#else
dkato	0:f782d9c66c49	171	#define __FPU_USED 0
dkato	0:f782d9c66c49	172	#endif
dkato	0:f782d9c66c49	173
dkato	0:f782d9c66c49	174	#elif defined ( __CSMC__ ) /* Cosmic */
dkato	0:f782d9c66c49	175	#if ( __CSMC__ & 0x400) // FPU present for parser
dkato	0:f782d9c66c49	176	#if (__FPU_PRESENT == 1)
dkato	0:f782d9c66c49	177	#define __FPU_USED 1
dkato	0:f782d9c66c49	178	#else
dkato	0:f782d9c66c49	179	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
dkato	0:f782d9c66c49	180	#define __FPU_USED 0
dkato	0:f782d9c66c49	181	#endif
dkato	0:f782d9c66c49	182	#else
dkato	0:f782d9c66c49	183	#define __FPU_USED 0
dkato	0:f782d9c66c49	184	#endif
dkato	0:f782d9c66c49	185	#endif
dkato	0:f782d9c66c49	186
dkato	0:f782d9c66c49	187	#include <stdint.h> /* standard types definitions */
dkato	0:f782d9c66c49	188	#include <core_cmInstr.h> /* Core Instruction Access */
dkato	0:f782d9c66c49	189	#include <core_cmFunc.h> /* Core Function Access */
dkato	0:f782d9c66c49	190	#include <core_cmSimd.h> /* Compiler specific SIMD Intrinsics */
dkato	0:f782d9c66c49	191
dkato	0:f782d9c66c49	192	#ifdef __cplusplus
dkato	0:f782d9c66c49	193	}
dkato	0:f782d9c66c49	194	#endif
dkato	0:f782d9c66c49	195
dkato	0:f782d9c66c49	196	#endif /* __CORE_CM7_H_GENERIC */
dkato	0:f782d9c66c49	197
dkato	0:f782d9c66c49	198	#ifndef __CMSIS_GENERIC
dkato	0:f782d9c66c49	199
dkato	0:f782d9c66c49	200	#ifndef __CORE_CM7_H_DEPENDANT
dkato	0:f782d9c66c49	201	#define __CORE_CM7_H_DEPENDANT
dkato	0:f782d9c66c49	202
dkato	0:f782d9c66c49	203	#ifdef __cplusplus
dkato	0:f782d9c66c49	204	extern "C" {
dkato	0:f782d9c66c49	205	#endif
dkato	0:f782d9c66c49	206
dkato	0:f782d9c66c49	207	/* check device defines and use defaults */
dkato	0:f782d9c66c49	208	#if defined __CHECK_DEVICE_DEFINES
dkato	0:f782d9c66c49	209	#ifndef __CM7_REV
dkato	0:f782d9c66c49	210	#define __CM7_REV 0x0000
dkato	0:f782d9c66c49	211	#warning "__CM7_REV not defined in device header file; using default!"
dkato	0:f782d9c66c49	212	#endif
dkato	0:f782d9c66c49	213
dkato	0:f782d9c66c49	214	#ifndef __FPU_PRESENT
dkato	0:f782d9c66c49	215	#define __FPU_PRESENT 0
dkato	0:f782d9c66c49	216	#warning "__FPU_PRESENT not defined in device header file; using default!"
dkato	0:f782d9c66c49	217	#endif
dkato	0:f782d9c66c49	218
dkato	0:f782d9c66c49	219	#ifndef __MPU_PRESENT
dkato	0:f782d9c66c49	220	#define __MPU_PRESENT 0
dkato	0:f782d9c66c49	221	#warning "__MPU_PRESENT not defined in device header file; using default!"
dkato	0:f782d9c66c49	222	#endif
dkato	0:f782d9c66c49	223
dkato	0:f782d9c66c49	224	#ifndef __ICACHE_PRESENT
dkato	0:f782d9c66c49	225	#define __ICACHE_PRESENT 0
dkato	0:f782d9c66c49	226	#warning "__ICACHE_PRESENT not defined in device header file; using default!"
dkato	0:f782d9c66c49	227	#endif
dkato	0:f782d9c66c49	228
dkato	0:f782d9c66c49	229	#ifndef __DCACHE_PRESENT
dkato	0:f782d9c66c49	230	#define __DCACHE_PRESENT 0
dkato	0:f782d9c66c49	231	#warning "__DCACHE_PRESENT not defined in device header file; using default!"
dkato	0:f782d9c66c49	232	#endif
dkato	0:f782d9c66c49	233
dkato	0:f782d9c66c49	234	#ifndef __DTCM_PRESENT
dkato	0:f782d9c66c49	235	#define __DTCM_PRESENT 0
dkato	0:f782d9c66c49	236	#warning "__DTCM_PRESENT not defined in device header file; using default!"
dkato	0:f782d9c66c49	237	#endif
dkato	0:f782d9c66c49	238
dkato	0:f782d9c66c49	239	#ifndef __NVIC_PRIO_BITS
dkato	0:f782d9c66c49	240	#define __NVIC_PRIO_BITS 3
dkato	0:f782d9c66c49	241	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
dkato	0:f782d9c66c49	242	#endif
dkato	0:f782d9c66c49	243
dkato	0:f782d9c66c49	244	#ifndef __Vendor_SysTickConfig
dkato	0:f782d9c66c49	245	#define __Vendor_SysTickConfig 0
dkato	0:f782d9c66c49	246	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
dkato	0:f782d9c66c49	247	#endif
dkato	0:f782d9c66c49	248	#endif
dkato	0:f782d9c66c49	249
dkato	0:f782d9c66c49	250	/* IO definitions (access restrictions to peripheral registers) */
dkato	0:f782d9c66c49	251	/**
dkato	0:f782d9c66c49	252	\defgroup CMSIS_glob_defs CMSIS Global Defines
dkato	0:f782d9c66c49	253
dkato	0:f782d9c66c49	254	<strong>IO Type Qualifiers</strong> are used
dkato	0:f782d9c66c49	255	\li to specify the access to peripheral variables.
dkato	0:f782d9c66c49	256	\li for automatic generation of peripheral register debug information.
dkato	0:f782d9c66c49	257	*/
dkato	0:f782d9c66c49	258	#ifdef __cplusplus
dkato	0:f782d9c66c49	259	#define __I volatile /!< Defines 'read only' permissions /
dkato	0:f782d9c66c49	260	#else
dkato	0:f782d9c66c49	261	#define __I volatile const /!< Defines 'read only' permissions /
dkato	0:f782d9c66c49	262	#endif
dkato	0:f782d9c66c49	263	#define __O volatile /!< Defines 'write only' permissions /
dkato	0:f782d9c66c49	264	#define __IO volatile /!< Defines 'read / write' permissions /
dkato	0:f782d9c66c49	265
dkato	0:f782d9c66c49	266	#ifdef __cplusplus
dkato	0:f782d9c66c49	267	#define __IM volatile /!< Defines 'read only' permissions /
dkato	0:f782d9c66c49	268	#else
dkato	0:f782d9c66c49	269	#define __IM volatile const /!< Defines 'read only' permissions /
dkato	0:f782d9c66c49	270	#endif
dkato	0:f782d9c66c49	271	#define __OM volatile /!< Defines 'write only' permissions /
dkato	0:f782d9c66c49	272	#define __IOM volatile /!< Defines 'read / write' permissions /
dkato	0:f782d9c66c49	273
dkato	0:f782d9c66c49	274	/@} end of group Cortex_M7 /
dkato	0:f782d9c66c49	275
dkato	0:f782d9c66c49	276
dkato	0:f782d9c66c49	277
dkato	0:f782d9c66c49	278	/*******************************************************************************
dkato	0:f782d9c66c49	279	* Register Abstraction
dkato	0:f782d9c66c49	280	Core Register contain:
dkato	0:f782d9c66c49	281	- Core Register
dkato	0:f782d9c66c49	282	- Core NVIC Register
dkato	0:f782d9c66c49	283	- Core SCB Register
dkato	0:f782d9c66c49	284	- Core SysTick Register
dkato	0:f782d9c66c49	285	- Core Debug Register
dkato	0:f782d9c66c49	286	- Core MPU Register
dkato	0:f782d9c66c49	287	- Core FPU Register
dkato	0:f782d9c66c49	288	******************************************************************************/
dkato	0:f782d9c66c49	289	/** \defgroup CMSIS_core_register Defines and Type Definitions
dkato	0:f782d9c66c49	290	\brief Type definitions and defines for Cortex-M processor based devices.
dkato	0:f782d9c66c49	291	*/
dkato	0:f782d9c66c49	292
dkato	0:f782d9c66c49	293	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	294	\defgroup CMSIS_CORE Status and Control Registers
dkato	0:f782d9c66c49	295	\brief Core Register type definitions.
dkato	0:f782d9c66c49	296	@{
dkato	0:f782d9c66c49	297	*/
dkato	0:f782d9c66c49	298
dkato	0:f782d9c66c49	299	/** \brief Union type to access the Application Program Status Register (APSR).
dkato	0:f782d9c66c49	300	*/
dkato	0:f782d9c66c49	301	typedef union
dkato	0:f782d9c66c49	302	{
dkato	0:f782d9c66c49	303	struct
dkato	0:f782d9c66c49	304	{
dkato	0:f782d9c66c49	305	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
dkato	0:f782d9c66c49	306	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
dkato	0:f782d9c66c49	307	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
dkato	0:f782d9c66c49	308	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
dkato	0:f782d9c66c49	309	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
dkato	0:f782d9c66c49	310	uint32_t C:1; /!< bit: 29 Carry condition code flag /
dkato	0:f782d9c66c49	311	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
dkato	0:f782d9c66c49	312	uint32_t N:1; /!< bit: 31 Negative condition code flag /
dkato	0:f782d9c66c49	313	} b; /!< Structure used for bit access /
dkato	0:f782d9c66c49	314	uint32_t w; /!< Type used for word access /
dkato	0:f782d9c66c49	315	} APSR_Type;
dkato	0:f782d9c66c49	316
dkato	0:f782d9c66c49	317	/* APSR Register Definitions */
dkato	0:f782d9c66c49	318	#define APSR_N_Pos 31 /!< APSR: N Position /
dkato	0:f782d9c66c49	319	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
dkato	0:f782d9c66c49	320
dkato	0:f782d9c66c49	321	#define APSR_Z_Pos 30 /!< APSR: Z Position /
dkato	0:f782d9c66c49	322	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
dkato	0:f782d9c66c49	323
dkato	0:f782d9c66c49	324	#define APSR_C_Pos 29 /!< APSR: C Position /
dkato	0:f782d9c66c49	325	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
dkato	0:f782d9c66c49	326
dkato	0:f782d9c66c49	327	#define APSR_V_Pos 28 /!< APSR: V Position /
dkato	0:f782d9c66c49	328	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
dkato	0:f782d9c66c49	329
dkato	0:f782d9c66c49	330	#define APSR_Q_Pos 27 /!< APSR: Q Position /
dkato	0:f782d9c66c49	331	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
dkato	0:f782d9c66c49	332
dkato	0:f782d9c66c49	333	#define APSR_GE_Pos 16 /!< APSR: GE Position /
dkato	0:f782d9c66c49	334	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
dkato	0:f782d9c66c49	335
dkato	0:f782d9c66c49	336
dkato	0:f782d9c66c49	337	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
dkato	0:f782d9c66c49	338	*/
dkato	0:f782d9c66c49	339	typedef union
dkato	0:f782d9c66c49	340	{
dkato	0:f782d9c66c49	341	struct
dkato	0:f782d9c66c49	342	{
dkato	0:f782d9c66c49	343	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
dkato	0:f782d9c66c49	344	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
dkato	0:f782d9c66c49	345	} b; /!< Structure used for bit access /
dkato	0:f782d9c66c49	346	uint32_t w; /!< Type used for word access /
dkato	0:f782d9c66c49	347	} IPSR_Type;
dkato	0:f782d9c66c49	348
dkato	0:f782d9c66c49	349	/* IPSR Register Definitions */
dkato	0:f782d9c66c49	350	#define IPSR_ISR_Pos 0 /!< IPSR: ISR Position /
dkato	0:f782d9c66c49	351	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
dkato	0:f782d9c66c49	352
dkato	0:f782d9c66c49	353
dkato	0:f782d9c66c49	354	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
dkato	0:f782d9c66c49	355	*/
dkato	0:f782d9c66c49	356	typedef union
dkato	0:f782d9c66c49	357	{
dkato	0:f782d9c66c49	358	struct
dkato	0:f782d9c66c49	359	{
dkato	0:f782d9c66c49	360	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
dkato	0:f782d9c66c49	361	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
dkato	0:f782d9c66c49	362	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
dkato	0:f782d9c66c49	363	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
dkato	0:f782d9c66c49	364	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
dkato	0:f782d9c66c49	365	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
dkato	0:f782d9c66c49	366	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
dkato	0:f782d9c66c49	367	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
dkato	0:f782d9c66c49	368	uint32_t C:1; /!< bit: 29 Carry condition code flag /
dkato	0:f782d9c66c49	369	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
dkato	0:f782d9c66c49	370	uint32_t N:1; /!< bit: 31 Negative condition code flag /
dkato	0:f782d9c66c49	371	} b; /!< Structure used for bit access /
dkato	0:f782d9c66c49	372	uint32_t w; /!< Type used for word access /
dkato	0:f782d9c66c49	373	} xPSR_Type;
dkato	0:f782d9c66c49	374
dkato	0:f782d9c66c49	375	/* xPSR Register Definitions */
dkato	0:f782d9c66c49	376	#define xPSR_N_Pos 31 /!< xPSR: N Position /
dkato	0:f782d9c66c49	377	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
dkato	0:f782d9c66c49	378
dkato	0:f782d9c66c49	379	#define xPSR_Z_Pos 30 /!< xPSR: Z Position /
dkato	0:f782d9c66c49	380	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
dkato	0:f782d9c66c49	381
dkato	0:f782d9c66c49	382	#define xPSR_C_Pos 29 /!< xPSR: C Position /
dkato	0:f782d9c66c49	383	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
dkato	0:f782d9c66c49	384
dkato	0:f782d9c66c49	385	#define xPSR_V_Pos 28 /!< xPSR: V Position /
dkato	0:f782d9c66c49	386	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
dkato	0:f782d9c66c49	387
dkato	0:f782d9c66c49	388	#define xPSR_Q_Pos 27 /!< xPSR: Q Position /
dkato	0:f782d9c66c49	389	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
dkato	0:f782d9c66c49	390
dkato	0:f782d9c66c49	391	#define xPSR_IT_Pos 25 /!< xPSR: IT Position /
dkato	0:f782d9c66c49	392	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
dkato	0:f782d9c66c49	393
dkato	0:f782d9c66c49	394	#define xPSR_T_Pos 24 /!< xPSR: T Position /
dkato	0:f782d9c66c49	395	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
dkato	0:f782d9c66c49	396
dkato	0:f782d9c66c49	397	#define xPSR_GE_Pos 16 /!< xPSR: GE Position /
dkato	0:f782d9c66c49	398	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
dkato	0:f782d9c66c49	399
dkato	0:f782d9c66c49	400	#define xPSR_ISR_Pos 0 /!< xPSR: ISR Position /
dkato	0:f782d9c66c49	401	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
dkato	0:f782d9c66c49	402
dkato	0:f782d9c66c49	403
dkato	0:f782d9c66c49	404	/** \brief Union type to access the Control Registers (CONTROL).
dkato	0:f782d9c66c49	405	*/
dkato	0:f782d9c66c49	406	typedef union
dkato	0:f782d9c66c49	407	{
dkato	0:f782d9c66c49	408	struct
dkato	0:f782d9c66c49	409	{
dkato	0:f782d9c66c49	410	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
dkato	0:f782d9c66c49	411	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
dkato	0:f782d9c66c49	412	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
dkato	0:f782d9c66c49	413	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
dkato	0:f782d9c66c49	414	} b; /!< Structure used for bit access /
dkato	0:f782d9c66c49	415	uint32_t w; /!< Type used for word access /
dkato	0:f782d9c66c49	416	} CONTROL_Type;
dkato	0:f782d9c66c49	417
dkato	0:f782d9c66c49	418	/* CONTROL Register Definitions */
dkato	0:f782d9c66c49	419	#define CONTROL_FPCA_Pos 2 /!< CONTROL: FPCA Position /
dkato	0:f782d9c66c49	420	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
dkato	0:f782d9c66c49	421
dkato	0:f782d9c66c49	422	#define CONTROL_SPSEL_Pos 1 /!< CONTROL: SPSEL Position /
dkato	0:f782d9c66c49	423	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
dkato	0:f782d9c66c49	424
dkato	0:f782d9c66c49	425	#define CONTROL_nPRIV_Pos 0 /!< CONTROL: nPRIV Position /
dkato	0:f782d9c66c49	426	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
dkato	0:f782d9c66c49	427
dkato	0:f782d9c66c49	428	/@} end of group CMSIS_CORE /
dkato	0:f782d9c66c49	429
dkato	0:f782d9c66c49	430
dkato	0:f782d9c66c49	431	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	432	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
dkato	0:f782d9c66c49	433	\brief Type definitions for the NVIC Registers
dkato	0:f782d9c66c49	434	@{
dkato	0:f782d9c66c49	435	*/
dkato	0:f782d9c66c49	436
dkato	0:f782d9c66c49	437	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
dkato	0:f782d9c66c49	438	*/
dkato	0:f782d9c66c49	439	typedef struct
dkato	0:f782d9c66c49	440	{
dkato	0:f782d9c66c49	441	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
dkato	0:f782d9c66c49	442	uint32_t RESERVED0[24];
dkato	0:f782d9c66c49	443	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
dkato	0:f782d9c66c49	444	uint32_t RSERVED1[24];
dkato	0:f782d9c66c49	445	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
dkato	0:f782d9c66c49	446	uint32_t RESERVED2[24];
dkato	0:f782d9c66c49	447	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
dkato	0:f782d9c66c49	448	uint32_t RESERVED3[24];
dkato	0:f782d9c66c49	449	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
dkato	0:f782d9c66c49	450	uint32_t RESERVED4[56];
dkato	0:f782d9c66c49	451	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
dkato	0:f782d9c66c49	452	uint32_t RESERVED5[644];
dkato	0:f782d9c66c49	453	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
dkato	0:f782d9c66c49	454	} NVIC_Type;
dkato	0:f782d9c66c49	455
dkato	0:f782d9c66c49	456	/* Software Triggered Interrupt Register Definitions */
dkato	0:f782d9c66c49	457	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
dkato	0:f782d9c66c49	458	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
dkato	0:f782d9c66c49	459
dkato	0:f782d9c66c49	460	/@} end of group CMSIS_NVIC /
dkato	0:f782d9c66c49	461
dkato	0:f782d9c66c49	462
dkato	0:f782d9c66c49	463	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	464	\defgroup CMSIS_SCB System Control Block (SCB)
dkato	0:f782d9c66c49	465	\brief Type definitions for the System Control Block Registers
dkato	0:f782d9c66c49	466	@{
dkato	0:f782d9c66c49	467	*/
dkato	0:f782d9c66c49	468
dkato	0:f782d9c66c49	469	/** \brief Structure type to access the System Control Block (SCB).
dkato	0:f782d9c66c49	470	*/
dkato	0:f782d9c66c49	471	typedef struct
dkato	0:f782d9c66c49	472	{
dkato	0:f782d9c66c49	473	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
dkato	0:f782d9c66c49	474	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
dkato	0:f782d9c66c49	475	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
dkato	0:f782d9c66c49	476	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
dkato	0:f782d9c66c49	477	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
dkato	0:f782d9c66c49	478	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
dkato	0:f782d9c66c49	479	__IO uint8_t SHPR[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
dkato	0:f782d9c66c49	480	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
dkato	0:f782d9c66c49	481	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
dkato	0:f782d9c66c49	482	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
dkato	0:f782d9c66c49	483	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
dkato	0:f782d9c66c49	484	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
dkato	0:f782d9c66c49	485	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
dkato	0:f782d9c66c49	486	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
dkato	0:f782d9c66c49	487	__I uint32_t ID_PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
dkato	0:f782d9c66c49	488	__I uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
dkato	0:f782d9c66c49	489	__I uint32_t ID_AFR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
dkato	0:f782d9c66c49	490	__I uint32_t ID_MFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
dkato	0:f782d9c66c49	491	__I uint32_t ID_ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
dkato	0:f782d9c66c49	492	uint32_t RESERVED0[1];
dkato	0:f782d9c66c49	493	__I uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
dkato	0:f782d9c66c49	494	__I uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
dkato	0:f782d9c66c49	495	__I uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
dkato	0:f782d9c66c49	496	__IO uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
dkato	0:f782d9c66c49	497	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
dkato	0:f782d9c66c49	498	uint32_t RESERVED3[93];
dkato	0:f782d9c66c49	499	__O uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
dkato	0:f782d9c66c49	500	uint32_t RESERVED4[15];
dkato	0:f782d9c66c49	501	__I uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
dkato	0:f782d9c66c49	502	__I uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
dkato	0:f782d9c66c49	503	__I uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 /
dkato	0:f782d9c66c49	504	uint32_t RESERVED5[1];
dkato	0:f782d9c66c49	505	__O uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
dkato	0:f782d9c66c49	506	uint32_t RESERVED6[1];
dkato	0:f782d9c66c49	507	__O uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
dkato	0:f782d9c66c49	508	__O uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
dkato	0:f782d9c66c49	509	__O uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
dkato	0:f782d9c66c49	510	__O uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
dkato	0:f782d9c66c49	511	__O uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
dkato	0:f782d9c66c49	512	__O uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
dkato	0:f782d9c66c49	513	__O uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
dkato	0:f782d9c66c49	514	__O uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
dkato	0:f782d9c66c49	515	uint32_t RESERVED7[6];
dkato	0:f782d9c66c49	516	__IO uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
dkato	0:f782d9c66c49	517	__IO uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
dkato	0:f782d9c66c49	518	__IO uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
dkato	0:f782d9c66c49	519	__IO uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
dkato	0:f782d9c66c49	520	__IO uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
dkato	0:f782d9c66c49	521	uint32_t RESERVED8[1];
dkato	0:f782d9c66c49	522	__IO uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
dkato	0:f782d9c66c49	523	} SCB_Type;
dkato	0:f782d9c66c49	524
dkato	0:f782d9c66c49	525	/* SCB CPUID Register Definitions */
dkato	0:f782d9c66c49	526	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
dkato	0:f782d9c66c49	527	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
dkato	0:f782d9c66c49	528
dkato	0:f782d9c66c49	529	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
dkato	0:f782d9c66c49	530	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
dkato	0:f782d9c66c49	531
dkato	0:f782d9c66c49	532	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
dkato	0:f782d9c66c49	533	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
dkato	0:f782d9c66c49	534
dkato	0:f782d9c66c49	535	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
dkato	0:f782d9c66c49	536	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
dkato	0:f782d9c66c49	537
dkato	0:f782d9c66c49	538	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
dkato	0:f782d9c66c49	539	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
dkato	0:f782d9c66c49	540
dkato	0:f782d9c66c49	541	/* SCB Interrupt Control State Register Definitions */
dkato	0:f782d9c66c49	542	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
dkato	0:f782d9c66c49	543	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
dkato	0:f782d9c66c49	544
dkato	0:f782d9c66c49	545	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
dkato	0:f782d9c66c49	546	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
dkato	0:f782d9c66c49	547
dkato	0:f782d9c66c49	548	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
dkato	0:f782d9c66c49	549	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
dkato	0:f782d9c66c49	550
dkato	0:f782d9c66c49	551	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
dkato	0:f782d9c66c49	552	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
dkato	0:f782d9c66c49	553
dkato	0:f782d9c66c49	554	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
dkato	0:f782d9c66c49	555	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
dkato	0:f782d9c66c49	556
dkato	0:f782d9c66c49	557	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
dkato	0:f782d9c66c49	558	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
dkato	0:f782d9c66c49	559
dkato	0:f782d9c66c49	560	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
dkato	0:f782d9c66c49	561	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
dkato	0:f782d9c66c49	562
dkato	0:f782d9c66c49	563	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
dkato	0:f782d9c66c49	564	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
dkato	0:f782d9c66c49	565
dkato	0:f782d9c66c49	566	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
dkato	0:f782d9c66c49	567	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
dkato	0:f782d9c66c49	568
dkato	0:f782d9c66c49	569	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
dkato	0:f782d9c66c49	570	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
dkato	0:f782d9c66c49	571
dkato	0:f782d9c66c49	572	/* SCB Vector Table Offset Register Definitions */
dkato	0:f782d9c66c49	573	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
dkato	0:f782d9c66c49	574	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
dkato	0:f782d9c66c49	575
dkato	0:f782d9c66c49	576	/* SCB Application Interrupt and Reset Control Register Definitions */
dkato	0:f782d9c66c49	577	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
dkato	0:f782d9c66c49	578	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
dkato	0:f782d9c66c49	579
dkato	0:f782d9c66c49	580	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
dkato	0:f782d9c66c49	581	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
dkato	0:f782d9c66c49	582
dkato	0:f782d9c66c49	583	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
dkato	0:f782d9c66c49	584	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
dkato	0:f782d9c66c49	585
dkato	0:f782d9c66c49	586	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
dkato	0:f782d9c66c49	587	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
dkato	0:f782d9c66c49	588
dkato	0:f782d9c66c49	589	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
dkato	0:f782d9c66c49	590	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
dkato	0:f782d9c66c49	591
dkato	0:f782d9c66c49	592	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
dkato	0:f782d9c66c49	593	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
dkato	0:f782d9c66c49	594
dkato	0:f782d9c66c49	595	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
dkato	0:f782d9c66c49	596	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
dkato	0:f782d9c66c49	597
dkato	0:f782d9c66c49	598	/* SCB System Control Register Definitions */
dkato	0:f782d9c66c49	599	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
dkato	0:f782d9c66c49	600	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
dkato	0:f782d9c66c49	601
dkato	0:f782d9c66c49	602	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
dkato	0:f782d9c66c49	603	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
dkato	0:f782d9c66c49	604
dkato	0:f782d9c66c49	605	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
dkato	0:f782d9c66c49	606	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
dkato	0:f782d9c66c49	607
dkato	0:f782d9c66c49	608	/* SCB Configuration Control Register Definitions */
dkato	0:f782d9c66c49	609	#define SCB_CCR_BP_Pos 18 /!< SCB CCR: Branch prediction enable bit Position /
dkato	0:f782d9c66c49	610	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: Branch prediction enable bit Mask /
dkato	0:f782d9c66c49	611
dkato	0:f782d9c66c49	612	#define SCB_CCR_IC_Pos 17 /!< SCB CCR: Instruction cache enable bit Position /
dkato	0:f782d9c66c49	613	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: Instruction cache enable bit Mask /
dkato	0:f782d9c66c49	614
dkato	0:f782d9c66c49	615	#define SCB_CCR_DC_Pos 16 /!< SCB CCR: Cache enable bit Position /
dkato	0:f782d9c66c49	616	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: Cache enable bit Mask /
dkato	0:f782d9c66c49	617
dkato	0:f782d9c66c49	618	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
dkato	0:f782d9c66c49	619	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
dkato	0:f782d9c66c49	620
dkato	0:f782d9c66c49	621	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
dkato	0:f782d9c66c49	622	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
dkato	0:f782d9c66c49	623
dkato	0:f782d9c66c49	624	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
dkato	0:f782d9c66c49	625	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
dkato	0:f782d9c66c49	626
dkato	0:f782d9c66c49	627	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
dkato	0:f782d9c66c49	628	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
dkato	0:f782d9c66c49	629
dkato	0:f782d9c66c49	630	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
dkato	0:f782d9c66c49	631	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
dkato	0:f782d9c66c49	632
dkato	0:f782d9c66c49	633	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
dkato	0:f782d9c66c49	634	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
dkato	0:f782d9c66c49	635
dkato	0:f782d9c66c49	636	/* SCB System Handler Control and State Register Definitions */
dkato	0:f782d9c66c49	637	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
dkato	0:f782d9c66c49	638	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
dkato	0:f782d9c66c49	639
dkato	0:f782d9c66c49	640	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
dkato	0:f782d9c66c49	641	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
dkato	0:f782d9c66c49	642
dkato	0:f782d9c66c49	643	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
dkato	0:f782d9c66c49	644	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
dkato	0:f782d9c66c49	645
dkato	0:f782d9c66c49	646	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
dkato	0:f782d9c66c49	647	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
dkato	0:f782d9c66c49	648
dkato	0:f782d9c66c49	649	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
dkato	0:f782d9c66c49	650	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
dkato	0:f782d9c66c49	651
dkato	0:f782d9c66c49	652	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
dkato	0:f782d9c66c49	653	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
dkato	0:f782d9c66c49	654
dkato	0:f782d9c66c49	655	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
dkato	0:f782d9c66c49	656	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
dkato	0:f782d9c66c49	657
dkato	0:f782d9c66c49	658	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
dkato	0:f782d9c66c49	659	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
dkato	0:f782d9c66c49	660
dkato	0:f782d9c66c49	661	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
dkato	0:f782d9c66c49	662	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
dkato	0:f782d9c66c49	663
dkato	0:f782d9c66c49	664	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
dkato	0:f782d9c66c49	665	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
dkato	0:f782d9c66c49	666
dkato	0:f782d9c66c49	667	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
dkato	0:f782d9c66c49	668	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
dkato	0:f782d9c66c49	669
dkato	0:f782d9c66c49	670	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
dkato	0:f782d9c66c49	671	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
dkato	0:f782d9c66c49	672
dkato	0:f782d9c66c49	673	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
dkato	0:f782d9c66c49	674	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
dkato	0:f782d9c66c49	675
dkato	0:f782d9c66c49	676	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
dkato	0:f782d9c66c49	677	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
dkato	0:f782d9c66c49	678
dkato	0:f782d9c66c49	679	/* SCB Configurable Fault Status Registers Definitions */
dkato	0:f782d9c66c49	680	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
dkato	0:f782d9c66c49	681	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
dkato	0:f782d9c66c49	682
dkato	0:f782d9c66c49	683	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
dkato	0:f782d9c66c49	684	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
dkato	0:f782d9c66c49	685
dkato	0:f782d9c66c49	686	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
dkato	0:f782d9c66c49	687	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
dkato	0:f782d9c66c49	688
dkato	0:f782d9c66c49	689	/* SCB Hard Fault Status Registers Definitions */
dkato	0:f782d9c66c49	690	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
dkato	0:f782d9c66c49	691	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
dkato	0:f782d9c66c49	692
dkato	0:f782d9c66c49	693	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
dkato	0:f782d9c66c49	694	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
dkato	0:f782d9c66c49	695
dkato	0:f782d9c66c49	696	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
dkato	0:f782d9c66c49	697	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
dkato	0:f782d9c66c49	698
dkato	0:f782d9c66c49	699	/* SCB Debug Fault Status Register Definitions */
dkato	0:f782d9c66c49	700	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
dkato	0:f782d9c66c49	701	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
dkato	0:f782d9c66c49	702
dkato	0:f782d9c66c49	703	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
dkato	0:f782d9c66c49	704	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
dkato	0:f782d9c66c49	705
dkato	0:f782d9c66c49	706	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
dkato	0:f782d9c66c49	707	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
dkato	0:f782d9c66c49	708
dkato	0:f782d9c66c49	709	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
dkato	0:f782d9c66c49	710	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
dkato	0:f782d9c66c49	711
dkato	0:f782d9c66c49	712	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
dkato	0:f782d9c66c49	713	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
dkato	0:f782d9c66c49	714
dkato	0:f782d9c66c49	715	/* Cache Level ID register */
dkato	0:f782d9c66c49	716	#define SCB_CLIDR_LOUU_Pos 27 /!< SCB CLIDR: LoUU Position /
dkato	0:f782d9c66c49	717	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
dkato	0:f782d9c66c49	718
dkato	0:f782d9c66c49	719	#define SCB_CLIDR_LOC_Pos 24 /!< SCB CLIDR: LoC Position /
dkato	0:f782d9c66c49	720	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /!< SCB CLIDR: LoC Mask /
dkato	0:f782d9c66c49	721
dkato	0:f782d9c66c49	722	/* Cache Type register */
dkato	0:f782d9c66c49	723	#define SCB_CTR_FORMAT_Pos 29 /!< SCB CTR: Format Position /
dkato	0:f782d9c66c49	724	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
dkato	0:f782d9c66c49	725
dkato	0:f782d9c66c49	726	#define SCB_CTR_CWG_Pos 24 /!< SCB CTR: CWG Position /
dkato	0:f782d9c66c49	727	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
dkato	0:f782d9c66c49	728
dkato	0:f782d9c66c49	729	#define SCB_CTR_ERG_Pos 20 /!< SCB CTR: ERG Position /
dkato	0:f782d9c66c49	730	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
dkato	0:f782d9c66c49	731
dkato	0:f782d9c66c49	732	#define SCB_CTR_DMINLINE_Pos 16 /!< SCB CTR: DminLine Position /
dkato	0:f782d9c66c49	733	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
dkato	0:f782d9c66c49	734
dkato	0:f782d9c66c49	735	#define SCB_CTR_IMINLINE_Pos 0 /!< SCB CTR: ImInLine Position /
dkato	0:f782d9c66c49	736	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
dkato	0:f782d9c66c49	737
dkato	0:f782d9c66c49	738	/* Cache Size ID Register */
dkato	0:f782d9c66c49	739	#define SCB_CCSIDR_WT_Pos 31 /!< SCB CCSIDR: WT Position /
dkato	0:f782d9c66c49	740	#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
dkato	0:f782d9c66c49	741
dkato	0:f782d9c66c49	742	#define SCB_CCSIDR_WB_Pos 30 /!< SCB CCSIDR: WB Position /
dkato	0:f782d9c66c49	743	#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
dkato	0:f782d9c66c49	744
dkato	0:f782d9c66c49	745	#define SCB_CCSIDR_RA_Pos 29 /!< SCB CCSIDR: RA Position /
dkato	0:f782d9c66c49	746	#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
dkato	0:f782d9c66c49	747
dkato	0:f782d9c66c49	748	#define SCB_CCSIDR_WA_Pos 28 /!< SCB CCSIDR: WA Position /
dkato	0:f782d9c66c49	749	#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
dkato	0:f782d9c66c49	750
dkato	0:f782d9c66c49	751	#define SCB_CCSIDR_NUMSETS_Pos 13 /!< SCB CCSIDR: NumSets Position /
dkato	0:f782d9c66c49	752	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
dkato	0:f782d9c66c49	753
dkato	0:f782d9c66c49	754	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /!< SCB CCSIDR: Associativity Position /
dkato	0:f782d9c66c49	755	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
dkato	0:f782d9c66c49	756
dkato	0:f782d9c66c49	757	#define SCB_CCSIDR_LINESIZE_Pos 0 /!< SCB CCSIDR: LineSize Position /
dkato	0:f782d9c66c49	758	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
dkato	0:f782d9c66c49	759
dkato	0:f782d9c66c49	760	/* Cache Size Selection Register */
dkato	0:f782d9c66c49	761	#define SCB_CSSELR_LEVEL_Pos 1 /!< SCB CSSELR: Level Position /
dkato	0:f782d9c66c49	762	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
dkato	0:f782d9c66c49	763
dkato	0:f782d9c66c49	764	#define SCB_CSSELR_IND_Pos 0 /!< SCB CSSELR: InD Position /
dkato	0:f782d9c66c49	765	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
dkato	0:f782d9c66c49	766
dkato	0:f782d9c66c49	767	/* SCB Software Triggered Interrupt Register */
dkato	0:f782d9c66c49	768	#define SCB_STIR_INTID_Pos 0 /!< SCB STIR: INTID Position /
dkato	0:f782d9c66c49	769	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
dkato	0:f782d9c66c49	770
dkato	0:f782d9c66c49	771	/* Instruction Tightly-Coupled Memory Control Register*/
dkato	0:f782d9c66c49	772	#define SCB_ITCMCR_SZ_Pos 3 /!< SCB ITCMCR: SZ Position /
dkato	0:f782d9c66c49	773	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
dkato	0:f782d9c66c49	774
dkato	0:f782d9c66c49	775	#define SCB_ITCMCR_RETEN_Pos 2 /!< SCB ITCMCR: RETEN Position /
dkato	0:f782d9c66c49	776	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
dkato	0:f782d9c66c49	777
dkato	0:f782d9c66c49	778	#define SCB_ITCMCR_RMW_Pos 1 /!< SCB ITCMCR: RMW Position /
dkato	0:f782d9c66c49	779	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
dkato	0:f782d9c66c49	780
dkato	0:f782d9c66c49	781	#define SCB_ITCMCR_EN_Pos 0 /!< SCB ITCMCR: EN Position /
dkato	0:f782d9c66c49	782	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
dkato	0:f782d9c66c49	783
dkato	0:f782d9c66c49	784	/* Data Tightly-Coupled Memory Control Registers */
dkato	0:f782d9c66c49	785	#define SCB_DTCMCR_SZ_Pos 3 /!< SCB DTCMCR: SZ Position /
dkato	0:f782d9c66c49	786	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
dkato	0:f782d9c66c49	787
dkato	0:f782d9c66c49	788	#define SCB_DTCMCR_RETEN_Pos 2 /!< SCB DTCMCR: RETEN Position /
dkato	0:f782d9c66c49	789	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
dkato	0:f782d9c66c49	790
dkato	0:f782d9c66c49	791	#define SCB_DTCMCR_RMW_Pos 1 /!< SCB DTCMCR: RMW Position /
dkato	0:f782d9c66c49	792	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
dkato	0:f782d9c66c49	793
dkato	0:f782d9c66c49	794	#define SCB_DTCMCR_EN_Pos 0 /!< SCB DTCMCR: EN Position /
dkato	0:f782d9c66c49	795	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
dkato	0:f782d9c66c49	796
dkato	0:f782d9c66c49	797	/* AHBP Control Register */
dkato	0:f782d9c66c49	798	#define SCB_AHBPCR_SZ_Pos 1 /!< SCB AHBPCR: SZ Position /
dkato	0:f782d9c66c49	799	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
dkato	0:f782d9c66c49	800
dkato	0:f782d9c66c49	801	#define SCB_AHBPCR_EN_Pos 0 /!< SCB AHBPCR: EN Position /
dkato	0:f782d9c66c49	802	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
dkato	0:f782d9c66c49	803
dkato	0:f782d9c66c49	804	/* L1 Cache Control Register */
dkato	0:f782d9c66c49	805	#define SCB_CACR_FORCEWT_Pos 2 /!< SCB CACR: FORCEWT Position /
dkato	0:f782d9c66c49	806	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
dkato	0:f782d9c66c49	807
dkato	0:f782d9c66c49	808	#define SCB_CACR_ECCEN_Pos 1 /!< SCB CACR: ECCEN Position /
dkato	0:f782d9c66c49	809	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
dkato	0:f782d9c66c49	810
dkato	0:f782d9c66c49	811	#define SCB_CACR_SIWT_Pos 0 /!< SCB CACR: SIWT Position /
dkato	0:f782d9c66c49	812	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
dkato	0:f782d9c66c49	813
dkato	0:f782d9c66c49	814	/* AHBS control register */
dkato	0:f782d9c66c49	815	#define SCB_AHBSCR_INITCOUNT_Pos 11 /!< SCB AHBSCR: INITCOUNT Position /
dkato	0:f782d9c66c49	816	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
dkato	0:f782d9c66c49	817
dkato	0:f782d9c66c49	818	#define SCB_AHBSCR_TPRI_Pos 2 /!< SCB AHBSCR: TPRI Position /
dkato	0:f782d9c66c49	819	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
dkato	0:f782d9c66c49	820
dkato	0:f782d9c66c49	821	#define SCB_AHBSCR_CTL_Pos 0 /!< SCB AHBSCR: CTL Position/
dkato	0:f782d9c66c49	822	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
dkato	0:f782d9c66c49	823
dkato	0:f782d9c66c49	824	/* Auxiliary Bus Fault Status Register */
dkato	0:f782d9c66c49	825	#define SCB_ABFSR_AXIMTYPE_Pos 8 /!< SCB ABFSR: AXIMTYPE Position/
dkato	0:f782d9c66c49	826	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
dkato	0:f782d9c66c49	827
dkato	0:f782d9c66c49	828	#define SCB_ABFSR_EPPB_Pos 4 /!< SCB ABFSR: EPPB Position/
dkato	0:f782d9c66c49	829	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
dkato	0:f782d9c66c49	830
dkato	0:f782d9c66c49	831	#define SCB_ABFSR_AXIM_Pos 3 /!< SCB ABFSR: AXIM Position/
dkato	0:f782d9c66c49	832	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
dkato	0:f782d9c66c49	833
dkato	0:f782d9c66c49	834	#define SCB_ABFSR_AHBP_Pos 2 /!< SCB ABFSR: AHBP Position/
dkato	0:f782d9c66c49	835	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
dkato	0:f782d9c66c49	836
dkato	0:f782d9c66c49	837	#define SCB_ABFSR_DTCM_Pos 1 /!< SCB ABFSR: DTCM Position/
dkato	0:f782d9c66c49	838	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
dkato	0:f782d9c66c49	839
dkato	0:f782d9c66c49	840	#define SCB_ABFSR_ITCM_Pos 0 /!< SCB ABFSR: ITCM Position/
dkato	0:f782d9c66c49	841	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
dkato	0:f782d9c66c49	842
dkato	0:f782d9c66c49	843	/@} end of group CMSIS_SCB /
dkato	0:f782d9c66c49	844
dkato	0:f782d9c66c49	845
dkato	0:f782d9c66c49	846	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	847	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
dkato	0:f782d9c66c49	848	\brief Type definitions for the System Control and ID Register not in the SCB
dkato	0:f782d9c66c49	849	@{
dkato	0:f782d9c66c49	850	*/
dkato	0:f782d9c66c49	851
dkato	0:f782d9c66c49	852	/** \brief Structure type to access the System Control and ID Register not in the SCB.
dkato	0:f782d9c66c49	853	*/
dkato	0:f782d9c66c49	854	typedef struct
dkato	0:f782d9c66c49	855	{
dkato	0:f782d9c66c49	856	uint32_t RESERVED0[1];
dkato	0:f782d9c66c49	857	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
dkato	0:f782d9c66c49	858	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
dkato	0:f782d9c66c49	859	} SCnSCB_Type;
dkato	0:f782d9c66c49	860
dkato	0:f782d9c66c49	861	/* Interrupt Controller Type Register Definitions */
dkato	0:f782d9c66c49	862	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
dkato	0:f782d9c66c49	863	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
dkato	0:f782d9c66c49	864
dkato	0:f782d9c66c49	865	/* Auxiliary Control Register Definitions */
dkato	0:f782d9c66c49	866	#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /!< ACTLR: DISITMATBFLUSH Position /
dkato	0:f782d9c66c49	867	#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /!< ACTLR: DISITMATBFLUSH Mask /
dkato	0:f782d9c66c49	868
dkato	0:f782d9c66c49	869	#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /!< ACTLR: DISRAMODE Position /
dkato	0:f782d9c66c49	870	#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /!< ACTLR: DISRAMODE Mask /
dkato	0:f782d9c66c49	871
dkato	0:f782d9c66c49	872	#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /!< ACTLR: FPEXCODIS Position /
dkato	0:f782d9c66c49	873	#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /!< ACTLR: FPEXCODIS Mask /
dkato	0:f782d9c66c49	874
dkato	0:f782d9c66c49	875	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
dkato	0:f782d9c66c49	876	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
dkato	0:f782d9c66c49	877
dkato	0:f782d9c66c49	878	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
dkato	0:f782d9c66c49	879	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /<< SCnSCB_ACTLR_DISMCYCINT_Pos/) /!< ACTLR: DISMCYCINT Mask /
dkato	0:f782d9c66c49	880
dkato	0:f782d9c66c49	881	/@} end of group CMSIS_SCnotSCB /
dkato	0:f782d9c66c49	882
dkato	0:f782d9c66c49	883
dkato	0:f782d9c66c49	884	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	885	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
dkato	0:f782d9c66c49	886	\brief Type definitions for the System Timer Registers.
dkato	0:f782d9c66c49	887	@{
dkato	0:f782d9c66c49	888	*/
dkato	0:f782d9c66c49	889
dkato	0:f782d9c66c49	890	/** \brief Structure type to access the System Timer (SysTick).
dkato	0:f782d9c66c49	891	*/
dkato	0:f782d9c66c49	892	typedef struct
dkato	0:f782d9c66c49	893	{
dkato	0:f782d9c66c49	894	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
dkato	0:f782d9c66c49	895	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
dkato	0:f782d9c66c49	896	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
dkato	0:f782d9c66c49	897	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
dkato	0:f782d9c66c49	898	} SysTick_Type;
dkato	0:f782d9c66c49	899
dkato	0:f782d9c66c49	900	/* SysTick Control / Status Register Definitions */
dkato	0:f782d9c66c49	901	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
dkato	0:f782d9c66c49	902	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
dkato	0:f782d9c66c49	903
dkato	0:f782d9c66c49	904	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
dkato	0:f782d9c66c49	905	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
dkato	0:f782d9c66c49	906
dkato	0:f782d9c66c49	907	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
dkato	0:f782d9c66c49	908	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
dkato	0:f782d9c66c49	909
dkato	0:f782d9c66c49	910	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
dkato	0:f782d9c66c49	911	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
dkato	0:f782d9c66c49	912
dkato	0:f782d9c66c49	913	/* SysTick Reload Register Definitions */
dkato	0:f782d9c66c49	914	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
dkato	0:f782d9c66c49	915	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
dkato	0:f782d9c66c49	916
dkato	0:f782d9c66c49	917	/* SysTick Current Register Definitions */
dkato	0:f782d9c66c49	918	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
dkato	0:f782d9c66c49	919	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
dkato	0:f782d9c66c49	920
dkato	0:f782d9c66c49	921	/* SysTick Calibration Register Definitions */
dkato	0:f782d9c66c49	922	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
dkato	0:f782d9c66c49	923	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
dkato	0:f782d9c66c49	924
dkato	0:f782d9c66c49	925	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
dkato	0:f782d9c66c49	926	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
dkato	0:f782d9c66c49	927
dkato	0:f782d9c66c49	928	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
dkato	0:f782d9c66c49	929	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
dkato	0:f782d9c66c49	930
dkato	0:f782d9c66c49	931	/@} end of group CMSIS_SysTick /
dkato	0:f782d9c66c49	932
dkato	0:f782d9c66c49	933
dkato	0:f782d9c66c49	934	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	935	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
dkato	0:f782d9c66c49	936	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
dkato	0:f782d9c66c49	937	@{
dkato	0:f782d9c66c49	938	*/
dkato	0:f782d9c66c49	939
dkato	0:f782d9c66c49	940	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
dkato	0:f782d9c66c49	941	*/
dkato	0:f782d9c66c49	942	typedef struct
dkato	0:f782d9c66c49	943	{
dkato	0:f782d9c66c49	944	__O union
dkato	0:f782d9c66c49	945	{
dkato	0:f782d9c66c49	946	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
dkato	0:f782d9c66c49	947	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
dkato	0:f782d9c66c49	948	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
dkato	0:f782d9c66c49	949	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
dkato	0:f782d9c66c49	950	uint32_t RESERVED0[864];
dkato	0:f782d9c66c49	951	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
dkato	0:f782d9c66c49	952	uint32_t RESERVED1[15];
dkato	0:f782d9c66c49	953	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
dkato	0:f782d9c66c49	954	uint32_t RESERVED2[15];
dkato	0:f782d9c66c49	955	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
dkato	0:f782d9c66c49	956	uint32_t RESERVED3[29];
dkato	0:f782d9c66c49	957	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
dkato	0:f782d9c66c49	958	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
dkato	0:f782d9c66c49	959	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
dkato	0:f782d9c66c49	960	uint32_t RESERVED4[43];
dkato	0:f782d9c66c49	961	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
dkato	0:f782d9c66c49	962	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
dkato	0:f782d9c66c49	963	uint32_t RESERVED5[6];
dkato	0:f782d9c66c49	964	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
dkato	0:f782d9c66c49	965	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
dkato	0:f782d9c66c49	966	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
dkato	0:f782d9c66c49	967	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
dkato	0:f782d9c66c49	968	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
dkato	0:f782d9c66c49	969	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
dkato	0:f782d9c66c49	970	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
dkato	0:f782d9c66c49	971	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
dkato	0:f782d9c66c49	972	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
dkato	0:f782d9c66c49	973	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
dkato	0:f782d9c66c49	974	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
dkato	0:f782d9c66c49	975	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
dkato	0:f782d9c66c49	976	} ITM_Type;
dkato	0:f782d9c66c49	977
dkato	0:f782d9c66c49	978	/* ITM Trace Privilege Register Definitions */
dkato	0:f782d9c66c49	979	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
dkato	0:f782d9c66c49	980	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
dkato	0:f782d9c66c49	981
dkato	0:f782d9c66c49	982	/* ITM Trace Control Register Definitions */
dkato	0:f782d9c66c49	983	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
dkato	0:f782d9c66c49	984	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
dkato	0:f782d9c66c49	985
dkato	0:f782d9c66c49	986	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
dkato	0:f782d9c66c49	987	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
dkato	0:f782d9c66c49	988
dkato	0:f782d9c66c49	989	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
dkato	0:f782d9c66c49	990	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
dkato	0:f782d9c66c49	991
dkato	0:f782d9c66c49	992	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
dkato	0:f782d9c66c49	993	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
dkato	0:f782d9c66c49	994
dkato	0:f782d9c66c49	995	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
dkato	0:f782d9c66c49	996	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
dkato	0:f782d9c66c49	997
dkato	0:f782d9c66c49	998	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
dkato	0:f782d9c66c49	999	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
dkato	0:f782d9c66c49	1000
dkato	0:f782d9c66c49	1001	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
dkato	0:f782d9c66c49	1002	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
dkato	0:f782d9c66c49	1003
dkato	0:f782d9c66c49	1004	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
dkato	0:f782d9c66c49	1005	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
dkato	0:f782d9c66c49	1006
dkato	0:f782d9c66c49	1007	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
dkato	0:f782d9c66c49	1008	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
dkato	0:f782d9c66c49	1009
dkato	0:f782d9c66c49	1010	/* ITM Integration Write Register Definitions */
dkato	0:f782d9c66c49	1011	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
dkato	0:f782d9c66c49	1012	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
dkato	0:f782d9c66c49	1013
dkato	0:f782d9c66c49	1014	/* ITM Integration Read Register Definitions */
dkato	0:f782d9c66c49	1015	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
dkato	0:f782d9c66c49	1016	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
dkato	0:f782d9c66c49	1017
dkato	0:f782d9c66c49	1018	/* ITM Integration Mode Control Register Definitions */
dkato	0:f782d9c66c49	1019	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
dkato	0:f782d9c66c49	1020	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
dkato	0:f782d9c66c49	1021
dkato	0:f782d9c66c49	1022	/* ITM Lock Status Register Definitions */
dkato	0:f782d9c66c49	1023	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
dkato	0:f782d9c66c49	1024	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
dkato	0:f782d9c66c49	1025
dkato	0:f782d9c66c49	1026	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
dkato	0:f782d9c66c49	1027	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
dkato	0:f782d9c66c49	1028
dkato	0:f782d9c66c49	1029	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
dkato	0:f782d9c66c49	1030	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
dkato	0:f782d9c66c49	1031
dkato	0:f782d9c66c49	1032	/@}/ /* end of group CMSIS_ITM */
dkato	0:f782d9c66c49	1033
dkato	0:f782d9c66c49	1034
dkato	0:f782d9c66c49	1035	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	1036	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
dkato	0:f782d9c66c49	1037	\brief Type definitions for the Data Watchpoint and Trace (DWT)
dkato	0:f782d9c66c49	1038	@{
dkato	0:f782d9c66c49	1039	*/
dkato	0:f782d9c66c49	1040
dkato	0:f782d9c66c49	1041	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
dkato	0:f782d9c66c49	1042	*/
dkato	0:f782d9c66c49	1043	typedef struct
dkato	0:f782d9c66c49	1044	{
dkato	0:f782d9c66c49	1045	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
dkato	0:f782d9c66c49	1046	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
dkato	0:f782d9c66c49	1047	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
dkato	0:f782d9c66c49	1048	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
dkato	0:f782d9c66c49	1049	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
dkato	0:f782d9c66c49	1050	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
dkato	0:f782d9c66c49	1051	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
dkato	0:f782d9c66c49	1052	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
dkato	0:f782d9c66c49	1053	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
dkato	0:f782d9c66c49	1054	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
dkato	0:f782d9c66c49	1055	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
dkato	0:f782d9c66c49	1056	uint32_t RESERVED0[1];
dkato	0:f782d9c66c49	1057	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
dkato	0:f782d9c66c49	1058	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
dkato	0:f782d9c66c49	1059	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
dkato	0:f782d9c66c49	1060	uint32_t RESERVED1[1];
dkato	0:f782d9c66c49	1061	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
dkato	0:f782d9c66c49	1062	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
dkato	0:f782d9c66c49	1063	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
dkato	0:f782d9c66c49	1064	uint32_t RESERVED2[1];
dkato	0:f782d9c66c49	1065	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
dkato	0:f782d9c66c49	1066	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
dkato	0:f782d9c66c49	1067	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
dkato	0:f782d9c66c49	1068	uint32_t RESERVED3[981];
dkato	0:f782d9c66c49	1069	__O uint32_t LAR; /!< Offset: 0xFB0 ( W) Lock Access Register /
dkato	0:f782d9c66c49	1070	__I uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
dkato	0:f782d9c66c49	1071	} DWT_Type;
dkato	0:f782d9c66c49	1072
dkato	0:f782d9c66c49	1073	/* DWT Control Register Definitions */
dkato	0:f782d9c66c49	1074	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
dkato	0:f782d9c66c49	1075	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
dkato	0:f782d9c66c49	1076
dkato	0:f782d9c66c49	1077	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
dkato	0:f782d9c66c49	1078	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
dkato	0:f782d9c66c49	1079
dkato	0:f782d9c66c49	1080	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
dkato	0:f782d9c66c49	1081	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
dkato	0:f782d9c66c49	1082
dkato	0:f782d9c66c49	1083	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
dkato	0:f782d9c66c49	1084	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
dkato	0:f782d9c66c49	1085
dkato	0:f782d9c66c49	1086	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
dkato	0:f782d9c66c49	1087	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
dkato	0:f782d9c66c49	1088
dkato	0:f782d9c66c49	1089	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
dkato	0:f782d9c66c49	1090	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
dkato	0:f782d9c66c49	1091
dkato	0:f782d9c66c49	1092	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
dkato	0:f782d9c66c49	1093	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
dkato	0:f782d9c66c49	1094
dkato	0:f782d9c66c49	1095	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
dkato	0:f782d9c66c49	1096	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
dkato	0:f782d9c66c49	1097
dkato	0:f782d9c66c49	1098	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
dkato	0:f782d9c66c49	1099	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
dkato	0:f782d9c66c49	1100
dkato	0:f782d9c66c49	1101	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
dkato	0:f782d9c66c49	1102	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
dkato	0:f782d9c66c49	1103
dkato	0:f782d9c66c49	1104	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
dkato	0:f782d9c66c49	1105	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
dkato	0:f782d9c66c49	1106
dkato	0:f782d9c66c49	1107	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
dkato	0:f782d9c66c49	1108	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
dkato	0:f782d9c66c49	1109
dkato	0:f782d9c66c49	1110	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
dkato	0:f782d9c66c49	1111	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
dkato	0:f782d9c66c49	1112
dkato	0:f782d9c66c49	1113	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
dkato	0:f782d9c66c49	1114	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
dkato	0:f782d9c66c49	1115
dkato	0:f782d9c66c49	1116	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
dkato	0:f782d9c66c49	1117	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
dkato	0:f782d9c66c49	1118
dkato	0:f782d9c66c49	1119	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
dkato	0:f782d9c66c49	1120	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
dkato	0:f782d9c66c49	1121
dkato	0:f782d9c66c49	1122	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
dkato	0:f782d9c66c49	1123	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
dkato	0:f782d9c66c49	1124
dkato	0:f782d9c66c49	1125	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
dkato	0:f782d9c66c49	1126	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
dkato	0:f782d9c66c49	1127
dkato	0:f782d9c66c49	1128	/* DWT CPI Count Register Definitions */
dkato	0:f782d9c66c49	1129	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
dkato	0:f782d9c66c49	1130	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
dkato	0:f782d9c66c49	1131
dkato	0:f782d9c66c49	1132	/* DWT Exception Overhead Count Register Definitions */
dkato	0:f782d9c66c49	1133	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
dkato	0:f782d9c66c49	1134	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
dkato	0:f782d9c66c49	1135
dkato	0:f782d9c66c49	1136	/* DWT Sleep Count Register Definitions */
dkato	0:f782d9c66c49	1137	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
dkato	0:f782d9c66c49	1138	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
dkato	0:f782d9c66c49	1139
dkato	0:f782d9c66c49	1140	/* DWT LSU Count Register Definitions */
dkato	0:f782d9c66c49	1141	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
dkato	0:f782d9c66c49	1142	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
dkato	0:f782d9c66c49	1143
dkato	0:f782d9c66c49	1144	/* DWT Folded-instruction Count Register Definitions */
dkato	0:f782d9c66c49	1145	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
dkato	0:f782d9c66c49	1146	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
dkato	0:f782d9c66c49	1147
dkato	0:f782d9c66c49	1148	/* DWT Comparator Mask Register Definitions */
dkato	0:f782d9c66c49	1149	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
dkato	0:f782d9c66c49	1150	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
dkato	0:f782d9c66c49	1151
dkato	0:f782d9c66c49	1152	/* DWT Comparator Function Register Definitions */
dkato	0:f782d9c66c49	1153	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
dkato	0:f782d9c66c49	1154	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
dkato	0:f782d9c66c49	1155
dkato	0:f782d9c66c49	1156	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
dkato	0:f782d9c66c49	1157	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
dkato	0:f782d9c66c49	1158
dkato	0:f782d9c66c49	1159	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
dkato	0:f782d9c66c49	1160	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
dkato	0:f782d9c66c49	1161
dkato	0:f782d9c66c49	1162	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
dkato	0:f782d9c66c49	1163	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
dkato	0:f782d9c66c49	1164
dkato	0:f782d9c66c49	1165	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
dkato	0:f782d9c66c49	1166	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
dkato	0:f782d9c66c49	1167
dkato	0:f782d9c66c49	1168	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
dkato	0:f782d9c66c49	1169	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
dkato	0:f782d9c66c49	1170
dkato	0:f782d9c66c49	1171	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
dkato	0:f782d9c66c49	1172	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
dkato	0:f782d9c66c49	1173
dkato	0:f782d9c66c49	1174	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
dkato	0:f782d9c66c49	1175	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
dkato	0:f782d9c66c49	1176
dkato	0:f782d9c66c49	1177	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
dkato	0:f782d9c66c49	1178	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
dkato	0:f782d9c66c49	1179
dkato	0:f782d9c66c49	1180	/@}/ /* end of group CMSIS_DWT */
dkato	0:f782d9c66c49	1181
dkato	0:f782d9c66c49	1182
dkato	0:f782d9c66c49	1183	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	1184	\defgroup CMSIS_TPI Trace Port Interface (TPI)
dkato	0:f782d9c66c49	1185	\brief Type definitions for the Trace Port Interface (TPI)
dkato	0:f782d9c66c49	1186	@{
dkato	0:f782d9c66c49	1187	*/
dkato	0:f782d9c66c49	1188
dkato	0:f782d9c66c49	1189	/** \brief Structure type to access the Trace Port Interface Register (TPI).
dkato	0:f782d9c66c49	1190	*/
dkato	0:f782d9c66c49	1191	typedef struct
dkato	0:f782d9c66c49	1192	{
dkato	0:f782d9c66c49	1193	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
dkato	0:f782d9c66c49	1194	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
dkato	0:f782d9c66c49	1195	uint32_t RESERVED0[2];
dkato	0:f782d9c66c49	1196	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
dkato	0:f782d9c66c49	1197	uint32_t RESERVED1[55];
dkato	0:f782d9c66c49	1198	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
dkato	0:f782d9c66c49	1199	uint32_t RESERVED2[131];
dkato	0:f782d9c66c49	1200	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
dkato	0:f782d9c66c49	1201	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
dkato	0:f782d9c66c49	1202	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
dkato	0:f782d9c66c49	1203	uint32_t RESERVED3[759];
dkato	0:f782d9c66c49	1204	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
dkato	0:f782d9c66c49	1205	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
dkato	0:f782d9c66c49	1206	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
dkato	0:f782d9c66c49	1207	uint32_t RESERVED4[1];
dkato	0:f782d9c66c49	1208	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
dkato	0:f782d9c66c49	1209	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
dkato	0:f782d9c66c49	1210	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
dkato	0:f782d9c66c49	1211	uint32_t RESERVED5[39];
dkato	0:f782d9c66c49	1212	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
dkato	0:f782d9c66c49	1213	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
dkato	0:f782d9c66c49	1214	uint32_t RESERVED7[8];
dkato	0:f782d9c66c49	1215	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
dkato	0:f782d9c66c49	1216	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
dkato	0:f782d9c66c49	1217	} TPI_Type;
dkato	0:f782d9c66c49	1218
dkato	0:f782d9c66c49	1219	/* TPI Asynchronous Clock Prescaler Register Definitions */
dkato	0:f782d9c66c49	1220	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
dkato	0:f782d9c66c49	1221	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
dkato	0:f782d9c66c49	1222
dkato	0:f782d9c66c49	1223	/* TPI Selected Pin Protocol Register Definitions */
dkato	0:f782d9c66c49	1224	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
dkato	0:f782d9c66c49	1225	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
dkato	0:f782d9c66c49	1226
dkato	0:f782d9c66c49	1227	/* TPI Formatter and Flush Status Register Definitions */
dkato	0:f782d9c66c49	1228	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
dkato	0:f782d9c66c49	1229	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
dkato	0:f782d9c66c49	1230
dkato	0:f782d9c66c49	1231	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
dkato	0:f782d9c66c49	1232	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
dkato	0:f782d9c66c49	1233
dkato	0:f782d9c66c49	1234	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
dkato	0:f782d9c66c49	1235	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
dkato	0:f782d9c66c49	1236
dkato	0:f782d9c66c49	1237	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
dkato	0:f782d9c66c49	1238	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
dkato	0:f782d9c66c49	1239
dkato	0:f782d9c66c49	1240	/* TPI Formatter and Flush Control Register Definitions */
dkato	0:f782d9c66c49	1241	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
dkato	0:f782d9c66c49	1242	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
dkato	0:f782d9c66c49	1243
dkato	0:f782d9c66c49	1244	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
dkato	0:f782d9c66c49	1245	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
dkato	0:f782d9c66c49	1246
dkato	0:f782d9c66c49	1247	/* TPI TRIGGER Register Definitions */
dkato	0:f782d9c66c49	1248	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
dkato	0:f782d9c66c49	1249	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
dkato	0:f782d9c66c49	1250
dkato	0:f782d9c66c49	1251	/* TPI Integration ETM Data Register Definitions (FIFO0) */
dkato	0:f782d9c66c49	1252	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
dkato	0:f782d9c66c49	1253	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
dkato	0:f782d9c66c49	1254
dkato	0:f782d9c66c49	1255	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
dkato	0:f782d9c66c49	1256	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
dkato	0:f782d9c66c49	1257
dkato	0:f782d9c66c49	1258	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
dkato	0:f782d9c66c49	1259	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
dkato	0:f782d9c66c49	1260
dkato	0:f782d9c66c49	1261	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
dkato	0:f782d9c66c49	1262	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
dkato	0:f782d9c66c49	1263
dkato	0:f782d9c66c49	1264	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
dkato	0:f782d9c66c49	1265	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
dkato	0:f782d9c66c49	1266
dkato	0:f782d9c66c49	1267	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
dkato	0:f782d9c66c49	1268	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
dkato	0:f782d9c66c49	1269
dkato	0:f782d9c66c49	1270	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
dkato	0:f782d9c66c49	1271	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
dkato	0:f782d9c66c49	1272
dkato	0:f782d9c66c49	1273	/* TPI ITATBCTR2 Register Definitions */
dkato	0:f782d9c66c49	1274	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
dkato	0:f782d9c66c49	1275	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
dkato	0:f782d9c66c49	1276
dkato	0:f782d9c66c49	1277	/* TPI Integration ITM Data Register Definitions (FIFO1) */
dkato	0:f782d9c66c49	1278	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
dkato	0:f782d9c66c49	1279	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
dkato	0:f782d9c66c49	1280
dkato	0:f782d9c66c49	1281	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
dkato	0:f782d9c66c49	1282	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
dkato	0:f782d9c66c49	1283
dkato	0:f782d9c66c49	1284	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
dkato	0:f782d9c66c49	1285	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
dkato	0:f782d9c66c49	1286
dkato	0:f782d9c66c49	1287	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
dkato	0:f782d9c66c49	1288	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
dkato	0:f782d9c66c49	1289
dkato	0:f782d9c66c49	1290	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
dkato	0:f782d9c66c49	1291	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
dkato	0:f782d9c66c49	1292
dkato	0:f782d9c66c49	1293	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
dkato	0:f782d9c66c49	1294	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
dkato	0:f782d9c66c49	1295
dkato	0:f782d9c66c49	1296	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
dkato	0:f782d9c66c49	1297	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
dkato	0:f782d9c66c49	1298
dkato	0:f782d9c66c49	1299	/* TPI ITATBCTR0 Register Definitions */
dkato	0:f782d9c66c49	1300	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
dkato	0:f782d9c66c49	1301	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
dkato	0:f782d9c66c49	1302
dkato	0:f782d9c66c49	1303	/* TPI Integration Mode Control Register Definitions */
dkato	0:f782d9c66c49	1304	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
dkato	0:f782d9c66c49	1305	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
dkato	0:f782d9c66c49	1306
dkato	0:f782d9c66c49	1307	/* TPI DEVID Register Definitions */
dkato	0:f782d9c66c49	1308	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
dkato	0:f782d9c66c49	1309	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
dkato	0:f782d9c66c49	1310
dkato	0:f782d9c66c49	1311	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
dkato	0:f782d9c66c49	1312	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
dkato	0:f782d9c66c49	1313
dkato	0:f782d9c66c49	1314	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
dkato	0:f782d9c66c49	1315	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
dkato	0:f782d9c66c49	1316
dkato	0:f782d9c66c49	1317	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
dkato	0:f782d9c66c49	1318	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
dkato	0:f782d9c66c49	1319
dkato	0:f782d9c66c49	1320	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
dkato	0:f782d9c66c49	1321	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
dkato	0:f782d9c66c49	1322
dkato	0:f782d9c66c49	1323	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
dkato	0:f782d9c66c49	1324	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
dkato	0:f782d9c66c49	1325
dkato	0:f782d9c66c49	1326	/* TPI DEVTYPE Register Definitions */
dkato	0:f782d9c66c49	1327	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
dkato	0:f782d9c66c49	1328	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
dkato	0:f782d9c66c49	1329
dkato	0:f782d9c66c49	1330	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
dkato	0:f782d9c66c49	1331	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
dkato	0:f782d9c66c49	1332
dkato	0:f782d9c66c49	1333	/@}/ /* end of group CMSIS_TPI */
dkato	0:f782d9c66c49	1334
dkato	0:f782d9c66c49	1335
dkato	0:f782d9c66c49	1336	#if (__MPU_PRESENT == 1)
dkato	0:f782d9c66c49	1337	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	1338	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
dkato	0:f782d9c66c49	1339	\brief Type definitions for the Memory Protection Unit (MPU)
dkato	0:f782d9c66c49	1340	@{
dkato	0:f782d9c66c49	1341	*/
dkato	0:f782d9c66c49	1342
dkato	0:f782d9c66c49	1343	/** \brief Structure type to access the Memory Protection Unit (MPU).
dkato	0:f782d9c66c49	1344	*/
dkato	0:f782d9c66c49	1345	typedef struct
dkato	0:f782d9c66c49	1346	{
dkato	0:f782d9c66c49	1347	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
dkato	0:f782d9c66c49	1348	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
dkato	0:f782d9c66c49	1349	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
dkato	0:f782d9c66c49	1350	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
dkato	0:f782d9c66c49	1351	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
dkato	0:f782d9c66c49	1352	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
dkato	0:f782d9c66c49	1353	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
dkato	0:f782d9c66c49	1354	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
dkato	0:f782d9c66c49	1355	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
dkato	0:f782d9c66c49	1356	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
dkato	0:f782d9c66c49	1357	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
dkato	0:f782d9c66c49	1358	} MPU_Type;
dkato	0:f782d9c66c49	1359
dkato	0:f782d9c66c49	1360	/* MPU Type Register */
dkato	0:f782d9c66c49	1361	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
dkato	0:f782d9c66c49	1362	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
dkato	0:f782d9c66c49	1363
dkato	0:f782d9c66c49	1364	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
dkato	0:f782d9c66c49	1365	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
dkato	0:f782d9c66c49	1366
dkato	0:f782d9c66c49	1367	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
dkato	0:f782d9c66c49	1368	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
dkato	0:f782d9c66c49	1369
dkato	0:f782d9c66c49	1370	/* MPU Control Register */
dkato	0:f782d9c66c49	1371	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
dkato	0:f782d9c66c49	1372	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
dkato	0:f782d9c66c49	1373
dkato	0:f782d9c66c49	1374	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
dkato	0:f782d9c66c49	1375	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
dkato	0:f782d9c66c49	1376
dkato	0:f782d9c66c49	1377	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
dkato	0:f782d9c66c49	1378	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
dkato	0:f782d9c66c49	1379
dkato	0:f782d9c66c49	1380	/* MPU Region Number Register */
dkato	0:f782d9c66c49	1381	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
dkato	0:f782d9c66c49	1382	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
dkato	0:f782d9c66c49	1383
dkato	0:f782d9c66c49	1384	/* MPU Region Base Address Register */
dkato	0:f782d9c66c49	1385	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
dkato	0:f782d9c66c49	1386	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
dkato	0:f782d9c66c49	1387
dkato	0:f782d9c66c49	1388	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
dkato	0:f782d9c66c49	1389	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
dkato	0:f782d9c66c49	1390
dkato	0:f782d9c66c49	1391	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
dkato	0:f782d9c66c49	1392	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
dkato	0:f782d9c66c49	1393
dkato	0:f782d9c66c49	1394	/* MPU Region Attribute and Size Register */
dkato	0:f782d9c66c49	1395	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
dkato	0:f782d9c66c49	1396	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
dkato	0:f782d9c66c49	1397
dkato	0:f782d9c66c49	1398	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
dkato	0:f782d9c66c49	1399	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
dkato	0:f782d9c66c49	1400
dkato	0:f782d9c66c49	1401	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
dkato	0:f782d9c66c49	1402	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
dkato	0:f782d9c66c49	1403
dkato	0:f782d9c66c49	1404	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
dkato	0:f782d9c66c49	1405	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
dkato	0:f782d9c66c49	1406
dkato	0:f782d9c66c49	1407	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
dkato	0:f782d9c66c49	1408	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
dkato	0:f782d9c66c49	1409
dkato	0:f782d9c66c49	1410	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
dkato	0:f782d9c66c49	1411	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
dkato	0:f782d9c66c49	1412
dkato	0:f782d9c66c49	1413	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
dkato	0:f782d9c66c49	1414	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
dkato	0:f782d9c66c49	1415
dkato	0:f782d9c66c49	1416	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
dkato	0:f782d9c66c49	1417	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
dkato	0:f782d9c66c49	1418
dkato	0:f782d9c66c49	1419	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
dkato	0:f782d9c66c49	1420	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
dkato	0:f782d9c66c49	1421
dkato	0:f782d9c66c49	1422	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
dkato	0:f782d9c66c49	1423	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
dkato	0:f782d9c66c49	1424
dkato	0:f782d9c66c49	1425	/@} end of group CMSIS_MPU /
dkato	0:f782d9c66c49	1426	#endif
dkato	0:f782d9c66c49	1427
dkato	0:f782d9c66c49	1428
dkato	0:f782d9c66c49	1429	#if (__FPU_PRESENT == 1)
dkato	0:f782d9c66c49	1430	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	1431	\defgroup CMSIS_FPU Floating Point Unit (FPU)
dkato	0:f782d9c66c49	1432	\brief Type definitions for the Floating Point Unit (FPU)
dkato	0:f782d9c66c49	1433	@{
dkato	0:f782d9c66c49	1434	*/
dkato	0:f782d9c66c49	1435
dkato	0:f782d9c66c49	1436	/** \brief Structure type to access the Floating Point Unit (FPU).
dkato	0:f782d9c66c49	1437	*/
dkato	0:f782d9c66c49	1438	typedef struct
dkato	0:f782d9c66c49	1439	{
dkato	0:f782d9c66c49	1440	uint32_t RESERVED0[1];
dkato	0:f782d9c66c49	1441	__IO uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
dkato	0:f782d9c66c49	1442	__IO uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
dkato	0:f782d9c66c49	1443	__IO uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
dkato	0:f782d9c66c49	1444	__I uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
dkato	0:f782d9c66c49	1445	__I uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
dkato	0:f782d9c66c49	1446	__I uint32_t MVFR2; /!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 /
dkato	0:f782d9c66c49	1447	} FPU_Type;
dkato	0:f782d9c66c49	1448
dkato	0:f782d9c66c49	1449	/* Floating-Point Context Control Register */
dkato	0:f782d9c66c49	1450	#define FPU_FPCCR_ASPEN_Pos 31 /!< FPCCR: ASPEN bit Position /
dkato	0:f782d9c66c49	1451	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
dkato	0:f782d9c66c49	1452
dkato	0:f782d9c66c49	1453	#define FPU_FPCCR_LSPEN_Pos 30 /!< FPCCR: LSPEN Position /
dkato	0:f782d9c66c49	1454	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
dkato	0:f782d9c66c49	1455
dkato	0:f782d9c66c49	1456	#define FPU_FPCCR_MONRDY_Pos 8 /!< FPCCR: MONRDY Position /
dkato	0:f782d9c66c49	1457	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
dkato	0:f782d9c66c49	1458
dkato	0:f782d9c66c49	1459	#define FPU_FPCCR_BFRDY_Pos 6 /!< FPCCR: BFRDY Position /
dkato	0:f782d9c66c49	1460	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
dkato	0:f782d9c66c49	1461
dkato	0:f782d9c66c49	1462	#define FPU_FPCCR_MMRDY_Pos 5 /!< FPCCR: MMRDY Position /
dkato	0:f782d9c66c49	1463	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
dkato	0:f782d9c66c49	1464
dkato	0:f782d9c66c49	1465	#define FPU_FPCCR_HFRDY_Pos 4 /!< FPCCR: HFRDY Position /
dkato	0:f782d9c66c49	1466	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
dkato	0:f782d9c66c49	1467
dkato	0:f782d9c66c49	1468	#define FPU_FPCCR_THREAD_Pos 3 /!< FPCCR: processor mode bit Position /
dkato	0:f782d9c66c49	1469	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
dkato	0:f782d9c66c49	1470
dkato	0:f782d9c66c49	1471	#define FPU_FPCCR_USER_Pos 1 /!< FPCCR: privilege level bit Position /
dkato	0:f782d9c66c49	1472	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
dkato	0:f782d9c66c49	1473
dkato	0:f782d9c66c49	1474	#define FPU_FPCCR_LSPACT_Pos 0 /!< FPCCR: Lazy state preservation active bit Position /
dkato	0:f782d9c66c49	1475	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
dkato	0:f782d9c66c49	1476
dkato	0:f782d9c66c49	1477	/* Floating-Point Context Address Register */
dkato	0:f782d9c66c49	1478	#define FPU_FPCAR_ADDRESS_Pos 3 /!< FPCAR: ADDRESS bit Position /
dkato	0:f782d9c66c49	1479	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
dkato	0:f782d9c66c49	1480
dkato	0:f782d9c66c49	1481	/* Floating-Point Default Status Control Register */
dkato	0:f782d9c66c49	1482	#define FPU_FPDSCR_AHP_Pos 26 /!< FPDSCR: AHP bit Position /
dkato	0:f782d9c66c49	1483	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
dkato	0:f782d9c66c49	1484
dkato	0:f782d9c66c49	1485	#define FPU_FPDSCR_DN_Pos 25 /!< FPDSCR: DN bit Position /
dkato	0:f782d9c66c49	1486	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
dkato	0:f782d9c66c49	1487
dkato	0:f782d9c66c49	1488	#define FPU_FPDSCR_FZ_Pos 24 /!< FPDSCR: FZ bit Position /
dkato	0:f782d9c66c49	1489	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
dkato	0:f782d9c66c49	1490
dkato	0:f782d9c66c49	1491	#define FPU_FPDSCR_RMode_Pos 22 /!< FPDSCR: RMode bit Position /
dkato	0:f782d9c66c49	1492	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
dkato	0:f782d9c66c49	1493
dkato	0:f782d9c66c49	1494	/* Media and FP Feature Register 0 */
dkato	0:f782d9c66c49	1495	#define FPU_MVFR0_FP_rounding_modes_Pos 28 /!< MVFR0: FP rounding modes bits Position /
dkato	0:f782d9c66c49	1496	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
dkato	0:f782d9c66c49	1497
dkato	0:f782d9c66c49	1498	#define FPU_MVFR0_Short_vectors_Pos 24 /!< MVFR0: Short vectors bits Position /
dkato	0:f782d9c66c49	1499	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
dkato	0:f782d9c66c49	1500
dkato	0:f782d9c66c49	1501	#define FPU_MVFR0_Square_root_Pos 20 /!< MVFR0: Square root bits Position /
dkato	0:f782d9c66c49	1502	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
dkato	0:f782d9c66c49	1503
dkato	0:f782d9c66c49	1504	#define FPU_MVFR0_Divide_Pos 16 /!< MVFR0: Divide bits Position /
dkato	0:f782d9c66c49	1505	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
dkato	0:f782d9c66c49	1506
dkato	0:f782d9c66c49	1507	#define FPU_MVFR0_FP_excep_trapping_Pos 12 /!< MVFR0: FP exception trapping bits Position /
dkato	0:f782d9c66c49	1508	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
dkato	0:f782d9c66c49	1509
dkato	0:f782d9c66c49	1510	#define FPU_MVFR0_Double_precision_Pos 8 /!< MVFR0: Double-precision bits Position /
dkato	0:f782d9c66c49	1511	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
dkato	0:f782d9c66c49	1512
dkato	0:f782d9c66c49	1513	#define FPU_MVFR0_Single_precision_Pos 4 /!< MVFR0: Single-precision bits Position /
dkato	0:f782d9c66c49	1514	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
dkato	0:f782d9c66c49	1515
dkato	0:f782d9c66c49	1516	#define FPU_MVFR0_A_SIMD_registers_Pos 0 /!< MVFR0: A_SIMD registers bits Position /
dkato	0:f782d9c66c49	1517	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
dkato	0:f782d9c66c49	1518
dkato	0:f782d9c66c49	1519	/* Media and FP Feature Register 1 */
dkato	0:f782d9c66c49	1520	#define FPU_MVFR1_FP_fused_MAC_Pos 28 /!< MVFR1: FP fused MAC bits Position /
dkato	0:f782d9c66c49	1521	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
dkato	0:f782d9c66c49	1522
dkato	0:f782d9c66c49	1523	#define FPU_MVFR1_FP_HPFP_Pos 24 /!< MVFR1: FP HPFP bits Position /
dkato	0:f782d9c66c49	1524	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
dkato	0:f782d9c66c49	1525
dkato	0:f782d9c66c49	1526	#define FPU_MVFR1_D_NaN_mode_Pos 4 /!< MVFR1: D_NaN mode bits Position /
dkato	0:f782d9c66c49	1527	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
dkato	0:f782d9c66c49	1528
dkato	0:f782d9c66c49	1529	#define FPU_MVFR1_FtZ_mode_Pos 0 /!< MVFR1: FtZ mode bits Position /
dkato	0:f782d9c66c49	1530	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
dkato	0:f782d9c66c49	1531
dkato	0:f782d9c66c49	1532	/* Media and FP Feature Register 2 */
dkato	0:f782d9c66c49	1533
dkato	0:f782d9c66c49	1534	/@} end of group CMSIS_FPU /
dkato	0:f782d9c66c49	1535	#endif
dkato	0:f782d9c66c49	1536
dkato	0:f782d9c66c49	1537
dkato	0:f782d9c66c49	1538	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	1539	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
dkato	0:f782d9c66c49	1540	\brief Type definitions for the Core Debug Registers
dkato	0:f782d9c66c49	1541	@{
dkato	0:f782d9c66c49	1542	*/
dkato	0:f782d9c66c49	1543
dkato	0:f782d9c66c49	1544	/** \brief Structure type to access the Core Debug Register (CoreDebug).
dkato	0:f782d9c66c49	1545	*/
dkato	0:f782d9c66c49	1546	typedef struct
dkato	0:f782d9c66c49	1547	{
dkato	0:f782d9c66c49	1548	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
dkato	0:f782d9c66c49	1549	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
dkato	0:f782d9c66c49	1550	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
dkato	0:f782d9c66c49	1551	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
dkato	0:f782d9c66c49	1552	} CoreDebug_Type;
dkato	0:f782d9c66c49	1553
dkato	0:f782d9c66c49	1554	/* Debug Halting Control and Status Register */
dkato	0:f782d9c66c49	1555	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
dkato	0:f782d9c66c49	1556	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
dkato	0:f782d9c66c49	1557
dkato	0:f782d9c66c49	1558	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
dkato	0:f782d9c66c49	1559	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
dkato	0:f782d9c66c49	1560
dkato	0:f782d9c66c49	1561	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
dkato	0:f782d9c66c49	1562	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
dkato	0:f782d9c66c49	1563
dkato	0:f782d9c66c49	1564	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
dkato	0:f782d9c66c49	1565	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
dkato	0:f782d9c66c49	1566
dkato	0:f782d9c66c49	1567	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
dkato	0:f782d9c66c49	1568	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
dkato	0:f782d9c66c49	1569
dkato	0:f782d9c66c49	1570	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
dkato	0:f782d9c66c49	1571	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
dkato	0:f782d9c66c49	1572
dkato	0:f782d9c66c49	1573	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
dkato	0:f782d9c66c49	1574	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
dkato	0:f782d9c66c49	1575
dkato	0:f782d9c66c49	1576	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
dkato	0:f782d9c66c49	1577	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
dkato	0:f782d9c66c49	1578
dkato	0:f782d9c66c49	1579	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
dkato	0:f782d9c66c49	1580	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
dkato	0:f782d9c66c49	1581
dkato	0:f782d9c66c49	1582	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
dkato	0:f782d9c66c49	1583	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
dkato	0:f782d9c66c49	1584
dkato	0:f782d9c66c49	1585	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
dkato	0:f782d9c66c49	1586	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
dkato	0:f782d9c66c49	1587
dkato	0:f782d9c66c49	1588	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
dkato	0:f782d9c66c49	1589	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
dkato	0:f782d9c66c49	1590
dkato	0:f782d9c66c49	1591	/* Debug Core Register Selector Register */
dkato	0:f782d9c66c49	1592	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
dkato	0:f782d9c66c49	1593	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
dkato	0:f782d9c66c49	1594
dkato	0:f782d9c66c49	1595	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
dkato	0:f782d9c66c49	1596	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
dkato	0:f782d9c66c49	1597
dkato	0:f782d9c66c49	1598	/* Debug Exception and Monitor Control Register */
dkato	0:f782d9c66c49	1599	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
dkato	0:f782d9c66c49	1600	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
dkato	0:f782d9c66c49	1601
dkato	0:f782d9c66c49	1602	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
dkato	0:f782d9c66c49	1603	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
dkato	0:f782d9c66c49	1604
dkato	0:f782d9c66c49	1605	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
dkato	0:f782d9c66c49	1606	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
dkato	0:f782d9c66c49	1607
dkato	0:f782d9c66c49	1608	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
dkato	0:f782d9c66c49	1609	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
dkato	0:f782d9c66c49	1610
dkato	0:f782d9c66c49	1611	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
dkato	0:f782d9c66c49	1612	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
dkato	0:f782d9c66c49	1613
dkato	0:f782d9c66c49	1614	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
dkato	0:f782d9c66c49	1615	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
dkato	0:f782d9c66c49	1616
dkato	0:f782d9c66c49	1617	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
dkato	0:f782d9c66c49	1618	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
dkato	0:f782d9c66c49	1619
dkato	0:f782d9c66c49	1620	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
dkato	0:f782d9c66c49	1621	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
dkato	0:f782d9c66c49	1622
dkato	0:f782d9c66c49	1623	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
dkato	0:f782d9c66c49	1624	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
dkato	0:f782d9c66c49	1625
dkato	0:f782d9c66c49	1626	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
dkato	0:f782d9c66c49	1627	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
dkato	0:f782d9c66c49	1628
dkato	0:f782d9c66c49	1629	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
dkato	0:f782d9c66c49	1630	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
dkato	0:f782d9c66c49	1631
dkato	0:f782d9c66c49	1632	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
dkato	0:f782d9c66c49	1633	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
dkato	0:f782d9c66c49	1634
dkato	0:f782d9c66c49	1635	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
dkato	0:f782d9c66c49	1636	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
dkato	0:f782d9c66c49	1637
dkato	0:f782d9c66c49	1638	/@} end of group CMSIS_CoreDebug /
dkato	0:f782d9c66c49	1639
dkato	0:f782d9c66c49	1640
dkato	0:f782d9c66c49	1641	/** \ingroup CMSIS_core_register
dkato	0:f782d9c66c49	1642	\defgroup CMSIS_core_base Core Definitions
dkato	0:f782d9c66c49	1643	\brief Definitions for base addresses, unions, and structures.
dkato	0:f782d9c66c49	1644	@{
dkato	0:f782d9c66c49	1645	*/
dkato	0:f782d9c66c49	1646
dkato	0:f782d9c66c49	1647	/* Memory mapping of Cortex-M4 Hardware */
dkato	0:f782d9c66c49	1648	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
dkato	0:f782d9c66c49	1649	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
dkato	0:f782d9c66c49	1650	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
dkato	0:f782d9c66c49	1651	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
dkato	0:f782d9c66c49	1652	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
dkato	0:f782d9c66c49	1653	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
dkato	0:f782d9c66c49	1654	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
dkato	0:f782d9c66c49	1655	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
dkato	0:f782d9c66c49	1656
dkato	0:f782d9c66c49	1657	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
dkato	0:f782d9c66c49	1658	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
dkato	0:f782d9c66c49	1659	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
dkato	0:f782d9c66c49	1660	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
dkato	0:f782d9c66c49	1661	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
dkato	0:f782d9c66c49	1662	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
dkato	0:f782d9c66c49	1663	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
dkato	0:f782d9c66c49	1664	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
dkato	0:f782d9c66c49	1665
dkato	0:f782d9c66c49	1666	#if (__MPU_PRESENT == 1)
dkato	0:f782d9c66c49	1667	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
dkato	0:f782d9c66c49	1668	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
dkato	0:f782d9c66c49	1669	#endif
dkato	0:f782d9c66c49	1670
dkato	0:f782d9c66c49	1671	#if (__FPU_PRESENT == 1)
dkato	0:f782d9c66c49	1672	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
dkato	0:f782d9c66c49	1673	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
dkato	0:f782d9c66c49	1674	#endif
dkato	0:f782d9c66c49	1675
dkato	0:f782d9c66c49	1676	/@} /
dkato	0:f782d9c66c49	1677
dkato	0:f782d9c66c49	1678
dkato	0:f782d9c66c49	1679
dkato	0:f782d9c66c49	1680	/*******************************************************************************
dkato	0:f782d9c66c49	1681	* Hardware Abstraction Layer
dkato	0:f782d9c66c49	1682	Core Function Interface contains:
dkato	0:f782d9c66c49	1683	- Core NVIC Functions
dkato	0:f782d9c66c49	1684	- Core SysTick Functions
dkato	0:f782d9c66c49	1685	- Core Debug Functions
dkato	0:f782d9c66c49	1686	- Core Register Access Functions
dkato	0:f782d9c66c49	1687	******************************************************************************/
dkato	0:f782d9c66c49	1688	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
dkato	0:f782d9c66c49	1689	*/
dkato	0:f782d9c66c49	1690
dkato	0:f782d9c66c49	1691
dkato	0:f782d9c66c49	1692
dkato	0:f782d9c66c49	1693	/* ########################## NVIC functions #################################### */
dkato	0:f782d9c66c49	1694	/** \ingroup CMSIS_Core_FunctionInterface
dkato	0:f782d9c66c49	1695	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
dkato	0:f782d9c66c49	1696	\brief Functions that manage interrupts and exceptions via the NVIC.
dkato	0:f782d9c66c49	1697	@{
dkato	0:f782d9c66c49	1698	*/
dkato	0:f782d9c66c49	1699
dkato	0:f782d9c66c49	1700	/** \brief Set Priority Grouping
dkato	0:f782d9c66c49	1701
dkato	0:f782d9c66c49	1702	The function sets the priority grouping field using the required unlock sequence.
dkato	0:f782d9c66c49	1703	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
dkato	0:f782d9c66c49	1704	Only values from 0..7 are used.
dkato	0:f782d9c66c49	1705	In case of a conflict between priority grouping and available
dkato	0:f782d9c66c49	1706	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
dkato	0:f782d9c66c49	1707
dkato	0:f782d9c66c49	1708	\param [in] PriorityGroup Priority grouping field.
dkato	0:f782d9c66c49	1709	*/
dkato	0:f782d9c66c49	1710	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
dkato	0:f782d9c66c49	1711	{
dkato	0:f782d9c66c49	1712	uint32_t reg_value;
dkato	0:f782d9c66c49	1713	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
dkato	0:f782d9c66c49	1714
dkato	0:f782d9c66c49	1715	reg_value = SCB->AIRCR; /* read old register configuration */
dkato	0:f782d9c66c49	1716	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
dkato	0:f782d9c66c49	1717	reg_value = (reg_value \|
dkato	0:f782d9c66c49	1718	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
dkato	0:f782d9c66c49	1719	(PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
dkato	0:f782d9c66c49	1720	SCB->AIRCR = reg_value;
dkato	0:f782d9c66c49	1721	}
dkato	0:f782d9c66c49	1722
dkato	0:f782d9c66c49	1723
dkato	0:f782d9c66c49	1724	/** \brief Get Priority Grouping
dkato	0:f782d9c66c49	1725
dkato	0:f782d9c66c49	1726	The function reads the priority grouping field from the NVIC Interrupt Controller.
dkato	0:f782d9c66c49	1727
dkato	0:f782d9c66c49	1728	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
dkato	0:f782d9c66c49	1729	*/
dkato	0:f782d9c66c49	1730	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
dkato	0:f782d9c66c49	1731	{
dkato	0:f782d9c66c49	1732	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
dkato	0:f782d9c66c49	1733	}
dkato	0:f782d9c66c49	1734
dkato	0:f782d9c66c49	1735
dkato	0:f782d9c66c49	1736	/** \brief Enable External Interrupt
dkato	0:f782d9c66c49	1737
dkato	0:f782d9c66c49	1738	The function enables a device-specific interrupt in the NVIC interrupt controller.
dkato	0:f782d9c66c49	1739
dkato	0:f782d9c66c49	1740	\param [in] IRQn External interrupt number. Value cannot be negative.
dkato	0:f782d9c66c49	1741	*/
dkato	0:f782d9c66c49	1742	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
dkato	0:f782d9c66c49	1743	{
dkato	0:f782d9c66c49	1744	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato	0:f782d9c66c49	1745	}
dkato	0:f782d9c66c49	1746
dkato	0:f782d9c66c49	1747
dkato	0:f782d9c66c49	1748	/** \brief Disable External Interrupt
dkato	0:f782d9c66c49	1749
dkato	0:f782d9c66c49	1750	The function disables a device-specific interrupt in the NVIC interrupt controller.
dkato	0:f782d9c66c49	1751
dkato	0:f782d9c66c49	1752	\param [in] IRQn External interrupt number. Value cannot be negative.
dkato	0:f782d9c66c49	1753	*/
dkato	0:f782d9c66c49	1754	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
dkato	0:f782d9c66c49	1755	{
dkato	0:f782d9c66c49	1756	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato	0:f782d9c66c49	1757	__DSB();
dkato	0:f782d9c66c49	1758	__ISB();
dkato	0:f782d9c66c49	1759	}
dkato	0:f782d9c66c49	1760
dkato	0:f782d9c66c49	1761
dkato	0:f782d9c66c49	1762	/** \brief Get Pending Interrupt
dkato	0:f782d9c66c49	1763
dkato	0:f782d9c66c49	1764	The function reads the pending register in the NVIC and returns the pending bit
dkato	0:f782d9c66c49	1765	for the specified interrupt.
dkato	0:f782d9c66c49	1766
dkato	0:f782d9c66c49	1767	\param [in] IRQn Interrupt number.
dkato	0:f782d9c66c49	1768
dkato	0:f782d9c66c49	1769	\return 0 Interrupt status is not pending.
dkato	0:f782d9c66c49	1770	\return 1 Interrupt status is pending.
dkato	0:f782d9c66c49	1771	*/
dkato	0:f782d9c66c49	1772	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
dkato	0:f782d9c66c49	1773	{
dkato	0:f782d9c66c49	1774	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
dkato	0:f782d9c66c49	1775	}
dkato	0:f782d9c66c49	1776
dkato	0:f782d9c66c49	1777
dkato	0:f782d9c66c49	1778	/** \brief Set Pending Interrupt
dkato	0:f782d9c66c49	1779
dkato	0:f782d9c66c49	1780	The function sets the pending bit of an external interrupt.
dkato	0:f782d9c66c49	1781
dkato	0:f782d9c66c49	1782	\param [in] IRQn Interrupt number. Value cannot be negative.
dkato	0:f782d9c66c49	1783	*/
dkato	0:f782d9c66c49	1784	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
dkato	0:f782d9c66c49	1785	{
dkato	0:f782d9c66c49	1786	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato	0:f782d9c66c49	1787	}
dkato	0:f782d9c66c49	1788
dkato	0:f782d9c66c49	1789
dkato	0:f782d9c66c49	1790	/** \brief Clear Pending Interrupt
dkato	0:f782d9c66c49	1791
dkato	0:f782d9c66c49	1792	The function clears the pending bit of an external interrupt.
dkato	0:f782d9c66c49	1793
dkato	0:f782d9c66c49	1794	\param [in] IRQn External interrupt number. Value cannot be negative.
dkato	0:f782d9c66c49	1795	*/
dkato	0:f782d9c66c49	1796	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
dkato	0:f782d9c66c49	1797	{
dkato	0:f782d9c66c49	1798	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
dkato	0:f782d9c66c49	1799	}
dkato	0:f782d9c66c49	1800
dkato	0:f782d9c66c49	1801
dkato	0:f782d9c66c49	1802	/** \brief Get Active Interrupt
dkato	0:f782d9c66c49	1803
dkato	0:f782d9c66c49	1804	The function reads the active register in NVIC and returns the active bit.
dkato	0:f782d9c66c49	1805
dkato	0:f782d9c66c49	1806	\param [in] IRQn Interrupt number.
dkato	0:f782d9c66c49	1807
dkato	0:f782d9c66c49	1808	\return 0 Interrupt status is not active.
dkato	0:f782d9c66c49	1809	\return 1 Interrupt status is active.
dkato	0:f782d9c66c49	1810	*/
dkato	0:f782d9c66c49	1811	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
dkato	0:f782d9c66c49	1812	{
dkato	0:f782d9c66c49	1813	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
dkato	0:f782d9c66c49	1814	}
dkato	0:f782d9c66c49	1815
dkato	0:f782d9c66c49	1816
dkato	0:f782d9c66c49	1817	/** \brief Set Interrupt Priority
dkato	0:f782d9c66c49	1818
dkato	0:f782d9c66c49	1819	The function sets the priority of an interrupt.
dkato	0:f782d9c66c49	1820
dkato	0:f782d9c66c49	1821	\note The priority cannot be set for every core interrupt.
dkato	0:f782d9c66c49	1822
dkato	0:f782d9c66c49	1823	\param [in] IRQn Interrupt number.
dkato	0:f782d9c66c49	1824	\param [in] priority Priority to set.
dkato	0:f782d9c66c49	1825	*/
dkato	0:f782d9c66c49	1826	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
dkato	0:f782d9c66c49	1827	{
dkato	0:f782d9c66c49	1828	if((int32_t)IRQn < 0) {
dkato	0:f782d9c66c49	1829	SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
dkato	0:f782d9c66c49	1830	}
dkato	0:f782d9c66c49	1831	else {
dkato	0:f782d9c66c49	1832	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
dkato	0:f782d9c66c49	1833	}
dkato	0:f782d9c66c49	1834	}
dkato	0:f782d9c66c49	1835
dkato	0:f782d9c66c49	1836
dkato	0:f782d9c66c49	1837	/** \brief Get Interrupt Priority
dkato	0:f782d9c66c49	1838
dkato	0:f782d9c66c49	1839	The function reads the priority of an interrupt. The interrupt
dkato	0:f782d9c66c49	1840	number can be positive to specify an external (device specific)
dkato	0:f782d9c66c49	1841	interrupt, or negative to specify an internal (core) interrupt.
dkato	0:f782d9c66c49	1842
dkato	0:f782d9c66c49	1843
dkato	0:f782d9c66c49	1844	\param [in] IRQn Interrupt number.
dkato	0:f782d9c66c49	1845	\return Interrupt Priority. Value is aligned automatically to the implemented
dkato	0:f782d9c66c49	1846	priority bits of the microcontroller.
dkato	0:f782d9c66c49	1847	*/
dkato	0:f782d9c66c49	1848	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
dkato	0:f782d9c66c49	1849	{
dkato	0:f782d9c66c49	1850
dkato	0:f782d9c66c49	1851	if((int32_t)IRQn < 0) {
dkato	0:f782d9c66c49	1852	return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
dkato	0:f782d9c66c49	1853	}
dkato	0:f782d9c66c49	1854	else {
dkato	0:f782d9c66c49	1855	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
dkato	0:f782d9c66c49	1856	}
dkato	0:f782d9c66c49	1857	}
dkato	0:f782d9c66c49	1858
dkato	0:f782d9c66c49	1859
dkato	0:f782d9c66c49	1860	/** \brief Encode Priority
dkato	0:f782d9c66c49	1861
dkato	0:f782d9c66c49	1862	The function encodes the priority for an interrupt with the given priority group,
dkato	0:f782d9c66c49	1863	preemptive priority value, and subpriority value.
dkato	0:f782d9c66c49	1864	In case of a conflict between priority grouping and available
dkato	0:f782d9c66c49	1865	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
dkato	0:f782d9c66c49	1866
dkato	0:f782d9c66c49	1867	\param [in] PriorityGroup Used priority group.
dkato	0:f782d9c66c49	1868	\param [in] PreemptPriority Preemptive priority value (starting from 0).
dkato	0:f782d9c66c49	1869	\param [in] SubPriority Subpriority value (starting from 0).
dkato	0:f782d9c66c49	1870	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
dkato	0:f782d9c66c49	1871	*/
dkato	0:f782d9c66c49	1872	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
dkato	0:f782d9c66c49	1873	{
dkato	0:f782d9c66c49	1874	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
dkato	0:f782d9c66c49	1875	uint32_t PreemptPriorityBits;
dkato	0:f782d9c66c49	1876	uint32_t SubPriorityBits;
dkato	0:f782d9c66c49	1877
dkato	0:f782d9c66c49	1878	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
dkato	0:f782d9c66c49	1879	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
dkato	0:f782d9c66c49	1880
dkato	0:f782d9c66c49	1881	return (
dkato	0:f782d9c66c49	1882	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
dkato	0:f782d9c66c49	1883	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
dkato	0:f782d9c66c49	1884	);
dkato	0:f782d9c66c49	1885	}
dkato	0:f782d9c66c49	1886
dkato	0:f782d9c66c49	1887
dkato	0:f782d9c66c49	1888	/** \brief Decode Priority
dkato	0:f782d9c66c49	1889
dkato	0:f782d9c66c49	1890	The function decodes an interrupt priority value with a given priority group to
dkato	0:f782d9c66c49	1891	preemptive priority value and subpriority value.
dkato	0:f782d9c66c49	1892	In case of a conflict between priority grouping and available
dkato	0:f782d9c66c49	1893	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
dkato	0:f782d9c66c49	1894
dkato	0:f782d9c66c49	1895	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
dkato	0:f782d9c66c49	1896	\param [in] PriorityGroup Used priority group.
dkato	0:f782d9c66c49	1897	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
dkato	0:f782d9c66c49	1898	\param [out] pSubPriority Subpriority value (starting from 0).
dkato	0:f782d9c66c49	1899	*/
dkato	0:f782d9c66c49	1900	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
dkato	0:f782d9c66c49	1901	{
dkato	0:f782d9c66c49	1902	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
dkato	0:f782d9c66c49	1903	uint32_t PreemptPriorityBits;
dkato	0:f782d9c66c49	1904	uint32_t SubPriorityBits;
dkato	0:f782d9c66c49	1905
dkato	0:f782d9c66c49	1906	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
dkato	0:f782d9c66c49	1907	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
dkato	0:f782d9c66c49	1908
dkato	0:f782d9c66c49	1909	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
dkato	0:f782d9c66c49	1910	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
dkato	0:f782d9c66c49	1911	}
dkato	0:f782d9c66c49	1912
dkato	0:f782d9c66c49	1913
dkato	0:f782d9c66c49	1914	/** \brief System Reset
dkato	0:f782d9c66c49	1915
dkato	0:f782d9c66c49	1916	The function initiates a system reset request to reset the MCU.
dkato	0:f782d9c66c49	1917	*/
dkato	0:f782d9c66c49	1918	__STATIC_INLINE void NVIC_SystemReset(void)
dkato	0:f782d9c66c49	1919	{
dkato	0:f782d9c66c49	1920	__DSB(); /* Ensure all outstanding memory accesses included
dkato	0:f782d9c66c49	1921	buffered write are completed before reset */
dkato	0:f782d9c66c49	1922	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
dkato	0:f782d9c66c49	1923	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
dkato	0:f782d9c66c49	1924	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
dkato	0:f782d9c66c49	1925	__DSB(); /* Ensure completion of memory access */
dkato	0:f782d9c66c49	1926	while(1) { __NOP(); } /* wait until reset */
dkato	0:f782d9c66c49	1927	}
dkato	0:f782d9c66c49	1928
dkato	0:f782d9c66c49	1929	/@} end of CMSIS_Core_NVICFunctions /
dkato	0:f782d9c66c49	1930
dkato	0:f782d9c66c49	1931
dkato	0:f782d9c66c49	1932	/* ########################## FPU functions #################################### */
dkato	0:f782d9c66c49	1933	/** \ingroup CMSIS_Core_FunctionInterface
dkato	0:f782d9c66c49	1934	\defgroup CMSIS_Core_FpuFunctions FPU Functions
dkato	0:f782d9c66c49	1935	\brief Function that provides FPU type.
dkato	0:f782d9c66c49	1936	@{
dkato	0:f782d9c66c49	1937	*/
dkato	0:f782d9c66c49	1938
dkato	0:f782d9c66c49	1939	/**
dkato	0:f782d9c66c49	1940	\fn uint32_t SCB_GetFPUType(void)
dkato	0:f782d9c66c49	1941	\brief get FPU type
dkato	0:f782d9c66c49	1942	\returns
dkato	0:f782d9c66c49	1943	- \b 0: No FPU
dkato	0:f782d9c66c49	1944	- \b 1: Single precision FPU
dkato	0:f782d9c66c49	1945	- \b 2: Double + Single precision FPU
dkato	0:f782d9c66c49	1946	*/
dkato	0:f782d9c66c49	1947	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
dkato	0:f782d9c66c49	1948	{
dkato	0:f782d9c66c49	1949	uint32_t mvfr0;
dkato	0:f782d9c66c49	1950
dkato	0:f782d9c66c49	1951	mvfr0 = SCB->MVFR0;
dkato	0:f782d9c66c49	1952	if ((mvfr0 & 0x00000FF0UL) == 0x220UL) {
dkato	0:f782d9c66c49	1953	return 2UL; // Double + Single precision FPU
dkato	0:f782d9c66c49	1954	} else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) {
dkato	0:f782d9c66c49	1955	return 1UL; // Single precision FPU
dkato	0:f782d9c66c49	1956	} else {
dkato	0:f782d9c66c49	1957	return 0UL; // No FPU
dkato	0:f782d9c66c49	1958	}
dkato	0:f782d9c66c49	1959	}
dkato	0:f782d9c66c49	1960
dkato	0:f782d9c66c49	1961
dkato	0:f782d9c66c49	1962	/@} end of CMSIS_Core_FpuFunctions /
dkato	0:f782d9c66c49	1963
dkato	0:f782d9c66c49	1964
dkato	0:f782d9c66c49	1965
dkato	0:f782d9c66c49	1966	/* ########################## Cache functions #################################### */
dkato	0:f782d9c66c49	1967	/** \ingroup CMSIS_Core_FunctionInterface
dkato	0:f782d9c66c49	1968	\defgroup CMSIS_Core_CacheFunctions Cache Functions
dkato	0:f782d9c66c49	1969	\brief Functions that configure Instruction and Data cache.
dkato	0:f782d9c66c49	1970	@{
dkato	0:f782d9c66c49	1971	*/
dkato	0:f782d9c66c49	1972
dkato	0:f782d9c66c49	1973	/* Cache Size ID Register Macros */
dkato	0:f782d9c66c49	1974	#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
dkato	0:f782d9c66c49	1975	#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
dkato	0:f782d9c66c49	1976	#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) />> SCB_CCSIDR_LINESIZE_Pos/ )
dkato	0:f782d9c66c49	1977
dkato	0:f782d9c66c49	1978
dkato	0:f782d9c66c49	1979	/** \brief Enable I-Cache
dkato	0:f782d9c66c49	1980
dkato	0:f782d9c66c49	1981	The function turns on I-Cache
dkato	0:f782d9c66c49	1982	*/
dkato	0:f782d9c66c49	1983	__STATIC_INLINE void SCB_EnableICache (void)
dkato	0:f782d9c66c49	1984	{
dkato	0:f782d9c66c49	1985	#if (__ICACHE_PRESENT == 1)
dkato	0:f782d9c66c49	1986	__DSB();
dkato	0:f782d9c66c49	1987	__ISB();
dkato	0:f782d9c66c49	1988	SCB->ICIALLU = 0UL; // invalidate I-Cache
dkato	0:f782d9c66c49	1989	SCB->CCR \|= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache
dkato	0:f782d9c66c49	1990	__DSB();
dkato	0:f782d9c66c49	1991	__ISB();
dkato	0:f782d9c66c49	1992	#endif
dkato	0:f782d9c66c49	1993	}
dkato	0:f782d9c66c49	1994
dkato	0:f782d9c66c49	1995
dkato	0:f782d9c66c49	1996	/** \brief Disable I-Cache
dkato	0:f782d9c66c49	1997
dkato	0:f782d9c66c49	1998	The function turns off I-Cache
dkato	0:f782d9c66c49	1999	*/
dkato	0:f782d9c66c49	2000	__STATIC_INLINE void SCB_DisableICache (void)
dkato	0:f782d9c66c49	2001	{
dkato	0:f782d9c66c49	2002	#if (__ICACHE_PRESENT == 1)
dkato	0:f782d9c66c49	2003	__DSB();
dkato	0:f782d9c66c49	2004	__ISB();
dkato	0:f782d9c66c49	2005	SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache
dkato	0:f782d9c66c49	2006	SCB->ICIALLU = 0UL; // invalidate I-Cache
dkato	0:f782d9c66c49	2007	__DSB();
dkato	0:f782d9c66c49	2008	__ISB();
dkato	0:f782d9c66c49	2009	#endif
dkato	0:f782d9c66c49	2010	}
dkato	0:f782d9c66c49	2011
dkato	0:f782d9c66c49	2012
dkato	0:f782d9c66c49	2013	/** \brief Invalidate I-Cache
dkato	0:f782d9c66c49	2014
dkato	0:f782d9c66c49	2015	The function invalidates I-Cache
dkato	0:f782d9c66c49	2016	*/
dkato	0:f782d9c66c49	2017	__STATIC_INLINE void SCB_InvalidateICache (void)
dkato	0:f782d9c66c49	2018	{
dkato	0:f782d9c66c49	2019	#if (__ICACHE_PRESENT == 1)
dkato	0:f782d9c66c49	2020	__DSB();
dkato	0:f782d9c66c49	2021	__ISB();
dkato	0:f782d9c66c49	2022	SCB->ICIALLU = 0UL;
dkato	0:f782d9c66c49	2023	__DSB();
dkato	0:f782d9c66c49	2024	__ISB();
dkato	0:f782d9c66c49	2025	#endif
dkato	0:f782d9c66c49	2026	}
dkato	0:f782d9c66c49	2027
dkato	0:f782d9c66c49	2028
dkato	0:f782d9c66c49	2029	/** \brief Enable D-Cache
dkato	0:f782d9c66c49	2030
dkato	0:f782d9c66c49	2031	The function turns on D-Cache
dkato	0:f782d9c66c49	2032	*/
dkato	0:f782d9c66c49	2033	__STATIC_INLINE void SCB_EnableDCache (void)
dkato	0:f782d9c66c49	2034	{
dkato	0:f782d9c66c49	2035	#if (__DCACHE_PRESENT == 1)
dkato	0:f782d9c66c49	2036	uint32_t ccsidr, sshift, wshift, sw;
dkato	0:f782d9c66c49	2037	uint32_t sets, ways;
dkato	0:f782d9c66c49	2038
dkato	0:f782d9c66c49	2039	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
dkato	0:f782d9c66c49	2040	ccsidr = SCB->CCSIDR;
dkato	0:f782d9c66c49	2041	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
dkato	0:f782d9c66c49	2042	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
dkato	0:f782d9c66c49	2043	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
dkato	0:f782d9c66c49	2044	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
dkato	0:f782d9c66c49	2045
dkato	0:f782d9c66c49	2046	__DSB();
dkato	0:f782d9c66c49	2047
dkato	0:f782d9c66c49	2048	do { // invalidate D-Cache
dkato	0:f782d9c66c49	2049	uint32_t tmpways = ways;
dkato	0:f782d9c66c49	2050	do {
dkato	0:f782d9c66c49	2051	sw = ((tmpways << wshift) \| (sets << sshift));
dkato	0:f782d9c66c49	2052	SCB->DCISW = sw;
dkato	0:f782d9c66c49	2053	} while(tmpways--);
dkato	0:f782d9c66c49	2054	} while(sets--);
dkato	0:f782d9c66c49	2055	__DSB();
dkato	0:f782d9c66c49	2056
dkato	0:f782d9c66c49	2057	SCB->CCR \|= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache
dkato	0:f782d9c66c49	2058
dkato	0:f782d9c66c49	2059	__DSB();
dkato	0:f782d9c66c49	2060	__ISB();
dkato	0:f782d9c66c49	2061	#endif
dkato	0:f782d9c66c49	2062	}
dkato	0:f782d9c66c49	2063
dkato	0:f782d9c66c49	2064
dkato	0:f782d9c66c49	2065	/** \brief Disable D-Cache
dkato	0:f782d9c66c49	2066
dkato	0:f782d9c66c49	2067	The function turns off D-Cache
dkato	0:f782d9c66c49	2068	*/
dkato	0:f782d9c66c49	2069	__STATIC_INLINE void SCB_DisableDCache (void)
dkato	0:f782d9c66c49	2070	{
dkato	0:f782d9c66c49	2071	#if (__DCACHE_PRESENT == 1)
dkato	0:f782d9c66c49	2072	uint32_t ccsidr, sshift, wshift, sw;
dkato	0:f782d9c66c49	2073	uint32_t sets, ways;
dkato	0:f782d9c66c49	2074
dkato	0:f782d9c66c49	2075	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
dkato	0:f782d9c66c49	2076	ccsidr = SCB->CCSIDR;
dkato	0:f782d9c66c49	2077	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
dkato	0:f782d9c66c49	2078	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
dkato	0:f782d9c66c49	2079	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
dkato	0:f782d9c66c49	2080	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
dkato	0:f782d9c66c49	2081
dkato	0:f782d9c66c49	2082	__DSB();
dkato	0:f782d9c66c49	2083
dkato	0:f782d9c66c49	2084	SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache
dkato	0:f782d9c66c49	2085
dkato	0:f782d9c66c49	2086	do { // clean & invalidate D-Cache
dkato	0:f782d9c66c49	2087	uint32_t tmpways = ways;
dkato	0:f782d9c66c49	2088	do {
dkato	0:f782d9c66c49	2089	sw = ((tmpways << wshift) \| (sets << sshift));
dkato	0:f782d9c66c49	2090	SCB->DCCISW = sw;
dkato	0:f782d9c66c49	2091	} while(tmpways--);
dkato	0:f782d9c66c49	2092	} while(sets--);
dkato	0:f782d9c66c49	2093
dkato	0:f782d9c66c49	2094
dkato	0:f782d9c66c49	2095	__DSB();
dkato	0:f782d9c66c49	2096	__ISB();
dkato	0:f782d9c66c49	2097	#endif
dkato	0:f782d9c66c49	2098	}
dkato	0:f782d9c66c49	2099
dkato	0:f782d9c66c49	2100
dkato	0:f782d9c66c49	2101	/** \brief Invalidate D-Cache
dkato	0:f782d9c66c49	2102
dkato	0:f782d9c66c49	2103	The function invalidates D-Cache
dkato	0:f782d9c66c49	2104	*/
dkato	0:f782d9c66c49	2105	__STATIC_INLINE void SCB_InvalidateDCache (void)
dkato	0:f782d9c66c49	2106	{
dkato	0:f782d9c66c49	2107	#if (__DCACHE_PRESENT == 1)
dkato	0:f782d9c66c49	2108	uint32_t ccsidr, sshift, wshift, sw;
dkato	0:f782d9c66c49	2109	uint32_t sets, ways;
dkato	0:f782d9c66c49	2110
dkato	0:f782d9c66c49	2111	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
dkato	0:f782d9c66c49	2112	ccsidr = SCB->CCSIDR;
dkato	0:f782d9c66c49	2113	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
dkato	0:f782d9c66c49	2114	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
dkato	0:f782d9c66c49	2115	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
dkato	0:f782d9c66c49	2116	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
dkato	0:f782d9c66c49	2117
dkato	0:f782d9c66c49	2118	__DSB();
dkato	0:f782d9c66c49	2119
dkato	0:f782d9c66c49	2120	do { // invalidate D-Cache
dkato	0:f782d9c66c49	2121	uint32_t tmpways = ways;
dkato	0:f782d9c66c49	2122	do {
dkato	0:f782d9c66c49	2123	sw = ((tmpways << wshift) \| (sets << sshift));
dkato	0:f782d9c66c49	2124	SCB->DCISW = sw;
dkato	0:f782d9c66c49	2125	} while(tmpways--);
dkato	0:f782d9c66c49	2126	} while(sets--);
dkato	0:f782d9c66c49	2127
dkato	0:f782d9c66c49	2128	__DSB();
dkato	0:f782d9c66c49	2129	__ISB();
dkato	0:f782d9c66c49	2130	#endif
dkato	0:f782d9c66c49	2131	}
dkato	0:f782d9c66c49	2132
dkato	0:f782d9c66c49	2133
dkato	0:f782d9c66c49	2134	/** \brief Clean D-Cache
dkato	0:f782d9c66c49	2135
dkato	0:f782d9c66c49	2136	The function cleans D-Cache
dkato	0:f782d9c66c49	2137	*/
dkato	0:f782d9c66c49	2138	__STATIC_INLINE void SCB_CleanDCache (void)
dkato	0:f782d9c66c49	2139	{
dkato	0:f782d9c66c49	2140	#if (__DCACHE_PRESENT == 1)
dkato	0:f782d9c66c49	2141	uint32_t ccsidr, sshift, wshift, sw;
dkato	0:f782d9c66c49	2142	uint32_t sets, ways;
dkato	0:f782d9c66c49	2143
dkato	0:f782d9c66c49	2144	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
dkato	0:f782d9c66c49	2145	ccsidr = SCB->CCSIDR;
dkato	0:f782d9c66c49	2146	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
dkato	0:f782d9c66c49	2147	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
dkato	0:f782d9c66c49	2148	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
dkato	0:f782d9c66c49	2149	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
dkato	0:f782d9c66c49	2150
dkato	0:f782d9c66c49	2151	__DSB();
dkato	0:f782d9c66c49	2152
dkato	0:f782d9c66c49	2153	do { // clean D-Cache
dkato	0:f782d9c66c49	2154	uint32_t tmpways = ways;
dkato	0:f782d9c66c49	2155	do {
dkato	0:f782d9c66c49	2156	sw = ((tmpways << wshift) \| (sets << sshift));
dkato	0:f782d9c66c49	2157	SCB->DCCSW = sw;
dkato	0:f782d9c66c49	2158	} while(tmpways--);
dkato	0:f782d9c66c49	2159	} while(sets--);
dkato	0:f782d9c66c49	2160
dkato	0:f782d9c66c49	2161	__DSB();
dkato	0:f782d9c66c49	2162	__ISB();
dkato	0:f782d9c66c49	2163	#endif
dkato	0:f782d9c66c49	2164	}
dkato	0:f782d9c66c49	2165
dkato	0:f782d9c66c49	2166
dkato	0:f782d9c66c49	2167	/** \brief Clean & Invalidate D-Cache
dkato	0:f782d9c66c49	2168
dkato	0:f782d9c66c49	2169	The function cleans and Invalidates D-Cache
dkato	0:f782d9c66c49	2170	*/
dkato	0:f782d9c66c49	2171	__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
dkato	0:f782d9c66c49	2172	{
dkato	0:f782d9c66c49	2173	#if (__DCACHE_PRESENT == 1)
dkato	0:f782d9c66c49	2174	uint32_t ccsidr, sshift, wshift, sw;
dkato	0:f782d9c66c49	2175	uint32_t sets, ways;
dkato	0:f782d9c66c49	2176
dkato	0:f782d9c66c49	2177	SCB->CSSELR = (0UL << 1) \| 0UL; // Level 1 data cache
dkato	0:f782d9c66c49	2178	ccsidr = SCB->CCSIDR;
dkato	0:f782d9c66c49	2179	sets = (uint32_t)(CCSIDR_SETS(ccsidr));
dkato	0:f782d9c66c49	2180	sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL);
dkato	0:f782d9c66c49	2181	ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
dkato	0:f782d9c66c49	2182	wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL);
dkato	0:f782d9c66c49	2183
dkato	0:f782d9c66c49	2184	__DSB();
dkato	0:f782d9c66c49	2185
dkato	0:f782d9c66c49	2186	do { // clean & invalidate D-Cache
dkato	0:f782d9c66c49	2187	uint32_t tmpways = ways;
dkato	0:f782d9c66c49	2188	do {
dkato	0:f782d9c66c49	2189	sw = ((tmpways << wshift) \| (sets << sshift));
dkato	0:f782d9c66c49	2190	SCB->DCCISW = sw;
dkato	0:f782d9c66c49	2191	} while(tmpways--);
dkato	0:f782d9c66c49	2192	} while(sets--);
dkato	0:f782d9c66c49	2193
dkato	0:f782d9c66c49	2194	__DSB();
dkato	0:f782d9c66c49	2195	__ISB();
dkato	0:f782d9c66c49	2196	#endif
dkato	0:f782d9c66c49	2197	}
dkato	0:f782d9c66c49	2198
dkato	0:f782d9c66c49	2199
dkato	0:f782d9c66c49	2200	/**
dkato	0:f782d9c66c49	2201	\fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
dkato	0:f782d9c66c49	2202	\brief D-Cache Invalidate by address
dkato	0:f782d9c66c49	2203	\param[in] addr address (aligned to 32-byte boundary)
dkato	0:f782d9c66c49	2204	\param[in] dsize size of memory block (in number of bytes)
dkato	0:f782d9c66c49	2205	*/
dkato	0:f782d9c66c49	2206	__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
dkato	0:f782d9c66c49	2207	{
dkato	0:f782d9c66c49	2208	#if (__DCACHE_PRESENT == 1)
dkato	0:f782d9c66c49	2209	int32_t op_size = dsize;
dkato	0:f782d9c66c49	2210	uint32_t op_addr = (uint32_t)addr;
dkato	0:f782d9c66c49	2211	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
dkato	0:f782d9c66c49	2212
dkato	0:f782d9c66c49	2213	__DSB();
dkato	0:f782d9c66c49	2214
dkato	0:f782d9c66c49	2215	while (op_size > 0) {
dkato	0:f782d9c66c49	2216	SCB->DCIMVAC = op_addr;
dkato	0:f782d9c66c49	2217	op_addr += linesize;
dkato	0:f782d9c66c49	2218	op_size -= (int32_t)linesize;
dkato	0:f782d9c66c49	2219	}
dkato	0:f782d9c66c49	2220
dkato	0:f782d9c66c49	2221	__DSB();
dkato	0:f782d9c66c49	2222	__ISB();
dkato	0:f782d9c66c49	2223	#endif
dkato	0:f782d9c66c49	2224	}
dkato	0:f782d9c66c49	2225
dkato	0:f782d9c66c49	2226
dkato	0:f782d9c66c49	2227	/**
dkato	0:f782d9c66c49	2228	\fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
dkato	0:f782d9c66c49	2229	\brief D-Cache Clean by address
dkato	0:f782d9c66c49	2230	\param[in] addr address (aligned to 32-byte boundary)
dkato	0:f782d9c66c49	2231	\param[in] dsize size of memory block (in number of bytes)
dkato	0:f782d9c66c49	2232	*/
dkato	0:f782d9c66c49	2233	__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
dkato	0:f782d9c66c49	2234	{
dkato	0:f782d9c66c49	2235	#if (__DCACHE_PRESENT == 1)
dkato	0:f782d9c66c49	2236	int32_t op_size = dsize;
dkato	0:f782d9c66c49	2237	uint32_t op_addr = (uint32_t) addr;
dkato	0:f782d9c66c49	2238	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
dkato	0:f782d9c66c49	2239
dkato	0:f782d9c66c49	2240	__DSB();
dkato	0:f782d9c66c49	2241
dkato	0:f782d9c66c49	2242	while (op_size > 0) {
dkato	0:f782d9c66c49	2243	SCB->DCCMVAC = op_addr;
dkato	0:f782d9c66c49	2244	op_addr += linesize;
dkato	0:f782d9c66c49	2245	op_size -= (int32_t)linesize;
dkato	0:f782d9c66c49	2246	}
dkato	0:f782d9c66c49	2247
dkato	0:f782d9c66c49	2248	__DSB();
dkato	0:f782d9c66c49	2249	__ISB();
dkato	0:f782d9c66c49	2250	#endif
dkato	0:f782d9c66c49	2251	}
dkato	0:f782d9c66c49	2252
dkato	0:f782d9c66c49	2253
dkato	0:f782d9c66c49	2254	/**
dkato	0:f782d9c66c49	2255	\fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize)
dkato	0:f782d9c66c49	2256	\brief D-Cache Clean and Invalidate by address
dkato	0:f782d9c66c49	2257	\param[in] addr address (aligned to 32-byte boundary)
dkato	0:f782d9c66c49	2258	\param[in] dsize size of memory block (in number of bytes)
dkato	0:f782d9c66c49	2259	*/
dkato	0:f782d9c66c49	2260	__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
dkato	0:f782d9c66c49	2261	{
dkato	0:f782d9c66c49	2262	#if (__DCACHE_PRESENT == 1)
dkato	0:f782d9c66c49	2263	int32_t op_size = dsize;
dkato	0:f782d9c66c49	2264	uint32_t op_addr = (uint32_t) addr;
dkato	0:f782d9c66c49	2265	uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes)
dkato	0:f782d9c66c49	2266
dkato	0:f782d9c66c49	2267	__DSB();
dkato	0:f782d9c66c49	2268
dkato	0:f782d9c66c49	2269	while (op_size > 0) {
dkato	0:f782d9c66c49	2270	SCB->DCCIMVAC = op_addr;
dkato	0:f782d9c66c49	2271	op_addr += linesize;
dkato	0:f782d9c66c49	2272	op_size -= (int32_t)linesize;
dkato	0:f782d9c66c49	2273	}
dkato	0:f782d9c66c49	2274
dkato	0:f782d9c66c49	2275	__DSB();
dkato	0:f782d9c66c49	2276	__ISB();
dkato	0:f782d9c66c49	2277	#endif
dkato	0:f782d9c66c49	2278	}
dkato	0:f782d9c66c49	2279
dkato	0:f782d9c66c49	2280
dkato	0:f782d9c66c49	2281	/@} end of CMSIS_Core_CacheFunctions /
dkato	0:f782d9c66c49	2282
dkato	0:f782d9c66c49	2283
dkato	0:f782d9c66c49	2284
dkato	0:f782d9c66c49	2285	/* ################################## SysTick function ############################################ */
dkato	0:f782d9c66c49	2286	/** \ingroup CMSIS_Core_FunctionInterface
dkato	0:f782d9c66c49	2287	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
dkato	0:f782d9c66c49	2288	\brief Functions that configure the System.
dkato	0:f782d9c66c49	2289	@{
dkato	0:f782d9c66c49	2290	*/
dkato	0:f782d9c66c49	2291
dkato	0:f782d9c66c49	2292	#if (__Vendor_SysTickConfig == 0)
dkato	0:f782d9c66c49	2293
dkato	0:f782d9c66c49	2294	/** \brief System Tick Configuration
dkato	0:f782d9c66c49	2295
dkato	0:f782d9c66c49	2296	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
dkato	0:f782d9c66c49	2297	Counter is in free running mode to generate periodic interrupts.
dkato	0:f782d9c66c49	2298
dkato	0:f782d9c66c49	2299	\param [in] ticks Number of ticks between two interrupts.
dkato	0:f782d9c66c49	2300
dkato	0:f782d9c66c49	2301	\return 0 Function succeeded.
dkato	0:f782d9c66c49	2302	\return 1 Function failed.
dkato	0:f782d9c66c49	2303
dkato	0:f782d9c66c49	2304	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
dkato	0:f782d9c66c49	2305	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
dkato	0:f782d9c66c49	2306	must contain a vendor-specific implementation of this function.
dkato	0:f782d9c66c49	2307
dkato	0:f782d9c66c49	2308	*/
dkato	0:f782d9c66c49	2309	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
dkato	0:f782d9c66c49	2310	{
dkato	0:f782d9c66c49	2311	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
dkato	0:f782d9c66c49	2312
dkato	0:f782d9c66c49	2313	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
dkato	0:f782d9c66c49	2314	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
dkato	0:f782d9c66c49	2315	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
dkato	0:f782d9c66c49	2316	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
dkato	0:f782d9c66c49	2317	SysTick_CTRL_TICKINT_Msk \|
dkato	0:f782d9c66c49	2318	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
dkato	0:f782d9c66c49	2319	return (0UL); /* Function successful */
dkato	0:f782d9c66c49	2320	}
dkato	0:f782d9c66c49	2321
dkato	0:f782d9c66c49	2322	#endif
dkato	0:f782d9c66c49	2323
dkato	0:f782d9c66c49	2324	/@} end of CMSIS_Core_SysTickFunctions /
dkato	0:f782d9c66c49	2325
dkato	0:f782d9c66c49	2326
dkato	0:f782d9c66c49	2327
dkato	0:f782d9c66c49	2328	/* ##################################### Debug In/Output function ########################################### */
dkato	0:f782d9c66c49	2329	/** \ingroup CMSIS_Core_FunctionInterface
dkato	0:f782d9c66c49	2330	\defgroup CMSIS_core_DebugFunctions ITM Functions
dkato	0:f782d9c66c49	2331	\brief Functions that access the ITM debug interface.
dkato	0:f782d9c66c49	2332	@{
dkato	0:f782d9c66c49	2333	*/
dkato	0:f782d9c66c49	2334
dkato	0:f782d9c66c49	2335	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
dkato	0:f782d9c66c49	2336	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
dkato	0:f782d9c66c49	2337
dkato	0:f782d9c66c49	2338
dkato	0:f782d9c66c49	2339	/** \brief ITM Send Character
dkato	0:f782d9c66c49	2340
dkato	0:f782d9c66c49	2341	The function transmits a character via the ITM channel 0, and
dkato	0:f782d9c66c49	2342	\li Just returns when no debugger is connected that has booked the output.
dkato	0:f782d9c66c49	2343	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
dkato	0:f782d9c66c49	2344
dkato	0:f782d9c66c49	2345	\param [in] ch Character to transmit.
dkato	0:f782d9c66c49	2346
dkato	0:f782d9c66c49	2347	\returns Character to transmit.
dkato	0:f782d9c66c49	2348	*/
dkato	0:f782d9c66c49	2349	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
dkato	0:f782d9c66c49	2350	{
dkato	0:f782d9c66c49	2351	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
dkato	0:f782d9c66c49	2352	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
dkato	0:f782d9c66c49	2353	{
dkato	0:f782d9c66c49	2354	while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
dkato	0:f782d9c66c49	2355	ITM->PORT[0].u8 = (uint8_t)ch;
dkato	0:f782d9c66c49	2356	}
dkato	0:f782d9c66c49	2357	return (ch);
dkato	0:f782d9c66c49	2358	}
dkato	0:f782d9c66c49	2359
dkato	0:f782d9c66c49	2360
dkato	0:f782d9c66c49	2361	/** \brief ITM Receive Character
dkato	0:f782d9c66c49	2362
dkato	0:f782d9c66c49	2363	The function inputs a character via the external variable \ref ITM_RxBuffer.
dkato	0:f782d9c66c49	2364
dkato	0:f782d9c66c49	2365	\return Received character.
dkato	0:f782d9c66c49	2366	\return -1 No character pending.
dkato	0:f782d9c66c49	2367	*/
dkato	0:f782d9c66c49	2368	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
dkato	0:f782d9c66c49	2369	int32_t ch = -1; /* no character available */
dkato	0:f782d9c66c49	2370
dkato	0:f782d9c66c49	2371	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
dkato	0:f782d9c66c49	2372	ch = ITM_RxBuffer;
dkato	0:f782d9c66c49	2373	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
dkato	0:f782d9c66c49	2374	}
dkato	0:f782d9c66c49	2375
dkato	0:f782d9c66c49	2376	return (ch);
dkato	0:f782d9c66c49	2377	}
dkato	0:f782d9c66c49	2378
dkato	0:f782d9c66c49	2379
dkato	0:f782d9c66c49	2380	/** \brief ITM Check Character
dkato	0:f782d9c66c49	2381
dkato	0:f782d9c66c49	2382	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
dkato	0:f782d9c66c49	2383
dkato	0:f782d9c66c49	2384	\return 0 No character available.
dkato	0:f782d9c66c49	2385	\return 1 Character available.
dkato	0:f782d9c66c49	2386	*/
dkato	0:f782d9c66c49	2387	__STATIC_INLINE int32_t ITM_CheckChar (void) {
dkato	0:f782d9c66c49	2388
dkato	0:f782d9c66c49	2389	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
dkato	0:f782d9c66c49	2390	return (0); /* no character available */
dkato	0:f782d9c66c49	2391	} else {
dkato	0:f782d9c66c49	2392	return (1); /* character available */
dkato	0:f782d9c66c49	2393	}
dkato	0:f782d9c66c49	2394	}
dkato	0:f782d9c66c49	2395
dkato	0:f782d9c66c49	2396	/@} end of CMSIS_core_DebugFunctions /
dkato	0:f782d9c66c49	2397
dkato	0:f782d9c66c49	2398
dkato	0:f782d9c66c49	2399
dkato	0:f782d9c66c49	2400
dkato	0:f782d9c66c49	2401	#ifdef __cplusplus
dkato	0:f782d9c66c49	2402	}
dkato	0:f782d9c66c49	2403	#endif
dkato	0:f782d9c66c49	2404
dkato	0:f782d9c66c49	2405	#endif /* __CORE_CM7_H_DEPENDANT */
dkato	0:f782d9c66c49	2406
dkato	0:f782d9c66c49	2407	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	02 Feb 2018
Imports:	83
Forks:	0
Commits:	1
Dependents:	10
Dependencies:	0
Followers:	4

cmsis/core_cm7.h@0:f782d9c66c49, 2018-02-02 (annotated)

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