Daiki Kato / mbed-dev_tmp

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targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/i2c/fsl_i2c_hal.h@108:af734d017ad0, 2016-04-26 (annotated)

Committer:
dkato
Date:
Tue Apr 26 02:02:58 2016 +0000
Revision:
108:af734d017ad0
Parent:
0:9b334a45a8ff 
bugfixs

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /*
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
bogdanm 0:9b334a45a8ff 3 * All rights reserved.
bogdanm 0:9b334a45a8ff 4 *
bogdanm 0:9b334a45a8ff 5 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 6 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * o Redistributions of source code must retain the above copyright notice, this list
bogdanm 0:9b334a45a8ff 9 * of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * o Redistributions in binary form must reproduce the above copyright notice, this
bogdanm 0:9b334a45a8ff 12 * list of conditions and the following disclaimer in the documentation and/or
bogdanm 0:9b334a45a8ff 13 * other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
bogdanm 0:9b334a45a8ff 16 * contributors may be used to endorse or promote products derived from this
bogdanm 0:9b334a45a8ff 17 * software without specific prior written permission.
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
bogdanm 0:9b334a45a8ff 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
bogdanm 0:9b334a45a8ff 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
bogdanm 0:9b334a45a8ff 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
bogdanm 0:9b334a45a8ff 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
bogdanm 0:9b334a45a8ff 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
bogdanm 0:9b334a45a8ff 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
bogdanm 0:9b334a45a8ff 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
bogdanm 0:9b334a45a8ff 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 29 */
bogdanm 0:9b334a45a8ff 30 #if !defined(__FSL_I2C_HAL_H__)
bogdanm 0:9b334a45a8ff 31 #define __FSL_I2C_HAL_H__
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 #include <assert.h>
bogdanm 0:9b334a45a8ff 34 #include <stdbool.h>
bogdanm 0:9b334a45a8ff 35 #include "fsl_i2c_features.h"
bogdanm 0:9b334a45a8ff 36 #include "fsl_device_registers.h"
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /*!
bogdanm 0:9b334a45a8ff 39 * @addtogroup i2c_hal
bogdanm 0:9b334a45a8ff 40 * @{
bogdanm 0:9b334a45a8ff 41 */
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /*******************************************************************************
bogdanm 0:9b334a45a8ff 44 * Definitions
bogdanm 0:9b334a45a8ff 45 ******************************************************************************/
bogdanm 0:9b334a45a8ff 46 /*! @brief I2C status return codes.*/
bogdanm 0:9b334a45a8ff 47 typedef enum _i2c_status {
bogdanm 0:9b334a45a8ff 48 kStatus_I2C_Success = 0x0U,
bogdanm 0:9b334a45a8ff 49 kStatus_I2C_OutOfRange = 0x1U,
bogdanm 0:9b334a45a8ff 50 kStatus_I2C_Fail = 0x2U,
bogdanm 0:9b334a45a8ff 51 kStatus_I2C_Busy = 0x3U, /*!< The master is already performing a transfer.*/
bogdanm 0:9b334a45a8ff 52 kStatus_I2C_Timeout = 0x4U, /*!< The transfer timed out.*/
bogdanm 0:9b334a45a8ff 53 kStatus_I2C_ReceivedNak = 0x5U, /*!< The slave device sent a NAK in response to a byte.*/
bogdanm 0:9b334a45a8ff 54 kStatus_I2C_SlaveTxUnderrun = 0x6U, /*!< I2C Slave TX Underrun error.*/
bogdanm 0:9b334a45a8ff 55 kStatus_I2C_SlaveRxOverrun = 0x7U, /*!< I2C Slave RX Overrun error.*/
bogdanm 0:9b334a45a8ff 56 kStatus_I2C_AribtrationLost = 0x8U, /*!< I2C Arbitration Lost error.*/
bogdanm 0:9b334a45a8ff 57 } i2c_status_t;
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /*! @brief I2C status flags. */
bogdanm 0:9b334a45a8ff 60 typedef enum _i2c_status_flag {
bogdanm 0:9b334a45a8ff 61 kI2CTransferComplete = BP_I2C_S_TCF,
bogdanm 0:9b334a45a8ff 62 kI2CAddressAsSlave = BP_I2C_S_IAAS,
bogdanm 0:9b334a45a8ff 63 kI2CBusBusy = BP_I2C_S_BUSY,
bogdanm 0:9b334a45a8ff 64 kI2CArbitrationLost = BP_I2C_S_ARBL,
bogdanm 0:9b334a45a8ff 65 kI2CAddressMatch = BP_I2C_S_RAM,
bogdanm 0:9b334a45a8ff 66 kI2CSlaveTransmit = BP_I2C_S_SRW,
bogdanm 0:9b334a45a8ff 67 kI2CInterruptPending = BP_I2C_S_IICIF,
bogdanm 0:9b334a45a8ff 68 kI2CReceivedNak = BP_I2C_S_RXAK
bogdanm 0:9b334a45a8ff 69 } i2c_status_flag_t;
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 /*! @brief Direction of master and slave transfers.*/
bogdanm 0:9b334a45a8ff 72 typedef enum _i2c_direction {
bogdanm 0:9b334a45a8ff 73 kI2CReceive = 0U, /*!< Master and slave receive.*/
bogdanm 0:9b334a45a8ff 74 kI2CSend = 1U /*!< Master and slave transmit.*/
bogdanm 0:9b334a45a8ff 75 } i2c_direction_t;
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 /*******************************************************************************
bogdanm 0:9b334a45a8ff 78 * API
bogdanm 0:9b334a45a8ff 79 ******************************************************************************/
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 #if defined(__cplusplus)
bogdanm 0:9b334a45a8ff 82 extern "C" {
bogdanm 0:9b334a45a8ff 83 #endif
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 /*!
bogdanm 0:9b334a45a8ff 86 * @name Module controls
bogdanm 0:9b334a45a8ff 87 * @{
bogdanm 0:9b334a45a8ff 88 */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /*!
bogdanm 0:9b334a45a8ff 91 * @brief Restores the I2C peripheral to reset state.
bogdanm 0:9b334a45a8ff 92 *
bogdanm 0:9b334a45a8ff 93 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 94 */
bogdanm 0:9b334a45a8ff 95 void I2C_HAL_Init(uint32_t baseAddr);
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /*!
bogdanm 0:9b334a45a8ff 98 * @brief Enables the I2C module operation.
bogdanm 0:9b334a45a8ff 99 *
bogdanm 0:9b334a45a8ff 100 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 101 */
bogdanm 0:9b334a45a8ff 102 static inline void I2C_HAL_Enable(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 103 {
bogdanm 0:9b334a45a8ff 104 BW_I2C_C1_IICEN(baseAddr, 0x1U);
bogdanm 0:9b334a45a8ff 105 }
bogdanm 0:9b334a45a8ff 106
bogdanm 0:9b334a45a8ff 107 /*!
bogdanm 0:9b334a45a8ff 108 * @brief Disables the I2C module operation.
bogdanm 0:9b334a45a8ff 109 *
bogdanm 0:9b334a45a8ff 110 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 111 */
bogdanm 0:9b334a45a8ff 112 static inline void I2C_HAL_Disable(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 113 {
bogdanm 0:9b334a45a8ff 114 BW_I2C_C1_IICEN(baseAddr, 0x0U);
bogdanm 0:9b334a45a8ff 115 }
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /*@}*/
bogdanm 0:9b334a45a8ff 118
bogdanm 0:9b334a45a8ff 119 /*!
bogdanm 0:9b334a45a8ff 120 * @name DMA
bogdanm 0:9b334a45a8ff 121 * @{
bogdanm 0:9b334a45a8ff 122 */
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 /*!
bogdanm 0:9b334a45a8ff 125 * @brief Enables or disables the DMA support.
bogdanm 0:9b334a45a8ff 126 *
bogdanm 0:9b334a45a8ff 127 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 128 * @param enable Pass true to enable DMA transfer signalling
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130 static inline void I2C_HAL_SetDmaCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 131 {
bogdanm 0:9b334a45a8ff 132 BW_I2C_C1_DMAEN(baseAddr, (uint8_t)enable);
bogdanm 0:9b334a45a8ff 133 }
bogdanm 0:9b334a45a8ff 134
bogdanm 0:9b334a45a8ff 135 /*!
bogdanm 0:9b334a45a8ff 136 * @brief Returns whether I2C DMA support is enabled.
bogdanm 0:9b334a45a8ff 137 *
bogdanm 0:9b334a45a8ff 138 * @param baseAddr The I2C peripheral base address.
bogdanm 0:9b334a45a8ff 139 * @retval true I2C DMA is enabled.
bogdanm 0:9b334a45a8ff 140 * @retval false I2C DMA is disabled.
bogdanm 0:9b334a45a8ff 141 */
bogdanm 0:9b334a45a8ff 142 static inline bool I2C_HAL_GetDmaCmd(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 143 {
bogdanm 0:9b334a45a8ff 144 return BR_I2C_C1_DMAEN(baseAddr);
bogdanm 0:9b334a45a8ff 145 }
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147 /*@}*/
bogdanm 0:9b334a45a8ff 148
bogdanm 0:9b334a45a8ff 149 /*!
bogdanm 0:9b334a45a8ff 150 * @name Pin functions
bogdanm 0:9b334a45a8ff 151 * @{
bogdanm 0:9b334a45a8ff 152 */
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 /*!
bogdanm 0:9b334a45a8ff 155 * @brief Controls the drive capability of the I2C pads.
bogdanm 0:9b334a45a8ff 156 *
bogdanm 0:9b334a45a8ff 157 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 158 * @param enable Passing true will enable high drive mode of the I2C pads. False sets normal
bogdanm 0:9b334a45a8ff 159 * drive mode.
bogdanm 0:9b334a45a8ff 160 */
bogdanm 0:9b334a45a8ff 161 static inline void I2C_HAL_SetHighDriveCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 162 {
bogdanm 0:9b334a45a8ff 163 BW_I2C_C2_HDRS(baseAddr, (uint8_t)enable);
bogdanm 0:9b334a45a8ff 164 }
bogdanm 0:9b334a45a8ff 165
bogdanm 0:9b334a45a8ff 166 /*!
bogdanm 0:9b334a45a8ff 167 * @brief Controls the width of the programmable glitch filter.
bogdanm 0:9b334a45a8ff 168 *
bogdanm 0:9b334a45a8ff 169 * Controls the width of the glitch, in terms of bus clock cycles, that the filter must absorb.
bogdanm 0:9b334a45a8ff 170 * The filter does not allow any glitch whose size is less than or equal to this width setting,
bogdanm 0:9b334a45a8ff 171 * to pass.
bogdanm 0:9b334a45a8ff 172 *
bogdanm 0:9b334a45a8ff 173 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 174 * @param glitchWidth Maximum width in bus clock cycles of the glitches that is filtered.
bogdanm 0:9b334a45a8ff 175 * Pass zero to disable the glitch filter.
bogdanm 0:9b334a45a8ff 176 */
bogdanm 0:9b334a45a8ff 177 static inline void I2C_HAL_SetGlitchWidth(uint32_t baseAddr, uint8_t glitchWidth)
bogdanm 0:9b334a45a8ff 178 {
bogdanm 0:9b334a45a8ff 179 BW_I2C_FLT_FLT(baseAddr, glitchWidth);
bogdanm 0:9b334a45a8ff 180 }
bogdanm 0:9b334a45a8ff 181
bogdanm 0:9b334a45a8ff 182 /*@}*/
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /*!
bogdanm 0:9b334a45a8ff 185 * @name Low power
bogdanm 0:9b334a45a8ff 186 * @{
bogdanm 0:9b334a45a8ff 187 */
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /*!
bogdanm 0:9b334a45a8ff 190 * @brief Controls the I2C wakeup enable.
bogdanm 0:9b334a45a8ff 191 *
bogdanm 0:9b334a45a8ff 192 * The I2C module can wake the MCU from low power mode with no peripheral bus running when
bogdanm 0:9b334a45a8ff 193 * slave address matching occurs.
bogdanm 0:9b334a45a8ff 194 *
bogdanm 0:9b334a45a8ff 195 * @param baseAddr The I2C peripheral base address.
bogdanm 0:9b334a45a8ff 196 * @param enable true - Enables the wakeup function in low power mode.<br>
bogdanm 0:9b334a45a8ff 197 * false - Normal operation. No interrupt is generated when address matching in
bogdanm 0:9b334a45a8ff 198 * low power mode.
bogdanm 0:9b334a45a8ff 199 */
bogdanm 0:9b334a45a8ff 200 static inline void I2C_HAL_SetWakeupCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 201 {
bogdanm 0:9b334a45a8ff 202 BW_I2C_C1_WUEN(baseAddr, (uint8_t)enable);
bogdanm 0:9b334a45a8ff 203 }
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 #if FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF
bogdanm 0:9b334a45a8ff 206 /*!
bogdanm 0:9b334a45a8ff 207 * @brief Controls the stop mode hold off.
bogdanm 0:9b334a45a8ff 208 *
bogdanm 0:9b334a45a8ff 209 * This function lets you enable the hold off entry to low power stop mode when any data transmission
bogdanm 0:9b334a45a8ff 210 * or reception is occurring.
bogdanm 0:9b334a45a8ff 211 *
bogdanm 0:9b334a45a8ff 212 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 213 * @param enable false - Stop hold off is disabled. The MCU's entry to stop mode is not gated.<br>
bogdanm 0:9b334a45a8ff 214 * true - Stop hold off is enabled.
bogdanm 0:9b334a45a8ff 215 */
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 static inline void I2C_HAL_SetStopHoldoffCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 218 {
bogdanm 0:9b334a45a8ff 219 BW_I2C_FLT_SHEN(baseAddr, (uint8_t)enable);
bogdanm 0:9b334a45a8ff 220 }
bogdanm 0:9b334a45a8ff 221 #endif /* FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF*/
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 /*@}*/
bogdanm 0:9b334a45a8ff 224
bogdanm 0:9b334a45a8ff 225 /*!
bogdanm 0:9b334a45a8ff 226 * @name Baud rate
bogdanm 0:9b334a45a8ff 227 * @{
bogdanm 0:9b334a45a8ff 228 */
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /*!
bogdanm 0:9b334a45a8ff 231 * @brief Sets the I2C bus frequency for master transactions.
bogdanm 0:9b334a45a8ff 232 *
bogdanm 0:9b334a45a8ff 233 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 234 * @param sourceClockInHz I2C source input clock in Hertz
bogdanm 0:9b334a45a8ff 235 * @param kbps Requested bus frequency in kilohertz. Common values are either 100 or 400.
bogdanm 0:9b334a45a8ff 236 * @param absoluteError_Hz If this parameter is not NULL, it is filled in with the
bogdanm 0:9b334a45a8ff 237 * difference in Hertz between the requested bus frequency and the closest frequency
bogdanm 0:9b334a45a8ff 238 * possible given available divider values.
bogdanm 0:9b334a45a8ff 239 *
bogdanm 0:9b334a45a8ff 240 * @retval kStatus_Success The baud rate was changed successfully. However, there is no
bogdanm 0:9b334a45a8ff 241 * guarantee on the minimum error. If you want to ensure that the baud was set to within
bogdanm 0:9b334a45a8ff 242 * a certain error, then use the @a absoluteError_Hz parameter.
bogdanm 0:9b334a45a8ff 243 * @retval kStatus_OutOfRange The requested baud rate was not within the range of rates
bogdanm 0:9b334a45a8ff 244 * supported by the peripheral.
bogdanm 0:9b334a45a8ff 245 */
bogdanm 0:9b334a45a8ff 246 i2c_status_t I2C_HAL_SetBaudRate(uint32_t baseAddr, uint32_t sourceClockInHz, uint32_t kbps,
bogdanm 0:9b334a45a8ff 247 uint32_t * absoluteError_Hz);
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /*!
bogdanm 0:9b334a45a8ff 250 * @brief Sets the I2C baud rate multiplier and table entry.
bogdanm 0:9b334a45a8ff 251 *
bogdanm 0:9b334a45a8ff 252 * Use this function to set the I2C bus frequency register values directly, if they are
bogdanm 0:9b334a45a8ff 253 * known in advance.
bogdanm 0:9b334a45a8ff 254 *
bogdanm 0:9b334a45a8ff 255 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 256 * @param mult Value of the MULT bitfield, ranging from 0-2.
bogdanm 0:9b334a45a8ff 257 * @param icr The ICR bitfield value, which is the index into an internal table in the I2C
bogdanm 0:9b334a45a8ff 258 * hardware that selects the baud rate divisor and SCL hold time.
bogdanm 0:9b334a45a8ff 259 */
bogdanm 0:9b334a45a8ff 260 static inline void I2C_HAL_SetFreqDiv(uint32_t baseAddr, uint8_t mult, uint8_t icr)
bogdanm 0:9b334a45a8ff 261 {
bogdanm 0:9b334a45a8ff 262 HW_I2C_F_WR(baseAddr, BF_I2C_F_MULT(mult) | BF_I2C_F_ICR(icr));
bogdanm 0:9b334a45a8ff 263 }
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 /*!
bogdanm 0:9b334a45a8ff 266 * @brief Slave baud rate control
bogdanm 0:9b334a45a8ff 267 *
bogdanm 0:9b334a45a8ff 268 * Enables an independent slave mode baud rate at the maximum frequency. This forces clock stretching
bogdanm 0:9b334a45a8ff 269 * on the SCL in very fast I2C modes.
bogdanm 0:9b334a45a8ff 270 *
bogdanm 0:9b334a45a8ff 271 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 272 * @param enable true - Slave baud rate is independent of the master baud rate;<br>
bogdanm 0:9b334a45a8ff 273 * false - The slave baud rate follows the master baud rate and clock stretching may occur.
bogdanm 0:9b334a45a8ff 274 */
bogdanm 0:9b334a45a8ff 275 static inline void I2C_HAL_SetSlaveBaudCtrlCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 276 {
bogdanm 0:9b334a45a8ff 277 BW_I2C_C2_SBRC(baseAddr, (uint8_t)enable);
bogdanm 0:9b334a45a8ff 278 }
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /*@}*/
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 /*!
bogdanm 0:9b334a45a8ff 283 * @name Bus operations
bogdanm 0:9b334a45a8ff 284 * @{
bogdanm 0:9b334a45a8ff 285 */
bogdanm 0:9b334a45a8ff 286
bogdanm 0:9b334a45a8ff 287 /*!
bogdanm 0:9b334a45a8ff 288 * @brief Sends a START or a Repeated START signal on the I2C bus.
bogdanm 0:9b334a45a8ff 289 *
bogdanm 0:9b334a45a8ff 290 * This function is used to initiate a new master mode transfer by sending the START signal. It
bogdanm 0:9b334a45a8ff 291 * is also used to send a Repeated START signal when a transfer is already in progress.
bogdanm 0:9b334a45a8ff 292 *
bogdanm 0:9b334a45a8ff 293 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 294 */
bogdanm 0:9b334a45a8ff 295 void I2C_HAL_SendStart(uint32_t baseAddr);
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /*!
bogdanm 0:9b334a45a8ff 298 * @brief Sends a STOP signal on the I2C bus.
bogdanm 0:9b334a45a8ff 299 *
bogdanm 0:9b334a45a8ff 300 * This function changes the direction to receive.
bogdanm 0:9b334a45a8ff 301 *
bogdanm 0:9b334a45a8ff 302 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 303 */
bogdanm 0:9b334a45a8ff 304 static inline void I2C_HAL_SendStop(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 305 {
bogdanm 0:9b334a45a8ff 306 assert(BR_I2C_C1_MST(baseAddr) == 1);
bogdanm 0:9b334a45a8ff 307 HW_I2C_C1_CLR(baseAddr, BM_I2C_C1_MST | BM_I2C_C1_TX);
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309
bogdanm 0:9b334a45a8ff 310 /*!
bogdanm 0:9b334a45a8ff 311 * @brief Causes an ACK to be sent on the bus.
bogdanm 0:9b334a45a8ff 312 *
bogdanm 0:9b334a45a8ff 313 * This function specifies that an ACK signal is sent in response to the next received byte.
bogdanm 0:9b334a45a8ff 314 *
bogdanm 0:9b334a45a8ff 315 * Note that the behavior of this function is changed when the I2C peripheral is placed in
bogdanm 0:9b334a45a8ff 316 * Fast ACK mode. In this case, this function causes an ACK signal to be sent in
bogdanm 0:9b334a45a8ff 317 * response to the current byte, rather than the next received byte.
bogdanm 0:9b334a45a8ff 318 *
bogdanm 0:9b334a45a8ff 319 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 320 */
bogdanm 0:9b334a45a8ff 321 static inline void I2C_HAL_SendAck(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 322 {
bogdanm 0:9b334a45a8ff 323 BW_I2C_C1_TXAK(baseAddr, 0x0U);
bogdanm 0:9b334a45a8ff 324 }
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 /*!
bogdanm 0:9b334a45a8ff 327 * @brief Causes a NAK to be sent on the bus.
bogdanm 0:9b334a45a8ff 328 *
bogdanm 0:9b334a45a8ff 329 * This function specifies that a NAK signal is sent in response to the next received byte.
bogdanm 0:9b334a45a8ff 330 *
bogdanm 0:9b334a45a8ff 331 * Note that the behavior of this function is changed when the I2C peripheral is placed in the
bogdanm 0:9b334a45a8ff 332 * Fast ACK mode. In this case, this function causes an NAK signal to be sent in
bogdanm 0:9b334a45a8ff 333 * response to the current byte, rather than the next received byte.
bogdanm 0:9b334a45a8ff 334 *
bogdanm 0:9b334a45a8ff 335 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 336 */
bogdanm 0:9b334a45a8ff 337 static inline void I2C_HAL_SendNak(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 338 {
bogdanm 0:9b334a45a8ff 339 BW_I2C_C1_TXAK(baseAddr, 0x1U);
bogdanm 0:9b334a45a8ff 340 }
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 /*!
bogdanm 0:9b334a45a8ff 343 * @brief Selects either transmit or receive mode.
bogdanm 0:9b334a45a8ff 344 *
bogdanm 0:9b334a45a8ff 345 * @param baseAddr The I2C peripheral base address.
bogdanm 0:9b334a45a8ff 346 * @param direction Specifies either transmit mode or receive mode. The valid values are:
bogdanm 0:9b334a45a8ff 347 * - #kI2CTransmit
bogdanm 0:9b334a45a8ff 348 * - #kI2CReceive
bogdanm 0:9b334a45a8ff 349 */
bogdanm 0:9b334a45a8ff 350 static inline void I2C_HAL_SetDirMode(uint32_t baseAddr, i2c_direction_t direction)
bogdanm 0:9b334a45a8ff 351 {
bogdanm 0:9b334a45a8ff 352 BW_I2C_C1_TX(baseAddr, (uint8_t)direction);
bogdanm 0:9b334a45a8ff 353 }
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /*!
bogdanm 0:9b334a45a8ff 356 * @brief Returns the currently selected transmit or receive mode.
bogdanm 0:9b334a45a8ff 357 *
bogdanm 0:9b334a45a8ff 358 * @param baseAddr The I2C peripheral base address.
bogdanm 0:9b334a45a8ff 359 * @retval #kI2CTransmit I2C is configured for master or slave transmit mode.
bogdanm 0:9b334a45a8ff 360 * @retval #kI2CReceive I2C is configured for master or slave receive mode.
bogdanm 0:9b334a45a8ff 361 */
bogdanm 0:9b334a45a8ff 362 static inline i2c_direction_t I2C_HAL_GetDirMode(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 363 {
bogdanm 0:9b334a45a8ff 364 return (i2c_direction_t)BR_I2C_C1_TX(baseAddr);
bogdanm 0:9b334a45a8ff 365 }
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 /*@}*/
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 /*!
bogdanm 0:9b334a45a8ff 370 * @name Data transfer
bogdanm 0:9b334a45a8ff 371 * @{
bogdanm 0:9b334a45a8ff 372 */
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 /*!
bogdanm 0:9b334a45a8ff 375 * @brief Returns the last byte of data read from the bus and initiate another read.
bogdanm 0:9b334a45a8ff 376 *
bogdanm 0:9b334a45a8ff 377 * In a master receive mode, calling this function initiates receiving the next byte of data.
bogdanm 0:9b334a45a8ff 378 *
bogdanm 0:9b334a45a8ff 379 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 380 * @return This function returns the last byte received while the I2C module is configured in master
bogdanm 0:9b334a45a8ff 381 * receive or slave receive mode.
bogdanm 0:9b334a45a8ff 382 */
bogdanm 0:9b334a45a8ff 383 static inline uint8_t I2C_HAL_ReadByte(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 384 {
bogdanm 0:9b334a45a8ff 385 return HW_I2C_D_RD(baseAddr);
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /*!
bogdanm 0:9b334a45a8ff 389 * @brief Writes one byte of data to the I2C bus.
bogdanm 0:9b334a45a8ff 390 *
bogdanm 0:9b334a45a8ff 391 * When this function is called in the master transmit mode, a data transfer is initiated. In slave
bogdanm 0:9b334a45a8ff 392 * mode, the same function is available after an address match occurs.
bogdanm 0:9b334a45a8ff 393 *
bogdanm 0:9b334a45a8ff 394 * In a master transmit mode, the first byte of data written following the start bit or repeated
bogdanm 0:9b334a45a8ff 395 * start bit is used for the address transfer and must consist of the slave address (in bits 7-1)
bogdanm 0:9b334a45a8ff 396 * concatenated with the required R/\#W bit (in position bit 0).
bogdanm 0:9b334a45a8ff 397 *
bogdanm 0:9b334a45a8ff 398 * @param baseAddr The I2C peripheral base address.
bogdanm 0:9b334a45a8ff 399 * @param byte The byte of data to transmit.
bogdanm 0:9b334a45a8ff 400 */
bogdanm 0:9b334a45a8ff 401 static inline void I2C_HAL_WriteByte(uint32_t baseAddr, uint8_t byte)
bogdanm 0:9b334a45a8ff 402 {
bogdanm 0:9b334a45a8ff 403 HW_I2C_D_WR(baseAddr, byte);
bogdanm 0:9b334a45a8ff 404 }
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 /*@}*/
bogdanm 0:9b334a45a8ff 407
bogdanm 0:9b334a45a8ff 408 /*!
bogdanm 0:9b334a45a8ff 409 * @name Slave address
bogdanm 0:9b334a45a8ff 410 * @{
bogdanm 0:9b334a45a8ff 411 */
bogdanm 0:9b334a45a8ff 412
bogdanm 0:9b334a45a8ff 413 /*!
bogdanm 0:9b334a45a8ff 414 * @brief Sets the primary 7-bit slave address.
bogdanm 0:9b334a45a8ff 415 *
bogdanm 0:9b334a45a8ff 416 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 417 * @param address The slave address in the upper 7 bits. Bit 0 of this value must be 0.
bogdanm 0:9b334a45a8ff 418 */
bogdanm 0:9b334a45a8ff 419 void I2C_HAL_SetAddress7bit(uint32_t baseAddr, uint8_t address);
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 /*!
bogdanm 0:9b334a45a8ff 422 * @brief Sets the primary slave address and enables 10-bit address mode.
bogdanm 0:9b334a45a8ff 423 *
bogdanm 0:9b334a45a8ff 424 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 425 * @param address The 10-bit slave address, in bits [10:1] of the value. Bit 0 must be 0.
bogdanm 0:9b334a45a8ff 426 */
bogdanm 0:9b334a45a8ff 427 void I2C_HAL_SetAddress10bit(uint32_t baseAddr, uint16_t address);
bogdanm 0:9b334a45a8ff 428
bogdanm 0:9b334a45a8ff 429 /*!
bogdanm 0:9b334a45a8ff 430 * @brief Enables or disables the extension address (10-bit).
bogdanm 0:9b334a45a8ff 431 *
bogdanm 0:9b334a45a8ff 432 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 433 * @param enable true: 10-bit address is enabled.
bogdanm 0:9b334a45a8ff 434 * false: 10-bit address is not enabled.
bogdanm 0:9b334a45a8ff 435 */
bogdanm 0:9b334a45a8ff 436 static inline void I2C_HAL_SetExtensionAddrCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 437 {
bogdanm 0:9b334a45a8ff 438 BW_I2C_C2_ADEXT(baseAddr, (uint8_t)enable);
bogdanm 0:9b334a45a8ff 439 }
bogdanm 0:9b334a45a8ff 440
bogdanm 0:9b334a45a8ff 441 /*!
bogdanm 0:9b334a45a8ff 442 * @brief Returns whether the extension address is enabled or not.
bogdanm 0:9b334a45a8ff 443 *
bogdanm 0:9b334a45a8ff 444 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 445 * @return true: 10-bit address is enabled.
bogdanm 0:9b334a45a8ff 446 * false: 10-bit address is not enabled.
bogdanm 0:9b334a45a8ff 447 */
bogdanm 0:9b334a45a8ff 448 static inline bool I2C_HAL_GetExtensionAddrCmd(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 449 {
bogdanm 0:9b334a45a8ff 450 return BR_I2C_C2_ADEXT(baseAddr);
bogdanm 0:9b334a45a8ff 451 }
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /*!
bogdanm 0:9b334a45a8ff 454 * @brief Controls whether the general call address is recognized.
bogdanm 0:9b334a45a8ff 455 *
bogdanm 0:9b334a45a8ff 456 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 457 * @param enable Whether to enable the general call address.
bogdanm 0:9b334a45a8ff 458 */
bogdanm 0:9b334a45a8ff 459 static inline void I2C_HAL_SetGeneralCallCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 460 {
bogdanm 0:9b334a45a8ff 461 BW_I2C_C2_GCAEN(baseAddr, (uint8_t)enable);
bogdanm 0:9b334a45a8ff 462 }
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 /*!
bogdanm 0:9b334a45a8ff 465 * @brief Enables or disables the slave address range matching.
bogdanm 0:9b334a45a8ff 466 *
bogdanm 0:9b334a45a8ff 467 * @param baseAddr The I2C peripheral base address.
bogdanm 0:9b334a45a8ff 468 * @param enable Pass true to enable range address matching. You must also call
bogdanm 0:9b334a45a8ff 469 * I2C_HAL_SetUpperAddress7bit() to set the upper address.
bogdanm 0:9b334a45a8ff 470 */
bogdanm 0:9b334a45a8ff 471 static inline void I2C_HAL_SetRangeMatchCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 472 {
bogdanm 0:9b334a45a8ff 473 BW_I2C_C2_RMEN(baseAddr, (uint8_t)enable);
bogdanm 0:9b334a45a8ff 474 }
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 /*!
bogdanm 0:9b334a45a8ff 477 * @brief Sets the upper slave address.
bogdanm 0:9b334a45a8ff 478 *
bogdanm 0:9b334a45a8ff 479 * This slave address is used as a secondary slave address. If range address
bogdanm 0:9b334a45a8ff 480 * matching is enabled, this slave address acts as the upper bound on the slave address
bogdanm 0:9b334a45a8ff 481 * range.
bogdanm 0:9b334a45a8ff 482 *
bogdanm 0:9b334a45a8ff 483 * This function sets only a 7-bit slave address. If 10-bit addressing was enabled by calling
bogdanm 0:9b334a45a8ff 484 * I2C_HAL_SetAddress10bit(), then the top 3 bits set with that function are also used
bogdanm 0:9b334a45a8ff 485 * with the address set with this function to form a 10-bit address.
bogdanm 0:9b334a45a8ff 486 *
bogdanm 0:9b334a45a8ff 487 * Passing 0 for the @a address parameter disables matching the upper slave address.
bogdanm 0:9b334a45a8ff 488 *
bogdanm 0:9b334a45a8ff 489 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 490 * @param address The upper slave address in the upper 7 bits. Bit 0 of this value must be 0.
bogdanm 0:9b334a45a8ff 491 * In addition, this address must be greater than the primary slave address that is set by
bogdanm 0:9b334a45a8ff 492 * calling I2C_HAL_SetAddress7bit().
bogdanm 0:9b334a45a8ff 493 */
bogdanm 0:9b334a45a8ff 494 static inline void I2C_HAL_SetUpperAddress7bit(uint32_t baseAddr, uint8_t address)
bogdanm 0:9b334a45a8ff 495 {
bogdanm 0:9b334a45a8ff 496 assert((address & 1) == 0);
bogdanm 0:9b334a45a8ff 497 assert((address == 0) || (address > HW_I2C_A1_RD(baseAddr)));
bogdanm 0:9b334a45a8ff 498 HW_I2C_RA_WR(baseAddr, address);
bogdanm 0:9b334a45a8ff 499 }
bogdanm 0:9b334a45a8ff 500
bogdanm 0:9b334a45a8ff 501 /*@}*/
bogdanm 0:9b334a45a8ff 502
bogdanm 0:9b334a45a8ff 503 /*!
bogdanm 0:9b334a45a8ff 504 * @name Status
bogdanm 0:9b334a45a8ff 505 * @{
bogdanm 0:9b334a45a8ff 506 */
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /*!
bogdanm 0:9b334a45a8ff 509 * @brief Gets the I2C status flag state.
bogdanm 0:9b334a45a8ff 510 *
bogdanm 0:9b334a45a8ff 511 * @param baseAddr The I2C peripheral base address.
bogdanm 0:9b334a45a8ff 512 * @param statusFlag The status flag, defined in type i2c_status_flag_t.
bogdanm 0:9b334a45a8ff 513 * @return State of the status flag: asserted (true) or not-asserted (false).
bogdanm 0:9b334a45a8ff 514 * - true: related status flag is being set.
bogdanm 0:9b334a45a8ff 515 * - false: related status flag is not set.
bogdanm 0:9b334a45a8ff 516 */
bogdanm 0:9b334a45a8ff 517 static inline bool I2C_HAL_GetStatusFlag(uint32_t baseAddr, i2c_status_flag_t statusFlag)
bogdanm 0:9b334a45a8ff 518 {
bogdanm 0:9b334a45a8ff 519 return (bool)((HW_I2C_S_RD(baseAddr) >> statusFlag) & 0x1U);
bogdanm 0:9b334a45a8ff 520 }
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 /*!
bogdanm 0:9b334a45a8ff 523 * @brief Returns whether the I2C module is in master mode.
bogdanm 0:9b334a45a8ff 524 *
bogdanm 0:9b334a45a8ff 525 * @param baseAddr The I2C peripheral base address.
bogdanm 0:9b334a45a8ff 526 * @retval true The module is in master mode, which implies it is also performing a transfer.
bogdanm 0:9b334a45a8ff 527 * @retval false The module is in slave mode.
bogdanm 0:9b334a45a8ff 528 */
bogdanm 0:9b334a45a8ff 529 static inline bool I2C_HAL_IsMaster(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 530 {
bogdanm 0:9b334a45a8ff 531 return (bool)BR_I2C_C1_MST(baseAddr);
bogdanm 0:9b334a45a8ff 532 }
bogdanm 0:9b334a45a8ff 533
bogdanm 0:9b334a45a8ff 534 /*!
bogdanm 0:9b334a45a8ff 535 * @brief Clears the arbitration lost flag.
bogdanm 0:9b334a45a8ff 536 *
bogdanm 0:9b334a45a8ff 537 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 538 */
bogdanm 0:9b334a45a8ff 539 static inline void I2C_HAL_ClearArbitrationLost(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 540 {
bogdanm 0:9b334a45a8ff 541 BW_I2C_S_ARBL(baseAddr, 0x1U);
bogdanm 0:9b334a45a8ff 542 }
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 /*@}*/
bogdanm 0:9b334a45a8ff 545
bogdanm 0:9b334a45a8ff 546 /*!
bogdanm 0:9b334a45a8ff 547 * @name Interrupt
bogdanm 0:9b334a45a8ff 548 * @{
bogdanm 0:9b334a45a8ff 549 */
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /*!
bogdanm 0:9b334a45a8ff 552 * @brief Enables or disables I2C interrupt requests.
bogdanm 0:9b334a45a8ff 553 *
bogdanm 0:9b334a45a8ff 554 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 555 * @param enable Pass true to enable interrupt, flase to disable.
bogdanm 0:9b334a45a8ff 556 */
bogdanm 0:9b334a45a8ff 557 static inline void I2C_HAL_SetIntCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 558 {
bogdanm 0:9b334a45a8ff 559 BW_I2C_C1_IICIE(baseAddr, (uint8_t)enable);
bogdanm 0:9b334a45a8ff 560 }
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 /*!
bogdanm 0:9b334a45a8ff 563 * @brief Returns whether the I2C interrupts are enabled.
bogdanm 0:9b334a45a8ff 564 *
bogdanm 0:9b334a45a8ff 565 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 566 * @retval true I2C interrupts are enabled.
bogdanm 0:9b334a45a8ff 567 * @retval false I2C interrupts are disabled.
bogdanm 0:9b334a45a8ff 568 */
bogdanm 0:9b334a45a8ff 569 static inline bool I2C_HAL_GetIntCmd(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 570 {
bogdanm 0:9b334a45a8ff 571 return (bool)BR_I2C_C1_IICIE(baseAddr);
bogdanm 0:9b334a45a8ff 572 }
bogdanm 0:9b334a45a8ff 573
bogdanm 0:9b334a45a8ff 574 /*!
bogdanm 0:9b334a45a8ff 575 * @brief Returns the current I2C interrupt flag.
bogdanm 0:9b334a45a8ff 576 *
bogdanm 0:9b334a45a8ff 577 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 578 * @retval true An interrupt is pending.
bogdanm 0:9b334a45a8ff 579 * @retval false No interrupt is pending.
bogdanm 0:9b334a45a8ff 580 */
bogdanm 0:9b334a45a8ff 581 static inline bool I2C_HAL_IsIntPending(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 582 {
bogdanm 0:9b334a45a8ff 583 return (bool)BR_I2C_S_IICIF(baseAddr);
bogdanm 0:9b334a45a8ff 584 }
bogdanm 0:9b334a45a8ff 585
bogdanm 0:9b334a45a8ff 586 /*!
bogdanm 0:9b334a45a8ff 587 * @brief Clears the I2C interrupt if set.
bogdanm 0:9b334a45a8ff 588 *
bogdanm 0:9b334a45a8ff 589 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 590 */
bogdanm 0:9b334a45a8ff 591 static inline void I2C_HAL_ClearInt(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 592 {
bogdanm 0:9b334a45a8ff 593 BW_I2C_S_IICIF(baseAddr, 0x1U);
bogdanm 0:9b334a45a8ff 594 }
bogdanm 0:9b334a45a8ff 595
bogdanm 0:9b334a45a8ff 596 /*@}*/
bogdanm 0:9b334a45a8ff 597
bogdanm 0:9b334a45a8ff 598 #if FSL_FEATURE_I2C_HAS_STOP_DETECT
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 /*!
bogdanm 0:9b334a45a8ff 601 * @name Bus stop detection status
bogdanm 0:9b334a45a8ff 602 * @{
bogdanm 0:9b334a45a8ff 603 */
bogdanm 0:9b334a45a8ff 604
bogdanm 0:9b334a45a8ff 605 /*!
bogdanm 0:9b334a45a8ff 606 * @brief Gets the flag indicating a STOP signal was detected on the I2C bus.
bogdanm 0:9b334a45a8ff 607 *
bogdanm 0:9b334a45a8ff 608 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 609 * @retval true STOP signal detected on bus.
bogdanm 0:9b334a45a8ff 610 * @retval false No STOP signal was detected on the bus.
bogdanm 0:9b334a45a8ff 611 */
bogdanm 0:9b334a45a8ff 612 static inline bool I2C_HAL_GetStopFlag(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 613 {
bogdanm 0:9b334a45a8ff 614 return (bool)BR_I2C_FLT_STOPF(baseAddr);
bogdanm 0:9b334a45a8ff 615 }
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 /*!
bogdanm 0:9b334a45a8ff 618 * @brief Clears the bus STOP signal detected flag.
bogdanm 0:9b334a45a8ff 619 *
bogdanm 0:9b334a45a8ff 620 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 621 */
bogdanm 0:9b334a45a8ff 622 static inline void I2C_HAL_ClearStopFlag(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 623 {
bogdanm 0:9b334a45a8ff 624 BW_I2C_FLT_STOPF(baseAddr, 0x1U);
bogdanm 0:9b334a45a8ff 625 }
bogdanm 0:9b334a45a8ff 626
bogdanm 0:9b334a45a8ff 627 /*@}*/
bogdanm 0:9b334a45a8ff 628
bogdanm 0:9b334a45a8ff 629 #if FSL_FEATURE_I2C_HAS_START_DETECT
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 /*!
bogdanm 0:9b334a45a8ff 632 * @name Bus stop detection interrupt
bogdanm 0:9b334a45a8ff 633 * @{
bogdanm 0:9b334a45a8ff 634 */
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 /*!
bogdanm 0:9b334a45a8ff 637 * @brief Enables the I2C bus stop detection interrupt.
bogdanm 0:9b334a45a8ff 638 *
bogdanm 0:9b334a45a8ff 639 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 640 * @param enable Pass true to enable interrupt, flase to disable.
bogdanm 0:9b334a45a8ff 641 */
bogdanm 0:9b334a45a8ff 642 static inline void I2C_HAL_SetStopIntCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 643 {
bogdanm 0:9b334a45a8ff 644 BW_I2C_FLT_SSIE(baseAddr, enable);
bogdanm 0:9b334a45a8ff 645 }
bogdanm 0:9b334a45a8ff 646
bogdanm 0:9b334a45a8ff 647 /*!
bogdanm 0:9b334a45a8ff 648 * @brief Returns whether the I2C bus stop detection interrupts are enabled.
bogdanm 0:9b334a45a8ff 649 *
bogdanm 0:9b334a45a8ff 650 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 651 * @retval true Stop detect interrupts are enabled.
bogdanm 0:9b334a45a8ff 652 * @retval false Stop detect interrupts are disabled.
bogdanm 0:9b334a45a8ff 653 */
bogdanm 0:9b334a45a8ff 654 static inline bool I2C_HAL_GetStopIntCmd(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 655 {
bogdanm 0:9b334a45a8ff 656 return (bool)BR_I2C_FLT_SSIE(baseAddr);
bogdanm 0:9b334a45a8ff 657 }
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 #else
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 /*! @name Bus stop detection interrupt*/
bogdanm 0:9b334a45a8ff 662 /*@{*/
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 /*!
bogdanm 0:9b334a45a8ff 665 * @brief Enables the I2C bus stop detection interrupt.
bogdanm 0:9b334a45a8ff 666 *
bogdanm 0:9b334a45a8ff 667 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 668 */
bogdanm 0:9b334a45a8ff 669 static inline void I2C_HAL_SetStopIntCmd(uint32_t baseAddr, bool enable)
bogdanm 0:9b334a45a8ff 670 {
bogdanm 0:9b334a45a8ff 671 BW_I2C_FLT_STOPIE(baseAddr, enable);
bogdanm 0:9b334a45a8ff 672 }
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674 /*!
bogdanm 0:9b334a45a8ff 675 * @brief Returns whether the I2C bus stop detection interrupts are enabled.
bogdanm 0:9b334a45a8ff 676 *
bogdanm 0:9b334a45a8ff 677 * @param baseAddr The I2C peripheral base address
bogdanm 0:9b334a45a8ff 678 * @retval true Stop detect interrupts are enabled.
bogdanm 0:9b334a45a8ff 679 * @retval false Stop detect interrupts are disabled.
bogdanm 0:9b334a45a8ff 680 */
bogdanm 0:9b334a45a8ff 681 static inline bool I2C_HAL_GetStopIntCmd(uint32_t baseAddr)
bogdanm 0:9b334a45a8ff 682 {
bogdanm 0:9b334a45a8ff 683 return (bool)BR_I2C_FLT_STOPIE(baseAddr);
bogdanm 0:9b334a45a8ff 684 }
bogdanm 0:9b334a45a8ff 685
bogdanm 0:9b334a45a8ff 686 #endif /* FSL_FEATURE_I2C_HAS_START_DETECT*/
bogdanm 0:9b334a45a8ff 687
bogdanm 0:9b334a45a8ff 688 /*@}*/
bogdanm 0:9b334a45a8ff 689 #endif /* FSL_FEATURE_I2C_HAS_STOP_DETECT*/
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691 #if defined(__cplusplus)
bogdanm 0:9b334a45a8ff 692 }
bogdanm 0:9b334a45a8ff 693 #endif
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /*! @} */
bogdanm 0:9b334a45a8ff 696
bogdanm 0:9b334a45a8ff 697 #endif /* __FSL_I2C_HAL_H__*/
bogdanm 0:9b334a45a8ff 698 /*******************************************************************************
bogdanm 0:9b334a45a8ff 699 * EOF
bogdanm 0:9b334a45a8ff 700 ******************************************************************************/
bogdanm 0:9b334a45a8ff 701
bogdanm 0:9b334a45a8ff 702