Daiki Kato
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mbed-dev_tmp
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targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c@108:af734d017ad0, 2016-04-26 (annotated)
- Committer:
- dkato
- Date:
- Tue Apr 26 02:02:58 2016 +0000
- Revision:
- 108:af734d017ad0
- Parent:
- 0:9b334a45a8ff
bugfixs
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /** |
| bogdanm | 0:9b334a45a8ff | 2 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 3 | * @file system_stm32l1xx.c |
| bogdanm | 0:9b334a45a8ff | 4 | * @author MCD Application Team |
| bogdanm | 0:9b334a45a8ff | 5 | * @version V2.0.0 |
| bogdanm | 0:9b334a45a8ff | 6 | * @date 5-September-2014 |
| bogdanm | 0:9b334a45a8ff | 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. |
| bogdanm | 0:9b334a45a8ff | 8 | * |
| bogdanm | 0:9b334a45a8ff | 9 | * This file provides two functions and one global variable to be called from |
| bogdanm | 0:9b334a45a8ff | 10 | * user application: |
| bogdanm | 0:9b334a45a8ff | 11 | * - SystemInit(): This function is called at startup just after reset and |
| bogdanm | 0:9b334a45a8ff | 12 | * before branch to main program. This call is made inside |
| bogdanm | 0:9b334a45a8ff | 13 | * the "startup_stm32l1xx.s" file. |
| bogdanm | 0:9b334a45a8ff | 14 | * |
| bogdanm | 0:9b334a45a8ff | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| bogdanm | 0:9b334a45a8ff | 16 | * by the user application to setup the SysTick |
| bogdanm | 0:9b334a45a8ff | 17 | * timer or configure other parameters. |
| bogdanm | 0:9b334a45a8ff | 18 | * |
| bogdanm | 0:9b334a45a8ff | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| bogdanm | 0:9b334a45a8ff | 20 | * be called whenever the core clock is changed |
| bogdanm | 0:9b334a45a8ff | 21 | * during program execution. |
| bogdanm | 0:9b334a45a8ff | 22 | * |
| bogdanm | 0:9b334a45a8ff | 23 | * This file configures the system clock as follows: |
| bogdanm | 0:9b334a45a8ff | 24 | *----------------------------------------------------------------------------- |
| bogdanm | 0:9b334a45a8ff | 25 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
| bogdanm | 0:9b334a45a8ff | 26 | * | (external 8 MHz clock) | (internal 16 MHz) |
| bogdanm | 0:9b334a45a8ff | 27 | * | 2- PLL_HSE_XTAL | |
| bogdanm | 0:9b334a45a8ff | 28 | * | (external 8 MHz xtal) | |
| bogdanm | 0:9b334a45a8ff | 29 | *----------------------------------------------------------------------------- |
| bogdanm | 0:9b334a45a8ff | 30 | * SYSCLK(MHz) | 24 | 32 |
| bogdanm | 0:9b334a45a8ff | 31 | *----------------------------------------------------------------------------- |
| bogdanm | 0:9b334a45a8ff | 32 | * AHBCLK (MHz) | 24 | 32 |
| bogdanm | 0:9b334a45a8ff | 33 | *----------------------------------------------------------------------------- |
| bogdanm | 0:9b334a45a8ff | 34 | * APB1CLK (MHz) | 24 | 32 |
| bogdanm | 0:9b334a45a8ff | 35 | *----------------------------------------------------------------------------- |
| bogdanm | 0:9b334a45a8ff | 36 | * APB2CLK (MHz) | 24 | 32 |
| bogdanm | 0:9b334a45a8ff | 37 | *----------------------------------------------------------------------------- |
| bogdanm | 0:9b334a45a8ff | 38 | * USB capable (48 MHz precise clock) | YES | NO |
| bogdanm | 0:9b334a45a8ff | 39 | *----------------------------------------------------------------------------- |
| bogdanm | 0:9b334a45a8ff | 40 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 41 | * @attention |
| bogdanm | 0:9b334a45a8ff | 42 | * |
| bogdanm | 0:9b334a45a8ff | 43 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 0:9b334a45a8ff | 44 | * |
| bogdanm | 0:9b334a45a8ff | 45 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 0:9b334a45a8ff | 46 | * are permitted provided that the following conditions are met: |
| bogdanm | 0:9b334a45a8ff | 47 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 48 | * this list of conditions and the following disclaimer. |
| bogdanm | 0:9b334a45a8ff | 49 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 0:9b334a45a8ff | 50 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 0:9b334a45a8ff | 51 | * and/or other materials provided with the distribution. |
| bogdanm | 0:9b334a45a8ff | 52 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 0:9b334a45a8ff | 53 | * may be used to endorse or promote products derived from this software |
| bogdanm | 0:9b334a45a8ff | 54 | * without specific prior written permission. |
| bogdanm | 0:9b334a45a8ff | 55 | * |
| bogdanm | 0:9b334a45a8ff | 56 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 0:9b334a45a8ff | 57 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 0:9b334a45a8ff | 58 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 0:9b334a45a8ff | 59 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 0:9b334a45a8ff | 60 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 0:9b334a45a8ff | 61 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 0:9b334a45a8ff | 62 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 0:9b334a45a8ff | 63 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 0:9b334a45a8ff | 64 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 0:9b334a45a8ff | 65 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 0:9b334a45a8ff | 66 | * |
| bogdanm | 0:9b334a45a8ff | 67 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 68 | */ |
| bogdanm | 0:9b334a45a8ff | 69 | |
| bogdanm | 0:9b334a45a8ff | 70 | /** @addtogroup CMSIS |
| bogdanm | 0:9b334a45a8ff | 71 | * @{ |
| bogdanm | 0:9b334a45a8ff | 72 | */ |
| bogdanm | 0:9b334a45a8ff | 73 | |
| bogdanm | 0:9b334a45a8ff | 74 | /** @addtogroup stm32l1xx_system |
| bogdanm | 0:9b334a45a8ff | 75 | * @{ |
| bogdanm | 0:9b334a45a8ff | 76 | */ |
| bogdanm | 0:9b334a45a8ff | 77 | |
| bogdanm | 0:9b334a45a8ff | 78 | /** @addtogroup STM32L1xx_System_Private_Includes |
| bogdanm | 0:9b334a45a8ff | 79 | * @{ |
| bogdanm | 0:9b334a45a8ff | 80 | */ |
| bogdanm | 0:9b334a45a8ff | 81 | |
| bogdanm | 0:9b334a45a8ff | 82 | #include "stm32l1xx.h" |
| bogdanm | 0:9b334a45a8ff | 83 | #include "hal_tick.h" |
| bogdanm | 0:9b334a45a8ff | 84 | |
| bogdanm | 0:9b334a45a8ff | 85 | /** |
| bogdanm | 0:9b334a45a8ff | 86 | * @} |
| bogdanm | 0:9b334a45a8ff | 87 | */ |
| bogdanm | 0:9b334a45a8ff | 88 | |
| bogdanm | 0:9b334a45a8ff | 89 | /** @addtogroup STM32L1xx_System_Private_TypesDefinitions |
| bogdanm | 0:9b334a45a8ff | 90 | * @{ |
| bogdanm | 0:9b334a45a8ff | 91 | */ |
| bogdanm | 0:9b334a45a8ff | 92 | |
| bogdanm | 0:9b334a45a8ff | 93 | /** |
| bogdanm | 0:9b334a45a8ff | 94 | * @} |
| bogdanm | 0:9b334a45a8ff | 95 | */ |
| bogdanm | 0:9b334a45a8ff | 96 | |
| bogdanm | 0:9b334a45a8ff | 97 | /** @addtogroup STM32L1xx_System_Private_Defines |
| bogdanm | 0:9b334a45a8ff | 98 | * @{ |
| bogdanm | 0:9b334a45a8ff | 99 | */ |
| bogdanm | 0:9b334a45a8ff | 100 | #if !defined (HSE_VALUE) |
| bogdanm | 0:9b334a45a8ff | 101 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. |
| bogdanm | 0:9b334a45a8ff | 102 | This value can be provided and adapted by the user application. */ |
| bogdanm | 0:9b334a45a8ff | 103 | #endif /* HSE_VALUE */ |
| bogdanm | 0:9b334a45a8ff | 104 | |
| bogdanm | 0:9b334a45a8ff | 105 | #if !defined (HSI_VALUE) |
| bogdanm | 0:9b334a45a8ff | 106 | #define HSI_VALUE ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz. |
| bogdanm | 0:9b334a45a8ff | 107 | This value can be provided and adapted by the user application. */ |
| bogdanm | 0:9b334a45a8ff | 108 | #endif /* HSI_VALUE */ |
| bogdanm | 0:9b334a45a8ff | 109 | |
| bogdanm | 0:9b334a45a8ff | 110 | /*!< Uncomment the following line if you need to use external SRAM mounted |
| bogdanm | 0:9b334a45a8ff | 111 | on STM32L152D_EVAL board as data memory */ |
| bogdanm | 0:9b334a45a8ff | 112 | /* #define DATA_IN_ExtSRAM */ |
| bogdanm | 0:9b334a45a8ff | 113 | |
| bogdanm | 0:9b334a45a8ff | 114 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| bogdanm | 0:9b334a45a8ff | 115 | Internal SRAM. */ |
| bogdanm | 0:9b334a45a8ff | 116 | /* #define VECT_TAB_SRAM */ |
| bogdanm | 0:9b334a45a8ff | 117 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. |
| bogdanm | 0:9b334a45a8ff | 118 | This value must be a multiple of 0x200. */ |
| bogdanm | 0:9b334a45a8ff | 119 | /** |
| bogdanm | 0:9b334a45a8ff | 120 | * @} |
| bogdanm | 0:9b334a45a8ff | 121 | */ |
| bogdanm | 0:9b334a45a8ff | 122 | |
| bogdanm | 0:9b334a45a8ff | 123 | /** @addtogroup STM32L1xx_System_Private_Macros |
| bogdanm | 0:9b334a45a8ff | 124 | * @{ |
| bogdanm | 0:9b334a45a8ff | 125 | */ |
| bogdanm | 0:9b334a45a8ff | 126 | |
| bogdanm | 0:9b334a45a8ff | 127 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
| bogdanm | 0:9b334a45a8ff | 128 | #define USE_PLL_HSE_EXTC (0) /* Use external clock */ |
| bogdanm | 0:9b334a45a8ff | 129 | #define USE_PLL_HSE_XTAL (1) /* Use external xtal */ |
| bogdanm | 0:9b334a45a8ff | 130 | |
| bogdanm | 0:9b334a45a8ff | 131 | /** |
| bogdanm | 0:9b334a45a8ff | 132 | * @} |
| bogdanm | 0:9b334a45a8ff | 133 | */ |
| bogdanm | 0:9b334a45a8ff | 134 | |
| bogdanm | 0:9b334a45a8ff | 135 | /** @addtogroup STM32L1xx_System_Private_Variables |
| bogdanm | 0:9b334a45a8ff | 136 | * @{ |
| bogdanm | 0:9b334a45a8ff | 137 | */ |
| bogdanm | 0:9b334a45a8ff | 138 | /* This variable is updated in three ways: |
| bogdanm | 0:9b334a45a8ff | 139 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| bogdanm | 0:9b334a45a8ff | 140 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| bogdanm | 0:9b334a45a8ff | 141 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| bogdanm | 0:9b334a45a8ff | 142 | Note: If you use this function to configure the system clock; then there |
| bogdanm | 0:9b334a45a8ff | 143 | is no need to call the 2 first functions listed above, since SystemCoreClock |
| bogdanm | 0:9b334a45a8ff | 144 | variable is updated automatically. |
| bogdanm | 0:9b334a45a8ff | 145 | */ |
| bogdanm | 0:9b334a45a8ff | 146 | uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */ |
| bogdanm | 0:9b334a45a8ff | 147 | const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; |
| bogdanm | 0:9b334a45a8ff | 148 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| bogdanm | 0:9b334a45a8ff | 149 | |
| bogdanm | 0:9b334a45a8ff | 150 | /** |
| bogdanm | 0:9b334a45a8ff | 151 | * @} |
| bogdanm | 0:9b334a45a8ff | 152 | */ |
| bogdanm | 0:9b334a45a8ff | 153 | |
| bogdanm | 0:9b334a45a8ff | 154 | /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes |
| bogdanm | 0:9b334a45a8ff | 155 | * @{ |
| bogdanm | 0:9b334a45a8ff | 156 | */ |
| bogdanm | 0:9b334a45a8ff | 157 | |
| bogdanm | 0:9b334a45a8ff | 158 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
| bogdanm | 0:9b334a45a8ff | 159 | #ifdef DATA_IN_ExtSRAM |
| bogdanm | 0:9b334a45a8ff | 160 | static void SystemInit_ExtMemCtl(void); |
| bogdanm | 0:9b334a45a8ff | 161 | #endif /* DATA_IN_ExtSRAM */ |
| bogdanm | 0:9b334a45a8ff | 162 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| bogdanm | 0:9b334a45a8ff | 163 | |
| bogdanm | 0:9b334a45a8ff | 164 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| bogdanm | 0:9b334a45a8ff | 165 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
| bogdanm | 0:9b334a45a8ff | 166 | #endif |
| bogdanm | 0:9b334a45a8ff | 167 | |
| bogdanm | 0:9b334a45a8ff | 168 | uint8_t SetSysClock_PLL_HSI(void); |
| bogdanm | 0:9b334a45a8ff | 169 | |
| bogdanm | 0:9b334a45a8ff | 170 | /** |
| bogdanm | 0:9b334a45a8ff | 171 | * @} |
| bogdanm | 0:9b334a45a8ff | 172 | */ |
| bogdanm | 0:9b334a45a8ff | 173 | |
| bogdanm | 0:9b334a45a8ff | 174 | /** @addtogroup STM32L1xx_System_Private_Functions |
| bogdanm | 0:9b334a45a8ff | 175 | * @{ |
| bogdanm | 0:9b334a45a8ff | 176 | */ |
| bogdanm | 0:9b334a45a8ff | 177 | |
| bogdanm | 0:9b334a45a8ff | 178 | /** |
| bogdanm | 0:9b334a45a8ff | 179 | * @brief Setup the microcontroller system. |
| bogdanm | 0:9b334a45a8ff | 180 | * Initialize the Embedded Flash Interface, the PLL and update the |
| bogdanm | 0:9b334a45a8ff | 181 | * SystemCoreClock variable. |
| bogdanm | 0:9b334a45a8ff | 182 | * @param None |
| bogdanm | 0:9b334a45a8ff | 183 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 184 | */ |
| bogdanm | 0:9b334a45a8ff | 185 | void SystemInit (void) |
| bogdanm | 0:9b334a45a8ff | 186 | { |
| bogdanm | 0:9b334a45a8ff | 187 | /*!< Set MSION bit */ |
| bogdanm | 0:9b334a45a8ff | 188 | RCC->CR |= (uint32_t)0x00000100; |
| bogdanm | 0:9b334a45a8ff | 189 | |
| bogdanm | 0:9b334a45a8ff | 190 | /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ |
| bogdanm | 0:9b334a45a8ff | 191 | RCC->CFGR &= (uint32_t)0x88FFC00C; |
| bogdanm | 0:9b334a45a8ff | 192 | |
| bogdanm | 0:9b334a45a8ff | 193 | /*!< Reset HSION, HSEON, CSSON and PLLON bits */ |
| bogdanm | 0:9b334a45a8ff | 194 | RCC->CR &= (uint32_t)0xEEFEFFFE; |
| bogdanm | 0:9b334a45a8ff | 195 | |
| bogdanm | 0:9b334a45a8ff | 196 | /*!< Reset HSEBYP bit */ |
| bogdanm | 0:9b334a45a8ff | 197 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| bogdanm | 0:9b334a45a8ff | 198 | |
| bogdanm | 0:9b334a45a8ff | 199 | /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ |
| bogdanm | 0:9b334a45a8ff | 200 | RCC->CFGR &= (uint32_t)0xFF02FFFF; |
| bogdanm | 0:9b334a45a8ff | 201 | |
| bogdanm | 0:9b334a45a8ff | 202 | /*!< Disable all interrupts */ |
| bogdanm | 0:9b334a45a8ff | 203 | RCC->CIR = 0x00000000; |
| bogdanm | 0:9b334a45a8ff | 204 | |
| bogdanm | 0:9b334a45a8ff | 205 | #ifdef DATA_IN_ExtSRAM |
| bogdanm | 0:9b334a45a8ff | 206 | SystemInit_ExtMemCtl(); |
| bogdanm | 0:9b334a45a8ff | 207 | #endif /* DATA_IN_ExtSRAM */ |
| bogdanm | 0:9b334a45a8ff | 208 | |
| bogdanm | 0:9b334a45a8ff | 209 | #ifdef VECT_TAB_SRAM |
| bogdanm | 0:9b334a45a8ff | 210 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ |
| bogdanm | 0:9b334a45a8ff | 211 | #else |
| bogdanm | 0:9b334a45a8ff | 212 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ |
| bogdanm | 0:9b334a45a8ff | 213 | #endif |
| bogdanm | 0:9b334a45a8ff | 214 | |
| bogdanm | 0:9b334a45a8ff | 215 | /* Configure the Cube driver */ |
| bogdanm | 0:9b334a45a8ff | 216 | SystemCoreClock = 16000000; // At this stage the HSI is used as system clock |
| bogdanm | 0:9b334a45a8ff | 217 | HAL_Init(); |
| bogdanm | 0:9b334a45a8ff | 218 | |
| bogdanm | 0:9b334a45a8ff | 219 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
| bogdanm | 0:9b334a45a8ff | 220 | AHB/APBx prescalers and Flash settings */ |
| bogdanm | 0:9b334a45a8ff | 221 | SetSysClock(); |
| bogdanm | 0:9b334a45a8ff | 222 | |
| bogdanm | 0:9b334a45a8ff | 223 | /* Reset the timer to avoid issues after the RAM initialization */ |
| bogdanm | 0:9b334a45a8ff | 224 | TIM_MST_RESET_ON; |
| bogdanm | 0:9b334a45a8ff | 225 | TIM_MST_RESET_OFF; |
| bogdanm | 0:9b334a45a8ff | 226 | } |
| bogdanm | 0:9b334a45a8ff | 227 | |
| bogdanm | 0:9b334a45a8ff | 228 | /** |
| bogdanm | 0:9b334a45a8ff | 229 | * @brief Update SystemCoreClock according to Clock Register Values |
| bogdanm | 0:9b334a45a8ff | 230 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| bogdanm | 0:9b334a45a8ff | 231 | * be used by the user application to setup the SysTick timer or configure |
| bogdanm | 0:9b334a45a8ff | 232 | * other parameters. |
| bogdanm | 0:9b334a45a8ff | 233 | * |
| bogdanm | 0:9b334a45a8ff | 234 | * @note Each time the core clock (HCLK) changes, this function must be called |
| bogdanm | 0:9b334a45a8ff | 235 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| bogdanm | 0:9b334a45a8ff | 236 | * based on this variable will be incorrect. |
| bogdanm | 0:9b334a45a8ff | 237 | * |
| bogdanm | 0:9b334a45a8ff | 238 | * @note - The system frequency computed by this function is not the real |
| bogdanm | 0:9b334a45a8ff | 239 | * frequency in the chip. It is calculated based on the predefined |
| bogdanm | 0:9b334a45a8ff | 240 | * constant and the selected clock source: |
| bogdanm | 0:9b334a45a8ff | 241 | * |
| bogdanm | 0:9b334a45a8ff | 242 | * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI |
| bogdanm | 0:9b334a45a8ff | 243 | * value as defined by the MSI range. |
| bogdanm | 0:9b334a45a8ff | 244 | * |
| bogdanm | 0:9b334a45a8ff | 245 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| bogdanm | 0:9b334a45a8ff | 246 | * |
| bogdanm | 0:9b334a45a8ff | 247 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| bogdanm | 0:9b334a45a8ff | 248 | * |
| bogdanm | 0:9b334a45a8ff | 249 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| bogdanm | 0:9b334a45a8ff | 250 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| bogdanm | 0:9b334a45a8ff | 251 | * |
| bogdanm | 0:9b334a45a8ff | 252 | * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value |
| bogdanm | 0:9b334a45a8ff | 253 | * 16 MHz) but the real value may vary depending on the variations |
| bogdanm | 0:9b334a45a8ff | 254 | * in voltage and temperature. |
| bogdanm | 0:9b334a45a8ff | 255 | * |
| bogdanm | 0:9b334a45a8ff | 256 | * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value |
| bogdanm | 0:9b334a45a8ff | 257 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
| bogdanm | 0:9b334a45a8ff | 258 | * frequency of the crystal used. Otherwise, this function may |
| bogdanm | 0:9b334a45a8ff | 259 | * have wrong result. |
| bogdanm | 0:9b334a45a8ff | 260 | * |
| bogdanm | 0:9b334a45a8ff | 261 | * - The result of this function could be not correct when using fractional |
| bogdanm | 0:9b334a45a8ff | 262 | * value for HSE crystal. |
| bogdanm | 0:9b334a45a8ff | 263 | * @param None |
| bogdanm | 0:9b334a45a8ff | 264 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 265 | */ |
| bogdanm | 0:9b334a45a8ff | 266 | void SystemCoreClockUpdate (void) |
| bogdanm | 0:9b334a45a8ff | 267 | { |
| bogdanm | 0:9b334a45a8ff | 268 | uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; |
| bogdanm | 0:9b334a45a8ff | 269 | |
| bogdanm | 0:9b334a45a8ff | 270 | /* Get SYSCLK source -------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 271 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| bogdanm | 0:9b334a45a8ff | 272 | |
| bogdanm | 0:9b334a45a8ff | 273 | switch (tmp) |
| bogdanm | 0:9b334a45a8ff | 274 | { |
| bogdanm | 0:9b334a45a8ff | 275 | case 0x00: /* MSI used as system clock */ |
| bogdanm | 0:9b334a45a8ff | 276 | msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; |
| bogdanm | 0:9b334a45a8ff | 277 | SystemCoreClock = (32768 * (1 << (msirange + 1))); |
| bogdanm | 0:9b334a45a8ff | 278 | break; |
| bogdanm | 0:9b334a45a8ff | 279 | case 0x04: /* HSI used as system clock */ |
| bogdanm | 0:9b334a45a8ff | 280 | SystemCoreClock = HSI_VALUE; |
| bogdanm | 0:9b334a45a8ff | 281 | break; |
| bogdanm | 0:9b334a45a8ff | 282 | case 0x08: /* HSE used as system clock */ |
| bogdanm | 0:9b334a45a8ff | 283 | SystemCoreClock = HSE_VALUE; |
| bogdanm | 0:9b334a45a8ff | 284 | break; |
| bogdanm | 0:9b334a45a8ff | 285 | case 0x0C: /* PLL used as system clock */ |
| bogdanm | 0:9b334a45a8ff | 286 | /* Get PLL clock source and multiplication factor ----------------------*/ |
| bogdanm | 0:9b334a45a8ff | 287 | pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; |
| bogdanm | 0:9b334a45a8ff | 288 | plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; |
| bogdanm | 0:9b334a45a8ff | 289 | pllmul = PLLMulTable[(pllmul >> 18)]; |
| bogdanm | 0:9b334a45a8ff | 290 | plldiv = (plldiv >> 22) + 1; |
| bogdanm | 0:9b334a45a8ff | 291 | |
| bogdanm | 0:9b334a45a8ff | 292 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
| bogdanm | 0:9b334a45a8ff | 293 | |
| bogdanm | 0:9b334a45a8ff | 294 | if (pllsource == 0x00) |
| bogdanm | 0:9b334a45a8ff | 295 | { |
| bogdanm | 0:9b334a45a8ff | 296 | /* HSI oscillator clock selected as PLL clock entry */ |
| bogdanm | 0:9b334a45a8ff | 297 | SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); |
| bogdanm | 0:9b334a45a8ff | 298 | } |
| bogdanm | 0:9b334a45a8ff | 299 | else |
| bogdanm | 0:9b334a45a8ff | 300 | { |
| bogdanm | 0:9b334a45a8ff | 301 | /* HSE selected as PLL clock entry */ |
| bogdanm | 0:9b334a45a8ff | 302 | SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); |
| bogdanm | 0:9b334a45a8ff | 303 | } |
| bogdanm | 0:9b334a45a8ff | 304 | break; |
| bogdanm | 0:9b334a45a8ff | 305 | default: /* MSI used as system clock */ |
| bogdanm | 0:9b334a45a8ff | 306 | msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; |
| bogdanm | 0:9b334a45a8ff | 307 | SystemCoreClock = (32768 * (1 << (msirange + 1))); |
| bogdanm | 0:9b334a45a8ff | 308 | break; |
| bogdanm | 0:9b334a45a8ff | 309 | } |
| bogdanm | 0:9b334a45a8ff | 310 | /* Compute HCLK clock frequency --------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 311 | /* Get HCLK prescaler */ |
| bogdanm | 0:9b334a45a8ff | 312 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| bogdanm | 0:9b334a45a8ff | 313 | /* HCLK clock frequency */ |
| bogdanm | 0:9b334a45a8ff | 314 | SystemCoreClock >>= tmp; |
| bogdanm | 0:9b334a45a8ff | 315 | } |
| bogdanm | 0:9b334a45a8ff | 316 | |
| bogdanm | 0:9b334a45a8ff | 317 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
| bogdanm | 0:9b334a45a8ff | 318 | #ifdef DATA_IN_ExtSRAM |
| bogdanm | 0:9b334a45a8ff | 319 | /** |
| bogdanm | 0:9b334a45a8ff | 320 | * @brief Setup the external memory controller. |
| bogdanm | 0:9b334a45a8ff | 321 | * Called in SystemInit() function before jump to main. |
| bogdanm | 0:9b334a45a8ff | 322 | * This function configures the external SRAM mounted on STM32L152D_EVAL board |
| bogdanm | 0:9b334a45a8ff | 323 | * This SRAM will be used as program data memory (including heap and stack). |
| bogdanm | 0:9b334a45a8ff | 324 | * @param None |
| bogdanm | 0:9b334a45a8ff | 325 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 326 | */ |
| bogdanm | 0:9b334a45a8ff | 327 | void SystemInit_ExtMemCtl(void) |
| bogdanm | 0:9b334a45a8ff | 328 | { |
| bogdanm | 0:9b334a45a8ff | 329 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 330 | /* |
| bogdanm | 0:9b334a45a8ff | 331 | +-------------------+--------------------+------------------+------------------+ |
| bogdanm | 0:9b334a45a8ff | 332 | + SRAM pins assignment + |
| bogdanm | 0:9b334a45a8ff | 333 | +-------------------+--------------------+------------------+------------------+ |
| bogdanm | 0:9b334a45a8ff | 334 | | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | |
| bogdanm | 0:9b334a45a8ff | 335 | | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | |
| bogdanm | 0:9b334a45a8ff | 336 | | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | |
| bogdanm | 0:9b334a45a8ff | 337 | | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | |
| bogdanm | 0:9b334a45a8ff | 338 | | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | |
| bogdanm | 0:9b334a45a8ff | 339 | | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | |
| bogdanm | 0:9b334a45a8ff | 340 | | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 | |
| bogdanm | 0:9b334a45a8ff | 341 | | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ |
| bogdanm | 0:9b334a45a8ff | 342 | | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | |
| bogdanm | 0:9b334a45a8ff | 343 | | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | |
| bogdanm | 0:9b334a45a8ff | 344 | | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+ |
| bogdanm | 0:9b334a45a8ff | 345 | | PD15 <-> FSMC_D1 |--------------------+ |
| bogdanm | 0:9b334a45a8ff | 346 | +-------------------+ |
| bogdanm | 0:9b334a45a8ff | 347 | */ |
| bogdanm | 0:9b334a45a8ff | 348 | |
| bogdanm | 0:9b334a45a8ff | 349 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
| bogdanm | 0:9b334a45a8ff | 350 | RCC->AHBENR = 0x000080D8; |
| bogdanm | 0:9b334a45a8ff | 351 | |
| bogdanm | 0:9b334a45a8ff | 352 | /* Connect PDx pins to FSMC Alternate function */ |
| bogdanm | 0:9b334a45a8ff | 353 | GPIOD->AFR[0] = 0x00CC00CC; |
| bogdanm | 0:9b334a45a8ff | 354 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| bogdanm | 0:9b334a45a8ff | 355 | /* Configure PDx pins in Alternate function mode */ |
| bogdanm | 0:9b334a45a8ff | 356 | GPIOD->MODER = 0xAAAA0A0A; |
| bogdanm | 0:9b334a45a8ff | 357 | /* Configure PDx pins speed to 40 MHz */ |
| bogdanm | 0:9b334a45a8ff | 358 | GPIOD->OSPEEDR = 0xFFFF0F0F; |
| bogdanm | 0:9b334a45a8ff | 359 | /* Configure PDx pins Output type to push-pull */ |
| bogdanm | 0:9b334a45a8ff | 360 | GPIOD->OTYPER = 0x00000000; |
| bogdanm | 0:9b334a45a8ff | 361 | /* No pull-up, pull-down for PDx pins */ |
| bogdanm | 0:9b334a45a8ff | 362 | GPIOD->PUPDR = 0x00000000; |
| bogdanm | 0:9b334a45a8ff | 363 | |
| bogdanm | 0:9b334a45a8ff | 364 | /* Connect PEx pins to FSMC Alternate function */ |
| bogdanm | 0:9b334a45a8ff | 365 | GPIOE->AFR[0] = 0xC00000CC; |
| bogdanm | 0:9b334a45a8ff | 366 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| bogdanm | 0:9b334a45a8ff | 367 | /* Configure PEx pins in Alternate function mode */ |
| bogdanm | 0:9b334a45a8ff | 368 | GPIOE->MODER = 0xAAAA800A; |
| bogdanm | 0:9b334a45a8ff | 369 | /* Configure PEx pins speed to 40 MHz */ |
| bogdanm | 0:9b334a45a8ff | 370 | GPIOE->OSPEEDR = 0xFFFFC00F; |
| bogdanm | 0:9b334a45a8ff | 371 | /* Configure PEx pins Output type to push-pull */ |
| bogdanm | 0:9b334a45a8ff | 372 | GPIOE->OTYPER = 0x00000000; |
| bogdanm | 0:9b334a45a8ff | 373 | /* No pull-up, pull-down for PEx pins */ |
| bogdanm | 0:9b334a45a8ff | 374 | GPIOE->PUPDR = 0x00000000; |
| bogdanm | 0:9b334a45a8ff | 375 | |
| bogdanm | 0:9b334a45a8ff | 376 | /* Connect PFx pins to FSMC Alternate function */ |
| bogdanm | 0:9b334a45a8ff | 377 | GPIOF->AFR[0] = 0x00CCCCCC; |
| bogdanm | 0:9b334a45a8ff | 378 | GPIOF->AFR[1] = 0xCCCC0000; |
| bogdanm | 0:9b334a45a8ff | 379 | /* Configure PFx pins in Alternate function mode */ |
| bogdanm | 0:9b334a45a8ff | 380 | GPIOF->MODER = 0xAA000AAA; |
| bogdanm | 0:9b334a45a8ff | 381 | /* Configure PFx pins speed to 40 MHz */ |
| bogdanm | 0:9b334a45a8ff | 382 | GPIOF->OSPEEDR = 0xFF000FFF; |
| bogdanm | 0:9b334a45a8ff | 383 | /* Configure PFx pins Output type to push-pull */ |
| bogdanm | 0:9b334a45a8ff | 384 | GPIOF->OTYPER = 0x00000000; |
| bogdanm | 0:9b334a45a8ff | 385 | /* No pull-up, pull-down for PFx pins */ |
| bogdanm | 0:9b334a45a8ff | 386 | GPIOF->PUPDR = 0x00000000; |
| bogdanm | 0:9b334a45a8ff | 387 | |
| bogdanm | 0:9b334a45a8ff | 388 | /* Connect PGx pins to FSMC Alternate function */ |
| bogdanm | 0:9b334a45a8ff | 389 | GPIOG->AFR[0] = 0x00CCCCCC; |
| bogdanm | 0:9b334a45a8ff | 390 | GPIOG->AFR[1] = 0x00000C00; |
| bogdanm | 0:9b334a45a8ff | 391 | /* Configure PGx pins in Alternate function mode */ |
| bogdanm | 0:9b334a45a8ff | 392 | GPIOG->MODER = 0x00200AAA; |
| bogdanm | 0:9b334a45a8ff | 393 | /* Configure PGx pins speed to 40 MHz */ |
| bogdanm | 0:9b334a45a8ff | 394 | GPIOG->OSPEEDR = 0x00300FFF; |
| bogdanm | 0:9b334a45a8ff | 395 | /* Configure PGx pins Output type to push-pull */ |
| bogdanm | 0:9b334a45a8ff | 396 | GPIOG->OTYPER = 0x00000000; |
| bogdanm | 0:9b334a45a8ff | 397 | /* No pull-up, pull-down for PGx pins */ |
| bogdanm | 0:9b334a45a8ff | 398 | GPIOG->PUPDR = 0x00000000; |
| bogdanm | 0:9b334a45a8ff | 399 | |
| bogdanm | 0:9b334a45a8ff | 400 | /*-- FSMC Configuration ------------------------------------------------------*/ |
| bogdanm | 0:9b334a45a8ff | 401 | /* Enable the FSMC interface clock */ |
| bogdanm | 0:9b334a45a8ff | 402 | RCC->AHBENR = 0x400080D8; |
| bogdanm | 0:9b334a45a8ff | 403 | |
| bogdanm | 0:9b334a45a8ff | 404 | /* Configure and enable Bank1_SRAM3 */ |
| bogdanm | 0:9b334a45a8ff | 405 | FSMC_Bank1->BTCR[4] = 0x00001011; |
| bogdanm | 0:9b334a45a8ff | 406 | FSMC_Bank1->BTCR[5] = 0x00000300; |
| bogdanm | 0:9b334a45a8ff | 407 | FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; |
| bogdanm | 0:9b334a45a8ff | 408 | /* |
| bogdanm | 0:9b334a45a8ff | 409 | Bank1_SRAM3 is configured as follow: |
| bogdanm | 0:9b334a45a8ff | 410 | |
| bogdanm | 0:9b334a45a8ff | 411 | p.FSMC_AddressSetupTime = 0; |
| bogdanm | 0:9b334a45a8ff | 412 | p.FSMC_AddressHoldTime = 0; |
| bogdanm | 0:9b334a45a8ff | 413 | p.FSMC_DataSetupTime = 3; |
| bogdanm | 0:9b334a45a8ff | 414 | p.FSMC_BusTurnAroundDuration = 0; |
| bogdanm | 0:9b334a45a8ff | 415 | p.FSMC_CLKDivision = 0; |
| bogdanm | 0:9b334a45a8ff | 416 | p.FSMC_DataLatency = 0; |
| bogdanm | 0:9b334a45a8ff | 417 | p.FSMC_AccessMode = FSMC_AccessMode_A; |
| bogdanm | 0:9b334a45a8ff | 418 | |
| bogdanm | 0:9b334a45a8ff | 419 | FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; |
| bogdanm | 0:9b334a45a8ff | 420 | FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; |
| bogdanm | 0:9b334a45a8ff | 421 | FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; |
| bogdanm | 0:9b334a45a8ff | 422 | FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; |
| bogdanm | 0:9b334a45a8ff | 423 | FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; |
| bogdanm | 0:9b334a45a8ff | 424 | FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; |
| bogdanm | 0:9b334a45a8ff | 425 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; |
| bogdanm | 0:9b334a45a8ff | 426 | FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; |
| bogdanm | 0:9b334a45a8ff | 427 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; |
| bogdanm | 0:9b334a45a8ff | 428 | FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; |
| bogdanm | 0:9b334a45a8ff | 429 | FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; |
| bogdanm | 0:9b334a45a8ff | 430 | FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; |
| bogdanm | 0:9b334a45a8ff | 431 | FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; |
| bogdanm | 0:9b334a45a8ff | 432 | FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; |
| bogdanm | 0:9b334a45a8ff | 433 | FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; |
| bogdanm | 0:9b334a45a8ff | 434 | |
| bogdanm | 0:9b334a45a8ff | 435 | FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); |
| bogdanm | 0:9b334a45a8ff | 436 | |
| bogdanm | 0:9b334a45a8ff | 437 | FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); |
| bogdanm | 0:9b334a45a8ff | 438 | */ |
| bogdanm | 0:9b334a45a8ff | 439 | |
| bogdanm | 0:9b334a45a8ff | 440 | } |
| bogdanm | 0:9b334a45a8ff | 441 | #endif /* DATA_IN_ExtSRAM */ |
| bogdanm | 0:9b334a45a8ff | 442 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| bogdanm | 0:9b334a45a8ff | 443 | |
| bogdanm | 0:9b334a45a8ff | 444 | /** |
| bogdanm | 0:9b334a45a8ff | 445 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
| bogdanm | 0:9b334a45a8ff | 446 | * AHB/APBx prescalers and Flash settings |
| bogdanm | 0:9b334a45a8ff | 447 | * @note This function should be called only once the RCC clock configuration |
| bogdanm | 0:9b334a45a8ff | 448 | * is reset to the default reset state (done in SystemInit() function). |
| bogdanm | 0:9b334a45a8ff | 449 | * @param None |
| bogdanm | 0:9b334a45a8ff | 450 | * @retval None |
| bogdanm | 0:9b334a45a8ff | 451 | */ |
| bogdanm | 0:9b334a45a8ff | 452 | void SetSysClock(void) |
| bogdanm | 0:9b334a45a8ff | 453 | { |
| bogdanm | 0:9b334a45a8ff | 454 | /* 1- Try to start with HSE and external clock */ |
| bogdanm | 0:9b334a45a8ff | 455 | #if USE_PLL_HSE_EXTC != 0 |
| bogdanm | 0:9b334a45a8ff | 456 | if (SetSysClock_PLL_HSE(1) == 0) |
| bogdanm | 0:9b334a45a8ff | 457 | #endif |
| bogdanm | 0:9b334a45a8ff | 458 | { |
| bogdanm | 0:9b334a45a8ff | 459 | /* 2- If fail try to start with HSE and external xtal */ |
| bogdanm | 0:9b334a45a8ff | 460 | #if USE_PLL_HSE_XTAL != 0 |
| bogdanm | 0:9b334a45a8ff | 461 | if (SetSysClock_PLL_HSE(0) == 0) |
| bogdanm | 0:9b334a45a8ff | 462 | #endif |
| bogdanm | 0:9b334a45a8ff | 463 | { |
| bogdanm | 0:9b334a45a8ff | 464 | /* 3- If fail start with HSI clock */ |
| bogdanm | 0:9b334a45a8ff | 465 | if (SetSysClock_PLL_HSI() == 0) |
| bogdanm | 0:9b334a45a8ff | 466 | { |
| bogdanm | 0:9b334a45a8ff | 467 | while(1) |
| bogdanm | 0:9b334a45a8ff | 468 | { |
| bogdanm | 0:9b334a45a8ff | 469 | // [TODO] Put something here to tell the user that a problem occured... |
| bogdanm | 0:9b334a45a8ff | 470 | } |
| bogdanm | 0:9b334a45a8ff | 471 | } |
| bogdanm | 0:9b334a45a8ff | 472 | } |
| bogdanm | 0:9b334a45a8ff | 473 | } |
| bogdanm | 0:9b334a45a8ff | 474 | |
| bogdanm | 0:9b334a45a8ff | 475 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| bogdanm | 0:9b334a45a8ff | 476 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); |
| bogdanm | 0:9b334a45a8ff | 477 | } |
| bogdanm | 0:9b334a45a8ff | 478 | |
| bogdanm | 0:9b334a45a8ff | 479 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
| bogdanm | 0:9b334a45a8ff | 480 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 481 | /* PLL (clocked by HSE) used as System clock source */ |
| bogdanm | 0:9b334a45a8ff | 482 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 483 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
| bogdanm | 0:9b334a45a8ff | 484 | { |
| bogdanm | 0:9b334a45a8ff | 485 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| bogdanm | 0:9b334a45a8ff | 486 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| bogdanm | 0:9b334a45a8ff | 487 | |
| bogdanm | 0:9b334a45a8ff | 488 | if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) |
| bogdanm | 0:9b334a45a8ff | 489 | return 1; // already on HSE PLL, could occur from deepsleep waking |
| bogdanm | 0:9b334a45a8ff | 490 | |
| bogdanm | 0:9b334a45a8ff | 491 | /* Used to gain time after DeepSleep in case HSI is used */ |
| bogdanm | 0:9b334a45a8ff | 492 | if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) |
| bogdanm | 0:9b334a45a8ff | 493 | { |
| bogdanm | 0:9b334a45a8ff | 494 | return 0; |
| bogdanm | 0:9b334a45a8ff | 495 | } |
| bogdanm | 0:9b334a45a8ff | 496 | |
| bogdanm | 0:9b334a45a8ff | 497 | /* The voltage scaling allows optimizing the power consumption when the device is |
| bogdanm | 0:9b334a45a8ff | 498 | clocked below the maximum system frequency, to update the voltage scaling value |
| bogdanm | 0:9b334a45a8ff | 499 | regarding system frequency refer to product datasheet. */ |
| bogdanm | 0:9b334a45a8ff | 500 | __PWR_CLK_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 501 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
| bogdanm | 0:9b334a45a8ff | 502 | |
| bogdanm | 0:9b334a45a8ff | 503 | /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ |
| bogdanm | 0:9b334a45a8ff | 504 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; |
| bogdanm | 0:9b334a45a8ff | 505 | if (bypass == 0) |
| bogdanm | 0:9b334a45a8ff | 506 | { |
| bogdanm | 0:9b334a45a8ff | 507 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ |
| bogdanm | 0:9b334a45a8ff | 508 | } |
| bogdanm | 0:9b334a45a8ff | 509 | else |
| bogdanm | 0:9b334a45a8ff | 510 | { |
| bogdanm | 0:9b334a45a8ff | 511 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ |
| bogdanm | 0:9b334a45a8ff | 512 | } |
| bogdanm | 0:9b334a45a8ff | 513 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
| bogdanm | 0:9b334a45a8ff | 514 | // SYSCLK = 24 MHz ((8 MHz * 6) / 2) |
| bogdanm | 0:9b334a45a8ff | 515 | // USBCLK = 48 MHz (8 MHz * 6) --> USB OK |
| bogdanm | 0:9b334a45a8ff | 516 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| bogdanm | 0:9b334a45a8ff | 517 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| bogdanm | 0:9b334a45a8ff | 518 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; |
| bogdanm | 0:9b334a45a8ff | 519 | RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2; |
| bogdanm | 0:9b334a45a8ff | 520 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| bogdanm | 0:9b334a45a8ff | 521 | { |
| bogdanm | 0:9b334a45a8ff | 522 | return 0; // FAIL |
| bogdanm | 0:9b334a45a8ff | 523 | } |
| bogdanm | 0:9b334a45a8ff | 524 | |
| bogdanm | 0:9b334a45a8ff | 525 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| bogdanm | 0:9b334a45a8ff | 526 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| bogdanm | 0:9b334a45a8ff | 527 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz |
| bogdanm | 0:9b334a45a8ff | 528 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz |
| bogdanm | 0:9b334a45a8ff | 529 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz |
| bogdanm | 0:9b334a45a8ff | 530 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz |
| bogdanm | 0:9b334a45a8ff | 531 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
| bogdanm | 0:9b334a45a8ff | 532 | { |
| bogdanm | 0:9b334a45a8ff | 533 | return 0; // FAIL |
| bogdanm | 0:9b334a45a8ff | 534 | } |
| bogdanm | 0:9b334a45a8ff | 535 | |
| bogdanm | 0:9b334a45a8ff | 536 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| bogdanm | 0:9b334a45a8ff | 537 | //if (bypass == 0) |
| bogdanm | 0:9b334a45a8ff | 538 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz |
| bogdanm | 0:9b334a45a8ff | 539 | //else |
| bogdanm | 0:9b334a45a8ff | 540 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz |
| bogdanm | 0:9b334a45a8ff | 541 | |
| bogdanm | 0:9b334a45a8ff | 542 | return 1; // OK |
| bogdanm | 0:9b334a45a8ff | 543 | } |
| bogdanm | 0:9b334a45a8ff | 544 | #endif |
| bogdanm | 0:9b334a45a8ff | 545 | |
| bogdanm | 0:9b334a45a8ff | 546 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 547 | /* PLL (clocked by HSI) used as System clock source */ |
| bogdanm | 0:9b334a45a8ff | 548 | /******************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 549 | uint8_t SetSysClock_PLL_HSI(void) |
| bogdanm | 0:9b334a45a8ff | 550 | { |
| bogdanm | 0:9b334a45a8ff | 551 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| bogdanm | 0:9b334a45a8ff | 552 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| bogdanm | 0:9b334a45a8ff | 553 | |
| bogdanm | 0:9b334a45a8ff | 554 | /* The voltage scaling allows optimizing the power consumption when the device is |
| bogdanm | 0:9b334a45a8ff | 555 | clocked below the maximum system frequency, to update the voltage scaling value |
| bogdanm | 0:9b334a45a8ff | 556 | regarding system frequency refer to product datasheet. */ |
| bogdanm | 0:9b334a45a8ff | 557 | __PWR_CLK_ENABLE(); |
| bogdanm | 0:9b334a45a8ff | 558 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
| bogdanm | 0:9b334a45a8ff | 559 | |
| bogdanm | 0:9b334a45a8ff | 560 | /* Enable HSI oscillator and activate PLL with HSI as source */ |
| bogdanm | 0:9b334a45a8ff | 561 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
| bogdanm | 0:9b334a45a8ff | 562 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
| bogdanm | 0:9b334a45a8ff | 563 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
| bogdanm | 0:9b334a45a8ff | 564 | // SYSCLK = 32 MHz ((16 MHz * 4) / 2) |
| bogdanm | 0:9b334a45a8ff | 565 | // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible |
| bogdanm | 0:9b334a45a8ff | 566 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| bogdanm | 0:9b334a45a8ff | 567 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
| bogdanm | 0:9b334a45a8ff | 568 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4; |
| bogdanm | 0:9b334a45a8ff | 569 | RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2; |
| bogdanm | 0:9b334a45a8ff | 570 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
| bogdanm | 0:9b334a45a8ff | 571 | { |
| bogdanm | 0:9b334a45a8ff | 572 | return 0; // FAIL |
| bogdanm | 0:9b334a45a8ff | 573 | } |
| bogdanm | 0:9b334a45a8ff | 574 | |
| bogdanm | 0:9b334a45a8ff | 575 | /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */ |
| bogdanm | 0:9b334a45a8ff | 576 | while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {}; |
| bogdanm | 0:9b334a45a8ff | 577 | |
| bogdanm | 0:9b334a45a8ff | 578 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
| bogdanm | 0:9b334a45a8ff | 579 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
| bogdanm | 0:9b334a45a8ff | 580 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz |
| bogdanm | 0:9b334a45a8ff | 581 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz |
| bogdanm | 0:9b334a45a8ff | 582 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
| bogdanm | 0:9b334a45a8ff | 583 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
| bogdanm | 0:9b334a45a8ff | 584 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
| bogdanm | 0:9b334a45a8ff | 585 | { |
| bogdanm | 0:9b334a45a8ff | 586 | return 0; // FAIL |
| bogdanm | 0:9b334a45a8ff | 587 | } |
| bogdanm | 0:9b334a45a8ff | 588 | |
| bogdanm | 0:9b334a45a8ff | 589 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
| bogdanm | 0:9b334a45a8ff | 590 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz |
| bogdanm | 0:9b334a45a8ff | 591 | |
| bogdanm | 0:9b334a45a8ff | 592 | return 1; // OK |
| bogdanm | 0:9b334a45a8ff | 593 | } |
| bogdanm | 0:9b334a45a8ff | 594 | |
| bogdanm | 0:9b334a45a8ff | 595 | /** |
| bogdanm | 0:9b334a45a8ff | 596 | * @} |
| bogdanm | 0:9b334a45a8ff | 597 | */ |
| bogdanm | 0:9b334a45a8ff | 598 | |
| bogdanm | 0:9b334a45a8ff | 599 | /** |
| bogdanm | 0:9b334a45a8ff | 600 | * @} |
| bogdanm | 0:9b334a45a8ff | 601 | */ |
| bogdanm | 0:9b334a45a8ff | 602 | |
| bogdanm | 0:9b334a45a8ff | 603 | /** |
| bogdanm | 0:9b334a45a8ff | 604 | * @} |
| bogdanm | 0:9b334a45a8ff | 605 | */ |
| bogdanm | 0:9b334a45a8ff | 606 | |
| bogdanm | 0:9b334a45a8ff | 607 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |