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mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h@15:a81a8d6c1dfe, 2015-11-04 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Nov 04 16:30:11 2015 +0000
- Revision:
- 15:a81a8d6c1dfe
Synchronized with git revision 46af745ef4405614c3fa49abbd9a706a362ea514
Full URL: https://github.com/mbedmicro/mbed/commit/46af745ef4405614c3fa49abbd9a706a362ea514/
Renamed TARGET_SAM_CortexM0+ to TARGET_SAM_CortexM0P for compatiblity with online compiler
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 15:a81a8d6c1dfe | 1 | /** |
| mbed_official | 15:a81a8d6c1dfe | 2 | * \file |
| mbed_official | 15:a81a8d6c1dfe | 3 | * |
| mbed_official | 15:a81a8d6c1dfe | 4 | * \brief Component description for ADC |
| mbed_official | 15:a81a8d6c1dfe | 5 | * |
| mbed_official | 15:a81a8d6c1dfe | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
| mbed_official | 15:a81a8d6c1dfe | 7 | * |
| mbed_official | 15:a81a8d6c1dfe | 8 | * \asf_license_start |
| mbed_official | 15:a81a8d6c1dfe | 9 | * |
| mbed_official | 15:a81a8d6c1dfe | 10 | * \page License |
| mbed_official | 15:a81a8d6c1dfe | 11 | * |
| mbed_official | 15:a81a8d6c1dfe | 12 | * Redistribution and use in source and binary forms, with or without |
| mbed_official | 15:a81a8d6c1dfe | 13 | * modification, are permitted provided that the following conditions are met: |
| mbed_official | 15:a81a8d6c1dfe | 14 | * |
| mbed_official | 15:a81a8d6c1dfe | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 15:a81a8d6c1dfe | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 15:a81a8d6c1dfe | 17 | * |
| mbed_official | 15:a81a8d6c1dfe | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 15:a81a8d6c1dfe | 19 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 15:a81a8d6c1dfe | 20 | * and/or other materials provided with the distribution. |
| mbed_official | 15:a81a8d6c1dfe | 21 | * |
| mbed_official | 15:a81a8d6c1dfe | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| mbed_official | 15:a81a8d6c1dfe | 23 | * from this software without specific prior written permission. |
| mbed_official | 15:a81a8d6c1dfe | 24 | * |
| mbed_official | 15:a81a8d6c1dfe | 25 | * 4. This software may only be redistributed and used in connection with an |
| mbed_official | 15:a81a8d6c1dfe | 26 | * Atmel microcontroller product. |
| mbed_official | 15:a81a8d6c1dfe | 27 | * |
| mbed_official | 15:a81a8d6c1dfe | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| mbed_official | 15:a81a8d6c1dfe | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| mbed_official | 15:a81a8d6c1dfe | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| mbed_official | 15:a81a8d6c1dfe | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| mbed_official | 15:a81a8d6c1dfe | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 15:a81a8d6c1dfe | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| mbed_official | 15:a81a8d6c1dfe | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| mbed_official | 15:a81a8d6c1dfe | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| mbed_official | 15:a81a8d6c1dfe | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| mbed_official | 15:a81a8d6c1dfe | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| mbed_official | 15:a81a8d6c1dfe | 38 | * POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 15:a81a8d6c1dfe | 39 | * |
| mbed_official | 15:a81a8d6c1dfe | 40 | * \asf_license_stop |
| mbed_official | 15:a81a8d6c1dfe | 41 | * |
| mbed_official | 15:a81a8d6c1dfe | 42 | */ |
| mbed_official | 15:a81a8d6c1dfe | 43 | /* |
| mbed_official | 15:a81a8d6c1dfe | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
| mbed_official | 15:a81a8d6c1dfe | 45 | */ |
| mbed_official | 15:a81a8d6c1dfe | 46 | |
| mbed_official | 15:a81a8d6c1dfe | 47 | #ifndef _SAMD21_ADC_COMPONENT_ |
| mbed_official | 15:a81a8d6c1dfe | 48 | #define _SAMD21_ADC_COMPONENT_ |
| mbed_official | 15:a81a8d6c1dfe | 49 | |
| mbed_official | 15:a81a8d6c1dfe | 50 | /* ========================================================================== */ |
| mbed_official | 15:a81a8d6c1dfe | 51 | /** SOFTWARE API DEFINITION FOR ADC */ |
| mbed_official | 15:a81a8d6c1dfe | 52 | /* ========================================================================== */ |
| mbed_official | 15:a81a8d6c1dfe | 53 | /** \addtogroup SAMD21_ADC Analog Digital Converter */ |
| mbed_official | 15:a81a8d6c1dfe | 54 | /*@{*/ |
| mbed_official | 15:a81a8d6c1dfe | 55 | |
| mbed_official | 15:a81a8d6c1dfe | 56 | #define ADC_U2204 |
| mbed_official | 15:a81a8d6c1dfe | 57 | #define REV_ADC 0x120 |
| mbed_official | 15:a81a8d6c1dfe | 58 | |
| mbed_official | 15:a81a8d6c1dfe | 59 | /* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 60 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 61 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 62 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 63 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */ |
| mbed_official | 15:a81a8d6c1dfe | 64 | uint8_t ENABLE:1; /*!< bit: 1 Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 65 | uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ |
| mbed_official | 15:a81a8d6c1dfe | 66 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 67 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 68 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 69 | } ADC_CTRLA_Type; |
| mbed_official | 15:a81a8d6c1dfe | 70 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 71 | |
| mbed_official | 15:a81a8d6c1dfe | 72 | #define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ |
| mbed_official | 15:a81a8d6c1dfe | 73 | #define ADC_CTRLA_RESETVALUE 0x00ul /**< \brief (ADC_CTRLA reset_value) Control A */ |
| mbed_official | 15:a81a8d6c1dfe | 74 | |
| mbed_official | 15:a81a8d6c1dfe | 75 | #define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ |
| mbed_official | 15:a81a8d6c1dfe | 76 | #define ADC_CTRLA_SWRST (0x1ul << ADC_CTRLA_SWRST_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 77 | #define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 78 | #define ADC_CTRLA_ENABLE (0x1ul << ADC_CTRLA_ENABLE_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 79 | #define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ |
| mbed_official | 15:a81a8d6c1dfe | 80 | #define ADC_CTRLA_RUNSTDBY (0x1ul << ADC_CTRLA_RUNSTDBY_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 81 | #define ADC_CTRLA_MASK 0x07ul /**< \brief (ADC_CTRLA) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 82 | |
| mbed_official | 15:a81a8d6c1dfe | 83 | /* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 84 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 85 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 86 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 87 | uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ |
| mbed_official | 15:a81a8d6c1dfe | 88 | uint8_t :3; /*!< bit: 4.. 6 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 89 | uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 90 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 91 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 92 | } ADC_REFCTRL_Type; |
| mbed_official | 15:a81a8d6c1dfe | 93 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 94 | |
| mbed_official | 15:a81a8d6c1dfe | 95 | #define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ |
| mbed_official | 15:a81a8d6c1dfe | 96 | #define ADC_REFCTRL_RESETVALUE 0x00ul /**< \brief (ADC_REFCTRL reset_value) Reference Control */ |
| mbed_official | 15:a81a8d6c1dfe | 97 | |
| mbed_official | 15:a81a8d6c1dfe | 98 | #define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ |
| mbed_official | 15:a81a8d6c1dfe | 99 | #define ADC_REFCTRL_REFSEL_Msk (0xFul << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 100 | #define ADC_REFCTRL_REFSEL(value) ((ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 101 | #define ADC_REFCTRL_REFSEL_INT1V_Val 0x0ul /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ |
| mbed_official | 15:a81a8d6c1dfe | 102 | #define ADC_REFCTRL_REFSEL_INTVCC0_Val 0x1ul /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ |
| mbed_official | 15:a81a8d6c1dfe | 103 | #define ADC_REFCTRL_REFSEL_INTVCC1_Val 0x2ul /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ |
| mbed_official | 15:a81a8d6c1dfe | 104 | #define ADC_REFCTRL_REFSEL_AREFA_Val 0x3ul /**< \brief (ADC_REFCTRL) External reference */ |
| mbed_official | 15:a81a8d6c1dfe | 105 | #define ADC_REFCTRL_REFSEL_AREFB_Val 0x4ul /**< \brief (ADC_REFCTRL) External reference */ |
| mbed_official | 15:a81a8d6c1dfe | 106 | #define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 107 | #define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 108 | #define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 109 | #define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 110 | #define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 111 | #define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 112 | #define ADC_REFCTRL_REFCOMP (0x1ul << ADC_REFCTRL_REFCOMP_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 113 | #define ADC_REFCTRL_MASK 0x8Ful /**< \brief (ADC_REFCTRL) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 114 | |
| mbed_official | 15:a81a8d6c1dfe | 115 | /* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 116 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 117 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 118 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 119 | uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ |
| mbed_official | 15:a81a8d6c1dfe | 120 | uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ |
| mbed_official | 15:a81a8d6c1dfe | 121 | uint8_t :1; /*!< bit: 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 122 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 123 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 124 | } ADC_AVGCTRL_Type; |
| mbed_official | 15:a81a8d6c1dfe | 125 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 126 | |
| mbed_official | 15:a81a8d6c1dfe | 127 | #define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ |
| mbed_official | 15:a81a8d6c1dfe | 128 | #define ADC_AVGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_AVGCTRL reset_value) Average Control */ |
| mbed_official | 15:a81a8d6c1dfe | 129 | |
| mbed_official | 15:a81a8d6c1dfe | 130 | #define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ |
| mbed_official | 15:a81a8d6c1dfe | 131 | #define ADC_AVGCTRL_SAMPLENUM_Msk (0xFul << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 132 | #define ADC_AVGCTRL_SAMPLENUM(value) ((ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 133 | #define ADC_AVGCTRL_SAMPLENUM_1_Val 0x0ul /**< \brief (ADC_AVGCTRL) 1 sample */ |
| mbed_official | 15:a81a8d6c1dfe | 134 | #define ADC_AVGCTRL_SAMPLENUM_2_Val 0x1ul /**< \brief (ADC_AVGCTRL) 2 samples */ |
| mbed_official | 15:a81a8d6c1dfe | 135 | #define ADC_AVGCTRL_SAMPLENUM_4_Val 0x2ul /**< \brief (ADC_AVGCTRL) 4 samples */ |
| mbed_official | 15:a81a8d6c1dfe | 136 | #define ADC_AVGCTRL_SAMPLENUM_8_Val 0x3ul /**< \brief (ADC_AVGCTRL) 8 samples */ |
| mbed_official | 15:a81a8d6c1dfe | 137 | #define ADC_AVGCTRL_SAMPLENUM_16_Val 0x4ul /**< \brief (ADC_AVGCTRL) 16 samples */ |
| mbed_official | 15:a81a8d6c1dfe | 138 | #define ADC_AVGCTRL_SAMPLENUM_32_Val 0x5ul /**< \brief (ADC_AVGCTRL) 32 samples */ |
| mbed_official | 15:a81a8d6c1dfe | 139 | #define ADC_AVGCTRL_SAMPLENUM_64_Val 0x6ul /**< \brief (ADC_AVGCTRL) 64 samples */ |
| mbed_official | 15:a81a8d6c1dfe | 140 | #define ADC_AVGCTRL_SAMPLENUM_128_Val 0x7ul /**< \brief (ADC_AVGCTRL) 128 samples */ |
| mbed_official | 15:a81a8d6c1dfe | 141 | #define ADC_AVGCTRL_SAMPLENUM_256_Val 0x8ul /**< \brief (ADC_AVGCTRL) 256 samples */ |
| mbed_official | 15:a81a8d6c1dfe | 142 | #define ADC_AVGCTRL_SAMPLENUM_512_Val 0x9ul /**< \brief (ADC_AVGCTRL) 512 samples */ |
| mbed_official | 15:a81a8d6c1dfe | 143 | #define ADC_AVGCTRL_SAMPLENUM_1024_Val 0xAul /**< \brief (ADC_AVGCTRL) 1024 samples */ |
| mbed_official | 15:a81a8d6c1dfe | 144 | #define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 145 | #define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 146 | #define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 147 | #define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 148 | #define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 149 | #define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 150 | #define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 151 | #define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 152 | #define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 153 | #define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 154 | #define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 155 | #define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ |
| mbed_official | 15:a81a8d6c1dfe | 156 | #define ADC_AVGCTRL_ADJRES_Msk (0x7ul << ADC_AVGCTRL_ADJRES_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 157 | #define ADC_AVGCTRL_ADJRES(value) ((ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 158 | #define ADC_AVGCTRL_MASK 0x7Ful /**< \brief (ADC_AVGCTRL) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 159 | |
| mbed_official | 15:a81a8d6c1dfe | 160 | /* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 161 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 162 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 163 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 164 | uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ |
| mbed_official | 15:a81a8d6c1dfe | 165 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 166 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 167 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 168 | } ADC_SAMPCTRL_Type; |
| mbed_official | 15:a81a8d6c1dfe | 169 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 170 | |
| mbed_official | 15:a81a8d6c1dfe | 171 | #define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ |
| mbed_official | 15:a81a8d6c1dfe | 172 | #define ADC_SAMPCTRL_RESETVALUE 0x00ul /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ |
| mbed_official | 15:a81a8d6c1dfe | 173 | |
| mbed_official | 15:a81a8d6c1dfe | 174 | #define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ |
| mbed_official | 15:a81a8d6c1dfe | 175 | #define ADC_SAMPCTRL_SAMPLEN_Msk (0x3Ful << ADC_SAMPCTRL_SAMPLEN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 176 | #define ADC_SAMPCTRL_SAMPLEN(value) ((ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 177 | #define ADC_SAMPCTRL_MASK 0x3Ful /**< \brief (ADC_SAMPCTRL) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 178 | |
| mbed_official | 15:a81a8d6c1dfe | 179 | /* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 180 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 181 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 182 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 183 | uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ |
| mbed_official | 15:a81a8d6c1dfe | 184 | uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ |
| mbed_official | 15:a81a8d6c1dfe | 185 | uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ |
| mbed_official | 15:a81a8d6c1dfe | 186 | uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ |
| mbed_official | 15:a81a8d6c1dfe | 187 | uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ |
| mbed_official | 15:a81a8d6c1dfe | 188 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 189 | uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ |
| mbed_official | 15:a81a8d6c1dfe | 190 | uint16_t :5; /*!< bit: 11..15 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 191 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 192 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 193 | } ADC_CTRLB_Type; |
| mbed_official | 15:a81a8d6c1dfe | 194 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 195 | |
| mbed_official | 15:a81a8d6c1dfe | 196 | #define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ |
| mbed_official | 15:a81a8d6c1dfe | 197 | #define ADC_CTRLB_RESETVALUE 0x0000ul /**< \brief (ADC_CTRLB reset_value) Control B */ |
| mbed_official | 15:a81a8d6c1dfe | 198 | |
| mbed_official | 15:a81a8d6c1dfe | 199 | #define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ |
| mbed_official | 15:a81a8d6c1dfe | 200 | #define ADC_CTRLB_DIFFMODE (0x1ul << ADC_CTRLB_DIFFMODE_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 201 | #define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ |
| mbed_official | 15:a81a8d6c1dfe | 202 | #define ADC_CTRLB_LEFTADJ (0x1ul << ADC_CTRLB_LEFTADJ_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 203 | #define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ |
| mbed_official | 15:a81a8d6c1dfe | 204 | #define ADC_CTRLB_FREERUN (0x1ul << ADC_CTRLB_FREERUN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 205 | #define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ |
| mbed_official | 15:a81a8d6c1dfe | 206 | #define ADC_CTRLB_CORREN (0x1ul << ADC_CTRLB_CORREN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 207 | #define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ |
| mbed_official | 15:a81a8d6c1dfe | 208 | #define ADC_CTRLB_RESSEL_Msk (0x3ul << ADC_CTRLB_RESSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 209 | #define ADC_CTRLB_RESSEL(value) ((ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 210 | #define ADC_CTRLB_RESSEL_12BIT_Val 0x0ul /**< \brief (ADC_CTRLB) 12-bit result */ |
| mbed_official | 15:a81a8d6c1dfe | 211 | #define ADC_CTRLB_RESSEL_16BIT_Val 0x1ul /**< \brief (ADC_CTRLB) For averaging mode output */ |
| mbed_official | 15:a81a8d6c1dfe | 212 | #define ADC_CTRLB_RESSEL_10BIT_Val 0x2ul /**< \brief (ADC_CTRLB) 10-bit result */ |
| mbed_official | 15:a81a8d6c1dfe | 213 | #define ADC_CTRLB_RESSEL_8BIT_Val 0x3ul /**< \brief (ADC_CTRLB) 8-bit result */ |
| mbed_official | 15:a81a8d6c1dfe | 214 | #define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 215 | #define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 216 | #define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 217 | #define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 218 | #define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ |
| mbed_official | 15:a81a8d6c1dfe | 219 | #define ADC_CTRLB_PRESCALER_Msk (0x7ul << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 220 | #define ADC_CTRLB_PRESCALER(value) ((ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 221 | #define ADC_CTRLB_PRESCALER_DIV4_Val 0x0ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ |
| mbed_official | 15:a81a8d6c1dfe | 222 | #define ADC_CTRLB_PRESCALER_DIV8_Val 0x1ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ |
| mbed_official | 15:a81a8d6c1dfe | 223 | #define ADC_CTRLB_PRESCALER_DIV16_Val 0x2ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ |
| mbed_official | 15:a81a8d6c1dfe | 224 | #define ADC_CTRLB_PRESCALER_DIV32_Val 0x3ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ |
| mbed_official | 15:a81a8d6c1dfe | 225 | #define ADC_CTRLB_PRESCALER_DIV64_Val 0x4ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ |
| mbed_official | 15:a81a8d6c1dfe | 226 | #define ADC_CTRLB_PRESCALER_DIV128_Val 0x5ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ |
| mbed_official | 15:a81a8d6c1dfe | 227 | #define ADC_CTRLB_PRESCALER_DIV256_Val 0x6ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ |
| mbed_official | 15:a81a8d6c1dfe | 228 | #define ADC_CTRLB_PRESCALER_DIV512_Val 0x7ul /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ |
| mbed_official | 15:a81a8d6c1dfe | 229 | #define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 230 | #define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 231 | #define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 232 | #define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 233 | #define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 234 | #define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 235 | #define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 236 | #define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 237 | #define ADC_CTRLB_MASK 0x073Ful /**< \brief (ADC_CTRLB) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 238 | |
| mbed_official | 15:a81a8d6c1dfe | 239 | /* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 240 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 241 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 242 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 243 | uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ |
| mbed_official | 15:a81a8d6c1dfe | 244 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 245 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 246 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 247 | } ADC_WINCTRL_Type; |
| mbed_official | 15:a81a8d6c1dfe | 248 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 249 | |
| mbed_official | 15:a81a8d6c1dfe | 250 | #define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ |
| mbed_official | 15:a81a8d6c1dfe | 251 | #define ADC_WINCTRL_RESETVALUE 0x00ul /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ |
| mbed_official | 15:a81a8d6c1dfe | 252 | |
| mbed_official | 15:a81a8d6c1dfe | 253 | #define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ |
| mbed_official | 15:a81a8d6c1dfe | 254 | #define ADC_WINCTRL_WINMODE_Msk (0x7ul << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 255 | #define ADC_WINCTRL_WINMODE(value) ((ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 256 | #define ADC_WINCTRL_WINMODE_DISABLE_Val 0x0ul /**< \brief (ADC_WINCTRL) No window mode (default) */ |
| mbed_official | 15:a81a8d6c1dfe | 257 | #define ADC_WINCTRL_WINMODE_MODE1_Val 0x1ul /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ |
| mbed_official | 15:a81a8d6c1dfe | 258 | #define ADC_WINCTRL_WINMODE_MODE2_Val 0x2ul /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ |
| mbed_official | 15:a81a8d6c1dfe | 259 | #define ADC_WINCTRL_WINMODE_MODE3_Val 0x3ul /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ |
| mbed_official | 15:a81a8d6c1dfe | 260 | #define ADC_WINCTRL_WINMODE_MODE4_Val 0x4ul /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ |
| mbed_official | 15:a81a8d6c1dfe | 261 | #define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 262 | #define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 263 | #define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 264 | #define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 265 | #define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 266 | #define ADC_WINCTRL_MASK 0x07ul /**< \brief (ADC_WINCTRL) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 267 | |
| mbed_official | 15:a81a8d6c1dfe | 268 | /* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 269 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 270 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 271 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 272 | uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ |
| mbed_official | 15:a81a8d6c1dfe | 273 | uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ |
| mbed_official | 15:a81a8d6c1dfe | 274 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 275 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 276 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 277 | } ADC_SWTRIG_Type; |
| mbed_official | 15:a81a8d6c1dfe | 278 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 279 | |
| mbed_official | 15:a81a8d6c1dfe | 280 | #define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ |
| mbed_official | 15:a81a8d6c1dfe | 281 | #define ADC_SWTRIG_RESETVALUE 0x00ul /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ |
| mbed_official | 15:a81a8d6c1dfe | 282 | |
| mbed_official | 15:a81a8d6c1dfe | 283 | #define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ |
| mbed_official | 15:a81a8d6c1dfe | 284 | #define ADC_SWTRIG_FLUSH (0x1ul << ADC_SWTRIG_FLUSH_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 285 | #define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ |
| mbed_official | 15:a81a8d6c1dfe | 286 | #define ADC_SWTRIG_START (0x1ul << ADC_SWTRIG_START_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 287 | #define ADC_SWTRIG_MASK 0x03ul /**< \brief (ADC_SWTRIG) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 288 | |
| mbed_official | 15:a81a8d6c1dfe | 289 | /* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 290 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 291 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 292 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 293 | uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ |
| mbed_official | 15:a81a8d6c1dfe | 294 | uint32_t :3; /*!< bit: 5.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 295 | uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ |
| mbed_official | 15:a81a8d6c1dfe | 296 | uint32_t :3; /*!< bit: 13..15 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 297 | uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ |
| mbed_official | 15:a81a8d6c1dfe | 298 | uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ |
| mbed_official | 15:a81a8d6c1dfe | 299 | uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ |
| mbed_official | 15:a81a8d6c1dfe | 300 | uint32_t :4; /*!< bit: 28..31 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 301 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 302 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 303 | } ADC_INPUTCTRL_Type; |
| mbed_official | 15:a81a8d6c1dfe | 304 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 305 | |
| mbed_official | 15:a81a8d6c1dfe | 306 | #define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ |
| mbed_official | 15:a81a8d6c1dfe | 307 | #define ADC_INPUTCTRL_RESETVALUE 0x00000000ul /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ |
| mbed_official | 15:a81a8d6c1dfe | 308 | |
| mbed_official | 15:a81a8d6c1dfe | 309 | #define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ |
| mbed_official | 15:a81a8d6c1dfe | 310 | #define ADC_INPUTCTRL_MUXPOS_Msk (0x1Ful << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 311 | #define ADC_INPUTCTRL_MUXPOS(value) ((ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 312 | #define ADC_INPUTCTRL_MUXPOS_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 313 | #define ADC_INPUTCTRL_MUXPOS_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 314 | #define ADC_INPUTCTRL_MUXPOS_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 315 | #define ADC_INPUTCTRL_MUXPOS_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 316 | #define ADC_INPUTCTRL_MUXPOS_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 317 | #define ADC_INPUTCTRL_MUXPOS_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 318 | #define ADC_INPUTCTRL_MUXPOS_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 319 | #define ADC_INPUTCTRL_MUXPOS_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 320 | #define ADC_INPUTCTRL_MUXPOS_PIN8_Val 0x8ul /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 321 | #define ADC_INPUTCTRL_MUXPOS_PIN9_Val 0x9ul /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 322 | #define ADC_INPUTCTRL_MUXPOS_PIN10_Val 0xAul /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 323 | #define ADC_INPUTCTRL_MUXPOS_PIN11_Val 0xBul /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 324 | #define ADC_INPUTCTRL_MUXPOS_PIN12_Val 0xCul /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 325 | #define ADC_INPUTCTRL_MUXPOS_PIN13_Val 0xDul /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 326 | #define ADC_INPUTCTRL_MUXPOS_PIN14_Val 0xEul /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 327 | #define ADC_INPUTCTRL_MUXPOS_PIN15_Val 0xFul /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 328 | #define ADC_INPUTCTRL_MUXPOS_PIN16_Val 0x10ul /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 329 | #define ADC_INPUTCTRL_MUXPOS_PIN17_Val 0x11ul /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 330 | #define ADC_INPUTCTRL_MUXPOS_PIN18_Val 0x12ul /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 331 | #define ADC_INPUTCTRL_MUXPOS_PIN19_Val 0x13ul /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 332 | #define ADC_INPUTCTRL_MUXPOS_TEMP_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Temperature Reference */ |
| mbed_official | 15:a81a8d6c1dfe | 333 | #define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val 0x19ul /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ |
| mbed_official | 15:a81a8d6c1dfe | 334 | #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val 0x1Aul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ |
| mbed_official | 15:a81a8d6c1dfe | 335 | #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val 0x1Bul /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ |
| mbed_official | 15:a81a8d6c1dfe | 336 | #define ADC_INPUTCTRL_MUXPOS_DAC_Val 0x1Cul /**< \brief (ADC_INPUTCTRL) DAC Output */ |
| mbed_official | 15:a81a8d6c1dfe | 337 | #define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 338 | #define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 339 | #define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 340 | #define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 341 | #define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 342 | #define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 343 | #define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 344 | #define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 345 | #define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 346 | #define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 347 | #define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 348 | #define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 349 | #define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 350 | #define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 351 | #define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 352 | #define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 353 | #define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 354 | #define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 355 | #define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 356 | #define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 357 | #define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 358 | #define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 359 | #define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 360 | #define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 361 | #define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 362 | #define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ |
| mbed_official | 15:a81a8d6c1dfe | 363 | #define ADC_INPUTCTRL_MUXNEG_Msk (0x1Ful << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 364 | #define ADC_INPUTCTRL_MUXNEG(value) ((ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 365 | #define ADC_INPUTCTRL_MUXNEG_PIN0_Val 0x0ul /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 366 | #define ADC_INPUTCTRL_MUXNEG_PIN1_Val 0x1ul /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 367 | #define ADC_INPUTCTRL_MUXNEG_PIN2_Val 0x2ul /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 368 | #define ADC_INPUTCTRL_MUXNEG_PIN3_Val 0x3ul /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 369 | #define ADC_INPUTCTRL_MUXNEG_PIN4_Val 0x4ul /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 370 | #define ADC_INPUTCTRL_MUXNEG_PIN5_Val 0x5ul /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 371 | #define ADC_INPUTCTRL_MUXNEG_PIN6_Val 0x6ul /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 372 | #define ADC_INPUTCTRL_MUXNEG_PIN7_Val 0x7ul /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ |
| mbed_official | 15:a81a8d6c1dfe | 373 | #define ADC_INPUTCTRL_MUXNEG_GND_Val 0x18ul /**< \brief (ADC_INPUTCTRL) Internal Ground */ |
| mbed_official | 15:a81a8d6c1dfe | 374 | #define ADC_INPUTCTRL_MUXNEG_IOGND_Val 0x19ul /**< \brief (ADC_INPUTCTRL) I/O Ground */ |
| mbed_official | 15:a81a8d6c1dfe | 375 | #define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 376 | #define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 377 | #define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 378 | #define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 379 | #define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 380 | #define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 381 | #define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 382 | #define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 383 | #define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 384 | #define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 385 | #define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ |
| mbed_official | 15:a81a8d6c1dfe | 386 | #define ADC_INPUTCTRL_INPUTSCAN_Msk (0xFul << ADC_INPUTCTRL_INPUTSCAN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 387 | #define ADC_INPUTCTRL_INPUTSCAN(value) ((ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 388 | #define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ |
| mbed_official | 15:a81a8d6c1dfe | 389 | #define ADC_INPUTCTRL_INPUTOFFSET_Msk (0xFul << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 390 | #define ADC_INPUTCTRL_INPUTOFFSET(value) ((ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 391 | #define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ |
| mbed_official | 15:a81a8d6c1dfe | 392 | #define ADC_INPUTCTRL_GAIN_Msk (0xFul << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 393 | #define ADC_INPUTCTRL_GAIN(value) ((ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 394 | #define ADC_INPUTCTRL_GAIN_1X_Val 0x0ul /**< \brief (ADC_INPUTCTRL) 1x */ |
| mbed_official | 15:a81a8d6c1dfe | 395 | #define ADC_INPUTCTRL_GAIN_2X_Val 0x1ul /**< \brief (ADC_INPUTCTRL) 2x */ |
| mbed_official | 15:a81a8d6c1dfe | 396 | #define ADC_INPUTCTRL_GAIN_4X_Val 0x2ul /**< \brief (ADC_INPUTCTRL) 4x */ |
| mbed_official | 15:a81a8d6c1dfe | 397 | #define ADC_INPUTCTRL_GAIN_8X_Val 0x3ul /**< \brief (ADC_INPUTCTRL) 8x */ |
| mbed_official | 15:a81a8d6c1dfe | 398 | #define ADC_INPUTCTRL_GAIN_16X_Val 0x4ul /**< \brief (ADC_INPUTCTRL) 16x */ |
| mbed_official | 15:a81a8d6c1dfe | 399 | #define ADC_INPUTCTRL_GAIN_DIV2_Val 0xFul /**< \brief (ADC_INPUTCTRL) 1/2x */ |
| mbed_official | 15:a81a8d6c1dfe | 400 | #define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 401 | #define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 402 | #define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 403 | #define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 404 | #define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 405 | #define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 406 | #define ADC_INPUTCTRL_MASK 0x0FFF1F1Ful /**< \brief (ADC_INPUTCTRL) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 407 | |
| mbed_official | 15:a81a8d6c1dfe | 408 | /* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 409 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 410 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 411 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 412 | uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ |
| mbed_official | 15:a81a8d6c1dfe | 413 | uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ |
| mbed_official | 15:a81a8d6c1dfe | 414 | uint8_t :2; /*!< bit: 2.. 3 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 415 | uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ |
| mbed_official | 15:a81a8d6c1dfe | 416 | uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ |
| mbed_official | 15:a81a8d6c1dfe | 417 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 418 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 419 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 420 | } ADC_EVCTRL_Type; |
| mbed_official | 15:a81a8d6c1dfe | 421 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 422 | |
| mbed_official | 15:a81a8d6c1dfe | 423 | #define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ |
| mbed_official | 15:a81a8d6c1dfe | 424 | #define ADC_EVCTRL_RESETVALUE 0x00ul /**< \brief (ADC_EVCTRL reset_value) Event Control */ |
| mbed_official | 15:a81a8d6c1dfe | 425 | |
| mbed_official | 15:a81a8d6c1dfe | 426 | #define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ |
| mbed_official | 15:a81a8d6c1dfe | 427 | #define ADC_EVCTRL_STARTEI (0x1ul << ADC_EVCTRL_STARTEI_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 428 | #define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ |
| mbed_official | 15:a81a8d6c1dfe | 429 | #define ADC_EVCTRL_SYNCEI (0x1ul << ADC_EVCTRL_SYNCEI_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 430 | #define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ |
| mbed_official | 15:a81a8d6c1dfe | 431 | #define ADC_EVCTRL_RESRDYEO (0x1ul << ADC_EVCTRL_RESRDYEO_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 432 | #define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ |
| mbed_official | 15:a81a8d6c1dfe | 433 | #define ADC_EVCTRL_WINMONEO (0x1ul << ADC_EVCTRL_WINMONEO_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 434 | #define ADC_EVCTRL_MASK 0x33ul /**< \brief (ADC_EVCTRL) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 435 | |
| mbed_official | 15:a81a8d6c1dfe | 436 | /* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 437 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 438 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 439 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 440 | uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 441 | uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 442 | uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 443 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 444 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 445 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 446 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 447 | } ADC_INTENCLR_Type; |
| mbed_official | 15:a81a8d6c1dfe | 448 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 449 | |
| mbed_official | 15:a81a8d6c1dfe | 450 | #define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ |
| mbed_official | 15:a81a8d6c1dfe | 451 | #define ADC_INTENCLR_RESETVALUE 0x00ul /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ |
| mbed_official | 15:a81a8d6c1dfe | 452 | |
| mbed_official | 15:a81a8d6c1dfe | 453 | #define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 454 | #define ADC_INTENCLR_RESRDY (0x1ul << ADC_INTENCLR_RESRDY_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 455 | #define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 456 | #define ADC_INTENCLR_OVERRUN (0x1ul << ADC_INTENCLR_OVERRUN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 457 | #define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 458 | #define ADC_INTENCLR_WINMON (0x1ul << ADC_INTENCLR_WINMON_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 459 | #define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 460 | #define ADC_INTENCLR_SYNCRDY (0x1ul << ADC_INTENCLR_SYNCRDY_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 461 | #define ADC_INTENCLR_MASK 0x0Ful /**< \brief (ADC_INTENCLR) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 462 | |
| mbed_official | 15:a81a8d6c1dfe | 463 | /* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 464 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 465 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 466 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 467 | uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 468 | uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 469 | uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 470 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 471 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 472 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 473 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 474 | } ADC_INTENSET_Type; |
| mbed_official | 15:a81a8d6c1dfe | 475 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 476 | |
| mbed_official | 15:a81a8d6c1dfe | 477 | #define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ |
| mbed_official | 15:a81a8d6c1dfe | 478 | #define ADC_INTENSET_RESETVALUE 0x00ul /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ |
| mbed_official | 15:a81a8d6c1dfe | 479 | |
| mbed_official | 15:a81a8d6c1dfe | 480 | #define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 481 | #define ADC_INTENSET_RESRDY (0x1ul << ADC_INTENSET_RESRDY_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 482 | #define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 483 | #define ADC_INTENSET_OVERRUN (0x1ul << ADC_INTENSET_OVERRUN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 484 | #define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 485 | #define ADC_INTENSET_WINMON (0x1ul << ADC_INTENSET_WINMON_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 486 | #define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ |
| mbed_official | 15:a81a8d6c1dfe | 487 | #define ADC_INTENSET_SYNCRDY (0x1ul << ADC_INTENSET_SYNCRDY_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 488 | #define ADC_INTENSET_MASK 0x0Ful /**< \brief (ADC_INTENSET) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 489 | |
| mbed_official | 15:a81a8d6c1dfe | 490 | /* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 491 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 492 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 493 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 494 | uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ |
| mbed_official | 15:a81a8d6c1dfe | 495 | uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ |
| mbed_official | 15:a81a8d6c1dfe | 496 | uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ |
| mbed_official | 15:a81a8d6c1dfe | 497 | uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ |
| mbed_official | 15:a81a8d6c1dfe | 498 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 499 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 500 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 501 | } ADC_INTFLAG_Type; |
| mbed_official | 15:a81a8d6c1dfe | 502 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 503 | |
| mbed_official | 15:a81a8d6c1dfe | 504 | #define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ |
| mbed_official | 15:a81a8d6c1dfe | 505 | #define ADC_INTFLAG_RESETVALUE 0x00ul /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
| mbed_official | 15:a81a8d6c1dfe | 506 | |
| mbed_official | 15:a81a8d6c1dfe | 507 | #define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ |
| mbed_official | 15:a81a8d6c1dfe | 508 | #define ADC_INTFLAG_RESRDY (0x1ul << ADC_INTFLAG_RESRDY_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 509 | #define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ |
| mbed_official | 15:a81a8d6c1dfe | 510 | #define ADC_INTFLAG_OVERRUN (0x1ul << ADC_INTFLAG_OVERRUN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 511 | #define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ |
| mbed_official | 15:a81a8d6c1dfe | 512 | #define ADC_INTFLAG_WINMON (0x1ul << ADC_INTFLAG_WINMON_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 513 | #define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ |
| mbed_official | 15:a81a8d6c1dfe | 514 | #define ADC_INTFLAG_SYNCRDY (0x1ul << ADC_INTFLAG_SYNCRDY_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 515 | #define ADC_INTFLAG_MASK 0x0Ful /**< \brief (ADC_INTFLAG) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 516 | |
| mbed_official | 15:a81a8d6c1dfe | 517 | /* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 518 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 519 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 520 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 521 | uint8_t :7; /*!< bit: 0.. 6 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 522 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ |
| mbed_official | 15:a81a8d6c1dfe | 523 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 524 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 525 | } ADC_STATUS_Type; |
| mbed_official | 15:a81a8d6c1dfe | 526 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 527 | |
| mbed_official | 15:a81a8d6c1dfe | 528 | #define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ |
| mbed_official | 15:a81a8d6c1dfe | 529 | #define ADC_STATUS_RESETVALUE 0x00ul /**< \brief (ADC_STATUS reset_value) Status */ |
| mbed_official | 15:a81a8d6c1dfe | 530 | |
| mbed_official | 15:a81a8d6c1dfe | 531 | #define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ |
| mbed_official | 15:a81a8d6c1dfe | 532 | #define ADC_STATUS_SYNCBUSY (0x1ul << ADC_STATUS_SYNCBUSY_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 533 | #define ADC_STATUS_MASK 0x80ul /**< \brief (ADC_STATUS) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 534 | |
| mbed_official | 15:a81a8d6c1dfe | 535 | /* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 536 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 537 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 538 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 539 | uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ |
| mbed_official | 15:a81a8d6c1dfe | 540 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 541 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 542 | } ADC_RESULT_Type; |
| mbed_official | 15:a81a8d6c1dfe | 543 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 544 | |
| mbed_official | 15:a81a8d6c1dfe | 545 | #define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ |
| mbed_official | 15:a81a8d6c1dfe | 546 | #define ADC_RESULT_RESETVALUE 0x0000ul /**< \brief (ADC_RESULT reset_value) Result */ |
| mbed_official | 15:a81a8d6c1dfe | 547 | |
| mbed_official | 15:a81a8d6c1dfe | 548 | #define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ |
| mbed_official | 15:a81a8d6c1dfe | 549 | #define ADC_RESULT_RESULT_Msk (0xFFFFul << ADC_RESULT_RESULT_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 550 | #define ADC_RESULT_RESULT(value) ((ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 551 | #define ADC_RESULT_MASK 0xFFFFul /**< \brief (ADC_RESULT) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 552 | |
| mbed_official | 15:a81a8d6c1dfe | 553 | /* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 554 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 555 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 556 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 557 | uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ |
| mbed_official | 15:a81a8d6c1dfe | 558 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 559 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 560 | } ADC_WINLT_Type; |
| mbed_official | 15:a81a8d6c1dfe | 561 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 562 | |
| mbed_official | 15:a81a8d6c1dfe | 563 | #define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ |
| mbed_official | 15:a81a8d6c1dfe | 564 | #define ADC_WINLT_RESETVALUE 0x0000ul /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ |
| mbed_official | 15:a81a8d6c1dfe | 565 | |
| mbed_official | 15:a81a8d6c1dfe | 566 | #define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ |
| mbed_official | 15:a81a8d6c1dfe | 567 | #define ADC_WINLT_WINLT_Msk (0xFFFFul << ADC_WINLT_WINLT_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 568 | #define ADC_WINLT_WINLT(value) ((ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 569 | #define ADC_WINLT_MASK 0xFFFFul /**< \brief (ADC_WINLT) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 570 | |
| mbed_official | 15:a81a8d6c1dfe | 571 | /* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 572 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 573 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 574 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 575 | uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ |
| mbed_official | 15:a81a8d6c1dfe | 576 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 577 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 578 | } ADC_WINUT_Type; |
| mbed_official | 15:a81a8d6c1dfe | 579 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 580 | |
| mbed_official | 15:a81a8d6c1dfe | 581 | #define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ |
| mbed_official | 15:a81a8d6c1dfe | 582 | #define ADC_WINUT_RESETVALUE 0x0000ul /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ |
| mbed_official | 15:a81a8d6c1dfe | 583 | |
| mbed_official | 15:a81a8d6c1dfe | 584 | #define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ |
| mbed_official | 15:a81a8d6c1dfe | 585 | #define ADC_WINUT_WINUT_Msk (0xFFFFul << ADC_WINUT_WINUT_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 586 | #define ADC_WINUT_WINUT(value) ((ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 587 | #define ADC_WINUT_MASK 0xFFFFul /**< \brief (ADC_WINUT) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 588 | |
| mbed_official | 15:a81a8d6c1dfe | 589 | /* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 590 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 591 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 592 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 593 | uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ |
| mbed_official | 15:a81a8d6c1dfe | 594 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 595 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 596 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 597 | } ADC_GAINCORR_Type; |
| mbed_official | 15:a81a8d6c1dfe | 598 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 599 | |
| mbed_official | 15:a81a8d6c1dfe | 600 | #define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ |
| mbed_official | 15:a81a8d6c1dfe | 601 | #define ADC_GAINCORR_RESETVALUE 0x0000ul /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ |
| mbed_official | 15:a81a8d6c1dfe | 602 | |
| mbed_official | 15:a81a8d6c1dfe | 603 | #define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ |
| mbed_official | 15:a81a8d6c1dfe | 604 | #define ADC_GAINCORR_GAINCORR_Msk (0xFFFul << ADC_GAINCORR_GAINCORR_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 605 | #define ADC_GAINCORR_GAINCORR(value) ((ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 606 | #define ADC_GAINCORR_MASK 0x0FFFul /**< \brief (ADC_GAINCORR) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 607 | |
| mbed_official | 15:a81a8d6c1dfe | 608 | /* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 609 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 610 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 611 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 612 | uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ |
| mbed_official | 15:a81a8d6c1dfe | 613 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 614 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 615 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 616 | } ADC_OFFSETCORR_Type; |
| mbed_official | 15:a81a8d6c1dfe | 617 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 618 | |
| mbed_official | 15:a81a8d6c1dfe | 619 | #define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ |
| mbed_official | 15:a81a8d6c1dfe | 620 | #define ADC_OFFSETCORR_RESETVALUE 0x0000ul /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ |
| mbed_official | 15:a81a8d6c1dfe | 621 | |
| mbed_official | 15:a81a8d6c1dfe | 622 | #define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ |
| mbed_official | 15:a81a8d6c1dfe | 623 | #define ADC_OFFSETCORR_OFFSETCORR_Msk (0xFFFul << ADC_OFFSETCORR_OFFSETCORR_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 624 | #define ADC_OFFSETCORR_OFFSETCORR(value) ((ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 625 | #define ADC_OFFSETCORR_MASK 0x0FFFul /**< \brief (ADC_OFFSETCORR) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 626 | |
| mbed_official | 15:a81a8d6c1dfe | 627 | /* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 628 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 629 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 630 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 631 | uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ |
| mbed_official | 15:a81a8d6c1dfe | 632 | uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ |
| mbed_official | 15:a81a8d6c1dfe | 633 | uint16_t :5; /*!< bit: 11..15 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 634 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 635 | uint16_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 636 | } ADC_CALIB_Type; |
| mbed_official | 15:a81a8d6c1dfe | 637 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 638 | |
| mbed_official | 15:a81a8d6c1dfe | 639 | #define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ |
| mbed_official | 15:a81a8d6c1dfe | 640 | #define ADC_CALIB_RESETVALUE 0x0000ul /**< \brief (ADC_CALIB reset_value) Calibration */ |
| mbed_official | 15:a81a8d6c1dfe | 641 | |
| mbed_official | 15:a81a8d6c1dfe | 642 | #define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ |
| mbed_official | 15:a81a8d6c1dfe | 643 | #define ADC_CALIB_LINEARITY_CAL_Msk (0xFFul << ADC_CALIB_LINEARITY_CAL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 644 | #define ADC_CALIB_LINEARITY_CAL(value) ((ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 645 | #define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ |
| mbed_official | 15:a81a8d6c1dfe | 646 | #define ADC_CALIB_BIAS_CAL_Msk (0x7ul << ADC_CALIB_BIAS_CAL_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 647 | #define ADC_CALIB_BIAS_CAL(value) ((ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos))) |
| mbed_official | 15:a81a8d6c1dfe | 648 | #define ADC_CALIB_MASK 0x07FFul /**< \brief (ADC_CALIB) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 649 | |
| mbed_official | 15:a81a8d6c1dfe | 650 | /* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ |
| mbed_official | 15:a81a8d6c1dfe | 651 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 652 | typedef union { |
| mbed_official | 15:a81a8d6c1dfe | 653 | struct { |
| mbed_official | 15:a81a8d6c1dfe | 654 | uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ |
| mbed_official | 15:a81a8d6c1dfe | 655 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
| mbed_official | 15:a81a8d6c1dfe | 656 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 15:a81a8d6c1dfe | 657 | uint8_t reg; /*!< Type used for register access */ |
| mbed_official | 15:a81a8d6c1dfe | 658 | } ADC_DBGCTRL_Type; |
| mbed_official | 15:a81a8d6c1dfe | 659 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 660 | |
| mbed_official | 15:a81a8d6c1dfe | 661 | #define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ |
| mbed_official | 15:a81a8d6c1dfe | 662 | #define ADC_DBGCTRL_RESETVALUE 0x00ul /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ |
| mbed_official | 15:a81a8d6c1dfe | 663 | |
| mbed_official | 15:a81a8d6c1dfe | 664 | #define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ |
| mbed_official | 15:a81a8d6c1dfe | 665 | #define ADC_DBGCTRL_DBGRUN (0x1ul << ADC_DBGCTRL_DBGRUN_Pos) |
| mbed_official | 15:a81a8d6c1dfe | 666 | #define ADC_DBGCTRL_MASK 0x01ul /**< \brief (ADC_DBGCTRL) MASK Register */ |
| mbed_official | 15:a81a8d6c1dfe | 667 | |
| mbed_official | 15:a81a8d6c1dfe | 668 | /** \brief ADC hardware registers */ |
| mbed_official | 15:a81a8d6c1dfe | 669 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 15:a81a8d6c1dfe | 670 | typedef struct { |
| mbed_official | 15:a81a8d6c1dfe | 671 | __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ |
| mbed_official | 15:a81a8d6c1dfe | 672 | __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ |
| mbed_official | 15:a81a8d6c1dfe | 673 | __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ |
| mbed_official | 15:a81a8d6c1dfe | 674 | __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ |
| mbed_official | 15:a81a8d6c1dfe | 675 | __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ |
| mbed_official | 15:a81a8d6c1dfe | 676 | RoReg8 Reserved1[0x2]; |
| mbed_official | 15:a81a8d6c1dfe | 677 | __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ |
| mbed_official | 15:a81a8d6c1dfe | 678 | RoReg8 Reserved2[0x3]; |
| mbed_official | 15:a81a8d6c1dfe | 679 | __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ |
| mbed_official | 15:a81a8d6c1dfe | 680 | RoReg8 Reserved3[0x3]; |
| mbed_official | 15:a81a8d6c1dfe | 681 | __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ |
| mbed_official | 15:a81a8d6c1dfe | 682 | __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ |
| mbed_official | 15:a81a8d6c1dfe | 683 | RoReg8 Reserved4[0x1]; |
| mbed_official | 15:a81a8d6c1dfe | 684 | __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ |
| mbed_official | 15:a81a8d6c1dfe | 685 | __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ |
| mbed_official | 15:a81a8d6c1dfe | 686 | __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ |
| mbed_official | 15:a81a8d6c1dfe | 687 | __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ |
| mbed_official | 15:a81a8d6c1dfe | 688 | __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ |
| mbed_official | 15:a81a8d6c1dfe | 689 | __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ |
| mbed_official | 15:a81a8d6c1dfe | 690 | RoReg8 Reserved5[0x2]; |
| mbed_official | 15:a81a8d6c1dfe | 691 | __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ |
| mbed_official | 15:a81a8d6c1dfe | 692 | RoReg8 Reserved6[0x2]; |
| mbed_official | 15:a81a8d6c1dfe | 693 | __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ |
| mbed_official | 15:a81a8d6c1dfe | 694 | __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ |
| mbed_official | 15:a81a8d6c1dfe | 695 | __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ |
| mbed_official | 15:a81a8d6c1dfe | 696 | __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ |
| mbed_official | 15:a81a8d6c1dfe | 697 | } Adc; |
| mbed_official | 15:a81a8d6c1dfe | 698 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 15:a81a8d6c1dfe | 699 | |
| mbed_official | 15:a81a8d6c1dfe | 700 | /*@}*/ |
| mbed_official | 15:a81a8d6c1dfe | 701 | |
| mbed_official | 15:a81a8d6c1dfe | 702 | #endif /* _SAMD21_ADC_COMPONENT_ */ |