Daiki Kato / FlashAccess

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FlashAccess.h@0:5a74eeaefb5d, 2017-11-28 (annotated)

Committer:
dkato
Date:
Tue Nov 28 06:27:21 2017 +0000
Revision:
0:5a74eeaefb5d
Child:
1:652a093cf264
first commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:5a74eeaefb5d 1 /*******************************************************************************
dkato 0:5a74eeaefb5d 2 * DISCLAIMER
dkato 0:5a74eeaefb5d 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:5a74eeaefb5d 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:5a74eeaefb5d 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:5a74eeaefb5d 6 * all applicable laws, including copyright laws.
dkato 0:5a74eeaefb5d 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:5a74eeaefb5d 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:5a74eeaefb5d 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:5a74eeaefb5d 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:5a74eeaefb5d 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:5a74eeaefb5d 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:5a74eeaefb5d 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:5a74eeaefb5d 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:5a74eeaefb5d 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:5a74eeaefb5d 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:5a74eeaefb5d 17 * and to discontinue the availability of this software. By using this software,
dkato 0:5a74eeaefb5d 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:5a74eeaefb5d 19 * following link:
dkato 0:5a74eeaefb5d 20 * http://www.renesas.com/disclaimer
dkato 0:5a74eeaefb5d 21 *
dkato 0:5a74eeaefb5d 22 * Copyright (C) 2017 Renesas Electronics Corporation. All rights reserved.
dkato 0:5a74eeaefb5d 23 *******************************************************************************/
dkato 0:5a74eeaefb5d 24
dkato 0:5a74eeaefb5d 25 #ifndef FLASH_ACCESS_H
dkato 0:5a74eeaefb5d 26 #define FLASH_ACCESS_H
dkato 0:5a74eeaefb5d 27
dkato 0:5a74eeaefb5d 28 #include "mbed.h"
dkato 0:5a74eeaefb5d 29 #include "iodefine.h"
dkato 0:5a74eeaefb5d 30 #include "spibsc_iobitmask.h"
dkato 0:5a74eeaefb5d 31 #include "spibsc.h"
dkato 0:5a74eeaefb5d 32
dkato 0:5a74eeaefb5d 33 #define _RAM_PRG __attribute__((section("RAM_CODE")))
dkato 0:5a74eeaefb5d 34
dkato 0:5a74eeaefb5d 35 class FlashAccess {
dkato 0:5a74eeaefb5d 36
dkato 0:5a74eeaefb5d 37 public:
dkato 0:5a74eeaefb5d 38 /** Constructor
dkato 0:5a74eeaefb5d 39 *
dkato 0:5a74eeaefb5d 40 */
dkato 0:5a74eeaefb5d 41 FlashAccess();
dkato 0:5a74eeaefb5d 42
dkato 0:5a74eeaefb5d 43 /** Sector Erase
dkato 0:5a74eeaefb5d 44 *
dkato 0:5a74eeaefb5d 45 * The Sector Erase instruction sets all memory within a specified sector (4K-bytes)
dkato 0:5a74eeaefb5d 46 * to the erased state of all 1s (FFh).
dkato 0:5a74eeaefb5d 47 *
dkato 0:5a74eeaefb5d 48 * @param addr sector address
dkato 0:5a74eeaefb5d 49 * @return true = success, false = failure
dkato 0:5a74eeaefb5d 50 */
dkato 0:5a74eeaefb5d 51 bool SectorErase(uint32_t addr) _RAM_PRG;
dkato 0:5a74eeaefb5d 52
dkato 0:5a74eeaefb5d 53 /** Page Program
dkato 0:5a74eeaefb5d 54 *
dkato 0:5a74eeaefb5d 55 * The Page Program instruction allows from one byte to 256 bytes (a page) of data
dkato 0:5a74eeaefb5d 56 * to be programmed at previously erased (FFh) memory locations.
dkato 0:5a74eeaefb5d 57 *
dkato 0:5a74eeaefb5d 58 * @param addr starting address
dkato 0:5a74eeaefb5d 59 * @param buf the buffer to read into
dkato 0:5a74eeaefb5d 60 * @param size size of the data
dkato 0:5a74eeaefb5d 61 * @return true = success, false = failure
dkato 0:5a74eeaefb5d 62 */
dkato 0:5a74eeaefb5d 63 bool PageProgram(uint32_t addr, uint8_t * buf, int32_t size) _RAM_PRG;
dkato 0:5a74eeaefb5d 64
dkato 0:5a74eeaefb5d 65 /** Read
dkato 0:5a74eeaefb5d 66 *
dkato 0:5a74eeaefb5d 67 * The Read Data instruction allows one or more data bytes to be sequentially read
dkato 0:5a74eeaefb5d 68 * from the memory.
dkato 0:5a74eeaefb5d 69 *
dkato 0:5a74eeaefb5d 70 * @param addr starting address
dkato 0:5a74eeaefb5d 71 * @param buf the buffer to write from
dkato 0:5a74eeaefb5d 72 * @param size size of the data
dkato 0:5a74eeaefb5d 73 * @return true = success, false = failure
dkato 0:5a74eeaefb5d 74 */
dkato 0:5a74eeaefb5d 75 bool Read(uint32_t addr, uint8_t * buf, int32_t size) _RAM_PRG;
dkato 0:5a74eeaefb5d 76
dkato 0:5a74eeaefb5d 77 protected:
dkato 0:5a74eeaefb5d 78 typedef struct {
dkato 0:5a74eeaefb5d 79 uint32_t cdb; /* bit-width : command */
dkato 0:5a74eeaefb5d 80 uint32_t ocdb; /* bit-width : optional command */
dkato 0:5a74eeaefb5d 81 uint32_t adb; /* bit-width : address */
dkato 0:5a74eeaefb5d 82 uint32_t opdb; /* bit-width : option data */
dkato 0:5a74eeaefb5d 83 uint32_t spidb; /* bit-width : data */
dkato 0:5a74eeaefb5d 84
dkato 0:5a74eeaefb5d 85 uint32_t cde; /* Enable : command */
dkato 0:5a74eeaefb5d 86 uint32_t ocde; /* Enable : optional command */
dkato 0:5a74eeaefb5d 87 uint32_t ade; /* Enable : address */
dkato 0:5a74eeaefb5d 88 uint32_t opde; /* Enable : option data */
dkato 0:5a74eeaefb5d 89 uint32_t spide; /* Enable : data */
dkato 0:5a74eeaefb5d 90
dkato 0:5a74eeaefb5d 91 uint32_t sslkp; /* SPBSSL level */
dkato 0:5a74eeaefb5d 92 uint32_t spire; /* Enable data read */
dkato 0:5a74eeaefb5d 93 uint32_t spiwe; /* Enable data write */
dkato 0:5a74eeaefb5d 94
dkato 0:5a74eeaefb5d 95 uint32_t dme; /* Enable : dummy cycle */
dkato 0:5a74eeaefb5d 96
dkato 0:5a74eeaefb5d 97 uint32_t addre; /* DDR enable : address */
dkato 0:5a74eeaefb5d 98 uint32_t opdre; /* DDR enable : option data */
dkato 0:5a74eeaefb5d 99 uint32_t spidre; /* DDR enable : data */
dkato 0:5a74eeaefb5d 100
dkato 0:5a74eeaefb5d 101 uint8_t dmdb; /* bit-width : dummy cycle */
dkato 0:5a74eeaefb5d 102 uint8_t dmcyc; /* number of dummy cycles */
dkato 0:5a74eeaefb5d 103
dkato 0:5a74eeaefb5d 104 uint8_t cmd; /* command */
dkato 0:5a74eeaefb5d 105 uint8_t ocmd; /* optional command */
dkato 0:5a74eeaefb5d 106 uint32_t addr; /* address */
dkato 0:5a74eeaefb5d 107 uint8_t opd[4]; /* option data 3/2/1/0 */
dkato 0:5a74eeaefb5d 108 uint32_t smrdr[2]; /* read data */
dkato 0:5a74eeaefb5d 109 uint32_t smwdr[2]; /* write data */
dkato 0:5a74eeaefb5d 110 } st_spibsc_spimd_reg_t;
dkato 0:5a74eeaefb5d 111
dkato 0:5a74eeaefb5d 112 volatile struct st_spibsc* SPIBSC;
dkato 0:5a74eeaefb5d 113 st_spibsc_spimd_reg_t spimd_reg;
dkato 0:5a74eeaefb5d 114
dkato 0:5a74eeaefb5d 115 bool _SectorErase(uint32_t addr) _RAM_PRG;
dkato 0:5a74eeaefb5d 116 bool _PageProgram(uint32_t addr, uint8_t * buf, int32_t size) _RAM_PRG;
dkato 0:5a74eeaefb5d 117 bool _Read(uint32_t addr, uint8_t * buf, int32_t size) _RAM_PRG;
dkato 0:5a74eeaefb5d 118 bool _WriteEnable(void) _RAM_PRG;
dkato 0:5a74eeaefb5d 119 bool _busy_wait(void) _RAM_PRG;
dkato 0:5a74eeaefb5d 120 bool _read_register(uint8_t cmd, uint8_t * status) _RAM_PRG;
dkato 0:5a74eeaefb5d 121 bool data_send(uint32_t bit_width, uint32_t spbssl_level, uint8_t * buf, int32_t size) _RAM_PRG;
dkato 0:5a74eeaefb5d 122 bool data_recv(uint32_t bit_width, uint32_t spbssl_level, uint8_t * buf, int32_t size) _RAM_PRG;
dkato 0:5a74eeaefb5d 123 void spi_mode(void) _RAM_PRG;
dkato 0:5a74eeaefb5d 124 void ex_mode(void) _RAM_PRG;
dkato 0:5a74eeaefb5d 125 void clear_spimd_reg(st_spibsc_spimd_reg_t * regset) _RAM_PRG;
dkato 0:5a74eeaefb5d 126 bool spibsc_transfer(st_spibsc_spimd_reg_t * regset) _RAM_PRG;
dkato 0:5a74eeaefb5d 127 uint32_t RegRead_32(volatile uint32_t * ioreg, uint32_t shift, uint32_t mask) _RAM_PRG;
dkato 0:5a74eeaefb5d 128 void RegWwrite_32(volatile uint32_t * ioreg, uint32_t write_value, uint32_t shift, uint32_t mask) _RAM_PRG;
dkato 0:5a74eeaefb5d 129
dkato 0:5a74eeaefb5d 130 private:
dkato 0:5a74eeaefb5d 131 /* SPI Multi-I/O bus address space address definitions */
dkato 0:5a74eeaefb5d 132 #define SPIBSC_ADDR_START (0x18000000uL)
dkato 0:5a74eeaefb5d 133 #define SPIBSC_ADDR_END (0x1BFFFFFFuL)
dkato 0:5a74eeaefb5d 134
dkato 0:5a74eeaefb5d 135 typedef struct {
dkato 0:5a74eeaefb5d 136 uint32_t b0 : 1 ; /* bit 0 : - (0) */
dkato 0:5a74eeaefb5d 137 uint32_t b1 : 1 ; /* bit 1 : - (1) */
dkato 0:5a74eeaefb5d 138 uint32_t B : 1 ; /* bit 2 : B Memory region attribute bit */
dkato 0:5a74eeaefb5d 139 uint32_t C : 1 ; /* bit 3 : C Memory region attribute bit */
dkato 0:5a74eeaefb5d 140 uint32_t XN : 1 ; /* bit 4 : XN Execute-never bit */
dkato 0:5a74eeaefb5d 141 uint32_t Domain : 4 ; /* bit 8-5 : Domain Domain field */
dkato 0:5a74eeaefb5d 142 uint32_t b9 : 1 ; /* bit 9 : IMP IMPLEMENTATION DEFINED */
dkato 0:5a74eeaefb5d 143 uint32_t AP1_0 : 2 ; /* bit 11-10 : AP[1:0] Access permissions bits:bit1-0 */
dkato 0:5a74eeaefb5d 144 uint32_t TEX : 3 ; /* bit 14-12 : TEX[2:0] Memory region attribute bits */
dkato 0:5a74eeaefb5d 145 uint32_t AP2 : 1 ; /* bit 15 : AP[2] Access permissions bits:bit2 */
dkato 0:5a74eeaefb5d 146 uint32_t S : 1 ; /* bit 16 : S Shareable bit */
dkato 0:5a74eeaefb5d 147 uint32_t nG : 1 ; /* bit 17 : nG Not global bit */
dkato 0:5a74eeaefb5d 148 uint32_t b18 : 1 ; /* bit 18 : - (0) */
dkato 0:5a74eeaefb5d 149 uint32_t NS : 1 ; /* bit 19 : NS Non-secure bit */
dkato 0:5a74eeaefb5d 150 uint32_t base_addr : 12; /* bit 31-20 : PA[31:20] PA(physical address) bits:bit31-20 */
dkato 0:5a74eeaefb5d 151 } mmu_ttbl_desc_section_t;
dkato 0:5a74eeaefb5d 152
dkato 0:5a74eeaefb5d 153 mmu_ttbl_desc_section_t desc_tbl[(SPIBSC_ADDR_END >> 20) - (SPIBSC_ADDR_START >> 20) + 1];
dkato 0:5a74eeaefb5d 154
dkato 0:5a74eeaefb5d 155 void change_mmu_ttbl_spibsc(uint32_t type) _RAM_PRG;
dkato 0:5a74eeaefb5d 156 void spibsc_stop(void) _RAM_PRG;
dkato 0:5a74eeaefb5d 157 void cache_control(void) _RAM_PRG;
dkato 0:5a74eeaefb5d 158 };
dkato 0:5a74eeaefb5d 159 #endif