Djordje Trajkovic / Mbed 2 deprecated ccRF

Send&recive two byte over ccRF 2550

Dependencies:   mbed

regssrf04.h@0:a669868d99dd, 2015-06-30 (annotated)

Committer:
djtr
Date:
Tue Jun 30 21:47:55 2015 +0000
Revision:
0:a669868d99dd
CC2500, Nucleo

Who changed what in which revision?

UserRevisionLine numberNew contents of line
djtr 0:a669868d99dd 1 #ifndef REGSSRF04_H
djtr 0:a669868d99dd 2 #define REGSSRF04_H
djtr 0:a669868d99dd 3
djtr 0:a669868d99dd 4 //-------------------------------------------------------------------------------------------------------
djtr 0:a669868d99dd 5 // RF_SETTINGS is a data structure which contains all relevant CCxxx0 registers
djtr 0:a669868d99dd 6 typedef struct S_RF_SETTINGS{
djtr 0:a669868d99dd 7 char FSCTRL1; // Frequency synthesizer control.
djtr 0:a669868d99dd 8 char FSCTRL0; // Frequency synthesizer control.
djtr 0:a669868d99dd 9 char FREQ2; // Frequency control word, high char.
djtr 0:a669868d99dd 10 char FREQ1; // Frequency control word, middle char.
djtr 0:a669868d99dd 11 char FREQ0; // Frequency control word, low char.
djtr 0:a669868d99dd 12 char MDMCFG4; // Modem configuration.
djtr 0:a669868d99dd 13 char MDMCFG3; // Modem configuration.
djtr 0:a669868d99dd 14 char MDMCFG2; // Modem configuration.
djtr 0:a669868d99dd 15 char MDMCFG1; // Modem configuration.
djtr 0:a669868d99dd 16 char MDMCFG0; // Modem configuration.
djtr 0:a669868d99dd 17 char CHANNR; // Channel number.
djtr 0:a669868d99dd 18 char DEVIATN; // Modem deviation setting (when FSK modulation is enabled).
djtr 0:a669868d99dd 19 char FREND1; // Front end RX configuration.
djtr 0:a669868d99dd 20 char FREND0; // Front end RX configuration.
djtr 0:a669868d99dd 21 char MCSM0; // Main Radio Control State Machine configuration.
djtr 0:a669868d99dd 22 char FOCCFG; // Frequency Offset Compensation Configuration.
djtr 0:a669868d99dd 23 char BSCFG; // Bit synchronization Configuration.
djtr 0:a669868d99dd 24 char AGCCTRL2; // AGC control.
djtr 0:a669868d99dd 25 char AGCCTRL1; // AGC control.
djtr 0:a669868d99dd 26 char AGCCTRL0; // AGC control.
djtr 0:a669868d99dd 27 char FSCAL3; // Frequency synthesizer calibration.
djtr 0:a669868d99dd 28 char FSCAL2; // Frequency synthesizer calibration.
djtr 0:a669868d99dd 29 char FSCAL1; // Frequency synthesizer calibration.
djtr 0:a669868d99dd 30 char FSCAL0; // Frequency synthesizer calibration.
djtr 0:a669868d99dd 31 char FSTEST; // Frequency synthesizer calibration control
djtr 0:a669868d99dd 32 char TEST2; // Various test settings.
djtr 0:a669868d99dd 33 char TEST1; // Various test settings.
djtr 0:a669868d99dd 34 char TEST0; // Various test settings.
djtr 0:a669868d99dd 35 char FIFOTHR; // RXFIFO and TXFIFO thresholds.
djtr 0:a669868d99dd 36 char IOCFG2; // GDO2 output pin configuration
djtr 0:a669868d99dd 37 char IOCFG0; // GDO0 output pin configuration
djtr 0:a669868d99dd 38 char PKTCTRL1; // Packet automation control.
djtr 0:a669868d99dd 39 char PKTCTRL0; // Packet automation control.
djtr 0:a669868d99dd 40 char ADDR; // Device address.
djtr 0:a669868d99dd 41 char PKTLEN; // Packet length.
djtr 0:a669868d99dd 42 } RF_SETTINGS;
djtr 0:a669868d99dd 43
djtr 0:a669868d99dd 44
djtr 0:a669868d99dd 45
djtr 0:a669868d99dd 46 //------------------------------------------------------------------------------------------------------
djtr 0:a669868d99dd 47 // CC2500/CC1100 STROBE, CONTROL AND STATUS REGSITER
djtr 0:a669868d99dd 48 #define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration
djtr 0:a669868d99dd 49 #define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration
djtr 0:a669868d99dd 50 #define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration
djtr 0:a669868d99dd 51 #define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
djtr 0:a669868d99dd 52 #define CCxxx0_SYNC1 0x04 // Sync word, high byte
djtr 0:a669868d99dd 53 #define CCxxx0_SYNC0 0x05 // Sync word, low byte
djtr 0:a669868d99dd 54 #define CCxxx0_PKTLEN 0x06 // Packet length
djtr 0:a669868d99dd 55 #define CCxxx0_PKTCTRL1 0x07 // Packet automation control
djtr 0:a669868d99dd 56 #define CCxxx0_PKTCTRL0 0x08 // Packet automation control
djtr 0:a669868d99dd 57 #define CCxxx0_ADDR 0x09 // Device address
djtr 0:a669868d99dd 58 #define CCxxx0_CHANNR 0x0A // Channel number
djtr 0:a669868d99dd 59 #define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control
djtr 0:a669868d99dd 60 #define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control
djtr 0:a669868d99dd 61 #define CCxxx0_FREQ2 0x0D // Frequency control word, high byte
djtr 0:a669868d99dd 62 #define CCxxx0_FREQ1 0x0E // Frequency control word, middle byte
djtr 0:a669868d99dd 63 #define CCxxx0_FREQ0 0x0F // Frequency control word, low byte
djtr 0:a669868d99dd 64 #define CCxxx0_MDMCFG4 0x10 // Modem configuration
djtr 0:a669868d99dd 65 #define CCxxx0_MDMCFG3 0x11 // Modem configuration
djtr 0:a669868d99dd 66 #define CCxxx0_MDMCFG2 0x12 // Modem configuration
djtr 0:a669868d99dd 67 #define CCxxx0_MDMCFG1 0x13 // Modem configuration
djtr 0:a669868d99dd 68 #define CCxxx0_MDMCFG0 0x14 // Modem configuration
djtr 0:a669868d99dd 69 #define CCxxx0_DEVIATN 0x15 // Modem deviation setting
djtr 0:a669868d99dd 70 #define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration
djtr 0:a669868d99dd 71 #define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration
djtr 0:a669868d99dd 72 #define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration
djtr 0:a669868d99dd 73 #define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration
djtr 0:a669868d99dd 74 #define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration
djtr 0:a669868d99dd 75 #define CCxxx0_AGCCTRL2 0x1B // AGC control
djtr 0:a669868d99dd 76 #define CCxxx0_AGCCTRL1 0x1C // AGC control
djtr 0:a669868d99dd 77 #define CCxxx0_AGCCTRL0 0x1D // AGC control
djtr 0:a669868d99dd 78 #define CCxxx0_WOREVT1 0x1E // High byte Event 0 timeout
djtr 0:a669868d99dd 79 #define CCxxx0_WOREVT0 0x1F // Low byte Event 0 timeout
djtr 0:a669868d99dd 80 #define CCxxx0_WORCTRL 0x20 // Wake On Radio control
djtr 0:a669868d99dd 81 #define CCxxx0_FREND1 0x21 // Front end RX configuration
djtr 0:a669868d99dd 82 #define CCxxx0_FREND0 0x22 // Front end TX configuration
djtr 0:a669868d99dd 83 #define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration
djtr 0:a669868d99dd 84 #define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration
djtr 0:a669868d99dd 85 #define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration
djtr 0:a669868d99dd 86 #define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration
djtr 0:a669868d99dd 87 #define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration
djtr 0:a669868d99dd 88 #define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration
djtr 0:a669868d99dd 89 #define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control
djtr 0:a669868d99dd 90 #define CCxxx0_PTEST 0x2A // Production test
djtr 0:a669868d99dd 91 #define CCxxx0_AGCTEST 0x2B // AGC test
djtr 0:a669868d99dd 92 #define CCxxx0_TEST2 0x2C // Various test settings
djtr 0:a669868d99dd 93 #define CCxxx0_TEST1 0x2D // Various test settings
djtr 0:a669868d99dd 94 #define CCxxx0_TEST0 0x2E // Various test settings
djtr 0:a669868d99dd 95
djtr 0:a669868d99dd 96 // Strobe commands
djtr 0:a669868d99dd 97 #define CCxxx0_SRES 0x30 // Reset chip.
djtr 0:a669868d99dd 98 #define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
djtr 0:a669868d99dd 99 // If in RX/TX: Go to a wait state where only the synthesizer is
djtr 0:a669868d99dd 100 // running (for quick RX / TX turnaround).
djtr 0:a669868d99dd 101 #define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator.
djtr 0:a669868d99dd 102 #define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
djtr 0:a669868d99dd 103 // (enables quick start).
djtr 0:a669868d99dd 104 #define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
djtr 0:a669868d99dd 105 // MCSM0.FS_AUTOCAL=1.
djtr 0:a669868d99dd 106 #define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
djtr 0:a669868d99dd 107 // MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
djtr 0:a669868d99dd 108 // Only go to TX if channel is clear.
djtr 0:a669868d99dd 109 #define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
djtr 0:a669868d99dd 110 // Wake-On-Radio mode if applicable.
djtr 0:a669868d99dd 111 #define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
djtr 0:a669868d99dd 112 #define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
djtr 0:a669868d99dd 113 #define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high.
djtr 0:a669868d99dd 114 #define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer.
djtr 0:a669868d99dd 115 #define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer.
djtr 0:a669868d99dd 116 #define CCxxx0_SWORRST 0x3C // Reset real time clock.
djtr 0:a669868d99dd 117 #define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two
djtr 0:a669868d99dd 118 // bytes for simpler software.
djtr 0:a669868d99dd 119
djtr 0:a669868d99dd 120 #define CCxxx0_PARTNUM 0x30
djtr 0:a669868d99dd 121 #define CCxxx0_VERSION 0x31
djtr 0:a669868d99dd 122 #define CCxxx0_FREQEST 0x32
djtr 0:a669868d99dd 123 #define CCxxx0_LQI 0x33
djtr 0:a669868d99dd 124 #define CCxxx0_RSSI 0x34
djtr 0:a669868d99dd 125 #define CCxxx0_MARCSTATE 0x35
djtr 0:a669868d99dd 126 #define CCxxx0_WORTIME1 0x36
djtr 0:a669868d99dd 127 #define CCxxx0_WORTIME0 0x37
djtr 0:a669868d99dd 128 #define CCxxx0_PKTSTATUS 0x38
djtr 0:a669868d99dd 129 #define CCxxx0_VCO_VC_DAC 0x39
djtr 0:a669868d99dd 130 #define CCxxx0_TXBYTES 0x3A
djtr 0:a669868d99dd 131 #define CCxxx0_RXBYTES 0x3B
djtr 0:a669868d99dd 132 #define CCxxx0_RCCTRL1_STATUS 0x3C
djtr 0:a669868d99dd 133 #define CCxxx0_RCCTRL0_STATUS 0x3D
djtr 0:a669868d99dd 134
djtr 0:a669868d99dd 135 #define CCxxx0_PATABLE 0x3E
djtr 0:a669868d99dd 136 #define CCxxx0_TXFIFO 0x3F
djtr 0:a669868d99dd 137 #define CCxxx0_RXFIFO 0x3F
djtr 0:a669868d99dd 138
djtr 0:a669868d99dd 139
djtr 0:a669868d99dd 140 #define CCxxx0_RECEIVE_CRC_ERROR 0x00
djtr 0:a669868d99dd 141 #define CCxxx0_RECEIVE_CRC_OK 0x80
djtr 0:a669868d99dd 142
djtr 0:a669868d99dd 143 #endif//REGSSRF04_H