Stephen Dickey / C027-REVB

Fork to support REVB hardware.

Dependents:   C027_BootTest_revb C027_EthernetSniffTest C027_M3_SerialEcho C027_HelloWorld_revb ... more

Fork of C027 by u-blox

C027_PinNames.h@1:4a3bc6c3f1d0, 2013-10-01 (annotated)

Committer:
mazgch
Date:
Tue Oct 01 14:46:30 2013 +0000
Revision:
1:4a3bc6c3f1d0
Parent:
0:76bb2733db5d
Child:
2:b7bd3660ff64
comment

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mazgch 0:76bb2733db5d 1 /* Platform header file, for the u-blox C27-C20/U20/G35
mazgch 0:76bb2733db5d 2 * mbed Internet of Things Starter Kit
mazgch 0:76bb2733db5d 3 * http://mbed.org/platforms/u-blox-C27/
mazgch 0:76bb2733db5d 4 *
mazgch 0:76bb2733db5d 5 * Defines for pin connections of the LPC1768
mazgch 0:76bb2733db5d 6 */
mazgch 0:76bb2733db5d 7
mazgch 0:76bb2733db5d 8 #pragma once
mazgch 0:76bb2733db5d 9
mazgch 0:76bb2733db5d 10 // u-blox MAX-7Q GPS/GLONASS receiver
mazgch 0:76bb2733db5d 11 // http://www.u-blox.de/gps-modules.html
mazgch 0:76bb2733db5d 12 // -----------------------------------------------------------
mazgch 0:76bb2733db5d 13 // I2C (shared with LISA/SARA)
mazgch 0:76bb2733db5d 14 #define GPSSDA (P0_27)
mazgch 0:76bb2733db5d 15 #define GPSSCL (P0_28)
mazgch 0:76bb2733db5d 16 // UART
mazgch 0:76bb2733db5d 17 #define GPSTXD (P0_10)
mazgch 0:76bb2733db5d 18 #define GPSRXD (P0_11)
mazgch 0:76bb2733db5d 19 #define GPSBAUD 9600 // Default GPS Baud Rate
mazgch 0:76bb2733db5d 20 // Control
mazgch 0:76bb2733db5d 21 #define GPSRST (P1_18) // Reset (input to GPS, active low)
mazgch 0:76bb2733db5d 22 #define GPSPPS (P1_19) // 1PPS Timepulse (output from GPS)
mazgch 0:76bb2733db5d 23 #define GPSINT (P1_22) // Interrupt (input to GPS)
mazgch 0:76bb2733db5d 24 #define GPSEN (P1_29) // Supply Control (high = enabled)
mazgch 0:76bb2733db5d 25
mazgch 0:76bb2733db5d 26 // u-blox LISA/SARA cellular modem
mazgch 0:76bb2733db5d 27 // http://www.u-blox.de/wireless-modules.html
mazgch 0:76bb2733db5d 28 // -----------------------------------------------------------
mazgch 0:76bb2733db5d 29 // UART (LPC1768 = DTE, LISA/SARA = DCE)
mazgch 0:76bb2733db5d 30 #define MDMTXD (P0_15) // Transmit Data
mazgch 0:76bb2733db5d 31 #define MDMRXD (P0_16) // Receive Data
mazgch 0:76bb2733db5d 32 #define MDMCTS (P0_17) // Clear to Send
mazgch 0:76bb2733db5d 33 #define MDMDCD (P0_18) // Data Carrier Detect
mazgch 0:76bb2733db5d 34 #define MDMDSR (P0_19) // Data Set Ready
mazgch 0:76bb2733db5d 35 #define MDMDTR (P0_20) // Data Terminal Ready (set high or use handshake)
mazgch 0:76bb2733db5d 36 #define MDMRI (P0_21) // Ring Indicator
mazgch 0:76bb2733db5d 37 #define MDMRTS (P0_22) // Request to Send (set high or use handshake)
mazgch 0:76bb2733db5d 38 #define MDMBAUD 115200 // Default Modem Baud Rate
mazgch 0:76bb2733db5d 39 // USB (not available on C27-G35)
mazgch 0:76bb2733db5d 40 #define MDMUSBDP (P0_29) // USB D+
mazgch 0:76bb2733db5d 41 #define MDMUSBDN (P0_30) // USB D-
mazgch 0:76bb2733db5d 42 #define MDMUSBCON (P2_9) // USB Connect
mazgch 0:76bb2733db5d 43 // Control
mazgch 0:76bb2733db5d 44 #define MDMEN (P2_5) // Supply Control (high = enabled)
mazgch 0:76bb2733db5d 45 #define MDMPWRON (P2_6) //
mazgch 0:76bb2733db5d 46 #define MDMGPIO1 (P2_7) // GPIO1, Network status
mazgch 0:76bb2733db5d 47 #define MDMRST (P2_8) // Reset (active low, set as open drain!)
mazgch 0:76bb2733db5d 48
mazgch 0:76bb2733db5d 49 // PIN header connector
mazgch 0:76bb2733db5d 50 // for standard-based form factor with expansion board
mazgch 0:76bb2733db5d 51 // -----------------------------------------------------------
mazgch 0:76bb2733db5d 52 // PMW = Pulswidth Modulator
mazgch 0:76bb2733db5d 53 // EINT = External Interrupt
mazgch 0:76bb2733db5d 54 // AOUT = Analog Output
mazgch 0:76bb2733db5d 55
mazgch 0:76bb2733db5d 56 // Analog Ports (A0-A5)
mazgch 0:76bb2733db5d 57 #define A0 (P0_23) // I2S_CLK
mazgch 0:76bb2733db5d 58 #define A1 (P0_24) // I2S_WS
mazgch 0:76bb2733db5d 59 #define A2 (P0_25) // I2S_SDA
mazgch 0:76bb2733db5d 60 #define A3 (P0_26) // AOUT
mazgch 0:76bb2733db5d 61 #define A4 (P1_30) //
mazgch 0:76bb2733db5d 62 #define A5 (P1_31) //
mazgch 0:76bb2733db5d 63 // Digital Port (D0-D7)
mazgch 0:76bb2733db5d 64 #define D0 (P4_29) // TXD
mazgch 0:76bb2733db5d 65 #define D1 (P4_28) // RXD
mazgch 0:76bb2733db5d 66 #define D2 (P2_13) // EINT
mazgch 0:76bb2733db5d 67 #define D3 (P2_0) // PWM
mazgch 0:76bb2733db5d 68 #define D4 (P2_12) // EINT
mazgch 0:76bb2733db5d 69 #define D5 (P2_1) // PWM
mazgch 0:76bb2733db5d 70 #define D6 (P2_2) // PWM
mazgch 0:76bb2733db5d 71 #define D7 (P2_11) // EINT
mazgch 0:76bb2733db5d 72 // Digital Port (D8-D13)
mazgch 0:76bb2733db5d 73 #define D8 (P2_4) // PWM
mazgch 0:76bb2733db5d 74 #define D9 (P2_3) // PWM
mazgch 0:76bb2733db5d 75 #define D10 (P1_21) // PWM SSEL
mazgch 0:76bb2733db5d 76 #define D11 (P1_24) // PWM MOSI
mazgch 0:76bb2733db5d 77 #define D12 (P1_23) // PWM MISO
mazgch 0:76bb2733db5d 78 #define D13 (P1_20) // PWM SCK
mazgch 0:76bb2733db5d 79 // GND
mazgch 0:76bb2733db5d 80 // AREF
mazgch 0:76bb2733db5d 81 #define SDA (P0_0)
mazgch 0:76bb2733db5d 82 #define SCL (P0_1)
mazgch 0:76bb2733db5d 83
mazgch 0:76bb2733db5d 84 // CAN (TJA1040)
mazgch 0:76bb2733db5d 85 // -----------------------------------------------------------
mazgch 0:76bb2733db5d 86 #define CANRD (P0_4)
mazgch 0:76bb2733db5d 87 #define CANTD (P0_5)
mazgch 0:76bb2733db5d 88 #define CANS (P0_6) // standby (low=normal, high=standby/rxonly)
mazgch 0:76bb2733db5d 89
mazgch 0:76bb2733db5d 90 // Ethernet (DP83848)
mazgch 0:76bb2733db5d 91 // -----------------------------------------------------------
mazgch 0:76bb2733db5d 92 #define ETHTXD0 (P1_0)
mazgch 0:76bb2733db5d 93 #define ETHTXD1 (P1_1)
mazgch 0:76bb2733db5d 94 #define ETHTXEN (P1_4)
mazgch 0:76bb2733db5d 95 #define ETHCRS (P1_8)
mazgch 0:76bb2733db5d 96 #define ETHRXD0 (P1_9)
mazgch 0:76bb2733db5d 97 #define ETHRXD1 (P1_10)
mazgch 0:76bb2733db5d 98 #define ETHRXEN (P1_14)
mazgch 0:76bb2733db5d 99 #define ETHREFCLK (P1_15)
mazgch 0:76bb2733db5d 100 #define ETHMDC (P1_16)
mazgch 0:76bb2733db5d 101 #define ETHMDIO (P1_17)
mazgch 0:76bb2733db5d 102 #define ETHOSCEN (P1_27)
mazgch 0:76bb2733db5d 103 #define ETHRST (P1_28)
mazgch 0:76bb2733db5d 104 #define ETHLINK (P1_25) // LED_LINK
mazgch 0:76bb2733db5d 105 #define ETHSPEED (P1_26) // LED_SPEED
mazgch 0:76bb2733db5d 106
mazgch 0:76bb2733db5d 107 // mbed / debug IF (LPC11)
mazgch 0:76bb2733db5d 108 // -----------------------------------------------------------
mazgch 0:76bb2733db5d 109 // Serial Port
mazgch 1:4a3bc6c3f1d0 110 #define USBTXD (P0_2) // identical USBTX
mazgch 1:4a3bc6c3f1d0 111 #define USBRXD (P0_3) // identical USBRX
mazgch 0:76bb2733db5d 112 // ISP port
mazgch 0:76bb2733db5d 113 #define ISP (P2_10)
mazgch 0:76bb2733db5d 114
mazgch 0:76bb2733db5d 115 // Reserved / NC pins
mazgch 0:76bb2733db5d 116 // -----------------------------------------------------------
mazgch 0:76bb2733db5d 117 #define RSVD1 (P0_7)
mazgch 0:76bb2733db5d 118 #define RSVD2 (P0_8)
mazgch 0:76bb2733db5d 119 #define RSVD3 (P0_9)
mazgch 0:76bb2733db5d 120 #define RSVD4 (P3_25)
mazgch 0:76bb2733db5d 121 #define RSVD5 (P3_26)
mazgch 0:76bb2733db5d 122