Microchip SPI SRAM (23LC1024, 23LC512) access library.
Diff: 23LCxx_SPI.h
- Revision:
- 2:52d3272b886c
- Parent:
- 1:56e01e806364
--- a/23LCxx_SPI.h Fri Nov 27 03:46:10 2015 +0000 +++ b/23LCxx_SPI.h Sun Nov 29 11:31:24 2015 +0000 @@ -38,22 +38,22 @@ public: /** SPI COMMAND for Microchip 23LC1024, 23LC512 */ enum Microchip23LCxxCommnd { - READ = 0x03u, - WRITE = 0x02u, - EDIO = 0x3bu, - EQIO = 0x38u, - RSTIO = 0xffu, - RDMR = 0x05u, - WRMR = 0x01u, + READ = 0x03u, ///< Read data from memory array beginning at selected address + WRITE = 0x02u, ///< Write data to memory array beginning at selected address + EDIO = 0x3bu, ///< Enter Dual I/O access (enter SDI bus mode) + EQIO = 0x38u, ///< Enter Quad I/O access (enter QDI bus mode) + RSTIO = 0xffu, ///< Reset Dual and Quad I/O access (revert to SPI bus mode) + RDMR = 0x05u, ///< Read Mode Register + WRMR = 0x01u, ///< Write Mode Register }; /** Access mode for Microchip 23LC1024, 23LC512 */ enum Microchip23LCxxMode { - MODE_MASK = 0xc0u, - BYTE = 0x00u, - SEQUENTIAL = 0x40u, // default operation - PAGE = 0x80u, - RESERVED = 0xc0u, + MODE_MASK = 0xc0u, ///< mode bits [7:6] in mode register + BYTE = 0x00u, ///< 00: Byte mode + SEQUENTIAL = 0x40u, ///< 01: Sequential mode (default) + PAGE = 0x80u, ///< 10: Page mode + RESERVED = 0xc0u, ///< 11: Reserved }; /** Constructor.