Chihiro H / 23LCxx_SPI

Microchip SPI SRAM (23LC1024, 23LC512) access library.

23LCxx_SPI.h@2:52d3272b886c, 2015-11-29 (annotated)

Committer:
discypus
Date:
Sun Nov 29 11:31:24 2015 +0000
Revision:
2:52d3272b886c
Parent:
1:56e01e806364 
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discypus 0:625ac56d810e 1 #ifndef MICROCHIP_23LCXXX_SPI_H
discypus 0:625ac56d810e 2 #define MICROCHIP_23LCXXX_SPI_H
discypus 0:625ac56d810e 3
discypus 0:625ac56d810e 4 #include <mbed.h>
discypus 0:625ac56d810e 5
discypus 1:56e01e806364 6 /** Microchip SPI SRAM access library for 23LC1024, 23LC512
discypus 0:625ac56d810e 7 *
discypus 1:56e01e806364 8 * Example:
discypus 0:625ac56d810e 9 * @code
discypus 0:625ac56d810e 10 * #include <mbed.h>
discypus 0:625ac56d810e 11 * #include "23LCxx_SPI.h"
discypus 0:625ac56d810e 12 *
discypus 0:625ac56d810e 13 * Microchip23LCxx sram(SPI_MOSI, SPI_MISO, SPI_SCK, SPI_CS, 20 * 1000 * 1000);
discypus 0:625ac56d810e 14 *
discypus 0:625ac56d810e 15 * uint8_t buf[256] = {};
discypus 0:625ac56d810e 16 *
discypus 0:625ac56d810e 17 * void main() {
discypus 0:625ac56d810e 18 * const uint32_t address = 0x2000;
discypus 0:625ac56d810e 19 * const uint32_t size = 256;
discypus 0:625ac56d810e 20 *
discypus 0:625ac56d810e 21 * sram.change_mode(Microchip23LCxx::SEQUENTIAL);
discypus 0:625ac56d810e 22 *
discypus 0:625ac56d810e 23 * // write
discypus 0:625ac56d810e 24 * for (uint32_t i = 0; i < size; ++i) {
discypus 0:625ac56d810e 25 * buf[i] = i;
discypus 0:625ac56d810e 26 * }
discypus 0:625ac56d810e 27 * sram.write_bytes(address, buf, size);
discypus 0:625ac56d810e 28 *
discypus 0:625ac56d810e 29 * // read
discypus 0:625ac56d810e 30 * for (uint32_t i = 0; i < size; ++i) {
discypus 0:625ac56d810e 31 * buf[i] = 0;
discypus 0:625ac56d810e 32 * }
discypus 0:625ac56d810e 33 * sram.read_bytes(address, buf, size);
discypus 0:625ac56d810e 34 * }
discypus 0:625ac56d810e 35 * @endcode
discypus 0:625ac56d810e 36 */
discypus 0:625ac56d810e 37 class Microchip23LCxx {
discypus 0:625ac56d810e 38 public:
discypus 1:56e01e806364 39 /** SPI COMMAND for Microchip 23LC1024, 23LC512 */
discypus 1:56e01e806364 40 enum Microchip23LCxxCommnd {
discypus 2:52d3272b886c 41 READ = 0x03u, ///< Read data from memory array beginning at selected address
discypus 2:52d3272b886c 42 WRITE = 0x02u, ///< Write data to memory array beginning at selected address
discypus 2:52d3272b886c 43 EDIO = 0x3bu, ///< Enter Dual I/O access (enter SDI bus mode)
discypus 2:52d3272b886c 44 EQIO = 0x38u, ///< Enter Quad I/O access (enter QDI bus mode)
discypus 2:52d3272b886c 45 RSTIO = 0xffu, ///< Reset Dual and Quad I/O access (revert to SPI bus mode)
discypus 2:52d3272b886c 46 RDMR = 0x05u, ///< Read Mode Register
discypus 2:52d3272b886c 47 WRMR = 0x01u, ///< Write Mode Register
discypus 1:56e01e806364 48 };
discypus 1:56e01e806364 49
discypus 1:56e01e806364 50 /** Access mode for Microchip 23LC1024, 23LC512 */
discypus 1:56e01e806364 51 enum Microchip23LCxxMode {
discypus 2:52d3272b886c 52 MODE_MASK = 0xc0u, ///< mode bits [7:6] in mode register
discypus 2:52d3272b886c 53 BYTE = 0x00u, ///< 00: Byte mode
discypus 2:52d3272b886c 54 SEQUENTIAL = 0x40u, ///< 01: Sequential mode (default)
discypus 2:52d3272b886c 55 PAGE = 0x80u, ///< 10: Page mode
discypus 2:52d3272b886c 56 RESERVED = 0xc0u, ///< 11: Reserved
discypus 0:625ac56d810e 57 };
discypus 0:625ac56d810e 58
discypus 1:56e01e806364 59 /** Constructor.
discypus 1:56e01e806364 60 *
discypus 1:56e01e806364 61 * @param[in] mosi SPI MOSI pin name
discypus 1:56e01e806364 62 * @param[in] miso SPI MISO pin name
discypus 1:56e01e806364 63 * @param[in] sck SPI SCK pin name
discypus 1:56e01e806364 64 * @param[in] cs SPI CS pin name
discypus 1:56e01e806364 65 * @param[in] hz SPI Frequency
discypus 0:625ac56d810e 66 */
discypus 1:56e01e806364 67 Microchip23LCxx(const PinName mosi, const PinName miso, const PinName sck, const PinName cs, const uint32_t hz);
discypus 0:625ac56d810e 68
discypus 1:56e01e806364 69 /** read from mode register.
discypus 1:56e01e806364 70 *
discypus 0:625ac56d810e 71 * @return register value
discypus 0:625ac56d810e 72 */
discypus 0:625ac56d810e 73 uint8_t read_mode_register();
discypus 0:625ac56d810e 74
discypus 1:56e01e806364 75 /** write to mode register.
discypus 1:56e01e806364 76 *
discypus 0:625ac56d810e 77 * @param[in] mode
discypus 0:625ac56d810e 78 */
discypus 0:625ac56d810e 79 void write_mode_register(const uint8_t value);
discypus 0:625ac56d810e 80
discypus 1:56e01e806364 81 /** change mode bits.
discypus 1:56e01e806364 82 *
discypus 0:625ac56d810e 83 * @param[in] mode mode
discypus 0:625ac56d810e 84 * @return mode before change
discypus 0:625ac56d810e 85 * @invariant other bits in register.
discypus 0:625ac56d810e 86 */
discypus 0:625ac56d810e 87 uint8_t change_mode(const uint8_t next_mode);
discypus 0:625ac56d810e 88
discypus 1:56e01e806364 89 /** 1byte read
discypus 1:56e01e806364 90 *
discypus 0:625ac56d810e 91 * @param[in] address adress in 24bit
discypus 0:625ac56d810e 92 * @return read data
discypus 0:625ac56d810e 93 */
discypus 0:625ac56d810e 94 uint8_t read_byte(const uint32_t address);
discypus 0:625ac56d810e 95
discypus 1:56e01e806364 96 /** 1byte write
discypus 1:56e01e806364 97 *
discypus 0:625ac56d810e 98 * @param[in] address address in 24bit
discypus 0:625ac56d810e 99 * @param[in] write data
discypus 0:625ac56d810e 100 */
discypus 0:625ac56d810e 101 void write_byte(const uint32_t address, const uint8_t data);
discypus 0:625ac56d810e 102
discypus 1:56e01e806364 103 /** multi-byte read
discypus 1:56e01e806364 104 *
discypus 0:625ac56d810e 105 * @pre sequential mode or page mode is required.
discypus 0:625ac56d810e 106 */
discypus 0:625ac56d810e 107 void read_bytes(const uint32_t address, uint8_t __restrict data[], const uint32_t size);
discypus 0:625ac56d810e 108
discypus 1:56e01e806364 109 /** multi-byte write
discypus 1:56e01e806364 110 *
discypus 0:625ac56d810e 111 * @pre sequential mode or page mode is required.
discypus 0:625ac56d810e 112 */
discypus 0:625ac56d810e 113 void write_bytes(const uint32_t address, const uint8_t __restrict data[], const uint32_t size);
discypus 0:625ac56d810e 114
discypus 0:625ac56d810e 115 private:
discypus 0:625ac56d810e 116 SPI _spi;
discypus 0:625ac56d810e 117 DigitalOut _cs;
discypus 0:625ac56d810e 118 void _set_address(const uint32_t address);
discypus 0:625ac56d810e 119 };
discypus 0:625ac56d810e 120
discypus 0:625ac56d810e 121 #endif