Damian Gabino / picoGW_hal

Host driver/HAL to build a LoRa Picocell Gateway which communicates through USB with a concentrator board based on Semtech SX1308 multi-channel modem and SX1257/SX1255 RF transceivers.

libloragw/inc/loragw_sx125x.h@0:102b50f941d0, 2018-04-11 (annotated)

Committer:
dgabino
Date:
Wed Apr 11 14:38:42 2018 +0000
Revision:
0:102b50f941d0
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dgabino 0:102b50f941d0 1 /*
dgabino 0:102b50f941d0 2 / _____) _ | |
dgabino 0:102b50f941d0 3 ( (____ _____ ____ _| |_ _____ ____| |__
dgabino 0:102b50f941d0 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
dgabino 0:102b50f941d0 5 _____) ) ____| | | || |_| ____( (___| | | |
dgabino 0:102b50f941d0 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
dgabino 0:102b50f941d0 7 (C)2017 Semtech
dgabino 0:102b50f941d0 8
dgabino 0:102b50f941d0 9 Description: SX125x radio registers and constant definitions
dgabino 0:102b50f941d0 10
dgabino 0:102b50f941d0 11 License: Revised BSD License, see LICENSE.TXT file include in the project
dgabino 0:102b50f941d0 12
dgabino 0:102b50f941d0 13
dgabino 0:102b50f941d0 14 */
dgabino 0:102b50f941d0 15 #ifndef __SX125X_REGS_H__
dgabino 0:102b50f941d0 16 #define __SX125X_REGS_H__
dgabino 0:102b50f941d0 17
dgabino 0:102b50f941d0 18 /*
dgabino 0:102b50f941d0 19 SX1257 frequency setting :
dgabino 0:102b50f941d0 20 F_register(24bit) = F_rf (Hz) / F_step(Hz)
dgabino 0:102b50f941d0 21 = F_rf (Hz) * 2^19 / F_xtal(Hz)
dgabino 0:102b50f941d0 22 = F_rf (Hz) * 2^19 / 32e6
dgabino 0:102b50f941d0 23 = F_rf (Hz) * 256/15625
dgabino 0:102b50f941d0 24
dgabino 0:102b50f941d0 25 SX1255 frequency setting :
dgabino 0:102b50f941d0 26 F_register(24bit) = F_rf (Hz) / F_step(Hz)
dgabino 0:102b50f941d0 27 = F_rf (Hz) * 2^20 / F_xtal(Hz)
dgabino 0:102b50f941d0 28 = F_rf (Hz) * 2^20 / 32e6
dgabino 0:102b50f941d0 29 = F_rf (Hz) * 512/15625
dgabino 0:102b50f941d0 30 */
dgabino 0:102b50f941d0 31
dgabino 0:102b50f941d0 32 #define SX125x_TX_DAC_CLK_SEL 1 /* 0:int, 1:ext */
dgabino 0:102b50f941d0 33 #define SX125x_TX_DAC_GAIN 2 /* 3:0, 2:-3, 1:-6, 0:-9 dBFS (default 2) */
dgabino 0:102b50f941d0 34 #define SX125x_TX_MIX_GAIN 14 /* -38 + 2*TxMixGain dB (default 14) */
dgabino 0:102b50f941d0 35 #define SX125x_TX_PLL_BW 1 /* 0:75, 1:150, 2:225, 3:300 kHz (default 3) */
dgabino 0:102b50f941d0 36 #define SX125x_TX_ANA_BW 0 /* 17.5 / 2*(41-TxAnaBw) MHz (default 0) */
dgabino 0:102b50f941d0 37 #define SX125x_TX_DAC_BW 5 /* 24 + 8*TxDacBw Nb FIR taps (default 2) */
dgabino 0:102b50f941d0 38 #define SX125x_RX_LNA_GAIN 1 /* 1 to 6, 1 highest gain */
dgabino 0:102b50f941d0 39 #define SX125x_RX_BB_GAIN 12 /* 0 to 15 , 15 highest gain */
dgabino 0:102b50f941d0 40 #define SX125x_LNA_ZIN 1 /* 0:50, 1:200 Ohms (default 1) */
dgabino 0:102b50f941d0 41 #define SX125x_RX_ADC_BW 7 /* 0 to 7, 2:100<BW<200, 5:200<BW<400,7:400<BW kHz SSB (default 7) */
dgabino 0:102b50f941d0 42 #define SX125x_RX_ADC_TRIM 6 /* 0 to 7, 6 for 32MHz ref, 5 for 36MHz ref */
dgabino 0:102b50f941d0 43 #define SX125x_RX_BB_BW 0 /* 0:750, 1:500, 2:375; 3:250 kHz SSB (default 1, max 3) */
dgabino 0:102b50f941d0 44 #define SX125x_RX_PLL_BW 0 /* 0:75, 1:150, 2:225, 3:300 kHz (default 3, max 3) */
dgabino 0:102b50f941d0 45 #define SX125x_ADC_TEMP 0 /* ADC temperature measurement mode (default 0) */
dgabino 0:102b50f941d0 46 #define SX125x_XOSC_GM_STARTUP 13 /* (default 13) */
dgabino 0:102b50f941d0 47 #define SX125x_XOSC_DISABLE 2 /* Disable of Xtal Oscillator blocks bit0:regulator, bit1:core(gm), bit2:amplifier */
dgabino 0:102b50f941d0 48
dgabino 0:102b50f941d0 49 #endif // __SX125X_REGS_H__