David Fletcher / Mbed 2 deprecated CC3000WebServer

A Port of TI's Webserver for the CC3000

Dependencies:   mbed

CC3000Spi/spi.cpp@2:e6a185df9e4c, 2013-09-16 (annotated)

Committer:
dflet
Date:
Mon Sep 16 18:37:14 2013 +0000
Revision:
2:e6a185df9e4c
Parent:
0:6ad60d78b315 
ADC and Leds now work on board and config.html page.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dflet 0:6ad60d78b315 1
dflet 0:6ad60d78b315 2 /*****************************************************************************
dflet 0:6ad60d78b315 3 *
dflet 0:6ad60d78b315 4 * spi.c - CC3000 Host Driver Implementation.
dflet 0:6ad60d78b315 5 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
dflet 0:6ad60d78b315 6 *
dflet 0:6ad60d78b315 7 * Redistribution and use in source and binary forms, with or without
dflet 0:6ad60d78b315 8 * modification, are permitted provided that the following conditions
dflet 0:6ad60d78b315 9 * are met:
dflet 0:6ad60d78b315 10 *
dflet 0:6ad60d78b315 11 * Redistributions of source code must retain the above copyright
dflet 0:6ad60d78b315 12 * notice, this list of conditions and the following disclaimer.
dflet 0:6ad60d78b315 13 *
dflet 0:6ad60d78b315 14 * Redistributions in binary form must reproduce the above copyright
dflet 0:6ad60d78b315 15 * notice, this list of conditions and the following disclaimer in the
dflet 0:6ad60d78b315 16 * documentation and/or other materials provided with the
dflet 0:6ad60d78b315 17 * distribution.
dflet 0:6ad60d78b315 18 *
dflet 0:6ad60d78b315 19 * Neither the name of Texas Instruments Incorporated nor the names of
dflet 0:6ad60d78b315 20 * its contributors may be used to endorse or promote products derived
dflet 0:6ad60d78b315 21 * from this software without specific prior written permission.
dflet 0:6ad60d78b315 22 *
dflet 0:6ad60d78b315 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
dflet 0:6ad60d78b315 24 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
dflet 0:6ad60d78b315 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
dflet 0:6ad60d78b315 26 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
dflet 0:6ad60d78b315 27 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
dflet 0:6ad60d78b315 28 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
dflet 0:6ad60d78b315 29 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
dflet 0:6ad60d78b315 30 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
dflet 0:6ad60d78b315 31 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
dflet 0:6ad60d78b315 32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
dflet 0:6ad60d78b315 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
dflet 0:6ad60d78b315 34 *
dflet 0:6ad60d78b315 35 *****************************************************************************/
dflet 0:6ad60d78b315 36
dflet 0:6ad60d78b315 37 //*****************************************************************************
dflet 0:6ad60d78b315 38 //
dflet 0:6ad60d78b315 39 //! \addtogroup link_buff_api
dflet 0:6ad60d78b315 40 //! @{
dflet 0:6ad60d78b315 41 //
dflet 0:6ad60d78b315 42 //*****************************************************************************
dflet 0:6ad60d78b315 43 #include "mbed.h"
dflet 0:6ad60d78b315 44 #include "hci.h"
dflet 0:6ad60d78b315 45 #include "spi.h"
dflet 0:6ad60d78b315 46 #include "evnt_handler.h"
dflet 0:6ad60d78b315 47 #include "Board.h"
dflet 0:6ad60d78b315 48 //#include <msp430.h>
dflet 0:6ad60d78b315 49 #include "DigitalClass.h"
dflet 0:6ad60d78b315 50
dflet 0:6ad60d78b315 51 SPI spi(p5, p6, p7); // mosi, miso, sclk
dflet 0:6ad60d78b315 52 DigitalOut cs(p8); // chip select
dflet 0:6ad60d78b315 53
dflet 0:6ad60d78b315 54 DigitalClass Dio(p9, p10);
dflet 0:6ad60d78b315 55
dflet 0:6ad60d78b315 56 InterruptIn irq(p9);
dflet 0:6ad60d78b315 57
dflet 0:6ad60d78b315 58
dflet 0:6ad60d78b315 59 #define READ 3
dflet 0:6ad60d78b315 60 #define WRITE 1
dflet 0:6ad60d78b315 61
dflet 0:6ad60d78b315 62 #define HI(value) (((value) & 0xFF00) >> 8)
dflet 0:6ad60d78b315 63 #define LO(value) ((value) & 0x00FF)
dflet 0:6ad60d78b315 64
dflet 0:6ad60d78b315 65 #define ASSERT_CS() (cs = 0)//(RF_CS_OUT &= ~RF_CS)
dflet 0:6ad60d78b315 66
dflet 0:6ad60d78b315 67 #define DEASSERT_CS() (cs = 1)//(RF_CS_OUT |= RF_CS)
dflet 0:6ad60d78b315 68
dflet 0:6ad60d78b315 69 #define HEADERS_SIZE_EVNT (SPI_HEADER_SIZE + 5)
dflet 0:6ad60d78b315 70
dflet 0:6ad60d78b315 71 #define SPI_HEADER_SIZE (5)
dflet 0:6ad60d78b315 72
dflet 0:6ad60d78b315 73 #define eSPI_STATE_POWERUP (0)
dflet 0:6ad60d78b315 74 #define eSPI_STATE_INITIALIZED (1)
dflet 0:6ad60d78b315 75 #define eSPI_STATE_IDLE (2)
dflet 0:6ad60d78b315 76 #define eSPI_STATE_WRITE_IRQ (3)
dflet 0:6ad60d78b315 77 #define eSPI_STATE_WRITE_FIRST_PORTION (4)
dflet 0:6ad60d78b315 78 #define eSPI_STATE_WRITE_EOT (5)
dflet 0:6ad60d78b315 79 #define eSPI_STATE_READ_IRQ (6)
dflet 0:6ad60d78b315 80 #define eSPI_STATE_READ_FIRST_PORTION (7)
dflet 0:6ad60d78b315 81 #define eSPI_STATE_READ_EOT (8)
dflet 0:6ad60d78b315 82
dflet 0:6ad60d78b315 83 int a = 0;
dflet 0:6ad60d78b315 84
dflet 0:6ad60d78b315 85 typedef struct
dflet 0:6ad60d78b315 86 {
dflet 0:6ad60d78b315 87 gcSpiHandleRx SPIRxHandler;
dflet 0:6ad60d78b315 88 unsigned short usTxPacketLength;
dflet 0:6ad60d78b315 89 unsigned short usRxPacketLength;
dflet 0:6ad60d78b315 90 unsigned long ulSpiState;
dflet 0:6ad60d78b315 91 unsigned char *pTxPacket;
dflet 0:6ad60d78b315 92 unsigned char *pRxPacket;
dflet 0:6ad60d78b315 93
dflet 0:6ad60d78b315 94 }tSpiInformation;
dflet 0:6ad60d78b315 95
dflet 0:6ad60d78b315 96
dflet 0:6ad60d78b315 97 tSpiInformation sSpiInformation;
dflet 0:6ad60d78b315 98
dflet 0:6ad60d78b315 99
dflet 0:6ad60d78b315 100 // buffer for 5 bytes of SPI HEADER
dflet 0:6ad60d78b315 101 unsigned char tSpiReadHeader[] = {READ, 0, 0, 0, 0};
dflet 0:6ad60d78b315 102
dflet 0:6ad60d78b315 103
dflet 0:6ad60d78b315 104 void SpiWriteDataSynchronous(unsigned char *data, unsigned short size);
dflet 0:6ad60d78b315 105 void SpiWriteAsync(const unsigned char *data, unsigned short size);
dflet 0:6ad60d78b315 106 void SpiPauseSpi(void);
dflet 0:6ad60d78b315 107 void SpiResumeSpi(void);
dflet 0:6ad60d78b315 108 void SSIContReadOperation(void);
dflet 0:6ad60d78b315 109
dflet 0:6ad60d78b315 110 // The magic number that resides at the end of the TX/RX buffer (1 byte after
dflet 0:6ad60d78b315 111 // the allocated size) for the purpose of detection of the overrun. The location
dflet 0:6ad60d78b315 112 // of the memory where the magic number resides shall never be written. In case
dflet 0:6ad60d78b315 113 // it is written - the overrun occurred and either receive function or send
dflet 0:6ad60d78b315 114 // function will stuck forever.
dflet 0:6ad60d78b315 115 #define CC3000_BUFFER_MAGIC_NUMBER (0xDE)
dflet 0:6ad60d78b315 116
dflet 0:6ad60d78b315 117 ///////////////////////////////////////////////////////////////////////////////////////////////////////////
dflet 0:6ad60d78b315 118 //__no_init is used to prevent the buffer initialization in order to prevent hardware WDT expiration ///
dflet 0:6ad60d78b315 119 // before entering to 'main()'. ///
dflet 0:6ad60d78b315 120 //for every IDE, different syntax exists : 1. __CCS__ for CCS v5 ///
dflet 0:6ad60d78b315 121 // 2. __IAR_SYSTEMS_ICC__ for IAR Embedded Workbench ///
dflet 0:6ad60d78b315 122 // *CCS does not initialize variables - therefore, __no_init is not needed. ///
dflet 0:6ad60d78b315 123 ///////////////////////////////////////////////////////////////////////////////////////////////////////////
dflet 0:6ad60d78b315 124
dflet 0:6ad60d78b315 125 //#ifdef __CCS__
dflet 0:6ad60d78b315 126 char spi_buffer[CC3000_RX_BUFFER_SIZE];
dflet 0:6ad60d78b315 127
dflet 0:6ad60d78b315 128 //#elif __IAR_SYSTEMS_ICC__
dflet 0:6ad60d78b315 129 //__no_init char spi_buffer[CC3000_RX_BUFFER_SIZE];
dflet 0:6ad60d78b315 130 //#endif
dflet 0:6ad60d78b315 131
dflet 0:6ad60d78b315 132 //#ifdef __CCS__
dflet 0:6ad60d78b315 133 unsigned char wlan_tx_buffer[CC3000_TX_BUFFER_SIZE];
dflet 0:6ad60d78b315 134
dflet 0:6ad60d78b315 135 //#elif __IAR_SYSTEMS_ICC__
dflet 0:6ad60d78b315 136 //__no_init unsigned char wlan_tx_buffer[CC3000_TX_BUFFER_SIZE];
dflet 0:6ad60d78b315 137 //#endif
dflet 0:6ad60d78b315 138
dflet 0:6ad60d78b315 139 //*****************************************************************************
dflet 0:6ad60d78b315 140 //
dflet 0:6ad60d78b315 141 //! SpiCleanGPIOISR
dflet 0:6ad60d78b315 142 //!
dflet 0:6ad60d78b315 143 //! \param none
dflet 0:6ad60d78b315 144 //!
dflet 0:6ad60d78b315 145 //! \return none
dflet 0:6ad60d78b315 146 //!
dflet 0:6ad60d78b315 147 //! \brief This function get the reason for the GPIO interrupt and clear
dflet 0:6ad60d78b315 148 //! corresponding interrupt flag
dflet 0:6ad60d78b315 149 //
dflet 0:6ad60d78b315 150 //*****************************************************************************
dflet 0:6ad60d78b315 151 void
dflet 0:6ad60d78b315 152 SpiCleanGPIOISR(void)
dflet 0:6ad60d78b315 153 {
dflet 0:6ad60d78b315 154 WlanInterruptDisable();
dflet 0:6ad60d78b315 155 //SPI_IFG_PORT &= ~SPI_IRQ_PIN;
dflet 0:6ad60d78b315 156 }
dflet 0:6ad60d78b315 157
dflet 0:6ad60d78b315 158 //*****************************************************************************
dflet 0:6ad60d78b315 159 //
dflet 0:6ad60d78b315 160 //! SpiClose
dflet 0:6ad60d78b315 161 //!
dflet 0:6ad60d78b315 162 //! @param none
dflet 0:6ad60d78b315 163 //!
dflet 0:6ad60d78b315 164 //! @return none
dflet 0:6ad60d78b315 165 //!
dflet 0:6ad60d78b315 166 //! @brief Close Spi interface
dflet 0:6ad60d78b315 167 //
dflet 0:6ad60d78b315 168 //*****************************************************************************
dflet 0:6ad60d78b315 169 void
dflet 0:6ad60d78b315 170 SpiClose(void)
dflet 0:6ad60d78b315 171 {
dflet 0:6ad60d78b315 172 if (sSpiInformation.pRxPacket)
dflet 0:6ad60d78b315 173 {
dflet 0:6ad60d78b315 174 sSpiInformation.pRxPacket = 0;
dflet 0:6ad60d78b315 175 }
dflet 0:6ad60d78b315 176
dflet 0:6ad60d78b315 177 // Disable Interrupt
dflet 0:6ad60d78b315 178 tSLInformation.WlanInterruptDisable();
dflet 0:6ad60d78b315 179 }
dflet 0:6ad60d78b315 180
dflet 0:6ad60d78b315 181
dflet 0:6ad60d78b315 182 //*****************************************************************************
dflet 0:6ad60d78b315 183 //
dflet 0:6ad60d78b315 184 //! SpiOpen
dflet 0:6ad60d78b315 185 //!
dflet 0:6ad60d78b315 186 //! @param none
dflet 0:6ad60d78b315 187 //!
dflet 0:6ad60d78b315 188 //! @return none
dflet 0:6ad60d78b315 189 //!
dflet 0:6ad60d78b315 190 //! @brief Open Spi interface
dflet 0:6ad60d78b315 191 //
dflet 0:6ad60d78b315 192 //*****************************************************************************
dflet 0:6ad60d78b315 193 void
dflet 0:6ad60d78b315 194 SpiOpen(gcSpiHandleRx pfRxHandler)
dflet 0:6ad60d78b315 195 {
dflet 0:6ad60d78b315 196 sSpiInformation.ulSpiState = eSPI_STATE_POWERUP;
dflet 0:6ad60d78b315 197 sSpiInformation.SPIRxHandler = pfRxHandler;
dflet 0:6ad60d78b315 198 sSpiInformation.usTxPacketLength = 0;
dflet 0:6ad60d78b315 199 sSpiInformation.pTxPacket = NULL;
dflet 0:6ad60d78b315 200 sSpiInformation.pRxPacket = (unsigned char *)spi_buffer;
dflet 0:6ad60d78b315 201 sSpiInformation.usRxPacketLength = 0;
dflet 0:6ad60d78b315 202 spi_buffer[CC3000_RX_BUFFER_SIZE - 1] = CC3000_BUFFER_MAGIC_NUMBER;
dflet 0:6ad60d78b315 203 wlan_tx_buffer[CC3000_TX_BUFFER_SIZE - 1] = CC3000_BUFFER_MAGIC_NUMBER;
dflet 0:6ad60d78b315 204
dflet 0:6ad60d78b315 205 // Enable interrupt on WLAN IRQ pin
dflet 0:6ad60d78b315 206 tSLInformation.WlanInterruptEnable();
dflet 0:6ad60d78b315 207 }
dflet 0:6ad60d78b315 208
dflet 0:6ad60d78b315 209 //*****************************************************************************
dflet 0:6ad60d78b315 210 //
dflet 0:6ad60d78b315 211 //! init_spi
dflet 0:6ad60d78b315 212 //!
dflet 0:6ad60d78b315 213 //! @param none
dflet 0:6ad60d78b315 214 //!
dflet 0:6ad60d78b315 215 //! @return none
dflet 0:6ad60d78b315 216 //!
dflet 0:6ad60d78b315 217 //! @brief initializes an SPI interface
dflet 0:6ad60d78b315 218 //
dflet 0:6ad60d78b315 219 //*****************************************************************************
dflet 0:6ad60d78b315 220
dflet 0:6ad60d78b315 221 int init_spi(void)
dflet 0:6ad60d78b315 222 {
dflet 0:6ad60d78b315 223 spi.frequency(12000000);
dflet 0:6ad60d78b315 224 spi.format(8, 1);
dflet 0:6ad60d78b315 225 cs = 1;
dflet 0:6ad60d78b315 226
dflet 0:6ad60d78b315 227 //UCB0CTL1 |= UCSWRST; // Put state machine in reset
dflet 0:6ad60d78b315 228 //UCB0CTL0 = UCMSB + UCMST + UCMODE_0 + UCSYNC; // 3-pin, 8-bit SPI master
dflet 0:6ad60d78b315 229
dflet 0:6ad60d78b315 230 //UCB0CTL1 = UCSWRST + UCSSEL_2; // Use SMCLK, keep RESET
dflet 0:6ad60d78b315 231
dflet 0:6ad60d78b315 232 // Set SPI clock
dflet 0:6ad60d78b315 233 //UCB0CTL1 |= UCSWRST; // Put state machine in reset
dflet 0:6ad60d78b315 234 //UCB0BR0 = 2; // f_UCxCLK = 25MHz/2 = 12.5MHz
dflet 0:6ad60d78b315 235 //UCB0BR1 = 0;
dflet 0:6ad60d78b315 236 //UCB0CTL1 &= ~UCSWRST;
dflet 0:6ad60d78b315 237
dflet 0:6ad60d78b315 238 return(ESUCCESS);
dflet 0:6ad60d78b315 239 }
dflet 0:6ad60d78b315 240
dflet 0:6ad60d78b315 241 //*****************************************************************************
dflet 0:6ad60d78b315 242 //
dflet 0:6ad60d78b315 243 //! SpiFirstWrite
dflet 0:6ad60d78b315 244 //!
dflet 0:6ad60d78b315 245 //! @param ucBuf buffer to write
dflet 0:6ad60d78b315 246 //! @param usLength buffer's length
dflet 0:6ad60d78b315 247 //!
dflet 0:6ad60d78b315 248 //! @return none
dflet 0:6ad60d78b315 249 //!
dflet 0:6ad60d78b315 250 //! @brief enter point for first write flow
dflet 0:6ad60d78b315 251 //
dflet 0:6ad60d78b315 252 //*****************************************************************************
dflet 0:6ad60d78b315 253 long
dflet 0:6ad60d78b315 254 SpiFirstWrite(unsigned char *ucBuf, unsigned short usLength)
dflet 0:6ad60d78b315 255 {
dflet 0:6ad60d78b315 256 // workaround for first transaction
dflet 0:6ad60d78b315 257 ASSERT_CS();
dflet 0:6ad60d78b315 258
dflet 0:6ad60d78b315 259 // Assuming we are running on 24 MHz ~50 micro delay is 1200 cycles;
dflet 0:6ad60d78b315 260 //__delay_cycles(1200);
dflet 0:6ad60d78b315 261 wait_us(50);
dflet 0:6ad60d78b315 262 // SPI writes first 4 bytes of data
dflet 0:6ad60d78b315 263 SpiWriteDataSynchronous(ucBuf, 4);
dflet 0:6ad60d78b315 264 wait_us(50);
dflet 0:6ad60d78b315 265 //__delay_cycles(1200);
dflet 0:6ad60d78b315 266
dflet 0:6ad60d78b315 267 SpiWriteDataSynchronous(ucBuf + 4, usLength - 4);
dflet 0:6ad60d78b315 268
dflet 0:6ad60d78b315 269 // From this point on - operate in a regular way
dflet 0:6ad60d78b315 270 sSpiInformation.ulSpiState = eSPI_STATE_IDLE;
dflet 0:6ad60d78b315 271
dflet 0:6ad60d78b315 272 DEASSERT_CS();
dflet 0:6ad60d78b315 273
dflet 0:6ad60d78b315 274 return(0);
dflet 0:6ad60d78b315 275 }
dflet 0:6ad60d78b315 276
dflet 0:6ad60d78b315 277
dflet 0:6ad60d78b315 278 //*****************************************************************************
dflet 0:6ad60d78b315 279 //
dflet 0:6ad60d78b315 280 //! SpiWrite
dflet 0:6ad60d78b315 281 //!
dflet 0:6ad60d78b315 282 //! @param pUserBuffer buffer to write
dflet 0:6ad60d78b315 283 //! @param usLength buffer's length
dflet 0:6ad60d78b315 284 //!
dflet 0:6ad60d78b315 285 //! @return none
dflet 0:6ad60d78b315 286 //!
dflet 0:6ad60d78b315 287 //! @brief Spi write operation
dflet 0:6ad60d78b315 288 //
dflet 0:6ad60d78b315 289 //*****************************************************************************
dflet 0:6ad60d78b315 290 long
dflet 0:6ad60d78b315 291 SpiWrite(unsigned char *pUserBuffer, unsigned short usLength)
dflet 0:6ad60d78b315 292 {
dflet 0:6ad60d78b315 293 unsigned char ucPad = 0;
dflet 0:6ad60d78b315 294
dflet 0:6ad60d78b315 295 // Figure out the total length of the packet in order to figure out if there
dflet 0:6ad60d78b315 296 // is padding or not
dflet 0:6ad60d78b315 297 if(!(usLength & 0x0001))
dflet 0:6ad60d78b315 298 {
dflet 0:6ad60d78b315 299 ucPad++;
dflet 0:6ad60d78b315 300 }
dflet 0:6ad60d78b315 301
dflet 0:6ad60d78b315 302 pUserBuffer[0] = WRITE;
dflet 0:6ad60d78b315 303 pUserBuffer[1] = HI(usLength + ucPad);
dflet 0:6ad60d78b315 304 pUserBuffer[2] = LO(usLength + ucPad);
dflet 0:6ad60d78b315 305 pUserBuffer[3] = 0;
dflet 0:6ad60d78b315 306 pUserBuffer[4] = 0;
dflet 0:6ad60d78b315 307
dflet 0:6ad60d78b315 308 usLength += (SPI_HEADER_SIZE + ucPad);
dflet 0:6ad60d78b315 309
dflet 0:6ad60d78b315 310 // The magic number that resides at the end of the TX/RX buffer (1 byte after
dflet 0:6ad60d78b315 311 // the allocated size) for the purpose of detection of the overrun. If the
dflet 0:6ad60d78b315 312 // magic number is overwritten - buffer overrun occurred - and we will stuck
dflet 0:6ad60d78b315 313 // here forever!
dflet 0:6ad60d78b315 314 if (wlan_tx_buffer[CC3000_TX_BUFFER_SIZE - 1] != CC3000_BUFFER_MAGIC_NUMBER)
dflet 0:6ad60d78b315 315 {
dflet 0:6ad60d78b315 316 while (1)
dflet 0:6ad60d78b315 317 ;
dflet 0:6ad60d78b315 318 }
dflet 0:6ad60d78b315 319
dflet 0:6ad60d78b315 320 if (sSpiInformation.ulSpiState == eSPI_STATE_POWERUP)
dflet 0:6ad60d78b315 321 {
dflet 0:6ad60d78b315 322 while (sSpiInformation.ulSpiState != eSPI_STATE_INITIALIZED)
dflet 0:6ad60d78b315 323 ;
dflet 0:6ad60d78b315 324 }
dflet 0:6ad60d78b315 325
dflet 0:6ad60d78b315 326 if (sSpiInformation.ulSpiState == eSPI_STATE_INITIALIZED)
dflet 0:6ad60d78b315 327 {
dflet 0:6ad60d78b315 328 // This is time for first TX/RX transactions over SPI: the IRQ is down -
dflet 0:6ad60d78b315 329 // so need to send read buffer size command
dflet 0:6ad60d78b315 330 SpiFirstWrite(pUserBuffer, usLength);
dflet 0:6ad60d78b315 331 //printf("first TX/RX transaction....\r\n");
dflet 0:6ad60d78b315 332 }
dflet 0:6ad60d78b315 333 else
dflet 0:6ad60d78b315 334 {
dflet 0:6ad60d78b315 335 // We need to prevent here race that can occur in case 2 back to back
dflet 0:6ad60d78b315 336 // packets are sent to the device, so the state will move to IDLE and once
dflet 0:6ad60d78b315 337 //again to not IDLE due to IRQ
dflet 0:6ad60d78b315 338 tSLInformation.WlanInterruptDisable();
dflet 0:6ad60d78b315 339
dflet 0:6ad60d78b315 340 while (sSpiInformation.ulSpiState != eSPI_STATE_IDLE)
dflet 0:6ad60d78b315 341 {
dflet 0:6ad60d78b315 342 ;
dflet 0:6ad60d78b315 343 }
dflet 0:6ad60d78b315 344
dflet 0:6ad60d78b315 345
dflet 0:6ad60d78b315 346 sSpiInformation.ulSpiState = eSPI_STATE_WRITE_IRQ;
dflet 0:6ad60d78b315 347 sSpiInformation.pTxPacket = pUserBuffer;
dflet 0:6ad60d78b315 348 sSpiInformation.usTxPacketLength = usLength;
dflet 0:6ad60d78b315 349
dflet 0:6ad60d78b315 350 // Assert the CS line and wait till SSI IRQ line is active and then
dflet 0:6ad60d78b315 351 // initialize write operation
dflet 0:6ad60d78b315 352 ASSERT_CS();
dflet 0:6ad60d78b315 353
dflet 0:6ad60d78b315 354 // Re-enable IRQ - if it was not disabled - this is not a problem...
dflet 0:6ad60d78b315 355 tSLInformation.WlanInterruptEnable();
dflet 0:6ad60d78b315 356 //DEASSERT_CS();
dflet 0:6ad60d78b315 357
dflet 0:6ad60d78b315 358
dflet 0:6ad60d78b315 359 // check for a missing interrupt between the CS assertion and enabling back the interrupts
dflet 0:6ad60d78b315 360 if (tSLInformation.ReadWlanInterruptPin() == 0)
dflet 0:6ad60d78b315 361 {
dflet 0:6ad60d78b315 362 //printf("Deal with missing interrupt....\r\n");
dflet 0:6ad60d78b315 363 SpiWriteDataSynchronous(sSpiInformation.pTxPacket, sSpiInformation.usTxPacketLength);
dflet 0:6ad60d78b315 364
dflet 0:6ad60d78b315 365 sSpiInformation.ulSpiState = eSPI_STATE_IDLE;
dflet 0:6ad60d78b315 366
dflet 0:6ad60d78b315 367 DEASSERT_CS();
dflet 0:6ad60d78b315 368 }
dflet 0:6ad60d78b315 369
dflet 0:6ad60d78b315 370 }
dflet 0:6ad60d78b315 371
dflet 0:6ad60d78b315 372 // Due to the fact that we are currently implementing a blocking situation
dflet 0:6ad60d78b315 373 // here we will wait till end of transaction
dflet 0:6ad60d78b315 374 while (eSPI_STATE_IDLE != sSpiInformation.ulSpiState)
dflet 0:6ad60d78b315 375 ;
dflet 0:6ad60d78b315 376
dflet 0:6ad60d78b315 377 return(0);
dflet 0:6ad60d78b315 378 }
dflet 0:6ad60d78b315 379
dflet 0:6ad60d78b315 380
dflet 0:6ad60d78b315 381 //*****************************************************************************
dflet 0:6ad60d78b315 382 //
dflet 0:6ad60d78b315 383 //! SpiWriteDataSynchronous
dflet 0:6ad60d78b315 384 //!
dflet 0:6ad60d78b315 385 //! @param data buffer to write
dflet 0:6ad60d78b315 386 //! @param size buffer's size
dflet 0:6ad60d78b315 387 //!
dflet 0:6ad60d78b315 388 //! @return none
dflet 0:6ad60d78b315 389 //!
dflet 0:6ad60d78b315 390 //! @brief Spi write operation
dflet 0:6ad60d78b315 391 //
dflet 0:6ad60d78b315 392 //*****************************************************************************
dflet 0:6ad60d78b315 393 void
dflet 0:6ad60d78b315 394 SpiWriteDataSynchronous(unsigned char *data, unsigned short size)
dflet 0:6ad60d78b315 395 {
dflet 0:6ad60d78b315 396 //printf("SPI Write\r\n");
dflet 0:6ad60d78b315 397 while (size)
dflet 0:6ad60d78b315 398 {
dflet 0:6ad60d78b315 399 spi.write(*data);
dflet 0:6ad60d78b315 400
dflet 0:6ad60d78b315 401 size --;
dflet 0:6ad60d78b315 402 //if(*data > 31 && *data < 127){
dflet 0:6ad60d78b315 403 //printf(" %c",*data);
dflet 0:6ad60d78b315 404 //}else{
dflet 0:6ad60d78b315 405 //printf(" %x",*data);
dflet 0:6ad60d78b315 406 //}
dflet 0:6ad60d78b315 407
dflet 0:6ad60d78b315 408 data++;
dflet 0:6ad60d78b315 409 }
dflet 0:6ad60d78b315 410 //printf("\r\n");
dflet 0:6ad60d78b315 411 }
dflet 0:6ad60d78b315 412
dflet 0:6ad60d78b315 413 //*****************************************************************************
dflet 0:6ad60d78b315 414 //
dflet 0:6ad60d78b315 415 //! SpiReadDataSynchronous
dflet 0:6ad60d78b315 416 //!
dflet 0:6ad60d78b315 417 //! @param data buffer to read
dflet 0:6ad60d78b315 418 //! @param size buffer's size
dflet 0:6ad60d78b315 419 //!
dflet 0:6ad60d78b315 420 //! @return none
dflet 0:6ad60d78b315 421 //!
dflet 0:6ad60d78b315 422 //! @brief Spi read operation
dflet 0:6ad60d78b315 423 //
dflet 0:6ad60d78b315 424 //*****************************************************************************
dflet 0:6ad60d78b315 425 void
dflet 0:6ad60d78b315 426 SpiReadDataSynchronous(unsigned char *data, unsigned short size)
dflet 0:6ad60d78b315 427 {
dflet 0:6ad60d78b315 428 unsigned char *data_to_send = tSpiReadHeader;
dflet 0:6ad60d78b315 429 //printf("SPI Read\r\n");
dflet 0:6ad60d78b315 430 for (int i = 0; i < size; i ++)
dflet 0:6ad60d78b315 431 {
dflet 0:6ad60d78b315 432 data[i] = spi.write(data_to_send[0]);
dflet 0:6ad60d78b315 433
dflet 0:6ad60d78b315 434 //if(data[i] > 31 && data[i] < 127){
dflet 0:6ad60d78b315 435 //printf(" %c",data[i]);
dflet 0:6ad60d78b315 436 //}else{
dflet 0:6ad60d78b315 437 //printf(" %x",data[i]);
dflet 0:6ad60d78b315 438 //}
dflet 0:6ad60d78b315 439
dflet 0:6ad60d78b315 440 }
dflet 0:6ad60d78b315 441 //printf("\r\n");
dflet 0:6ad60d78b315 442 }
dflet 0:6ad60d78b315 443
dflet 0:6ad60d78b315 444
dflet 0:6ad60d78b315 445 //*****************************************************************************
dflet 0:6ad60d78b315 446 //
dflet 0:6ad60d78b315 447 //! SpiReadHeader
dflet 0:6ad60d78b315 448 //!
dflet 0:6ad60d78b315 449 //! \param buffer
dflet 0:6ad60d78b315 450 //!
dflet 0:6ad60d78b315 451 //! \return none
dflet 0:6ad60d78b315 452 //!
dflet 0:6ad60d78b315 453 //! \brief This function enter point for read flow: first we read minimal 5
dflet 0:6ad60d78b315 454 //! SPI header bytes and 5 Event Data bytes
dflet 0:6ad60d78b315 455 //
dflet 0:6ad60d78b315 456 //*****************************************************************************
dflet 0:6ad60d78b315 457 void
dflet 0:6ad60d78b315 458 SpiReadHeader(void)
dflet 0:6ad60d78b315 459 {
dflet 0:6ad60d78b315 460 SpiReadDataSynchronous(sSpiInformation.pRxPacket, 10);
dflet 0:6ad60d78b315 461 }
dflet 0:6ad60d78b315 462
dflet 0:6ad60d78b315 463
dflet 0:6ad60d78b315 464 //*****************************************************************************
dflet 0:6ad60d78b315 465 //
dflet 0:6ad60d78b315 466 //! SpiReadDataCont
dflet 0:6ad60d78b315 467 //!
dflet 0:6ad60d78b315 468 //! @param None
dflet 0:6ad60d78b315 469 //!
dflet 0:6ad60d78b315 470 //! @return None
dflet 0:6ad60d78b315 471 //!
dflet 0:6ad60d78b315 472 //! @brief This function processes received SPI Header and in accordance with
dflet 0:6ad60d78b315 473 //! it - continues reading the packet
dflet 0:6ad60d78b315 474 //
dflet 0:6ad60d78b315 475 //*****************************************************************************
dflet 0:6ad60d78b315 476 long
dflet 0:6ad60d78b315 477 SpiReadDataCont(void)
dflet 0:6ad60d78b315 478 {
dflet 0:6ad60d78b315 479 long data_to_recv;
dflet 0:6ad60d78b315 480 unsigned char *evnt_buff, type;
dflet 0:6ad60d78b315 481
dflet 0:6ad60d78b315 482 //determine what type of packet we have
dflet 0:6ad60d78b315 483 evnt_buff = sSpiInformation.pRxPacket;
dflet 0:6ad60d78b315 484 data_to_recv = 0;
dflet 0:6ad60d78b315 485 STREAM_TO_UINT8((char *)(evnt_buff + SPI_HEADER_SIZE), HCI_PACKET_TYPE_OFFSET, type);
dflet 0:6ad60d78b315 486
dflet 0:6ad60d78b315 487 switch(type)
dflet 0:6ad60d78b315 488 {
dflet 0:6ad60d78b315 489 case HCI_TYPE_DATA:
dflet 0:6ad60d78b315 490 {
dflet 0:6ad60d78b315 491 // We need to read the rest of data..
dflet 0:6ad60d78b315 492 STREAM_TO_UINT16((char *)(evnt_buff + SPI_HEADER_SIZE), HCI_DATA_LENGTH_OFFSET, data_to_recv);
dflet 0:6ad60d78b315 493
dflet 0:6ad60d78b315 494 if (!((HEADERS_SIZE_EVNT + data_to_recv) & 1))
dflet 0:6ad60d78b315 495 {
dflet 0:6ad60d78b315 496 data_to_recv++;
dflet 0:6ad60d78b315 497 }
dflet 0:6ad60d78b315 498
dflet 0:6ad60d78b315 499 if (data_to_recv)
dflet 0:6ad60d78b315 500 {
dflet 0:6ad60d78b315 501 SpiReadDataSynchronous(evnt_buff + 10, data_to_recv);
dflet 0:6ad60d78b315 502 }
dflet 0:6ad60d78b315 503 break;
dflet 0:6ad60d78b315 504 }
dflet 0:6ad60d78b315 505 case HCI_TYPE_EVNT:
dflet 0:6ad60d78b315 506 {
dflet 0:6ad60d78b315 507 // Calculate the rest length of the data
dflet 0:6ad60d78b315 508 STREAM_TO_UINT8((char *)(evnt_buff + SPI_HEADER_SIZE), HCI_EVENT_LENGTH_OFFSET, data_to_recv);
dflet 0:6ad60d78b315 509
dflet 0:6ad60d78b315 510 data_to_recv -= 1;
dflet 0:6ad60d78b315 511
dflet 0:6ad60d78b315 512 // Add padding byte if needed
dflet 0:6ad60d78b315 513 if ((HEADERS_SIZE_EVNT + data_to_recv) & 1)
dflet 0:6ad60d78b315 514 {
dflet 0:6ad60d78b315 515
dflet 0:6ad60d78b315 516 data_to_recv++;
dflet 0:6ad60d78b315 517 }
dflet 0:6ad60d78b315 518
dflet 0:6ad60d78b315 519 if (data_to_recv)
dflet 0:6ad60d78b315 520 {
dflet 0:6ad60d78b315 521 SpiReadDataSynchronous(evnt_buff + 10, data_to_recv);
dflet 0:6ad60d78b315 522 }
dflet 0:6ad60d78b315 523
dflet 0:6ad60d78b315 524 sSpiInformation.ulSpiState = eSPI_STATE_READ_EOT;
dflet 0:6ad60d78b315 525 break;
dflet 0:6ad60d78b315 526 }
dflet 0:6ad60d78b315 527 }
dflet 0:6ad60d78b315 528
dflet 0:6ad60d78b315 529 return (0);
dflet 0:6ad60d78b315 530 }
dflet 0:6ad60d78b315 531
dflet 0:6ad60d78b315 532
dflet 0:6ad60d78b315 533 //*****************************************************************************
dflet 0:6ad60d78b315 534 //
dflet 0:6ad60d78b315 535 //! SpiPauseSpi
dflet 0:6ad60d78b315 536 //!
dflet 0:6ad60d78b315 537 //! @param none
dflet 0:6ad60d78b315 538 //!
dflet 0:6ad60d78b315 539 //! @return none
dflet 0:6ad60d78b315 540 //!
dflet 0:6ad60d78b315 541 //! @brief Spi pause operation
dflet 0:6ad60d78b315 542 //
dflet 0:6ad60d78b315 543 //*****************************************************************************
dflet 0:6ad60d78b315 544
dflet 0:6ad60d78b315 545 void
dflet 0:6ad60d78b315 546 SpiPauseSpi(void)
dflet 0:6ad60d78b315 547 {
dflet 0:6ad60d78b315 548 WlanInterruptDisable();
dflet 0:6ad60d78b315 549 //SPI_IRQ_IE &= ~SPI_IRQ_PIN;
dflet 0:6ad60d78b315 550 }
dflet 0:6ad60d78b315 551
dflet 0:6ad60d78b315 552
dflet 0:6ad60d78b315 553 //*****************************************************************************
dflet 0:6ad60d78b315 554 //
dflet 0:6ad60d78b315 555 //! SpiResumeSpi
dflet 0:6ad60d78b315 556 //!
dflet 0:6ad60d78b315 557 //! @param none
dflet 0:6ad60d78b315 558 //!
dflet 0:6ad60d78b315 559 //! @return none
dflet 0:6ad60d78b315 560 //!
dflet 0:6ad60d78b315 561 //! @brief Spi resume operation
dflet 0:6ad60d78b315 562 //
dflet 0:6ad60d78b315 563 //*****************************************************************************
dflet 0:6ad60d78b315 564
dflet 0:6ad60d78b315 565 void
dflet 0:6ad60d78b315 566 SpiResumeSpi(void)
dflet 0:6ad60d78b315 567 {
dflet 0:6ad60d78b315 568 WlanInterruptEnable();
dflet 0:6ad60d78b315 569 //SPI_IRQ_IE |= SPI_IRQ_PIN;
dflet 0:6ad60d78b315 570 }
dflet 0:6ad60d78b315 571
dflet 0:6ad60d78b315 572
dflet 0:6ad60d78b315 573 //*****************************************************************************
dflet 0:6ad60d78b315 574 //
dflet 0:6ad60d78b315 575 //! SpiTriggerRxProcessing
dflet 0:6ad60d78b315 576 //!
dflet 0:6ad60d78b315 577 //! @param none
dflet 0:6ad60d78b315 578 //!
dflet 0:6ad60d78b315 579 //! @return none
dflet 0:6ad60d78b315 580 //!
dflet 0:6ad60d78b315 581 //! @brief Spi RX processing
dflet 0:6ad60d78b315 582 //
dflet 0:6ad60d78b315 583 //*****************************************************************************
dflet 0:6ad60d78b315 584 void
dflet 0:6ad60d78b315 585 SpiTriggerRxProcessing(void)
dflet 0:6ad60d78b315 586 {
dflet 0:6ad60d78b315 587
dflet 0:6ad60d78b315 588 // Trigger Rx processing
dflet 0:6ad60d78b315 589 SpiPauseSpi();
dflet 0:6ad60d78b315 590 DEASSERT_CS();
dflet 0:6ad60d78b315 591
dflet 0:6ad60d78b315 592 // The magic number that resides at the end of the TX/RX buffer (1 byte after
dflet 0:6ad60d78b315 593 // the allocated size) for the purpose of detection of the overrun. If the
dflet 0:6ad60d78b315 594 // magic number is overwritten - buffer overrun occurred - and we will stuck
dflet 0:6ad60d78b315 595 // here forever!
dflet 0:6ad60d78b315 596 if (sSpiInformation.pRxPacket[CC3000_RX_BUFFER_SIZE - 1] != CC3000_BUFFER_MAGIC_NUMBER)
dflet 0:6ad60d78b315 597 {
dflet 0:6ad60d78b315 598 while (1)
dflet 0:6ad60d78b315 599 ;
dflet 0:6ad60d78b315 600 }
dflet 0:6ad60d78b315 601
dflet 0:6ad60d78b315 602 sSpiInformation.ulSpiState = eSPI_STATE_IDLE;
dflet 0:6ad60d78b315 603 sSpiInformation.SPIRxHandler(sSpiInformation.pRxPacket + SPI_HEADER_SIZE);
dflet 0:6ad60d78b315 604 }
dflet 0:6ad60d78b315 605
dflet 0:6ad60d78b315 606 //*****************************************************************************
dflet 0:6ad60d78b315 607 //
dflet 0:6ad60d78b315 608 //! IntSpiGPIOHandler
dflet 0:6ad60d78b315 609 //!
dflet 0:6ad60d78b315 610 //! @param none
dflet 0:6ad60d78b315 611 //!
dflet 0:6ad60d78b315 612 //! @return none
dflet 0:6ad60d78b315 613 //!
dflet 0:6ad60d78b315 614 //! @brief GPIO A interrupt handler. When the external SSI WLAN device is
dflet 0:6ad60d78b315 615 //! ready to interact with Host CPU it generates an interrupt signal.
dflet 0:6ad60d78b315 616 //! After that Host CPU has registered this interrupt request
dflet 0:6ad60d78b315 617 //! it set the corresponding /CS in active state.
dflet 0:6ad60d78b315 618 //
dflet 0:6ad60d78b315 619 //*****************************************************************************
dflet 0:6ad60d78b315 620 //#pragma vector=PORT2_VECTOR
dflet 0:6ad60d78b315 621 //__interrupt
dflet 0:6ad60d78b315 622 void IntSpiGPIOHandler(void)
dflet 0:6ad60d78b315 623 {
dflet 0:6ad60d78b315 624 //switch(__even_in_range(P2IV, P2IV_P2IFG7))
dflet 0:6ad60d78b315 625 //{
dflet 0:6ad60d78b315 626 //case P2IV_P2IFG4:
dflet 0:6ad60d78b315 627 if (sSpiInformation.ulSpiState == eSPI_STATE_POWERUP)
dflet 0:6ad60d78b315 628 {
dflet 0:6ad60d78b315 629 //This means IRQ line was low call a callback of HCI Layer to inform
dflet 0:6ad60d78b315 630 //on event
dflet 0:6ad60d78b315 631 sSpiInformation.ulSpiState = eSPI_STATE_INITIALIZED;
dflet 0:6ad60d78b315 632 }
dflet 0:6ad60d78b315 633 else if (sSpiInformation.ulSpiState == eSPI_STATE_IDLE)
dflet 0:6ad60d78b315 634 {
dflet 0:6ad60d78b315 635 sSpiInformation.ulSpiState = eSPI_STATE_READ_IRQ;
dflet 0:6ad60d78b315 636
dflet 0:6ad60d78b315 637 /* IRQ line goes down - we are start reception */
dflet 0:6ad60d78b315 638 ASSERT_CS();
dflet 0:6ad60d78b315 639
dflet 0:6ad60d78b315 640 // Wait for TX/RX Compete which will come as DMA interrupt
dflet 0:6ad60d78b315 641 SpiReadHeader();
dflet 0:6ad60d78b315 642
dflet 0:6ad60d78b315 643 sSpiInformation.ulSpiState = eSPI_STATE_READ_EOT;
dflet 0:6ad60d78b315 644
dflet 0:6ad60d78b315 645 SSIContReadOperation();
dflet 0:6ad60d78b315 646 }
dflet 0:6ad60d78b315 647 else if (sSpiInformation.ulSpiState == eSPI_STATE_WRITE_IRQ)
dflet 0:6ad60d78b315 648 {
dflet 0:6ad60d78b315 649 SpiWriteDataSynchronous(sSpiInformation.pTxPacket, sSpiInformation.usTxPacketLength);
dflet 0:6ad60d78b315 650
dflet 0:6ad60d78b315 651 sSpiInformation.ulSpiState = eSPI_STATE_IDLE;
dflet 0:6ad60d78b315 652
dflet 0:6ad60d78b315 653 DEASSERT_CS();
dflet 0:6ad60d78b315 654 }
dflet 0:6ad60d78b315 655 // break;
dflet 0:6ad60d78b315 656 //default:
dflet 0:6ad60d78b315 657 // break;
dflet 0:6ad60d78b315 658 //}
dflet 0:6ad60d78b315 659
dflet 0:6ad60d78b315 660 }
dflet 0:6ad60d78b315 661
dflet 0:6ad60d78b315 662 //*****************************************************************************
dflet 0:6ad60d78b315 663 //
dflet 0:6ad60d78b315 664 //! SSIContReadOperation
dflet 0:6ad60d78b315 665 //!
dflet 0:6ad60d78b315 666 //! @param none
dflet 0:6ad60d78b315 667 //!
dflet 0:6ad60d78b315 668 //! @return none
dflet 0:6ad60d78b315 669 //!
dflet 0:6ad60d78b315 670 //! @brief SPI read operation
dflet 0:6ad60d78b315 671 //
dflet 0:6ad60d78b315 672 //*****************************************************************************
dflet 0:6ad60d78b315 673
dflet 0:6ad60d78b315 674 void
dflet 0:6ad60d78b315 675 SSIContReadOperation(void)
dflet 0:6ad60d78b315 676 {
dflet 0:6ad60d78b315 677 // The header was read - continue with the payload read
dflet 0:6ad60d78b315 678 if (!SpiReadDataCont())
dflet 0:6ad60d78b315 679 {
dflet 0:6ad60d78b315 680 // All the data was read - finalize handling by switching to the task
dflet 0:6ad60d78b315 681 // and calling from task Event Handler
dflet 0:6ad60d78b315 682 SpiTriggerRxProcessing();
dflet 0:6ad60d78b315 683 }
dflet 0:6ad60d78b315 684 }
dflet 0:6ad60d78b315 685
dflet 0:6ad60d78b315 686
dflet 0:6ad60d78b315 687 //*****************************************************************************
dflet 0:6ad60d78b315 688 //
dflet 0:6ad60d78b315 689 //! TXBufferIsEmpty
dflet 0:6ad60d78b315 690 //!
dflet 0:6ad60d78b315 691 //! @param
dflet 0:6ad60d78b315 692 //!
dflet 0:6ad60d78b315 693 //! @return returns 1 if buffer is empty, 0 otherwise
dflet 0:6ad60d78b315 694 //!
dflet 0:6ad60d78b315 695 //! @brief Indication if TX SPI buffer is empty
dflet 0:6ad60d78b315 696 //
dflet 0:6ad60d78b315 697 //*****************************************************************************
dflet 0:6ad60d78b315 698
dflet 0:6ad60d78b315 699 long TXBufferIsEmpty(void)
dflet 0:6ad60d78b315 700 {
dflet 0:6ad60d78b315 701 return 1;//(UCB0IFG&UCTXIFG);
dflet 0:6ad60d78b315 702 }
dflet 0:6ad60d78b315 703
dflet 0:6ad60d78b315 704 //*****************************************************************************
dflet 0:6ad60d78b315 705 //
dflet 0:6ad60d78b315 706 //! RXBufferIsEmpty
dflet 0:6ad60d78b315 707 //!
dflet 0:6ad60d78b315 708 //! @param none
dflet 0:6ad60d78b315 709 //!
dflet 0:6ad60d78b315 710 //! @return returns 1 if buffer is empty, 0 otherwise
dflet 0:6ad60d78b315 711 //!
dflet 0:6ad60d78b315 712 //! @brief Indication if RX SPI buffer is empty
dflet 0:6ad60d78b315 713 //
dflet 0:6ad60d78b315 714 //*****************************************************************************
dflet 0:6ad60d78b315 715
dflet 0:6ad60d78b315 716 long RXBufferIsEmpty(void)
dflet 0:6ad60d78b315 717 {
dflet 0:6ad60d78b315 718 return 1;//(UCB0IFG&UCRXIFG);
dflet 0:6ad60d78b315 719 }
dflet 0:6ad60d78b315 720
dflet 0:6ad60d78b315 721 //*****************************************************************************
dflet 0:6ad60d78b315 722 //
dflet 0:6ad60d78b315 723 //! ReadWlanInterruptPin
dflet 0:6ad60d78b315 724 //!
dflet 0:6ad60d78b315 725 //! @param none
dflet 0:6ad60d78b315 726 //!
dflet 0:6ad60d78b315 727 //! @return none
dflet 0:6ad60d78b315 728 //!
dflet 0:6ad60d78b315 729 //! @brief return wlan interrup pin
dflet 0:6ad60d78b315 730 //
dflet 0:6ad60d78b315 731 //*****************************************************************************
dflet 0:6ad60d78b315 732
dflet 0:6ad60d78b315 733 int ReadWlanInterruptPin(void)
dflet 0:6ad60d78b315 734 {
dflet 0:6ad60d78b315 735
dflet 0:6ad60d78b315 736 int8_t val;
dflet 0:6ad60d78b315 737 //printf("WLAN_IRQ %i \r\n",Dio.WLAN_IRQ.read());
dflet 0:6ad60d78b315 738 val = Dio.WLAN_IRQ.read();
dflet 0:6ad60d78b315 739 return (int)val;
dflet 0:6ad60d78b315 740
dflet 0:6ad60d78b315 741 }
dflet 0:6ad60d78b315 742
dflet 0:6ad60d78b315 743 //*****************************************************************************
dflet 0:6ad60d78b315 744 //
dflet 0:6ad60d78b315 745 //! WlanInterruptEnable
dflet 0:6ad60d78b315 746 //!
dflet 0:6ad60d78b315 747 //! @param none
dflet 0:6ad60d78b315 748 //!
dflet 0:6ad60d78b315 749 //! @return none
dflet 0:6ad60d78b315 750 //!
dflet 0:6ad60d78b315 751 //! @brief Enable wlan IRQ pin
dflet 0:6ad60d78b315 752 //
dflet 0:6ad60d78b315 753 //*****************************************************************************
dflet 0:6ad60d78b315 754
dflet 0:6ad60d78b315 755 void WlanInterruptEnable()
dflet 0:6ad60d78b315 756 {
dflet 0:6ad60d78b315 757 //int8_t val;
dflet 0:6ad60d78b315 758 //int a;
dflet 0:6ad60d78b315 759 //printf("IRQ Enabled....\r\n");
dflet 0:6ad60d78b315 760 //irq.fall(&IntSpiGPIOHandler);
dflet 0:6ad60d78b315 761 //wait_ms(1);
dflet 0:6ad60d78b315 762 //val = ReadWlanInterruptPin();
dflet 0:6ad60d78b315 763
dflet 0:6ad60d78b315 764 // Taken from SpiWrite above, it appears to work better here????
dflet 0:6ad60d78b315 765 // First deal with missing interrupt if any. Bypass first run,
dflet 0:6ad60d78b315 766 // refer to Wlan_start() (wlan.cpp) toggling IRQ.
dflet 0:6ad60d78b315 767 /*
dflet 0:6ad60d78b315 768 if (a < 1){
dflet 0:6ad60d78b315 769 a++;
dflet 0:6ad60d78b315 770 }
dflet 0:6ad60d78b315 771 else
dflet 0:6ad60d78b315 772 {
dflet 0:6ad60d78b315 773
dflet 0:6ad60d78b315 774 if (tSLInformation.ReadWlanInterruptPin() == 0)
dflet 0:6ad60d78b315 775 {
dflet 0:6ad60d78b315 776
dflet 0:6ad60d78b315 777 ASSERT_CS();
dflet 0:6ad60d78b315 778 //printf("Deal with missing interrupt....\r\n");
dflet 0:6ad60d78b315 779
dflet 0:6ad60d78b315 780 SpiWriteDataSynchronous(sSpiInformation.pTxPacket, sSpiInformation.usTxPacketLength);
dflet 0:6ad60d78b315 781
dflet 0:6ad60d78b315 782 sSpiInformation.ulSpiState = eSPI_STATE_IDLE;
dflet 0:6ad60d78b315 783
dflet 0:6ad60d78b315 784 DEASSERT_CS();
dflet 0:6ad60d78b315 785 }
dflet 0:6ad60d78b315 786 a=1;
dflet 0:6ad60d78b315 787 }
dflet 0:6ad60d78b315 788 */
dflet 0:6ad60d78b315 789 irq.fall(&IntSpiGPIOHandler);
dflet 0:6ad60d78b315 790 //SPI_IRQ_IES |= SPI_IRQ_PIN;
dflet 0:6ad60d78b315 791 //SPI_IRQ_IE |= SPI_IRQ_PIN;
dflet 0:6ad60d78b315 792 }
dflet 0:6ad60d78b315 793
dflet 0:6ad60d78b315 794 //*****************************************************************************
dflet 0:6ad60d78b315 795 //
dflet 0:6ad60d78b315 796 //! WlanInterruptDisable
dflet 0:6ad60d78b315 797 //!
dflet 0:6ad60d78b315 798 //! @param none
dflet 0:6ad60d78b315 799 //!
dflet 0:6ad60d78b315 800 //! @return none
dflet 0:6ad60d78b315 801 //!
dflet 0:6ad60d78b315 802 //! @brief Disable waln IrQ pin
dflet 0:6ad60d78b315 803 //
dflet 0:6ad60d78b315 804 //*****************************************************************************
dflet 0:6ad60d78b315 805
dflet 0:6ad60d78b315 806 void WlanInterruptDisable()
dflet 0:6ad60d78b315 807 {
dflet 0:6ad60d78b315 808
dflet 0:6ad60d78b315 809 irq.fall(NULL);
dflet 0:6ad60d78b315 810
dflet 0:6ad60d78b315 811 }
dflet 0:6ad60d78b315 812
dflet 0:6ad60d78b315 813 //*****************************************************************************
dflet 0:6ad60d78b315 814 //
dflet 0:6ad60d78b315 815 //! WriteWlanPin
dflet 0:6ad60d78b315 816 //!
dflet 0:6ad60d78b315 817 //! @param val value to write to wlan pin
dflet 0:6ad60d78b315 818 //!
dflet 0:6ad60d78b315 819 //! @return none
dflet 0:6ad60d78b315 820 //!
dflet 0:6ad60d78b315 821 //! @brief write value to wlan pin
dflet 0:6ad60d78b315 822 //
dflet 0:6ad60d78b315 823 //*****************************************************************************
dflet 0:6ad60d78b315 824
dflet 0:6ad60d78b315 825 void WriteWlanPin(unsigned char val)
dflet 0:6ad60d78b315 826 {
dflet 0:6ad60d78b315 827
dflet 0:6ad60d78b315 828 if (val) {
dflet 0:6ad60d78b315 829 Dio.WLAN_EN = 1;
dflet 0:6ad60d78b315 830 //printf("WLAN_EN %i \r\n",val);
dflet 0:6ad60d78b315 831 }
dflet 0:6ad60d78b315 832 else {
dflet 0:6ad60d78b315 833 Dio.WLAN_EN = 0;
dflet 0:6ad60d78b315 834 //printf("WLAN_EN %i \r\n",val);
dflet 0:6ad60d78b315 835 }
dflet 0:6ad60d78b315 836
dflet 0:6ad60d78b315 837 }
dflet 0:6ad60d78b315 838
dflet 0:6ad60d78b315 839 //*****************************************************************************
dflet 0:6ad60d78b315 840 //
dflet 0:6ad60d78b315 841 // Close the Doxygen group.
dflet 0:6ad60d78b315 842 //! @}
dflet 0:6ad60d78b315 843 //
dflet 0:6ad60d78b315 844 //*****************************************************************************
dflet 0:6ad60d78b315 845