Dewant Katare
lab practicals
Diff: arch/TARGET_Freescale/hardware_init_MK64F12.c
- Revision:
- 20:620d381e7f4c
- Parent:
- 18:b15a12222890
- Child:
- 26:32c3ccc5a8ef
diff -r 007f4e6b2776 -r 620d381e7f4c arch/TARGET_Freescale/hardware_init_MK64F12.c
--- a/arch/TARGET_Freescale/hardware_init_MK64F12.c Fri Sep 19 13:45:16 2014 +0100
+++ b/arch/TARGET_Freescale/hardware_init_MK64F12.c Mon Sep 22 17:30:30 2014 +0100
@@ -50,33 +50,33 @@
}
/* Configure gpio*/
- PORT_HAL_SetMuxMode(HW_PORTA, 12, kPortMuxAlt4); /*!< ENET RMII0_RXD1/MII0_RXD1*/
- PORT_HAL_SetMuxMode(HW_PORTA, 13, kPortMuxAlt4); /*!< ENET RMII0_RXD0/MII0_RXD0*/
- PORT_HAL_SetMuxMode(HW_PORTA, 14, kPortMuxAlt4); /*!< ENET RMII0_CRS_DV/MII0_RXDV*/
- PORT_HAL_SetMuxMode(HW_PORTA, 15, kPortMuxAlt4); /*!< ENET RMII0_TXEN/MII0_TXEN*/
- PORT_HAL_SetMuxMode(HW_PORTA, 16, kPortMuxAlt4); /*!< ENET RMII0_TXD0/MII0_TXD0*/
- PORT_HAL_SetMuxMode(HW_PORTA, 17, kPortMuxAlt4); /*!< ENET RMII0_TXD01/MII0_TXD1*/
- PORT_HAL_SetMuxMode(HW_PORTB, 0, kPortMuxAlt4); /*!< ENET RMII0_MDIO/MII0_MDIO*/
- PORT_HAL_SetOpenDrainCmd(HW_PORTB,0, true); /*!< ENET RMII0_MDC/MII0_MDC*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 12, kPortMuxAlt4); /*!< ENET RMII0_RXD1/MII0_RXD1*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 13, kPortMuxAlt4); /*!< ENET RMII0_RXD0/MII0_RXD0*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 14, kPortMuxAlt4); /*!< ENET RMII0_CRS_DV/MII0_RXDV*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 15, kPortMuxAlt4); /*!< ENET RMII0_TXEN/MII0_TXEN*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 16, kPortMuxAlt4); /*!< ENET RMII0_TXD0/MII0_TXD0*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 17, kPortMuxAlt4); /*!< ENET RMII0_TXD01/MII0_TXD1*/
+ PORT_HAL_SetMuxMode(PORTB_BASE, 0, kPortMuxAlt4); /*!< ENET RMII0_MDIO/MII0_MDIO*/
+ PORT_HAL_SetOpenDrainCmd(PORTB_BASE,0, true); /*!< ENET RMII0_MDC/MII0_MDC*/
// Added for FRDM-K64F
- PORT_HAL_SetPullMode(HW_PORTB, 0, kPortPullUp);
- PORT_HAL_SetPullCmd(HW_PORTB, 0, true);
+ PORT_HAL_SetPullMode(PORTB_BASE, 0, kPortPullUp);
+ PORT_HAL_SetPullCmd(PORTB_BASE, 0, true);
- PORT_HAL_SetMuxMode(HW_PORTB, 1, kPortMuxAlt4);
+ PORT_HAL_SetMuxMode(PORTB_BASE, 1, kPortMuxAlt4);
/* Configure GPIO for MII interface */
- PORT_HAL_SetMuxMode(HW_PORTA, 9, kPortMuxAlt4); /*!< ENET MII0_RXD3*/
- PORT_HAL_SetMuxMode(HW_PORTA, 10, kPortMuxAlt4); /*!< ENET MII0_RXD2*/
- PORT_HAL_SetMuxMode(HW_PORTA, 11, kPortMuxAlt4); /*!< ENET MII0_RXCLK*/
- PORT_HAL_SetMuxMode(HW_PORTA, 24, kPortMuxAlt4); /*!< ENET MII0_TXD2*/
- PORT_HAL_SetMuxMode(HW_PORTA, 25, kPortMuxAlt4); /*!< ENET MII0_TXCLK*/
- PORT_HAL_SetMuxMode(HW_PORTA, 26, kPortMuxAlt4); /*!< ENET MII0_TXD3*/
- PORT_HAL_SetMuxMode(HW_PORTA, 27, kPortMuxAlt4); /*!< ENET MII0_CRS*/
- PORT_HAL_SetMuxMode(HW_PORTA, 28, kPortMuxAlt4); /*!< ENET MII0_TXER*/
- PORT_HAL_SetMuxMode(HW_PORTA, 29, kPortMuxAlt4); /*!< ENET MII0_COL*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 9, kPortMuxAlt4); /*!< ENET MII0_RXD3*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 10, kPortMuxAlt4); /*!< ENET MII0_RXD2*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 11, kPortMuxAlt4); /*!< ENET MII0_RXCLK*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 24, kPortMuxAlt4); /*!< ENET MII0_TXD2*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 25, kPortMuxAlt4); /*!< ENET MII0_TXCLK*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 26, kPortMuxAlt4); /*!< ENET MII0_TXD3*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 27, kPortMuxAlt4); /*!< ENET MII0_CRS*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 28, kPortMuxAlt4); /*!< ENET MII0_TXER*/
+ PORT_HAL_SetMuxMode(PORTA_BASE, 29, kPortMuxAlt4); /*!< ENET MII0_COL*/
#if FSL_FEATURE_ENET_SUPPORT_PTP
- PORT_HAL_SetMuxMode(HW_PORTC, (16 + ENET_TIMER_CHANNEL_NUM), kPortMuxAlt4); /* ENET ENET0_1588_TMR0*/
- PORT_HAL_SetDriveStrengthMode(HW_PORTC, (16 + ENET_TIMER_CHANNEL_NUM), kPortHighDriveStrength);
+ PORT_HAL_SetMuxMode(PORTC_BASE, (16 + ENET_TIMER_CHANNEL_NUM), kPortMuxAlt4); /* ENET ENET0_1588_TMR0*/
+ PORT_HAL_SetDriveStrengthMode(PORTC_BASE, (16 + ENET_TIMER_CHANNEL_NUM), kPortHighDriveStrength);
#endif
/* Open ENET clock gate*/