Dewant Katare / lwip-eth_lab4

lab practicals

arch/lpc17xx_emac.h@1:0c9d93e2f51c, 2012-06-22 (annotated)

Committer:
emilmont
Date:
Fri Jun 22 11:17:21 2012 +0000
Revision:
1:0c9d93e2f51c
Child:
5:698d868a5285
Adapt NXP lwip Ethernet driver to CMSIS-RTOS and LPC1768

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:0c9d93e2f51c 1 /**********************************************************************
emilmont 1:0c9d93e2f51c 2 * $Id$ lpc17xx_emac.h 2010-05-21
emilmont 1:0c9d93e2f51c 3 *//**
emilmont 1:0c9d93e2f51c 4 * @file lpc17xx_emac.h
emilmont 1:0c9d93e2f51c 5 * @brief Contains all macro definitions and function prototypes
emilmont 1:0c9d93e2f51c 6 * support for Ethernet MAC firmware library on LPC17xx
emilmont 1:0c9d93e2f51c 7 * @version 2.0
emilmont 1:0c9d93e2f51c 8 * @date 21. May. 2010
emilmont 1:0c9d93e2f51c 9 * @author NXP MCU SW Application Team
emilmont 1:0c9d93e2f51c 10 *
emilmont 1:0c9d93e2f51c 11 * Copyright(C) 2010, NXP Semiconductor
emilmont 1:0c9d93e2f51c 12 * All rights reserved.
emilmont 1:0c9d93e2f51c 13 *
emilmont 1:0c9d93e2f51c 14 ***********************************************************************
emilmont 1:0c9d93e2f51c 15 * Software that is described herein is for illustrative purposes only
emilmont 1:0c9d93e2f51c 16 * which provides customers with programming information regarding the
emilmont 1:0c9d93e2f51c 17 * products. This software is supplied "AS IS" without any warranties.
emilmont 1:0c9d93e2f51c 18 * NXP Semiconductors assumes no responsibility or liability for the
emilmont 1:0c9d93e2f51c 19 * use of the software, conveys no license or title under any patent,
emilmont 1:0c9d93e2f51c 20 * copyright, or mask work right to the product. NXP Semiconductors
emilmont 1:0c9d93e2f51c 21 * reserves the right to make changes in the software without
emilmont 1:0c9d93e2f51c 22 * notification. NXP Semiconductors also make no representation or
emilmont 1:0c9d93e2f51c 23 * warranty that such application will be suitable for the specified
emilmont 1:0c9d93e2f51c 24 * use without further testing or modification.
emilmont 1:0c9d93e2f51c 25 **********************************************************************/
emilmont 1:0c9d93e2f51c 26
emilmont 1:0c9d93e2f51c 27 /* Peripheral group ----------------------------------------------------------- */
emilmont 1:0c9d93e2f51c 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
emilmont 1:0c9d93e2f51c 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
emilmont 1:0c9d93e2f51c 30 * @{
emilmont 1:0c9d93e2f51c 31 */
emilmont 1:0c9d93e2f51c 32
emilmont 1:0c9d93e2f51c 33 #ifndef LPC17XX_EMAC_H_
emilmont 1:0c9d93e2f51c 34 #define LPC17XX_EMAC_H_
emilmont 1:0c9d93e2f51c 35
emilmont 1:0c9d93e2f51c 36 /* Includes ------------------------------------------------------------------- */
emilmont 1:0c9d93e2f51c 37 #include "LPC17xx.h"
emilmont 1:0c9d93e2f51c 38
emilmont 1:0c9d93e2f51c 39 #ifdef __cplusplus
emilmont 1:0c9d93e2f51c 40 extern "C"
emilmont 1:0c9d93e2f51c 41 {
emilmont 1:0c9d93e2f51c 42 #endif
emilmont 1:0c9d93e2f51c 43
emilmont 1:0c9d93e2f51c 44 #define MCB_LPC_1768
emilmont 1:0c9d93e2f51c 45 //#define IAR_LPC_1768
emilmont 1:0c9d93e2f51c 46
emilmont 1:0c9d93e2f51c 47 /* Public Macros -------------------------------------------------------------- */
emilmont 1:0c9d93e2f51c 48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
emilmont 1:0c9d93e2f51c 49 * @{
emilmont 1:0c9d93e2f51c 50 */
emilmont 1:0c9d93e2f51c 51
emilmont 1:0c9d93e2f51c 52
emilmont 1:0c9d93e2f51c 53 /* EMAC PHY status type definitions */
emilmont 1:0c9d93e2f51c 54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
emilmont 1:0c9d93e2f51c 55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
emilmont 1:0c9d93e2f51c 56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
emilmont 1:0c9d93e2f51c 57
emilmont 1:0c9d93e2f51c 58 /* EMAC PHY device Speed definitions */
emilmont 1:0c9d93e2f51c 59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
emilmont 1:0c9d93e2f51c 60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
emilmont 1:0c9d93e2f51c 61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
emilmont 1:0c9d93e2f51c 62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
emilmont 1:0c9d93e2f51c 63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
emilmont 1:0c9d93e2f51c 64
emilmont 1:0c9d93e2f51c 65 /**
emilmont 1:0c9d93e2f51c 66 * @}
emilmont 1:0c9d93e2f51c 67 */
emilmont 1:0c9d93e2f51c 68 /* Private Macros ------------------------------------------------------------- */
emilmont 1:0c9d93e2f51c 69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
emilmont 1:0c9d93e2f51c 70 * @{
emilmont 1:0c9d93e2f51c 71 */
emilmont 1:0c9d93e2f51c 72
emilmont 1:0c9d93e2f51c 73
emilmont 1:0c9d93e2f51c 74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
emilmont 1:0c9d93e2f51c 75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
emilmont 1:0c9d93e2f51c 76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
emilmont 1:0c9d93e2f51c 77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
emilmont 1:0c9d93e2f51c 78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
emilmont 1:0c9d93e2f51c 79
emilmont 1:0c9d93e2f51c 80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
emilmont 1:0c9d93e2f51c 81 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 82 * Macro defines for MAC Configuration Register 1
emilmont 1:0c9d93e2f51c 83 **********************************************************************/
emilmont 1:0c9d93e2f51c 84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
emilmont 1:0c9d93e2f51c 85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
emilmont 1:0c9d93e2f51c 86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
emilmont 1:0c9d93e2f51c 87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
emilmont 1:0c9d93e2f51c 88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
emilmont 1:0c9d93e2f51c 89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
emilmont 1:0c9d93e2f51c 90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
emilmont 1:0c9d93e2f51c 91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
emilmont 1:0c9d93e2f51c 92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
emilmont 1:0c9d93e2f51c 93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
emilmont 1:0c9d93e2f51c 94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
emilmont 1:0c9d93e2f51c 95
emilmont 1:0c9d93e2f51c 96 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 97 * Macro defines for MAC Configuration Register 2
emilmont 1:0c9d93e2f51c 98 **********************************************************************/
emilmont 1:0c9d93e2f51c 99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
emilmont 1:0c9d93e2f51c 100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
emilmont 1:0c9d93e2f51c 101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
emilmont 1:0c9d93e2f51c 102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
emilmont 1:0c9d93e2f51c 103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
emilmont 1:0c9d93e2f51c 104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
emilmont 1:0c9d93e2f51c 105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
emilmont 1:0c9d93e2f51c 106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
emilmont 1:0c9d93e2f51c 107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
emilmont 1:0c9d93e2f51c 108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
emilmont 1:0c9d93e2f51c 109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
emilmont 1:0c9d93e2f51c 110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
emilmont 1:0c9d93e2f51c 111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
emilmont 1:0c9d93e2f51c 112
emilmont 1:0c9d93e2f51c 113 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
emilmont 1:0c9d93e2f51c 115 **********************************************************************/
emilmont 1:0c9d93e2f51c 116 /** Programmable field representing the nibble time offset of the minimum possible period
emilmont 1:0c9d93e2f51c 117 * between the end of any transmitted packet to the beginning of the next */
emilmont 1:0c9d93e2f51c 118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
emilmont 1:0c9d93e2f51c 119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
emilmont 1:0c9d93e2f51c 120 * offset of the minimum possible period between the end of any transmitted packet to the
emilmont 1:0c9d93e2f51c 121 * beginning of the next */
emilmont 1:0c9d93e2f51c 122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
emilmont 1:0c9d93e2f51c 123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
emilmont 1:0c9d93e2f51c 124 * offset of the minimum possible period between the end of any transmitted packet to the
emilmont 1:0c9d93e2f51c 125 * beginning of the next */
emilmont 1:0c9d93e2f51c 126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
emilmont 1:0c9d93e2f51c 127
emilmont 1:0c9d93e2f51c 128 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
emilmont 1:0c9d93e2f51c 130 **********************************************************************/
emilmont 1:0c9d93e2f51c 131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
emilmont 1:0c9d93e2f51c 132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
emilmont 1:0c9d93e2f51c 133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
emilmont 1:0c9d93e2f51c 134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
emilmont 1:0c9d93e2f51c 135 /** Programmable field representing the optional carrierSense window referenced in
emilmont 1:0c9d93e2f51c 136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
emilmont 1:0c9d93e2f51c 137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
emilmont 1:0c9d93e2f51c 138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
emilmont 1:0c9d93e2f51c 139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
emilmont 1:0c9d93e2f51c 140
emilmont 1:0c9d93e2f51c 141 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 142 * Macro defines for Collision Window/Retry Register
emilmont 1:0c9d93e2f51c 143 **********************************************************************/
emilmont 1:0c9d93e2f51c 144 /** Programmable field specifying the number of retransmission attempts following a collision before
emilmont 1:0c9d93e2f51c 145 * aborting the packet due to excessive collisions */
emilmont 1:0c9d93e2f51c 146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
emilmont 1:0c9d93e2f51c 147 /** Programmable field representing the slot time or collision window during which collisions occur
emilmont 1:0c9d93e2f51c 148 * in properly configured networks */
emilmont 1:0c9d93e2f51c 149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
emilmont 1:0c9d93e2f51c 150 /** Default value for Collision Window / Retry register */
emilmont 1:0c9d93e2f51c 151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
emilmont 1:0c9d93e2f51c 152
emilmont 1:0c9d93e2f51c 153 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 154 * Macro defines for Maximum Frame Register
emilmont 1:0c9d93e2f51c 155 **********************************************************************/
emilmont 1:0c9d93e2f51c 156 /** Represents a maximum receive frame of 1536 octets */
emilmont 1:0c9d93e2f51c 157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
emilmont 1:0c9d93e2f51c 158
emilmont 1:0c9d93e2f51c 159 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 160 * Macro defines for PHY Support Register
emilmont 1:0c9d93e2f51c 161 **********************************************************************/
emilmont 1:0c9d93e2f51c 162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
emilmont 1:0c9d93e2f51c 163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
emilmont 1:0c9d93e2f51c 164
emilmont 1:0c9d93e2f51c 165 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 166 * Macro defines for Test Register
emilmont 1:0c9d93e2f51c 167 **********************************************************************/
emilmont 1:0c9d93e2f51c 168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
emilmont 1:0c9d93e2f51c 169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
emilmont 1:0c9d93e2f51c 170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
emilmont 1:0c9d93e2f51c 171
emilmont 1:0c9d93e2f51c 172 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 173 * Macro defines for MII Management Configuration Register
emilmont 1:0c9d93e2f51c 174 **********************************************************************/
emilmont 1:0c9d93e2f51c 175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
emilmont 1:0c9d93e2f51c 176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
emilmont 1:0c9d93e2f51c 177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
emilmont 1:0c9d93e2f51c 178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
emilmont 1:0c9d93e2f51c 179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
emilmont 1:0c9d93e2f51c 180
emilmont 1:0c9d93e2f51c 181 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 182 * Macro defines for MII Management Command Register
emilmont 1:0c9d93e2f51c 183 **********************************************************************/
emilmont 1:0c9d93e2f51c 184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
emilmont 1:0c9d93e2f51c 185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
emilmont 1:0c9d93e2f51c 186
emilmont 1:0c9d93e2f51c 187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
emilmont 1:0c9d93e2f51c 188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
emilmont 1:0c9d93e2f51c 189
emilmont 1:0c9d93e2f51c 190 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 191 * Macro defines for MII Management Address Register
emilmont 1:0c9d93e2f51c 192 **********************************************************************/
emilmont 1:0c9d93e2f51c 193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
emilmont 1:0c9d93e2f51c 194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
emilmont 1:0c9d93e2f51c 195
emilmont 1:0c9d93e2f51c 196 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 197 * Macro defines for MII Management Write Data Register
emilmont 1:0c9d93e2f51c 198 **********************************************************************/
emilmont 1:0c9d93e2f51c 199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
emilmont 1:0c9d93e2f51c 200
emilmont 1:0c9d93e2f51c 201 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 202 * Macro defines for MII Management Read Data Register
emilmont 1:0c9d93e2f51c 203 **********************************************************************/
emilmont 1:0c9d93e2f51c 204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
emilmont 1:0c9d93e2f51c 205
emilmont 1:0c9d93e2f51c 206 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 207 * Macro defines for MII Management Indicators Register
emilmont 1:0c9d93e2f51c 208 **********************************************************************/
emilmont 1:0c9d93e2f51c 209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
emilmont 1:0c9d93e2f51c 210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
emilmont 1:0c9d93e2f51c 211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
emilmont 1:0c9d93e2f51c 212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
emilmont 1:0c9d93e2f51c 213
emilmont 1:0c9d93e2f51c 214 /* Station Address 0 Register */
emilmont 1:0c9d93e2f51c 215 /* Station Address 1 Register */
emilmont 1:0c9d93e2f51c 216 /* Station Address 2 Register */
emilmont 1:0c9d93e2f51c 217
emilmont 1:0c9d93e2f51c 218
emilmont 1:0c9d93e2f51c 219 /* Control register definitions --------------------------------------------------------------------------- */
emilmont 1:0c9d93e2f51c 220 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 221 * Macro defines for Command Register
emilmont 1:0c9d93e2f51c 222 **********************************************************************/
emilmont 1:0c9d93e2f51c 223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
emilmont 1:0c9d93e2f51c 224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
emilmont 1:0c9d93e2f51c 225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
emilmont 1:0c9d93e2f51c 226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
emilmont 1:0c9d93e2f51c 227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
emilmont 1:0c9d93e2f51c 228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
emilmont 1:0c9d93e2f51c 229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
emilmont 1:0c9d93e2f51c 230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
emilmont 1:0c9d93e2f51c 231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
emilmont 1:0c9d93e2f51c 232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
emilmont 1:0c9d93e2f51c 233
emilmont 1:0c9d93e2f51c 234 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 235 * Macro defines for Status Register
emilmont 1:0c9d93e2f51c 236 **********************************************************************/
emilmont 1:0c9d93e2f51c 237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
emilmont 1:0c9d93e2f51c 238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
emilmont 1:0c9d93e2f51c 239
emilmont 1:0c9d93e2f51c 240 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 241 * Macro defines for Transmit Status Vector 0 Register
emilmont 1:0c9d93e2f51c 242 **********************************************************************/
emilmont 1:0c9d93e2f51c 243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
emilmont 1:0c9d93e2f51c 244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
emilmont 1:0c9d93e2f51c 245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
emilmont 1:0c9d93e2f51c 246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
emilmont 1:0c9d93e2f51c 247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
emilmont 1:0c9d93e2f51c 248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
emilmont 1:0c9d93e2f51c 249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
emilmont 1:0c9d93e2f51c 250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
emilmont 1:0c9d93e2f51c 251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
emilmont 1:0c9d93e2f51c 252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
emilmont 1:0c9d93e2f51c 253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
emilmont 1:0c9d93e2f51c 254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
emilmont 1:0c9d93e2f51c 255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
emilmont 1:0c9d93e2f51c 256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
emilmont 1:0c9d93e2f51c 257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
emilmont 1:0c9d93e2f51c 258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
emilmont 1:0c9d93e2f51c 259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
emilmont 1:0c9d93e2f51c 260
emilmont 1:0c9d93e2f51c 261 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 262 * Macro defines for Transmit Status Vector 1 Register
emilmont 1:0c9d93e2f51c 263 **********************************************************************/
emilmont 1:0c9d93e2f51c 264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
emilmont 1:0c9d93e2f51c 265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
emilmont 1:0c9d93e2f51c 266
emilmont 1:0c9d93e2f51c 267 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 268 * Macro defines for Receive Status Vector Register
emilmont 1:0c9d93e2f51c 269 **********************************************************************/
emilmont 1:0c9d93e2f51c 270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
emilmont 1:0c9d93e2f51c 271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
emilmont 1:0c9d93e2f51c 272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
emilmont 1:0c9d93e2f51c 273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
emilmont 1:0c9d93e2f51c 274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
emilmont 1:0c9d93e2f51c 275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
emilmont 1:0c9d93e2f51c 276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
emilmont 1:0c9d93e2f51c 277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
emilmont 1:0c9d93e2f51c 278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
emilmont 1:0c9d93e2f51c 279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
emilmont 1:0c9d93e2f51c 280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
emilmont 1:0c9d93e2f51c 281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
emilmont 1:0c9d93e2f51c 282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
emilmont 1:0c9d93e2f51c 283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
emilmont 1:0c9d93e2f51c 284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
emilmont 1:0c9d93e2f51c 285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
emilmont 1:0c9d93e2f51c 286
emilmont 1:0c9d93e2f51c 287 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 288 * Macro defines for Flow Control Counter Register
emilmont 1:0c9d93e2f51c 289 **********************************************************************/
emilmont 1:0c9d93e2f51c 290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
emilmont 1:0c9d93e2f51c 291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
emilmont 1:0c9d93e2f51c 292
emilmont 1:0c9d93e2f51c 293 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 294 * Macro defines for Flow Control Status Register
emilmont 1:0c9d93e2f51c 295 **********************************************************************/
emilmont 1:0c9d93e2f51c 296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
emilmont 1:0c9d93e2f51c 297
emilmont 1:0c9d93e2f51c 298
emilmont 1:0c9d93e2f51c 299 /* Receive filter register definitions -------------------------------------------------------- */
emilmont 1:0c9d93e2f51c 300 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 301 * Macro defines for Receive Filter Control Register
emilmont 1:0c9d93e2f51c 302 **********************************************************************/
emilmont 1:0c9d93e2f51c 303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
emilmont 1:0c9d93e2f51c 304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
emilmont 1:0c9d93e2f51c 305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
emilmont 1:0c9d93e2f51c 306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
emilmont 1:0c9d93e2f51c 307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
emilmont 1:0c9d93e2f51c 308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
emilmont 1:0c9d93e2f51c 309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
emilmont 1:0c9d93e2f51c 310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
emilmont 1:0c9d93e2f51c 311
emilmont 1:0c9d93e2f51c 312 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 313 * Macro defines for Receive Filter WoL Status/Clear Registers
emilmont 1:0c9d93e2f51c 314 **********************************************************************/
emilmont 1:0c9d93e2f51c 315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
emilmont 1:0c9d93e2f51c 316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
emilmont 1:0c9d93e2f51c 317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
emilmont 1:0c9d93e2f51c 318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
emilmont 1:0c9d93e2f51c 319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
emilmont 1:0c9d93e2f51c 320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
emilmont 1:0c9d93e2f51c 321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
emilmont 1:0c9d93e2f51c 322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
emilmont 1:0c9d93e2f51c 323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
emilmont 1:0c9d93e2f51c 324
emilmont 1:0c9d93e2f51c 325
emilmont 1:0c9d93e2f51c 326 /* Module control register definitions ---------------------------------------------------- */
emilmont 1:0c9d93e2f51c 327 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
emilmont 1:0c9d93e2f51c 329 **********************************************************************/
emilmont 1:0c9d93e2f51c 330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
emilmont 1:0c9d93e2f51c 331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
emilmont 1:0c9d93e2f51c 332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
emilmont 1:0c9d93e2f51c 333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
emilmont 1:0c9d93e2f51c 334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
emilmont 1:0c9d93e2f51c 335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
emilmont 1:0c9d93e2f51c 336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
emilmont 1:0c9d93e2f51c 337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
emilmont 1:0c9d93e2f51c 338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
emilmont 1:0c9d93e2f51c 339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
emilmont 1:0c9d93e2f51c 340
emilmont 1:0c9d93e2f51c 341 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 342 * Macro defines for Power Down Register
emilmont 1:0c9d93e2f51c 343 **********************************************************************/
emilmont 1:0c9d93e2f51c 344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
emilmont 1:0c9d93e2f51c 345
emilmont 1:0c9d93e2f51c 346 /* Descriptor and status formats ---------------------------------------------------- */
emilmont 1:0c9d93e2f51c 347 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 348 * Macro defines for RX Descriptor Control Word
emilmont 1:0c9d93e2f51c 349 **********************************************************************/
emilmont 1:0c9d93e2f51c 350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
emilmont 1:0c9d93e2f51c 351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
emilmont 1:0c9d93e2f51c 352
emilmont 1:0c9d93e2f51c 353 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 354 * Macro defines for RX Status Hash CRC Word
emilmont 1:0c9d93e2f51c 355 **********************************************************************/
emilmont 1:0c9d93e2f51c 356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
emilmont 1:0c9d93e2f51c 357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
emilmont 1:0c9d93e2f51c 358
emilmont 1:0c9d93e2f51c 359 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 360 * Macro defines for RX Status Information Word
emilmont 1:0c9d93e2f51c 361 **********************************************************************/
emilmont 1:0c9d93e2f51c 362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
emilmont 1:0c9d93e2f51c 363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
emilmont 1:0c9d93e2f51c 364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
emilmont 1:0c9d93e2f51c 365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
emilmont 1:0c9d93e2f51c 366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
emilmont 1:0c9d93e2f51c 367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
emilmont 1:0c9d93e2f51c 368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
emilmont 1:0c9d93e2f51c 369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
emilmont 1:0c9d93e2f51c 370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
emilmont 1:0c9d93e2f51c 371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
emilmont 1:0c9d93e2f51c 372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
emilmont 1:0c9d93e2f51c 373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
emilmont 1:0c9d93e2f51c 374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
emilmont 1:0c9d93e2f51c 375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
emilmont 1:0c9d93e2f51c 376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
emilmont 1:0c9d93e2f51c 377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
emilmont 1:0c9d93e2f51c 378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
emilmont 1:0c9d93e2f51c 379
emilmont 1:0c9d93e2f51c 380 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 381 * Macro defines for TX Descriptor Control Word
emilmont 1:0c9d93e2f51c 382 **********************************************************************/
emilmont 1:0c9d93e2f51c 383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
emilmont 1:0c9d93e2f51c 384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
emilmont 1:0c9d93e2f51c 385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
emilmont 1:0c9d93e2f51c 386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
emilmont 1:0c9d93e2f51c 387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
emilmont 1:0c9d93e2f51c 388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
emilmont 1:0c9d93e2f51c 389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
emilmont 1:0c9d93e2f51c 390
emilmont 1:0c9d93e2f51c 391 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 392 * Macro defines for TX Status Information Word
emilmont 1:0c9d93e2f51c 393 **********************************************************************/
emilmont 1:0c9d93e2f51c 394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
emilmont 1:0c9d93e2f51c 395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
emilmont 1:0c9d93e2f51c 396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
emilmont 1:0c9d93e2f51c 397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
emilmont 1:0c9d93e2f51c 398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
emilmont 1:0c9d93e2f51c 399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
emilmont 1:0c9d93e2f51c 400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
emilmont 1:0c9d93e2f51c 401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
emilmont 1:0c9d93e2f51c 402
emilmont 1:0c9d93e2f51c 403 #ifdef MCB_LPC_1768
emilmont 1:0c9d93e2f51c 404 /* DP83848C PHY definition ------------------------------------------------------------ */
emilmont 1:0c9d93e2f51c 405
emilmont 1:0c9d93e2f51c 406 /** PHY device reset time out definition */
emilmont 1:0c9d93e2f51c 407 #define EMAC_PHY_RESP_TOUT 0x100000UL
emilmont 1:0c9d93e2f51c 408
emilmont 1:0c9d93e2f51c 409 /* ENET Device Revision ID */
emilmont 1:0c9d93e2f51c 410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
emilmont 1:0c9d93e2f51c 411
emilmont 1:0c9d93e2f51c 412 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 413 * Macro defines for DP83848C PHY Registers
emilmont 1:0c9d93e2f51c 414 **********************************************************************/
emilmont 1:0c9d93e2f51c 415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
emilmont 1:0c9d93e2f51c 416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
emilmont 1:0c9d93e2f51c 417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
emilmont 1:0c9d93e2f51c 418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
emilmont 1:0c9d93e2f51c 419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
emilmont 1:0c9d93e2f51c 420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
emilmont 1:0c9d93e2f51c 421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
emilmont 1:0c9d93e2f51c 422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
emilmont 1:0c9d93e2f51c 423 #define EMAC_PHY_REG_LPNPA 0x08
emilmont 1:0c9d93e2f51c 424
emilmont 1:0c9d93e2f51c 425 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 426 * Macro defines for PHY Extended Registers
emilmont 1:0c9d93e2f51c 427 **********************************************************************/
emilmont 1:0c9d93e2f51c 428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
emilmont 1:0c9d93e2f51c 429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
emilmont 1:0c9d93e2f51c 430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
emilmont 1:0c9d93e2f51c 431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
emilmont 1:0c9d93e2f51c 432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
emilmont 1:0c9d93e2f51c 433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
emilmont 1:0c9d93e2f51c 434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
emilmont 1:0c9d93e2f51c 435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
emilmont 1:0c9d93e2f51c 436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
emilmont 1:0c9d93e2f51c 437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
emilmont 1:0c9d93e2f51c 438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
emilmont 1:0c9d93e2f51c 439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
emilmont 1:0c9d93e2f51c 440
emilmont 1:0c9d93e2f51c 441 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 442 * Macro defines for PHY Basic Mode Control Register
emilmont 1:0c9d93e2f51c 443 **********************************************************************/
emilmont 1:0c9d93e2f51c 444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
emilmont 1:0c9d93e2f51c 445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
emilmont 1:0c9d93e2f51c 446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
emilmont 1:0c9d93e2f51c 447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
emilmont 1:0c9d93e2f51c 448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
emilmont 1:0c9d93e2f51c 449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
emilmont 1:0c9d93e2f51c 450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
emilmont 1:0c9d93e2f51c 451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
emilmont 1:0c9d93e2f51c 452
emilmont 1:0c9d93e2f51c 453 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 454 * Macro defines for PHY Basic Mode Status Status Register
emilmont 1:0c9d93e2f51c 455 **********************************************************************/
emilmont 1:0c9d93e2f51c 456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
emilmont 1:0c9d93e2f51c 457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
emilmont 1:0c9d93e2f51c 458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
emilmont 1:0c9d93e2f51c 459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
emilmont 1:0c9d93e2f51c 460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
emilmont 1:0c9d93e2f51c 461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
emilmont 1:0c9d93e2f51c 462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
emilmont 1:0c9d93e2f51c 463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
emilmont 1:0c9d93e2f51c 464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
emilmont 1:0c9d93e2f51c 465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
emilmont 1:0c9d93e2f51c 466
emilmont 1:0c9d93e2f51c 467 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 468 * Macro defines for PHY Status Register
emilmont 1:0c9d93e2f51c 469 **********************************************************************/
emilmont 1:0c9d93e2f51c 470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
emilmont 1:0c9d93e2f51c 471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
emilmont 1:0c9d93e2f51c 472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
emilmont 1:0c9d93e2f51c 473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
emilmont 1:0c9d93e2f51c 474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
emilmont 1:0c9d93e2f51c 475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
emilmont 1:0c9d93e2f51c 476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
emilmont 1:0c9d93e2f51c 477
emilmont 1:0c9d93e2f51c 478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
emilmont 1:0c9d93e2f51c 479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
emilmont 1:0c9d93e2f51c 480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
emilmont 1:0c9d93e2f51c 481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
emilmont 1:0c9d93e2f51c 482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
emilmont 1:0c9d93e2f51c 483
emilmont 1:0c9d93e2f51c 484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
emilmont 1:0c9d93e2f51c 485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
emilmont 1:0c9d93e2f51c 486
emilmont 1:0c9d93e2f51c 487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
emilmont 1:0c9d93e2f51c 488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
emilmont 1:0c9d93e2f51c 489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
emilmont 1:0c9d93e2f51c 490
emilmont 1:0c9d93e2f51c 491 #elif defined(IAR_LPC_1768)
emilmont 1:0c9d93e2f51c 492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
emilmont 1:0c9d93e2f51c 493 /** PHY device reset time out definition */
emilmont 1:0c9d93e2f51c 494 #define EMAC_PHY_RESP_TOUT 0x100000UL
emilmont 1:0c9d93e2f51c 495
emilmont 1:0c9d93e2f51c 496 /* ENET Device Revision ID */
emilmont 1:0c9d93e2f51c 497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
emilmont 1:0c9d93e2f51c 498
emilmont 1:0c9d93e2f51c 499 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 500 * Macro defines for KSZ8721BL PHY Registers
emilmont 1:0c9d93e2f51c 501 **********************************************************************/
emilmont 1:0c9d93e2f51c 502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
emilmont 1:0c9d93e2f51c 503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
emilmont 1:0c9d93e2f51c 504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
emilmont 1:0c9d93e2f51c 505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
emilmont 1:0c9d93e2f51c 506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
emilmont 1:0c9d93e2f51c 507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
emilmont 1:0c9d93e2f51c 508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
emilmont 1:0c9d93e2f51c 509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
emilmont 1:0c9d93e2f51c 510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
emilmont 1:0c9d93e2f51c 511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
emilmont 1:0c9d93e2f51c 512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
emilmont 1:0c9d93e2f51c 513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
emilmont 1:0c9d93e2f51c 514
emilmont 1:0c9d93e2f51c 515 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 516 * Macro defines for PHY Basic Mode Control Register
emilmont 1:0c9d93e2f51c 517 **********************************************************************/
emilmont 1:0c9d93e2f51c 518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
emilmont 1:0c9d93e2f51c 519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
emilmont 1:0c9d93e2f51c 520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
emilmont 1:0c9d93e2f51c 521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
emilmont 1:0c9d93e2f51c 522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
emilmont 1:0c9d93e2f51c 523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
emilmont 1:0c9d93e2f51c 524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
emilmont 1:0c9d93e2f51c 525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
emilmont 1:0c9d93e2f51c 526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
emilmont 1:0c9d93e2f51c 527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
emilmont 1:0c9d93e2f51c 528
emilmont 1:0c9d93e2f51c 529 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 530 * Macro defines for PHY Basic Mode Status Register
emilmont 1:0c9d93e2f51c 531 **********************************************************************/
emilmont 1:0c9d93e2f51c 532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
emilmont 1:0c9d93e2f51c 533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
emilmont 1:0c9d93e2f51c 534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
emilmont 1:0c9d93e2f51c 535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
emilmont 1:0c9d93e2f51c 536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
emilmont 1:0c9d93e2f51c 537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
emilmont 1:0c9d93e2f51c 538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
emilmont 1:0c9d93e2f51c 539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
emilmont 1:0c9d93e2f51c 540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
emilmont 1:0c9d93e2f51c 541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
emilmont 1:0c9d93e2f51c 542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
emilmont 1:0c9d93e2f51c 543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
emilmont 1:0c9d93e2f51c 544
emilmont 1:0c9d93e2f51c 545 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 546 * Macro defines for PHY Identifier
emilmont 1:0c9d93e2f51c 547 **********************************************************************/
emilmont 1:0c9d93e2f51c 548 /* PHY Identifier 1 bitmap definitions */
emilmont 1:0c9d93e2f51c 549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
emilmont 1:0c9d93e2f51c 550
emilmont 1:0c9d93e2f51c 551 /* PHY Identifier 2 bitmap definitions */
emilmont 1:0c9d93e2f51c 552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
emilmont 1:0c9d93e2f51c 553
emilmont 1:0c9d93e2f51c 554 /*********************************************************************//**
emilmont 1:0c9d93e2f51c 555 * Macro defines for Auto-Negotiation Advertisement
emilmont 1:0c9d93e2f51c 556 **********************************************************************/
emilmont 1:0c9d93e2f51c 557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
emilmont 1:0c9d93e2f51c 558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
emilmont 1:0c9d93e2f51c 559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
emilmont 1:0c9d93e2f51c 560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
emilmont 1:0c9d93e2f51c 561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
emilmont 1:0c9d93e2f51c 562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
emilmont 1:0c9d93e2f51c 563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
emilmont 1:0c9d93e2f51c 564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
emilmont 1:0c9d93e2f51c 565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
emilmont 1:0c9d93e2f51c 566
emilmont 1:0c9d93e2f51c 567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
emilmont 1:0c9d93e2f51c 568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
emilmont 1:0c9d93e2f51c 569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
emilmont 1:0c9d93e2f51c 570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
emilmont 1:0c9d93e2f51c 571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
emilmont 1:0c9d93e2f51c 572
emilmont 1:0c9d93e2f51c 573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
emilmont 1:0c9d93e2f51c 574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
emilmont 1:0c9d93e2f51c 575
emilmont 1:0c9d93e2f51c 576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
emilmont 1:0c9d93e2f51c 577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
emilmont 1:0c9d93e2f51c 578 #endif
emilmont 1:0c9d93e2f51c 579
emilmont 1:0c9d93e2f51c 580 /**
emilmont 1:0c9d93e2f51c 581 * @}
emilmont 1:0c9d93e2f51c 582 */
emilmont 1:0c9d93e2f51c 583
emilmont 1:0c9d93e2f51c 584
emilmont 1:0c9d93e2f51c 585 /* Public Types --------------------------------------------------------------- */
emilmont 1:0c9d93e2f51c 586 /** @defgroup EMAC_Public_Types EMAC Public Types
emilmont 1:0c9d93e2f51c 587 * @{
emilmont 1:0c9d93e2f51c 588 */
emilmont 1:0c9d93e2f51c 589
emilmont 1:0c9d93e2f51c 590 /* Descriptor and status formats ---------------------------------------------- */
emilmont 1:0c9d93e2f51c 591
emilmont 1:0c9d93e2f51c 592 /**
emilmont 1:0c9d93e2f51c 593 * @brief RX Descriptor structure type definition
emilmont 1:0c9d93e2f51c 594 */
emilmont 1:0c9d93e2f51c 595 typedef struct {
emilmont 1:0c9d93e2f51c 596 uint32_t Packet; /**< Receive Packet Descriptor */
emilmont 1:0c9d93e2f51c 597 uint32_t Ctrl; /**< Receive Control Descriptor */
emilmont 1:0c9d93e2f51c 598 } RX_Desc;
emilmont 1:0c9d93e2f51c 599
emilmont 1:0c9d93e2f51c 600 /**
emilmont 1:0c9d93e2f51c 601 * @brief RX Status structure type definition
emilmont 1:0c9d93e2f51c 602 */
emilmont 1:0c9d93e2f51c 603 typedef struct {
emilmont 1:0c9d93e2f51c 604 uint32_t Info; /**< Receive Information Status */
emilmont 1:0c9d93e2f51c 605 uint32_t HashCRC; /**< Receive Hash CRC Status */
emilmont 1:0c9d93e2f51c 606 } RX_Stat;
emilmont 1:0c9d93e2f51c 607
emilmont 1:0c9d93e2f51c 608 /**
emilmont 1:0c9d93e2f51c 609 * @brief TX Descriptor structure type definition
emilmont 1:0c9d93e2f51c 610 */
emilmont 1:0c9d93e2f51c 611 typedef struct {
emilmont 1:0c9d93e2f51c 612 uint32_t Packet; /**< Transmit Packet Descriptor */
emilmont 1:0c9d93e2f51c 613 uint32_t Ctrl; /**< Transmit Control Descriptor */
emilmont 1:0c9d93e2f51c 614 } TX_Desc;
emilmont 1:0c9d93e2f51c 615
emilmont 1:0c9d93e2f51c 616 /**
emilmont 1:0c9d93e2f51c 617 * @brief TX Status structure type definition
emilmont 1:0c9d93e2f51c 618 */
emilmont 1:0c9d93e2f51c 619 typedef struct {
emilmont 1:0c9d93e2f51c 620 uint32_t Info; /**< Transmit Information Status */
emilmont 1:0c9d93e2f51c 621 } TX_Stat;
emilmont 1:0c9d93e2f51c 622
emilmont 1:0c9d93e2f51c 623
emilmont 1:0c9d93e2f51c 624 /**
emilmont 1:0c9d93e2f51c 625 * @brief TX Data Buffer structure definition
emilmont 1:0c9d93e2f51c 626 */
emilmont 1:0c9d93e2f51c 627 typedef struct {
emilmont 1:0c9d93e2f51c 628 uint32_t ulDataLen; /**< Data length */
emilmont 1:0c9d93e2f51c 629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
emilmont 1:0c9d93e2f51c 630 } EMAC_PACKETBUF_Type;
emilmont 1:0c9d93e2f51c 631
emilmont 1:0c9d93e2f51c 632 /**
emilmont 1:0c9d93e2f51c 633 * @brief EMAC configuration structure definition
emilmont 1:0c9d93e2f51c 634 */
emilmont 1:0c9d93e2f51c 635 typedef struct {
emilmont 1:0c9d93e2f51c 636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
emilmont 1:0c9d93e2f51c 637 - EMAC_MODE_AUTO
emilmont 1:0c9d93e2f51c 638 - EMAC_MODE_10M_FULL
emilmont 1:0c9d93e2f51c 639 - EMAC_MODE_10M_HALF
emilmont 1:0c9d93e2f51c 640 - EMAC_MODE_100M_FULL
emilmont 1:0c9d93e2f51c 641 - EMAC_MODE_100M_HALF
emilmont 1:0c9d93e2f51c 642 */
emilmont 1:0c9d93e2f51c 643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
emilmont 1:0c9d93e2f51c 644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
emilmont 1:0c9d93e2f51c 645 */
emilmont 1:0c9d93e2f51c 646 } EMAC_CFG_Type;
emilmont 1:0c9d93e2f51c 647
emilmont 1:0c9d93e2f51c 648 /** Ethernet block power/clock control bit*/
emilmont 1:0c9d93e2f51c 649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
emilmont 1:0c9d93e2f51c 650
emilmont 1:0c9d93e2f51c 651 #ifdef __cplusplus
emilmont 1:0c9d93e2f51c 652 }
emilmont 1:0c9d93e2f51c 653 #endif
emilmont 1:0c9d93e2f51c 654
emilmont 1:0c9d93e2f51c 655 #endif /* LPC17XX_EMAC_H_ */
emilmont 1:0c9d93e2f51c 656
emilmont 1:0c9d93e2f51c 657 /**
emilmont 1:0c9d93e2f51c 658 * @}
emilmont 1:0c9d93e2f51c 659 */
emilmont 1:0c9d93e2f51c 660
emilmont 1:0c9d93e2f51c 661 /* --------------------------------- End Of File ------------------------------ */