Dependencies: keypad SDHCFileSystem TextLCD mbed FPointer wave_player
scmRTOS/CortexM3/OS_Target.h@0:57ece500234e, 2012-02-20 (annotated)
- Committer:
- daryl2110
- Date:
- Mon Feb 20 07:32:56 2012 +0000
- Revision:
- 0:57ece500234e
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
daryl2110 | 0:57ece500234e | 1 | //****************************************************************************** |
daryl2110 | 0:57ece500234e | 2 | //* |
daryl2110 | 0:57ece500234e | 3 | //* FULLNAME: Single-Chip Microcontroller Real-Time Operating System |
daryl2110 | 0:57ece500234e | 4 | //* |
daryl2110 | 0:57ece500234e | 5 | //* NICKNAME: scmRTOS |
daryl2110 | 0:57ece500234e | 6 | //* |
daryl2110 | 0:57ece500234e | 7 | //* PROCESSOR: ARM Cortex-M3 |
daryl2110 | 0:57ece500234e | 8 | //* |
daryl2110 | 0:57ece500234e | 9 | //* TOOLKIT: RVCT (ARM) |
daryl2110 | 0:57ece500234e | 10 | //* |
daryl2110 | 0:57ece500234e | 11 | //* PURPOSE: Target Dependent Stuff Header. Declarations And Definitions |
daryl2110 | 0:57ece500234e | 12 | //* |
daryl2110 | 0:57ece500234e | 13 | //* Version: 3.10 |
daryl2110 | 0:57ece500234e | 14 | //* |
daryl2110 | 0:57ece500234e | 15 | //* $Revision: 195 $ |
daryl2110 | 0:57ece500234e | 16 | //* $Date:: 2008-06-19 #$ |
daryl2110 | 0:57ece500234e | 17 | //* |
daryl2110 | 0:57ece500234e | 18 | //* Copyright (c) 2003-2010, Harry E. Zhurov |
daryl2110 | 0:57ece500234e | 19 | //* |
daryl2110 | 0:57ece500234e | 20 | //* Permission is hereby granted, free of charge, to any person |
daryl2110 | 0:57ece500234e | 21 | //* obtaining a copy of this software and associated documentation |
daryl2110 | 0:57ece500234e | 22 | //* files (the "Software"), to deal in the Software without restriction, |
daryl2110 | 0:57ece500234e | 23 | //* including without limitation the rights to use, copy, modify, merge, |
daryl2110 | 0:57ece500234e | 24 | //* publish, distribute, sublicense, and/or sell copies of the Software, |
daryl2110 | 0:57ece500234e | 25 | //* and to permit persons to whom the Software is furnished to do so, |
daryl2110 | 0:57ece500234e | 26 | //* subject to the following conditions: |
daryl2110 | 0:57ece500234e | 27 | //* |
daryl2110 | 0:57ece500234e | 28 | //* The above copyright notice and this permission notice shall be included |
daryl2110 | 0:57ece500234e | 29 | //* in all copies or substantial portions of the Software. |
daryl2110 | 0:57ece500234e | 30 | //* |
daryl2110 | 0:57ece500234e | 31 | //* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
daryl2110 | 0:57ece500234e | 32 | //* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
daryl2110 | 0:57ece500234e | 33 | //* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
daryl2110 | 0:57ece500234e | 34 | //* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
daryl2110 | 0:57ece500234e | 35 | //* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
daryl2110 | 0:57ece500234e | 36 | //* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH |
daryl2110 | 0:57ece500234e | 37 | //* THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
daryl2110 | 0:57ece500234e | 38 | //* |
daryl2110 | 0:57ece500234e | 39 | //* ================================================================= |
daryl2110 | 0:57ece500234e | 40 | //* See http://scmrtos.sourceforge.net for documentation, latest |
daryl2110 | 0:57ece500234e | 41 | //* information, license and contact details. |
daryl2110 | 0:57ece500234e | 42 | //* ================================================================= |
daryl2110 | 0:57ece500234e | 43 | //* |
daryl2110 | 0:57ece500234e | 44 | //****************************************************************************** |
daryl2110 | 0:57ece500234e | 45 | //* Ported by Andrey Chuikin, Copyright (c) 2008-2010 |
daryl2110 | 0:57ece500234e | 46 | |
daryl2110 | 0:57ece500234e | 47 | #ifndef scmRTOS_CORTEXM3_H |
daryl2110 | 0:57ece500234e | 48 | #define scmRTOS_CORTEXM3_H |
daryl2110 | 0:57ece500234e | 49 | |
daryl2110 | 0:57ece500234e | 50 | #include <commdefs.h> |
daryl2110 | 0:57ece500234e | 51 | |
daryl2110 | 0:57ece500234e | 52 | //------------------------------------------------------------------------------ |
daryl2110 | 0:57ece500234e | 53 | // |
daryl2110 | 0:57ece500234e | 54 | // Compiler and Target checks |
daryl2110 | 0:57ece500234e | 55 | // |
daryl2110 | 0:57ece500234e | 56 | // |
daryl2110 | 0:57ece500234e | 57 | #ifndef __ARMCC_VERSION |
daryl2110 | 0:57ece500234e | 58 | #error "This file should only be compiled with ARM RVCT Compiler" |
daryl2110 | 0:57ece500234e | 59 | #endif // __ARMCC_VERSION |
daryl2110 | 0:57ece500234e | 60 | |
daryl2110 | 0:57ece500234e | 61 | #if __TARGET_ARCH_ARM != 0 || __TARGET_ARCH_THUMB != 4 |
daryl2110 | 0:57ece500234e | 62 | #error "This file must be compiled for ARMv7-M (Cortex-M3) processor only." |
daryl2110 | 0:57ece500234e | 63 | #endif |
daryl2110 | 0:57ece500234e | 64 | |
daryl2110 | 0:57ece500234e | 65 | //------------------------------------------------------------------------------ |
daryl2110 | 0:57ece500234e | 66 | // |
daryl2110 | 0:57ece500234e | 67 | // Target specific types |
daryl2110 | 0:57ece500234e | 68 | // |
daryl2110 | 0:57ece500234e | 69 | // |
daryl2110 | 0:57ece500234e | 70 | typedef dword TStackItem; |
daryl2110 | 0:57ece500234e | 71 | typedef dword TStatusReg; |
daryl2110 | 0:57ece500234e | 72 | |
daryl2110 | 0:57ece500234e | 73 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 74 | // |
daryl2110 | 0:57ece500234e | 75 | // Configuration macros |
daryl2110 | 0:57ece500234e | 76 | // |
daryl2110 | 0:57ece500234e | 77 | // |
daryl2110 | 0:57ece500234e | 78 | #define OS_PROCESS __attribute__((__noreturn__)) |
daryl2110 | 0:57ece500234e | 79 | #define OS_INTERRUPT |
daryl2110 | 0:57ece500234e | 80 | #define DUMMY_INSTR() __NOP() |
daryl2110 | 0:57ece500234e | 81 | #define INLINE_PROCESS_CTOR INLINE inline |
daryl2110 | 0:57ece500234e | 82 | |
daryl2110 | 0:57ece500234e | 83 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 84 | // |
daryl2110 | 0:57ece500234e | 85 | // Uncomment macro value below for SystemTimer() run in critical section |
daryl2110 | 0:57ece500234e | 86 | // |
daryl2110 | 0:57ece500234e | 87 | // This is useful (and necessary) when target processor has hardware |
daryl2110 | 0:57ece500234e | 88 | // enabled nested interrups. Cortex-M3 have such interrupts. |
daryl2110 | 0:57ece500234e | 89 | // |
daryl2110 | 0:57ece500234e | 90 | #define SYS_TIMER_CRIT_SECT() TCritSect cs |
daryl2110 | 0:57ece500234e | 91 | |
daryl2110 | 0:57ece500234e | 92 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 93 | // Separate return stack not required |
daryl2110 | 0:57ece500234e | 94 | #define SEPARATE_RETURN_STACK 0 |
daryl2110 | 0:57ece500234e | 95 | |
daryl2110 | 0:57ece500234e | 96 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 97 | // Software interrupt stack switching not supported in Cortex-M3 port |
daryl2110 | 0:57ece500234e | 98 | // because processor implements hardware stack switching. |
daryl2110 | 0:57ece500234e | 99 | // So, system timer isr wrapper can't be choosen at project level |
daryl2110 | 0:57ece500234e | 100 | // |
daryl2110 | 0:57ece500234e | 101 | #define scmRTOS_ISRW_TYPE TISRW |
daryl2110 | 0:57ece500234e | 102 | |
daryl2110 | 0:57ece500234e | 103 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 104 | // |
daryl2110 | 0:57ece500234e | 105 | // scmRTOS Context Switch Scheme |
daryl2110 | 0:57ece500234e | 106 | // |
daryl2110 | 0:57ece500234e | 107 | // The macro defines a context switch manner. Value 0 sets direct context |
daryl2110 | 0:57ece500234e | 108 | // switch in the scheduler and in the OS ISRs. This is the primary method. |
daryl2110 | 0:57ece500234e | 109 | // Value 1 sets the second way to switch context - by using of software |
daryl2110 | 0:57ece500234e | 110 | // interrupt. See documentation fo details. |
daryl2110 | 0:57ece500234e | 111 | // Cortex-M3 port supports software interrupt switch method only. |
daryl2110 | 0:57ece500234e | 112 | // |
daryl2110 | 0:57ece500234e | 113 | #define scmRTOS_CONTEXT_SWITCH_SCHEME 1 |
daryl2110 | 0:57ece500234e | 114 | |
daryl2110 | 0:57ece500234e | 115 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 116 | // |
daryl2110 | 0:57ece500234e | 117 | // Include project-level configurations |
daryl2110 | 0:57ece500234e | 118 | // !!! The order of includes is important !!! |
daryl2110 | 0:57ece500234e | 119 | // |
daryl2110 | 0:57ece500234e | 120 | #include "../../scmRTOS_config.h" |
daryl2110 | 0:57ece500234e | 121 | #include "../scmRTOS_TARGET_CFG.h" |
daryl2110 | 0:57ece500234e | 122 | #include <scmRTOS_defs.h> |
daryl2110 | 0:57ece500234e | 123 | #include <LPC17xx.h> |
daryl2110 | 0:57ece500234e | 124 | |
daryl2110 | 0:57ece500234e | 125 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 126 | // |
daryl2110 | 0:57ece500234e | 127 | // The Critital Section Wrapper |
daryl2110 | 0:57ece500234e | 128 | // |
daryl2110 | 0:57ece500234e | 129 | // |
daryl2110 | 0:57ece500234e | 130 | #define __enable_interrupt() __enable_irq() |
daryl2110 | 0:57ece500234e | 131 | #define __disable_interrupt() __disable_irq() |
daryl2110 | 0:57ece500234e | 132 | |
daryl2110 | 0:57ece500234e | 133 | #define __set_interrupt_state(status) __set_PRIMASK(status) |
daryl2110 | 0:57ece500234e | 134 | #define __get_interrupt_state() __get_PRIMASK() |
daryl2110 | 0:57ece500234e | 135 | |
daryl2110 | 0:57ece500234e | 136 | class TCritSect |
daryl2110 | 0:57ece500234e | 137 | { |
daryl2110 | 0:57ece500234e | 138 | public: |
daryl2110 | 0:57ece500234e | 139 | TCritSect () : StatusReg(__get_interrupt_state()) { __disable_interrupt(); } |
daryl2110 | 0:57ece500234e | 140 | ~TCritSect() { __set_interrupt_state(StatusReg); } |
daryl2110 | 0:57ece500234e | 141 | |
daryl2110 | 0:57ece500234e | 142 | private: |
daryl2110 | 0:57ece500234e | 143 | TStatusReg StatusReg; |
daryl2110 | 0:57ece500234e | 144 | }; |
daryl2110 | 0:57ece500234e | 145 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 146 | |
daryl2110 | 0:57ece500234e | 147 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 148 | // |
daryl2110 | 0:57ece500234e | 149 | // Priority stuff |
daryl2110 | 0:57ece500234e | 150 | // |
daryl2110 | 0:57ece500234e | 151 | // |
daryl2110 | 0:57ece500234e | 152 | namespace OS |
daryl2110 | 0:57ece500234e | 153 | { |
daryl2110 | 0:57ece500234e | 154 | INLINE inline OS::TProcessMap GetPrioTag(const byte pr) { return static_cast<OS::TProcessMap> (1 << pr); } |
daryl2110 | 0:57ece500234e | 155 | |
daryl2110 | 0:57ece500234e | 156 | #if scmRTOS_PRIORITY_ORDER == 0 |
daryl2110 | 0:57ece500234e | 157 | INLINE inline byte GetHighPriority(TProcessMap pm) |
daryl2110 | 0:57ece500234e | 158 | { |
daryl2110 | 0:57ece500234e | 159 | byte pr = 0; |
daryl2110 | 0:57ece500234e | 160 | |
daryl2110 | 0:57ece500234e | 161 | while( !(pm & 0x0001) ) |
daryl2110 | 0:57ece500234e | 162 | { |
daryl2110 | 0:57ece500234e | 163 | pr++; |
daryl2110 | 0:57ece500234e | 164 | pm >>= 1; |
daryl2110 | 0:57ece500234e | 165 | } |
daryl2110 | 0:57ece500234e | 166 | return pr; |
daryl2110 | 0:57ece500234e | 167 | } |
daryl2110 | 0:57ece500234e | 168 | #else |
daryl2110 | 0:57ece500234e | 169 | INLINE inline byte GetHighPriority(TProcessMap pm) { return (31 - __clz(pm)); } |
daryl2110 | 0:57ece500234e | 170 | #endif // scmRTOS_PRIORITY_ORDER |
daryl2110 | 0:57ece500234e | 171 | } |
daryl2110 | 0:57ece500234e | 172 | |
daryl2110 | 0:57ece500234e | 173 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 174 | // |
daryl2110 | 0:57ece500234e | 175 | // Interrupt and Interrupt Service Routines support |
daryl2110 | 0:57ece500234e | 176 | // |
daryl2110 | 0:57ece500234e | 177 | INLINE inline TStatusReg GetInterruptState( ) { return __get_interrupt_state(); } |
daryl2110 | 0:57ece500234e | 178 | INLINE inline void SetInterruptState(TStatusReg sr) { __set_interrupt_state(sr); } |
daryl2110 | 0:57ece500234e | 179 | |
daryl2110 | 0:57ece500234e | 180 | INLINE inline void EnableInterrupts() { __enable_interrupt(); } |
daryl2110 | 0:57ece500234e | 181 | INLINE inline void DisableInterrupts() { __disable_interrupt(); } |
daryl2110 | 0:57ece500234e | 182 | |
daryl2110 | 0:57ece500234e | 183 | |
daryl2110 | 0:57ece500234e | 184 | namespace OS |
daryl2110 | 0:57ece500234e | 185 | { |
daryl2110 | 0:57ece500234e | 186 | INLINE inline void EnableContextSwitch() { EnableInterrupts(); } |
daryl2110 | 0:57ece500234e | 187 | INLINE inline void DisableContextSwitch() { DisableInterrupts(); } |
daryl2110 | 0:57ece500234e | 188 | } |
daryl2110 | 0:57ece500234e | 189 | |
daryl2110 | 0:57ece500234e | 190 | #include <OS_Kernel.h> |
daryl2110 | 0:57ece500234e | 191 | |
daryl2110 | 0:57ece500234e | 192 | namespace OS |
daryl2110 | 0:57ece500234e | 193 | { |
daryl2110 | 0:57ece500234e | 194 | //-------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 195 | // |
daryl2110 | 0:57ece500234e | 196 | // NAME : OS ISR support |
daryl2110 | 0:57ece500234e | 197 | // |
daryl2110 | 0:57ece500234e | 198 | // PURPOSE : Implements common actions on interrupt enter and exit |
daryl2110 | 0:57ece500234e | 199 | // under the OS |
daryl2110 | 0:57ece500234e | 200 | // |
daryl2110 | 0:57ece500234e | 201 | // DESCRIPTION: |
daryl2110 | 0:57ece500234e | 202 | // |
daryl2110 | 0:57ece500234e | 203 | // |
daryl2110 | 0:57ece500234e | 204 | class TISRW |
daryl2110 | 0:57ece500234e | 205 | { |
daryl2110 | 0:57ece500234e | 206 | public: |
daryl2110 | 0:57ece500234e | 207 | INLINE TISRW() { ISR_Enter(); } |
daryl2110 | 0:57ece500234e | 208 | INLINE ~TISRW() { ISR_Exit(); } |
daryl2110 | 0:57ece500234e | 209 | |
daryl2110 | 0:57ece500234e | 210 | private: |
daryl2110 | 0:57ece500234e | 211 | //----------------------------------------------------- |
daryl2110 | 0:57ece500234e | 212 | INLINE void ISR_Enter() |
daryl2110 | 0:57ece500234e | 213 | { |
daryl2110 | 0:57ece500234e | 214 | TCritSect cs; |
daryl2110 | 0:57ece500234e | 215 | Kernel.ISR_NestCount++; |
daryl2110 | 0:57ece500234e | 216 | } |
daryl2110 | 0:57ece500234e | 217 | //----------------------------------------------------- |
daryl2110 | 0:57ece500234e | 218 | INLINE void ISR_Exit() |
daryl2110 | 0:57ece500234e | 219 | { |
daryl2110 | 0:57ece500234e | 220 | TCritSect cs; |
daryl2110 | 0:57ece500234e | 221 | if(--Kernel.ISR_NestCount) return; |
daryl2110 | 0:57ece500234e | 222 | Kernel.SchedISR(); |
daryl2110 | 0:57ece500234e | 223 | } |
daryl2110 | 0:57ece500234e | 224 | //----------------------------------------------------- |
daryl2110 | 0:57ece500234e | 225 | }; |
daryl2110 | 0:57ece500234e | 226 | |
daryl2110 | 0:57ece500234e | 227 | // No software interrupt stack switching provided, |
daryl2110 | 0:57ece500234e | 228 | // TISRW_SS declared to be the same as TISRW for porting compability |
daryl2110 | 0:57ece500234e | 229 | #define TISRW_SS TISRW |
daryl2110 | 0:57ece500234e | 230 | |
daryl2110 | 0:57ece500234e | 231 | } // ns OS |
daryl2110 | 0:57ece500234e | 232 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 233 | |
daryl2110 | 0:57ece500234e | 234 | #endif // scmRTOS_CORTEXM3_H |
daryl2110 | 0:57ece500234e | 235 | //----------------------------------------------------------------------------- |
daryl2110 | 0:57ece500234e | 236 |