Danillo Mangue Baja
SysClockConf.cpp
- Committer:
- hudakz
- Date:
- 2016-07-05
- Revision:
- 4:306609fe9dc8
- Parent:
- 3:a92af4b1ffe1
- Child:
- 5:9fbbea76d6f6
File content as of revision 4:306609fe9dc8:
/* ****************************************************************************** * @file SysClockConf.c * @author Zoltan Hudak * @version * @date 05-July-2016 * @brief System Clock configuration for STM32F103C8T6 ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT(c) 2016 Zoltan Hudak <hudakz@inbox.com> * * All rights reserved. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include "SysClockConf.h" #include "mbed.h" bool HSE_SystemClock_Config(int freq) { RCC_OscInitTypeDef RCC_OscInitStruct; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; switch(freq) { case 36: RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; break; case 48: RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6; break; default: RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; } if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { return false; } RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { return false; } RCC_PeriphCLKInitTypeDef PeriphClkInit; PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC|RCC_PERIPHCLK_USB; switch(freq) { case 36: PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; break; case 48: PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV4; break; default: PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6; } PeriphClkInit.UsbClockSelection = RCC_USBPLLCLK_DIV1; if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) { return false; } return true; } bool confSysClock(int freq) { HAL_RCC_DeInit(); if (!HSE_SystemClock_Config(freq)) { return false; } SystemCoreClockUpdate(); return true; }