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Dependencies: PinDetect TextLCD mbed mRotaryEncoder

scmRTOS/CortexM3/OS_Target.h@0:afb2650fb49a, 2012-02-13 (annotated)

Committer:: cicklaus
Date:: Mon Feb 13 02:11:20 2012 +0000
Revision:: 0:afb2650fb49a

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User	Revision	Line number	New contents of line
cicklaus	0:afb2650fb49a	1	//******************************************************************************
cicklaus	0:afb2650fb49a	2	//*
cicklaus	0:afb2650fb49a	3	//* FULLNAME: Single-Chip Microcontroller Real-Time Operating System
cicklaus	0:afb2650fb49a	4	//*
cicklaus	0:afb2650fb49a	5	//* NICKNAME: scmRTOS
cicklaus	0:afb2650fb49a	6	//*
cicklaus	0:afb2650fb49a	7	//* PROCESSOR: ARM Cortex-M3
cicklaus	0:afb2650fb49a	8	//*
cicklaus	0:afb2650fb49a	9	//* TOOLKIT: RVCT (ARM)
cicklaus	0:afb2650fb49a	10	//*
cicklaus	0:afb2650fb49a	11	//* PURPOSE: Target Dependent Stuff Header. Declarations And Definitions
cicklaus	0:afb2650fb49a	12	//*
cicklaus	0:afb2650fb49a	13	//* Version: 3.10
cicklaus	0:afb2650fb49a	14	//*
cicklaus	0:afb2650fb49a	15	//* $Revision: 195 $
cicklaus	0:afb2650fb49a	16	//* $Date:: 2008-06-19 #$
cicklaus	0:afb2650fb49a	17	//*
cicklaus	0:afb2650fb49a	18	//* Copyright (c) 2003-2010, Harry E. Zhurov
cicklaus	0:afb2650fb49a	19	//*
cicklaus	0:afb2650fb49a	20	//* Permission is hereby granted, free of charge, to any person
cicklaus	0:afb2650fb49a	21	//* obtaining a copy of this software and associated documentation
cicklaus	0:afb2650fb49a	22	//* files (the "Software"), to deal in the Software without restriction,
cicklaus	0:afb2650fb49a	23	//* including without limitation the rights to use, copy, modify, merge,
cicklaus	0:afb2650fb49a	24	//* publish, distribute, sublicense, and/or sell copies of the Software,
cicklaus	0:afb2650fb49a	25	//* and to permit persons to whom the Software is furnished to do so,
cicklaus	0:afb2650fb49a	26	//* subject to the following conditions:
cicklaus	0:afb2650fb49a	27	//*
cicklaus	0:afb2650fb49a	28	//* The above copyright notice and this permission notice shall be included
cicklaus	0:afb2650fb49a	29	//* in all copies or substantial portions of the Software.
cicklaus	0:afb2650fb49a	30	//*
cicklaus	0:afb2650fb49a	31	//* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
cicklaus	0:afb2650fb49a	32	//* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
cicklaus	0:afb2650fb49a	33	//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
cicklaus	0:afb2650fb49a	34	//* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
cicklaus	0:afb2650fb49a	35	//* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
cicklaus	0:afb2650fb49a	36	//* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH
cicklaus	0:afb2650fb49a	37	//* THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
cicklaus	0:afb2650fb49a	38	//*
cicklaus	0:afb2650fb49a	39	//* =================================================================
cicklaus	0:afb2650fb49a	40	//* See http://scmrtos.sourceforge.net for documentation, latest
cicklaus	0:afb2650fb49a	41	//* information, license and contact details.
cicklaus	0:afb2650fb49a	42	//* =================================================================
cicklaus	0:afb2650fb49a	43	//*
cicklaus	0:afb2650fb49a	44	//******************************************************************************
cicklaus	0:afb2650fb49a	45	//* Ported by Andrey Chuikin, Copyright (c) 2008-2010
cicklaus	0:afb2650fb49a	46
cicklaus	0:afb2650fb49a	47	#ifndef scmRTOS_CORTEXM3_H
cicklaus	0:afb2650fb49a	48	#define scmRTOS_CORTEXM3_H
cicklaus	0:afb2650fb49a	49
cicklaus	0:afb2650fb49a	50	#include <commdefs.h>
cicklaus	0:afb2650fb49a	51
cicklaus	0:afb2650fb49a	52	//------------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	53	//
cicklaus	0:afb2650fb49a	54	// Compiler and Target checks
cicklaus	0:afb2650fb49a	55	//
cicklaus	0:afb2650fb49a	56	//
cicklaus	0:afb2650fb49a	57	#ifndef __ARMCC_VERSION
cicklaus	0:afb2650fb49a	58	#error "This file should only be compiled with ARM RVCT Compiler"
cicklaus	0:afb2650fb49a	59	#endif // __ARMCC_VERSION
cicklaus	0:afb2650fb49a	60
cicklaus	0:afb2650fb49a	61	#if __TARGET_ARCH_ARM != 0 \|\| __TARGET_ARCH_THUMB != 4
cicklaus	0:afb2650fb49a	62	#error "This file must be compiled for ARMv7-M (Cortex-M3) processor only."
cicklaus	0:afb2650fb49a	63	#endif
cicklaus	0:afb2650fb49a	64
cicklaus	0:afb2650fb49a	65	//------------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	66	//
cicklaus	0:afb2650fb49a	67	// Target specific types
cicklaus	0:afb2650fb49a	68	//
cicklaus	0:afb2650fb49a	69	//
cicklaus	0:afb2650fb49a	70	typedef dword TStackItem;
cicklaus	0:afb2650fb49a	71	typedef dword TStatusReg;
cicklaus	0:afb2650fb49a	72
cicklaus	0:afb2650fb49a	73	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	74	//
cicklaus	0:afb2650fb49a	75	// Configuration macros
cicklaus	0:afb2650fb49a	76	//
cicklaus	0:afb2650fb49a	77	//
cicklaus	0:afb2650fb49a	78	#define OS_PROCESS __attribute__((__noreturn__))
cicklaus	0:afb2650fb49a	79	#define OS_INTERRUPT
cicklaus	0:afb2650fb49a	80	#define DUMMY_INSTR() __NOP()
cicklaus	0:afb2650fb49a	81	#define INLINE_PROCESS_CTOR INLINE inline
cicklaus	0:afb2650fb49a	82
cicklaus	0:afb2650fb49a	83	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	84	//
cicklaus	0:afb2650fb49a	85	// Uncomment macro value below for SystemTimer() run in critical section
cicklaus	0:afb2650fb49a	86	//
cicklaus	0:afb2650fb49a	87	// This is useful (and necessary) when target processor has hardware
cicklaus	0:afb2650fb49a	88	// enabled nested interrups. Cortex-M3 have such interrupts.
cicklaus	0:afb2650fb49a	89	//
cicklaus	0:afb2650fb49a	90	#define SYS_TIMER_CRIT_SECT() TCritSect cs
cicklaus	0:afb2650fb49a	91
cicklaus	0:afb2650fb49a	92	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	93	// Separate return stack not required
cicklaus	0:afb2650fb49a	94	#define SEPARATE_RETURN_STACK 0
cicklaus	0:afb2650fb49a	95
cicklaus	0:afb2650fb49a	96	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	97	// Software interrupt stack switching not supported in Cortex-M3 port
cicklaus	0:afb2650fb49a	98	// because processor implements hardware stack switching.
cicklaus	0:afb2650fb49a	99	// So, system timer isr wrapper can't be choosen at project level
cicklaus	0:afb2650fb49a	100	//
cicklaus	0:afb2650fb49a	101	#define scmRTOS_ISRW_TYPE TISRW
cicklaus	0:afb2650fb49a	102
cicklaus	0:afb2650fb49a	103	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	104	//
cicklaus	0:afb2650fb49a	105	// scmRTOS Context Switch Scheme
cicklaus	0:afb2650fb49a	106	//
cicklaus	0:afb2650fb49a	107	// The macro defines a context switch manner. Value 0 sets direct context
cicklaus	0:afb2650fb49a	108	// switch in the scheduler and in the OS ISRs. This is the primary method.
cicklaus	0:afb2650fb49a	109	// Value 1 sets the second way to switch context - by using of software
cicklaus	0:afb2650fb49a	110	// interrupt. See documentation fo details.
cicklaus	0:afb2650fb49a	111	// Cortex-M3 port supports software interrupt switch method only.
cicklaus	0:afb2650fb49a	112	//
cicklaus	0:afb2650fb49a	113	#define scmRTOS_CONTEXT_SWITCH_SCHEME 1
cicklaus	0:afb2650fb49a	114
cicklaus	0:afb2650fb49a	115	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	116	//
cicklaus	0:afb2650fb49a	117	// Include project-level configurations
cicklaus	0:afb2650fb49a	118	// !!! The order of includes is important !!!
cicklaus	0:afb2650fb49a	119	//
cicklaus	0:afb2650fb49a	120	#include "../../scmRTOS_config.h"
cicklaus	0:afb2650fb49a	121	#include "../scmRTOS_TARGET_CFG.h"
cicklaus	0:afb2650fb49a	122	#include <scmRTOS_defs.h>
cicklaus	0:afb2650fb49a	123	#include <LPC17xx.h>
cicklaus	0:afb2650fb49a	124
cicklaus	0:afb2650fb49a	125	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	126	//
cicklaus	0:afb2650fb49a	127	// The Critital Section Wrapper
cicklaus	0:afb2650fb49a	128	//
cicklaus	0:afb2650fb49a	129	//
cicklaus	0:afb2650fb49a	130	#define __enable_interrupt() __enable_irq()
cicklaus	0:afb2650fb49a	131	#define __disable_interrupt() __disable_irq()
cicklaus	0:afb2650fb49a	132
cicklaus	0:afb2650fb49a	133	#define __set_interrupt_state(status) __set_PRIMASK(status)
cicklaus	0:afb2650fb49a	134	#define __get_interrupt_state() __get_PRIMASK()
cicklaus	0:afb2650fb49a	135
cicklaus	0:afb2650fb49a	136	class TCritSect
cicklaus	0:afb2650fb49a	137	{
cicklaus	0:afb2650fb49a	138	public:
cicklaus	0:afb2650fb49a	139	TCritSect () : StatusReg(__get_interrupt_state()) { __disable_interrupt(); }
cicklaus	0:afb2650fb49a	140	~TCritSect() { __set_interrupt_state(StatusReg); }
cicklaus	0:afb2650fb49a	141
cicklaus	0:afb2650fb49a	142	private:
cicklaus	0:afb2650fb49a	143	TStatusReg StatusReg;
cicklaus	0:afb2650fb49a	144	};
cicklaus	0:afb2650fb49a	145	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	146
cicklaus	0:afb2650fb49a	147	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	148	//
cicklaus	0:afb2650fb49a	149	// Priority stuff
cicklaus	0:afb2650fb49a	150	//
cicklaus	0:afb2650fb49a	151	//
cicklaus	0:afb2650fb49a	152	namespace OS
cicklaus	0:afb2650fb49a	153	{
cicklaus	0:afb2650fb49a	154	INLINE inline OS::TProcessMap GetPrioTag(const byte pr) { return static_cast<OS::TProcessMap> (1 << pr); }
cicklaus	0:afb2650fb49a	155
cicklaus	0:afb2650fb49a	156	#if scmRTOS_PRIORITY_ORDER == 0
cicklaus	0:afb2650fb49a	157	INLINE inline byte GetHighPriority(TProcessMap pm)
cicklaus	0:afb2650fb49a	158	{
cicklaus	0:afb2650fb49a	159	byte pr = 0;
cicklaus	0:afb2650fb49a	160
cicklaus	0:afb2650fb49a	161	while( !(pm & 0x0001) )
cicklaus	0:afb2650fb49a	162	{
cicklaus	0:afb2650fb49a	163	pr++;
cicklaus	0:afb2650fb49a	164	pm >>= 1;
cicklaus	0:afb2650fb49a	165	}
cicklaus	0:afb2650fb49a	166	return pr;
cicklaus	0:afb2650fb49a	167	}
cicklaus	0:afb2650fb49a	168	#else
cicklaus	0:afb2650fb49a	169	INLINE inline byte GetHighPriority(TProcessMap pm) { return (31 - __clz(pm)); }
cicklaus	0:afb2650fb49a	170	#endif // scmRTOS_PRIORITY_ORDER
cicklaus	0:afb2650fb49a	171	}
cicklaus	0:afb2650fb49a	172
cicklaus	0:afb2650fb49a	173	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	174	//
cicklaus	0:afb2650fb49a	175	// Interrupt and Interrupt Service Routines support
cicklaus	0:afb2650fb49a	176	//
cicklaus	0:afb2650fb49a	177	INLINE inline TStatusReg GetInterruptState( ) { return __get_interrupt_state(); }
cicklaus	0:afb2650fb49a	178	INLINE inline void SetInterruptState(TStatusReg sr) { __set_interrupt_state(sr); }
cicklaus	0:afb2650fb49a	179
cicklaus	0:afb2650fb49a	180	INLINE inline void EnableInterrupts() { __enable_interrupt(); }
cicklaus	0:afb2650fb49a	181	INLINE inline void DisableInterrupts() { __disable_interrupt(); }
cicklaus	0:afb2650fb49a	182
cicklaus	0:afb2650fb49a	183
cicklaus	0:afb2650fb49a	184	namespace OS
cicklaus	0:afb2650fb49a	185	{
cicklaus	0:afb2650fb49a	186	INLINE inline void EnableContextSwitch() { EnableInterrupts(); }
cicklaus	0:afb2650fb49a	187	INLINE inline void DisableContextSwitch() { DisableInterrupts(); }
cicklaus	0:afb2650fb49a	188	}
cicklaus	0:afb2650fb49a	189
cicklaus	0:afb2650fb49a	190	#include <OS_Kernel.h>
cicklaus	0:afb2650fb49a	191
cicklaus	0:afb2650fb49a	192	namespace OS
cicklaus	0:afb2650fb49a	193	{
cicklaus	0:afb2650fb49a	194	//--------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	195	//
cicklaus	0:afb2650fb49a	196	// NAME : OS ISR support
cicklaus	0:afb2650fb49a	197	//
cicklaus	0:afb2650fb49a	198	// PURPOSE : Implements common actions on interrupt enter and exit
cicklaus	0:afb2650fb49a	199	// under the OS
cicklaus	0:afb2650fb49a	200	//
cicklaus	0:afb2650fb49a	201	// DESCRIPTION:
cicklaus	0:afb2650fb49a	202	//
cicklaus	0:afb2650fb49a	203	//
cicklaus	0:afb2650fb49a	204	class TISRW
cicklaus	0:afb2650fb49a	205	{
cicklaus	0:afb2650fb49a	206	public:
cicklaus	0:afb2650fb49a	207	INLINE TISRW() { ISR_Enter(); }
cicklaus	0:afb2650fb49a	208	INLINE ~TISRW() { ISR_Exit(); }
cicklaus	0:afb2650fb49a	209
cicklaus	0:afb2650fb49a	210	private:
cicklaus	0:afb2650fb49a	211	//-----------------------------------------------------
cicklaus	0:afb2650fb49a	212	INLINE void ISR_Enter()
cicklaus	0:afb2650fb49a	213	{
cicklaus	0:afb2650fb49a	214	TCritSect cs;
cicklaus	0:afb2650fb49a	215	Kernel.ISR_NestCount++;
cicklaus	0:afb2650fb49a	216	}
cicklaus	0:afb2650fb49a	217	//-----------------------------------------------------
cicklaus	0:afb2650fb49a	218	INLINE void ISR_Exit()
cicklaus	0:afb2650fb49a	219	{
cicklaus	0:afb2650fb49a	220	TCritSect cs;
cicklaus	0:afb2650fb49a	221	if(--Kernel.ISR_NestCount) return;
cicklaus	0:afb2650fb49a	222	Kernel.SchedISR();
cicklaus	0:afb2650fb49a	223	}
cicklaus	0:afb2650fb49a	224	//-----------------------------------------------------
cicklaus	0:afb2650fb49a	225	};
cicklaus	0:afb2650fb49a	226
cicklaus	0:afb2650fb49a	227	// No software interrupt stack switching provided,
cicklaus	0:afb2650fb49a	228	// TISRW_SS declared to be the same as TISRW for porting compability
cicklaus	0:afb2650fb49a	229	#define TISRW_SS TISRW
cicklaus	0:afb2650fb49a	230
cicklaus	0:afb2650fb49a	231	} // ns OS
cicklaus	0:afb2650fb49a	232	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	233
cicklaus	0:afb2650fb49a	234	#endif // scmRTOS_CORTEXM3_H
cicklaus	0:afb2650fb49a	235	//-----------------------------------------------------------------------------
cicklaus	0:afb2650fb49a	236

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	13 Feb 2012
Imports:	15
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	4
Followers:	1

scmRTOS/CortexM3/OS_Target.h@0:afb2650fb49a, 2012-02-13 (annotated)

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