Diff: STM32_USB48MHz.cpp

Revision:

1:c97a4f5cb6cf

Parent:

0:0c251314fe4b

--- a/STM32_USB48MHz.cpp	Sat Jun 20 00:43:28 2015 +0000
+++ b/STM32_USB48MHz.cpp	Wed Sep 21 20:49:31 2016 +0100
@@ -97,6 +97,107 @@
     return src;
 }
 
+#elif defined(TARGET_STM32F3)
+bool HSE_SystemClock_Config(void) {
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+    RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+    RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+    RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return false;
+    }
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+        return false;
+    }
+    RCC_PeriphCLKInitTypeDef PeriphClkInit;
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+        return false;
+    }
+    return true;
+}
+
+bool HSI_SystemClock_Config(void) {
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+    RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+    RCC_OscInitStruct.HSICalibrationValue = 8;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+    RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI will be predivided by 2
+    RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+        return false;
+    }
+    RCC_ClkInitTypeDef RCC_ClkInitStruct;
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+    if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
+        return false;
+    }
+    RCC_PeriphCLKInitTypeDef PeriphClkInit;
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+    PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
+        return false;
+    }
+    return true;
+}
+
+uint32_t STM32_getUSBclock() {
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
+    uint32_t src = 0;
+    switch(RCC_OscInitStruct.PLL.PLLSource) {
+        case RCC_PLLSOURCE_HSI:
+            src = HSI_VALUE;
+            break;
+        case RCC_PLLSOURCE_HSE:
+            src = HSE_VALUE;
+            switch(RCC_OscInitStruct.HSEPredivValue) {
+                case RCC_HSE_PREDIV_DIV1: src /= 1; break;
+                case RCC_HSE_PREDIV_DIV2: src /= 2; break;
+            }
+            break;
+    }
+    switch(RCC_OscInitStruct.PLL.PLLMUL) {
+        case RCC_PLL_MUL2: src *= 2; break;
+        case RCC_PLL_MUL3: src *= 3; break;
+        case RCC_PLL_MUL4: src *= 4; break;
+        case RCC_PLL_MUL5: src *= 5; break;
+        case RCC_PLL_MUL6: src *= 6; break;
+        case RCC_PLL_MUL7: src *= 7; break;
+        case RCC_PLL_MUL8: src *= 8; break;
+        case RCC_PLL_MUL9: src *= 9; break;
+        case RCC_PLL_MUL10: src *= 10; break;
+        case RCC_PLL_MUL11: src *= 11; break;
+        case RCC_PLL_MUL12: src *= 12; break;
+        case RCC_PLL_MUL13: src *= 13; break;
+        case RCC_PLL_MUL14: src *= 14; break;
+        case RCC_PLL_MUL15: src *= 15; break;
+        case RCC_PLL_MUL16: src *= 16; break;
+    }
+    RCC_PeriphCLKInitTypeDef  PeriphClkInit;
+    HAL_RCCEx_GetPeriphCLKConfig(&PeriphClkInit);
+    switch(PeriphClkInit.USBClockSelection) {
+        case RCC_USBCLKSOURCE_PLL: src /= 1; break;
+        case RCC_USBCLKSOURCE_PLL_DIV1_5: src = src * 2 / 3; break;
+    }
+    return src;
+}
+
 #elif defined(TARGET_STM32L1)
 bool HSE_SystemClock_Config(void) { // STM32L152RE
     __PWR_CLK_ENABLE();