Bradley Scott / STM32_USB48MHz

STM32 USB clock configuration with STM32F3 support

Fork of STM32_USB48MHz by Norimasa Okamoto

STM32_USB48MHz.cpp@1:c97a4f5cb6cf, 2016-09-21 (annotated)

Committer:
Bradley Scott
Date:
Wed Sep 21 20:49:31 2016 +0100
Revision:
1:c97a4f5cb6cf
Parent:
0:0c251314fe4b 
Add STM32F3 support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
va009039 0:0c251314fe4b 1 // STM32_USB48MHz.cpp 2015/6/20
va009039 0:0c251314fe4b 2 #include "STM32_USB48MHz.h"
va009039 0:0c251314fe4b 3
va009039 0:0c251314fe4b 4 #if defined(TARGET_STM32F1)
va009039 0:0c251314fe4b 5 bool HSE_SystemClock_Config(void) { // STM32F103RB
va009039 0:0c251314fe4b 6 RCC_OscInitTypeDef RCC_OscInitStruct;
va009039 0:0c251314fe4b 7 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
va009039 0:0c251314fe4b 8 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
va009039 0:0c251314fe4b 9 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
va009039 0:0c251314fe4b 10 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
va009039 0:0c251314fe4b 11 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
va009039 0:0c251314fe4b 12 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
va009039 0:0c251314fe4b 13 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
va009039 0:0c251314fe4b 14 return false;
va009039 0:0c251314fe4b 15 }
va009039 0:0c251314fe4b 16 RCC_ClkInitTypeDef RCC_ClkInitStruct;
va009039 0:0c251314fe4b 17 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1;
va009039 0:0c251314fe4b 18 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
va009039 0:0c251314fe4b 19 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
va009039 0:0c251314fe4b 20 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
va009039 0:0c251314fe4b 21 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
va009039 0:0c251314fe4b 22 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
va009039 0:0c251314fe4b 23 return false;
va009039 0:0c251314fe4b 24 }
va009039 0:0c251314fe4b 25 RCC_PeriphCLKInitTypeDef PeriphClkInit;
va009039 0:0c251314fe4b 26 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
va009039 0:0c251314fe4b 27 PeriphClkInit.UsbClockSelection = RCC_USBPLLCLK_DIV1_5;
va009039 0:0c251314fe4b 28 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
va009039 0:0c251314fe4b 29 return false;
va009039 0:0c251314fe4b 30 }
va009039 0:0c251314fe4b 31 return true;
va009039 0:0c251314fe4b 32 }
va009039 0:0c251314fe4b 33
va009039 0:0c251314fe4b 34 bool HSI_SystemClock_Config(void) { // STM32F103RB
va009039 0:0c251314fe4b 35 RCC_OscInitTypeDef RCC_OscInitStruct;
va009039 0:0c251314fe4b 36 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
va009039 0:0c251314fe4b 37 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
va009039 0:0c251314fe4b 38 RCC_OscInitStruct.HSICalibrationValue = 16;
va009039 0:0c251314fe4b 39 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
va009039 0:0c251314fe4b 40 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
va009039 0:0c251314fe4b 41 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
va009039 0:0c251314fe4b 42 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
va009039 0:0c251314fe4b 43 return false;
va009039 0:0c251314fe4b 44 }
va009039 0:0c251314fe4b 45 RCC_ClkInitTypeDef RCC_ClkInitStruct;
va009039 0:0c251314fe4b 46 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1;
va009039 0:0c251314fe4b 47 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
va009039 0:0c251314fe4b 48 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
va009039 0:0c251314fe4b 49 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
va009039 0:0c251314fe4b 50 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
va009039 0:0c251314fe4b 51 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
va009039 0:0c251314fe4b 52 return false;
va009039 0:0c251314fe4b 53 }
va009039 0:0c251314fe4b 54 RCC_PeriphCLKInitTypeDef PeriphClkInit;
va009039 0:0c251314fe4b 55 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
va009039 0:0c251314fe4b 56 PeriphClkInit.UsbClockSelection = RCC_USBPLLCLK_DIV1;
va009039 0:0c251314fe4b 57 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
va009039 0:0c251314fe4b 58 return false;
va009039 0:0c251314fe4b 59 }
va009039 0:0c251314fe4b 60 return true;
va009039 0:0c251314fe4b 61 }
va009039 0:0c251314fe4b 62
va009039 0:0c251314fe4b 63 uint32_t STM32_getUSBclock() { // STM32F1
va009039 0:0c251314fe4b 64 RCC_OscInitTypeDef RCC_OscInitStruct;
va009039 0:0c251314fe4b 65 HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
va009039 0:0c251314fe4b 66 uint32_t src = 0;
va009039 0:0c251314fe4b 67 switch(RCC_OscInitStruct.PLL.PLLSource) {
va009039 0:0c251314fe4b 68 case RCC_PLLSOURCE_HSI_DIV2:
va009039 0:0c251314fe4b 69 src = HSI_VALUE / 2;
va009039 0:0c251314fe4b 70 break;
va009039 0:0c251314fe4b 71 case RCC_PLLSOURCE_HSE:
va009039 0:0c251314fe4b 72 src = HSE_VALUE;
va009039 0:0c251314fe4b 73 switch(RCC_OscInitStruct.HSEPredivValue) {
va009039 0:0c251314fe4b 74 case RCC_HSE_PREDIV_DIV1: src /= 1; break;
va009039 0:0c251314fe4b 75 case RCC_HSE_PREDIV_DIV2: src /= 2; break;
va009039 0:0c251314fe4b 76 }
va009039 0:0c251314fe4b 77 break;
va009039 0:0c251314fe4b 78 }
va009039 0:0c251314fe4b 79 switch(RCC_OscInitStruct.PLL.PLLMUL) {
va009039 0:0c251314fe4b 80 case RCC_PLL_MUL2: src *= 2; break;
va009039 0:0c251314fe4b 81 case RCC_PLL_MUL3: src *= 3; break;
va009039 0:0c251314fe4b 82 case RCC_PLL_MUL4: src *= 4; break;
va009039 0:0c251314fe4b 83 case RCC_PLL_MUL6: src *= 6; break;
va009039 0:0c251314fe4b 84 case RCC_PLL_MUL8: src *= 8; break;
va009039 0:0c251314fe4b 85 case RCC_PLL_MUL12: src *= 12; break;
va009039 0:0c251314fe4b 86 case RCC_PLL_MUL13: src *= 13; break;
va009039 0:0c251314fe4b 87 case RCC_PLL_MUL14: src *= 14; break;
va009039 0:0c251314fe4b 88 case RCC_PLL_MUL15: src *= 15; break;
va009039 0:0c251314fe4b 89 case RCC_PLL_MUL16: src *= 16; break;
va009039 0:0c251314fe4b 90 }
va009039 0:0c251314fe4b 91 RCC_PeriphCLKInitTypeDef PeriphClkInit;
va009039 0:0c251314fe4b 92 HAL_RCCEx_GetPeriphCLKConfig(&PeriphClkInit);
va009039 0:0c251314fe4b 93 switch(PeriphClkInit.UsbClockSelection) {
va009039 0:0c251314fe4b 94 case RCC_USBPLLCLK_DIV1: src /= 1; break;
va009039 0:0c251314fe4b 95 case RCC_USBPLLCLK_DIV1_5: src = src * 2 / 3; break;
va009039 0:0c251314fe4b 96 }
va009039 0:0c251314fe4b 97 return src;
va009039 0:0c251314fe4b 98 }
va009039 0:0c251314fe4b 99
Bradley Scott 1:c97a4f5cb6cf 100 #elif defined(TARGET_STM32F3)
Bradley Scott 1:c97a4f5cb6cf 101 bool HSE_SystemClock_Config(void) {
Bradley Scott 1:c97a4f5cb6cf 102 RCC_OscInitTypeDef RCC_OscInitStruct;
Bradley Scott 1:c97a4f5cb6cf 103 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
Bradley Scott 1:c97a4f5cb6cf 104 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
Bradley Scott 1:c97a4f5cb6cf 105 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
Bradley Scott 1:c97a4f5cb6cf 106 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Bradley Scott 1:c97a4f5cb6cf 107 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
Bradley Scott 1:c97a4f5cb6cf 108 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
Bradley Scott 1:c97a4f5cb6cf 109 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Bradley Scott 1:c97a4f5cb6cf 110 return false;
Bradley Scott 1:c97a4f5cb6cf 111 }
Bradley Scott 1:c97a4f5cb6cf 112 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Bradley Scott 1:c97a4f5cb6cf 113 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1;
Bradley Scott 1:c97a4f5cb6cf 114 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
Bradley Scott 1:c97a4f5cb6cf 115 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
Bradley Scott 1:c97a4f5cb6cf 116 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
Bradley Scott 1:c97a4f5cb6cf 117 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
Bradley Scott 1:c97a4f5cb6cf 118 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
Bradley Scott 1:c97a4f5cb6cf 119 return false;
Bradley Scott 1:c97a4f5cb6cf 120 }
Bradley Scott 1:c97a4f5cb6cf 121 RCC_PeriphCLKInitTypeDef PeriphClkInit;
Bradley Scott 1:c97a4f5cb6cf 122 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
Bradley Scott 1:c97a4f5cb6cf 123 PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
Bradley Scott 1:c97a4f5cb6cf 124 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
Bradley Scott 1:c97a4f5cb6cf 125 return false;
Bradley Scott 1:c97a4f5cb6cf 126 }
Bradley Scott 1:c97a4f5cb6cf 127 return true;
Bradley Scott 1:c97a4f5cb6cf 128 }
Bradley Scott 1:c97a4f5cb6cf 129
Bradley Scott 1:c97a4f5cb6cf 130 bool HSI_SystemClock_Config(void) {
Bradley Scott 1:c97a4f5cb6cf 131 RCC_OscInitTypeDef RCC_OscInitStruct;
Bradley Scott 1:c97a4f5cb6cf 132 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
Bradley Scott 1:c97a4f5cb6cf 133 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
Bradley Scott 1:c97a4f5cb6cf 134 RCC_OscInitStruct.HSICalibrationValue = 8;
Bradley Scott 1:c97a4f5cb6cf 135 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Bradley Scott 1:c97a4f5cb6cf 136 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI will be predivided by 2
Bradley Scott 1:c97a4f5cb6cf 137 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
Bradley Scott 1:c97a4f5cb6cf 138 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Bradley Scott 1:c97a4f5cb6cf 139 return false;
Bradley Scott 1:c97a4f5cb6cf 140 }
Bradley Scott 1:c97a4f5cb6cf 141 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Bradley Scott 1:c97a4f5cb6cf 142 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1;
Bradley Scott 1:c97a4f5cb6cf 143 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
Bradley Scott 1:c97a4f5cb6cf 144 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
Bradley Scott 1:c97a4f5cb6cf 145 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
Bradley Scott 1:c97a4f5cb6cf 146 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
Bradley Scott 1:c97a4f5cb6cf 147 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
Bradley Scott 1:c97a4f5cb6cf 148 return false;
Bradley Scott 1:c97a4f5cb6cf 149 }
Bradley Scott 1:c97a4f5cb6cf 150 RCC_PeriphCLKInitTypeDef PeriphClkInit;
Bradley Scott 1:c97a4f5cb6cf 151 PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
Bradley Scott 1:c97a4f5cb6cf 152 PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL;
Bradley Scott 1:c97a4f5cb6cf 153 if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
Bradley Scott 1:c97a4f5cb6cf 154 return false;
Bradley Scott 1:c97a4f5cb6cf 155 }
Bradley Scott 1:c97a4f5cb6cf 156 return true;
Bradley Scott 1:c97a4f5cb6cf 157 }
Bradley Scott 1:c97a4f5cb6cf 158
Bradley Scott 1:c97a4f5cb6cf 159 uint32_t STM32_getUSBclock() {
Bradley Scott 1:c97a4f5cb6cf 160 RCC_OscInitTypeDef RCC_OscInitStruct;
Bradley Scott 1:c97a4f5cb6cf 161 HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
Bradley Scott 1:c97a4f5cb6cf 162 uint32_t src = 0;
Bradley Scott 1:c97a4f5cb6cf 163 switch(RCC_OscInitStruct.PLL.PLLSource) {
Bradley Scott 1:c97a4f5cb6cf 164 case RCC_PLLSOURCE_HSI:
Bradley Scott 1:c97a4f5cb6cf 165 src = HSI_VALUE;
Bradley Scott 1:c97a4f5cb6cf 166 break;
Bradley Scott 1:c97a4f5cb6cf 167 case RCC_PLLSOURCE_HSE:
Bradley Scott 1:c97a4f5cb6cf 168 src = HSE_VALUE;
Bradley Scott 1:c97a4f5cb6cf 169 switch(RCC_OscInitStruct.HSEPredivValue) {
Bradley Scott 1:c97a4f5cb6cf 170 case RCC_HSE_PREDIV_DIV1: src /= 1; break;
Bradley Scott 1:c97a4f5cb6cf 171 case RCC_HSE_PREDIV_DIV2: src /= 2; break;
Bradley Scott 1:c97a4f5cb6cf 172 }
Bradley Scott 1:c97a4f5cb6cf 173 break;
Bradley Scott 1:c97a4f5cb6cf 174 }
Bradley Scott 1:c97a4f5cb6cf 175 switch(RCC_OscInitStruct.PLL.PLLMUL) {
Bradley Scott 1:c97a4f5cb6cf 176 case RCC_PLL_MUL2: src *= 2; break;
Bradley Scott 1:c97a4f5cb6cf 177 case RCC_PLL_MUL3: src *= 3; break;
Bradley Scott 1:c97a4f5cb6cf 178 case RCC_PLL_MUL4: src *= 4; break;
Bradley Scott 1:c97a4f5cb6cf 179 case RCC_PLL_MUL5: src *= 5; break;
Bradley Scott 1:c97a4f5cb6cf 180 case RCC_PLL_MUL6: src *= 6; break;
Bradley Scott 1:c97a4f5cb6cf 181 case RCC_PLL_MUL7: src *= 7; break;
Bradley Scott 1:c97a4f5cb6cf 182 case RCC_PLL_MUL8: src *= 8; break;
Bradley Scott 1:c97a4f5cb6cf 183 case RCC_PLL_MUL9: src *= 9; break;
Bradley Scott 1:c97a4f5cb6cf 184 case RCC_PLL_MUL10: src *= 10; break;
Bradley Scott 1:c97a4f5cb6cf 185 case RCC_PLL_MUL11: src *= 11; break;
Bradley Scott 1:c97a4f5cb6cf 186 case RCC_PLL_MUL12: src *= 12; break;
Bradley Scott 1:c97a4f5cb6cf 187 case RCC_PLL_MUL13: src *= 13; break;
Bradley Scott 1:c97a4f5cb6cf 188 case RCC_PLL_MUL14: src *= 14; break;
Bradley Scott 1:c97a4f5cb6cf 189 case RCC_PLL_MUL15: src *= 15; break;
Bradley Scott 1:c97a4f5cb6cf 190 case RCC_PLL_MUL16: src *= 16; break;
Bradley Scott 1:c97a4f5cb6cf 191 }
Bradley Scott 1:c97a4f5cb6cf 192 RCC_PeriphCLKInitTypeDef PeriphClkInit;
Bradley Scott 1:c97a4f5cb6cf 193 HAL_RCCEx_GetPeriphCLKConfig(&PeriphClkInit);
Bradley Scott 1:c97a4f5cb6cf 194 switch(PeriphClkInit.USBClockSelection) {
Bradley Scott 1:c97a4f5cb6cf 195 case RCC_USBCLKSOURCE_PLL: src /= 1; break;
Bradley Scott 1:c97a4f5cb6cf 196 case RCC_USBCLKSOURCE_PLL_DIV1_5: src = src * 2 / 3; break;
Bradley Scott 1:c97a4f5cb6cf 197 }
Bradley Scott 1:c97a4f5cb6cf 198 return src;
Bradley Scott 1:c97a4f5cb6cf 199 }
Bradley Scott 1:c97a4f5cb6cf 200
va009039 0:0c251314fe4b 201 #elif defined(TARGET_STM32L1)
va009039 0:0c251314fe4b 202 bool HSE_SystemClock_Config(void) { // STM32L152RE
va009039 0:0c251314fe4b 203 __PWR_CLK_ENABLE();
va009039 0:0c251314fe4b 204 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
va009039 0:0c251314fe4b 205 RCC_OscInitTypeDef RCC_OscInitStruct;
va009039 0:0c251314fe4b 206 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
va009039 0:0c251314fe4b 207 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
va009039 0:0c251314fe4b 208 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
va009039 0:0c251314fe4b 209 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
va009039 0:0c251314fe4b 210 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
va009039 0:0c251314fe4b 211 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
va009039 0:0c251314fe4b 212 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
va009039 0:0c251314fe4b 213 return false;
va009039 0:0c251314fe4b 214 }
va009039 0:0c251314fe4b 215 RCC_ClkInitTypeDef RCC_ClkInitStruct;
va009039 0:0c251314fe4b 216 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
va009039 0:0c251314fe4b 217 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
va009039 0:0c251314fe4b 218 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
va009039 0:0c251314fe4b 219 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
va009039 0:0c251314fe4b 220 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
va009039 0:0c251314fe4b 221 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
va009039 0:0c251314fe4b 222 return false;
va009039 0:0c251314fe4b 223 }
va009039 0:0c251314fe4b 224 return true;
va009039 0:0c251314fe4b 225 }
va009039 0:0c251314fe4b 226
va009039 0:0c251314fe4b 227 bool HSI_SystemClock_Config(void) { // STM32L152RE
va009039 0:0c251314fe4b 228 __PWR_CLK_ENABLE();
va009039 0:0c251314fe4b 229 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
va009039 0:0c251314fe4b 230 RCC_OscInitTypeDef RCC_OscInitStruct;
va009039 0:0c251314fe4b 231 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
va009039 0:0c251314fe4b 232 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
va009039 0:0c251314fe4b 233 RCC_OscInitStruct.HSICalibrationValue = 16;
va009039 0:0c251314fe4b 234 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
va009039 0:0c251314fe4b 235 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
va009039 0:0c251314fe4b 236 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
va009039 0:0c251314fe4b 237 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
va009039 0:0c251314fe4b 238 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
va009039 0:0c251314fe4b 239 return false;
va009039 0:0c251314fe4b 240 }
va009039 0:0c251314fe4b 241 RCC_ClkInitTypeDef RCC_ClkInitStruct;
va009039 0:0c251314fe4b 242 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
va009039 0:0c251314fe4b 243 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
va009039 0:0c251314fe4b 244 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
va009039 0:0c251314fe4b 245 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
va009039 0:0c251314fe4b 246 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
va009039 0:0c251314fe4b 247 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
va009039 0:0c251314fe4b 248 return false;
va009039 0:0c251314fe4b 249 }
va009039 0:0c251314fe4b 250 return true;
va009039 0:0c251314fe4b 251 }
va009039 0:0c251314fe4b 252
va009039 0:0c251314fe4b 253 uint32_t STM32_getUSBclock() { // STM32L1
va009039 0:0c251314fe4b 254 RCC_OscInitTypeDef RCC_OscInit;
va009039 0:0c251314fe4b 255 HAL_RCC_GetOscConfig(&RCC_OscInit);
va009039 0:0c251314fe4b 256 uint32_t src = 0;
va009039 0:0c251314fe4b 257 switch(RCC_OscInit.PLL.PLLSource) {
va009039 0:0c251314fe4b 258 case RCC_PLLSOURCE_HSI: src = HSI_VALUE; break;
va009039 0:0c251314fe4b 259 case RCC_PLLSOURCE_HSE: src = HSE_VALUE; break;
va009039 0:0c251314fe4b 260 }
va009039 0:0c251314fe4b 261 switch(RCC_OscInit.PLL.PLLMUL) {
va009039 0:0c251314fe4b 262 case RCC_PLL_MUL3: src *= 3; break;
va009039 0:0c251314fe4b 263 case RCC_PLL_MUL4: src *= 4; break;
va009039 0:0c251314fe4b 264 case RCC_PLL_MUL6: src *= 6; break;
va009039 0:0c251314fe4b 265 case RCC_PLL_MUL8: src *= 8; break;
va009039 0:0c251314fe4b 266 case RCC_PLL_MUL12: src *= 12; break;
va009039 0:0c251314fe4b 267 case RCC_PLL_MUL16: src *= 16; break;
va009039 0:0c251314fe4b 268 case RCC_PLL_MUL24: src *= 24; break;
va009039 0:0c251314fe4b 269 case RCC_PLL_MUL32: src *= 32; break;
va009039 0:0c251314fe4b 270 case RCC_PLL_MUL48: src *= 48; break;
va009039 0:0c251314fe4b 271 }
va009039 0:0c251314fe4b 272 return src / 2;
va009039 0:0c251314fe4b 273 }
va009039 0:0c251314fe4b 274 #else
va009039 0:0c251314fe4b 275 #error "target error"
va009039 0:0c251314fe4b 276 #endif
va009039 0:0c251314fe4b 277
va009039 0:0c251314fe4b 278 bool STM32_HSE_USB48MHz() {
va009039 0:0c251314fe4b 279 HAL_RCC_DeInit();
va009039 0:0c251314fe4b 280 if (!HSE_SystemClock_Config()) {
va009039 0:0c251314fe4b 281 return false;
va009039 0:0c251314fe4b 282 }
va009039 0:0c251314fe4b 283 SystemCoreClockUpdate();
va009039 0:0c251314fe4b 284 return true;
va009039 0:0c251314fe4b 285 }
va009039 0:0c251314fe4b 286
va009039 0:0c251314fe4b 287 bool STM32_HSI_USB48MHz() {
va009039 0:0c251314fe4b 288 HAL_RCC_DeInit();
va009039 0:0c251314fe4b 289 if (!HSI_SystemClock_Config()) {
va009039 0:0c251314fe4b 290 return false;
va009039 0:0c251314fe4b 291 }
va009039 0:0c251314fe4b 292 SystemCoreClockUpdate();
va009039 0:0c251314fe4b 293 return true;
va009039 0:0c251314fe4b 294 }
va009039 0:0c251314fe4b 295
va009039 0:0c251314fe4b 296 bool STM32_USB48MHz() {
va009039 0:0c251314fe4b 297 HAL_RCC_DeInit();
va009039 0:0c251314fe4b 298 if (!HSE_SystemClock_Config()) {
va009039 0:0c251314fe4b 299 if (!HSI_SystemClock_Config()) {
va009039 0:0c251314fe4b 300 return false;
va009039 0:0c251314fe4b 301 }
va009039 0:0c251314fe4b 302 }
va009039 0:0c251314fe4b 303 SystemCoreClockUpdate();
va009039 0:0c251314fe4b 304 return true;
va009039 0:0c251314fe4b 305 }
va009039 0:0c251314fe4b 306
va009039 0:0c251314fe4b 307