Benjamin Hepp / DW1000

Simple driver for DWM1000 modules.

DW1000.h@5:c34ebc7f650c, 2016-03-31 (annotated)

Committer:
bhepp
Date:
Thu Mar 31 15:36:39 2016 +0000
Revision:
5:c34ebc7f650c
Parent:
4:faf802b4af85 
Some cleanup

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bhepp 1:19b5bef7ecf4 1 // Adapted from Matthias Grob & Manuel Stalder - ETH Zürich - 2015
bhepp 2:12a2907957b8 2
bhepp 0:2c8820705cdd 3 #ifndef DW1000_H
bhepp 0:2c8820705cdd 4 #define DW1000_H
bhepp 0:2c8820705cdd 5
bhepp 0:2c8820705cdd 6 #include "mbed.h"
bhepp 0:2c8820705cdd 7
bhepp 0:2c8820705cdd 8 // register addresses
bhepp 0:2c8820705cdd 9 // Mnemonic Address Bytes Description
bhepp 0:2c8820705cdd 10 #define DW1000_DEV_ID 0x00 // 4 Device Identifier – includes device type and revision information
bhepp 0:2c8820705cdd 11 #define DW1000_EUI 0x01 // 8 Extended Unique Identifier
bhepp 0:2c8820705cdd 12 #define DW1000_PANADR 0x03 // 4 PAN Identifier and Short Address
bhepp 0:2c8820705cdd 13 #define DW1000_SYS_CFG 0x04 // 4 System Configuration bitmap
bhepp 0:2c8820705cdd 14 #define DW1000_SYS_TIME 0x06 // 5 System Time Counter (40-bit)
bhepp 0:2c8820705cdd 15 #define DW1000_TX_FCTRL 0x08 // 5 Transmit Frame Control
bhepp 0:2c8820705cdd 16 #define DW1000_TX_BUFFER 0x09 // 1024 Transmit Data Buffer
bhepp 0:2c8820705cdd 17 #define DW1000_DX_TIME 0x0A // 5 Delayed Send or Receive Time (40-bit)
bhepp 0:2c8820705cdd 18 #define DW1000_RX_FWTO 0x0C // 2 Receive Frame Wait Timeout Period
bhepp 0:2c8820705cdd 19 #define DW1000_SYS_CTRL 0x0D // 4 System Control Register
bhepp 0:2c8820705cdd 20 #define DW1000_SYS_MASK 0x0E // 4 System Event Mask Register
bhepp 0:2c8820705cdd 21 #define DW1000_SYS_STATUS 0x0F // 5 System Event Status Register
bhepp 0:2c8820705cdd 22 #define DW1000_RX_FINFO 0x10 // 4 RX Frame Information (in double buffer set)
bhepp 0:2c8820705cdd 23 #define DW1000_RX_BUFFER 0x11 // 1024 Receive Data Buffer (in double buffer set)
bhepp 0:2c8820705cdd 24 #define DW1000_RX_FQUAL 0x12 // 8 Rx Frame Quality information (in double buffer set)
bhepp 0:2c8820705cdd 25 #define DW1000_RX_TTCKI 0x13 // 4 Receiver Time Tracking Interval (in double buffer set)
bhepp 0:2c8820705cdd 26 #define DW1000_RX_TTCKO 0x14 // 5 Receiver Time Tracking Offset (in double buffer set)
bhepp 0:2c8820705cdd 27 #define DW1000_RX_TIME 0x15 // 14 Receive Message Time of Arrival (in double buffer set)
bhepp 0:2c8820705cdd 28 #define DW1000_TX_TIME 0x17 // 10 Transmit Message Time of Sending (in double buffer set)
bhepp 0:2c8820705cdd 29 #define DW1000_TX_ANTD 0x18 // 2 16-bit Delay from Transmit to Antenna
bhepp 0:2c8820705cdd 30 #define DW1000_SYS_STATE 0x19 // 5 System State information
bhepp 0:2c8820705cdd 31 #define DW1000_ACK_RESP_T 0x1A // 4 Acknowledgement Time and Response Time
bhepp 0:2c8820705cdd 32 #define DW1000_RX_SNIFF 0x1D // 4 Pulsed Preamble Reception Configuration
bhepp 0:2c8820705cdd 33 #define DW1000_TX_POWER 0x1E // 4 TX Power Control
bhepp 0:2c8820705cdd 34 #define DW1000_CHAN_CTRL 0x1F // 4 Channel Control
bhepp 0:2c8820705cdd 35 #define DW1000_USR_SFD 0x21 // 41 User-specified short/long TX/RX SFD sequences
bhepp 0:2c8820705cdd 36 #define DW1000_AGC_CTRL 0x23 // 32 Automatic Gain Control configuration
bhepp 0:2c8820705cdd 37 #define DW1000_EXT_SYNC 0x24 // 12 External synchronisation control.
bhepp 0:2c8820705cdd 38 #define DW1000_ACC_MEM 0x25 // 4064 Read access to accumulator data
bhepp 0:2c8820705cdd 39 #define DW1000_GPIO_CTRL 0x26 // 44 Peripheral register bus 1 access - GPIO control
bhepp 0:2c8820705cdd 40 #define DW1000_DRX_CONF 0x27 // 44 Digital Receiver configuration
bhepp 0:2c8820705cdd 41 #define DW1000_RF_CONF 0x28 // 58 Analog RF Configuration
bhepp 0:2c8820705cdd 42 #define DW1000_TX_CAL 0x2A // 52 Transmitter calibration block
bhepp 0:2c8820705cdd 43 #define DW1000_FS_CTRL 0x2B // 21 Frequency synthesiser control block
bhepp 0:2c8820705cdd 44 #define DW1000_AON 0x2C // 12 Always-On register set
bhepp 0:2c8820705cdd 45 #define DW1000_OTP_IF 0x2D // 18 One Time Programmable Memory Interface
bhepp 0:2c8820705cdd 46 #define DW1000_LDE_CTRL 0x2E // - Leading edge detection control block
bhepp 0:2c8820705cdd 47 #define DW1000_DIG_DIAG 0x2F // 41 Digital Diagnostics Interface
bhepp 0:2c8820705cdd 48 #define DW1000_PMSC 0x36 // 48 Power Management System Control Block
bhepp 0:2c8820705cdd 49
bhepp 0:2c8820705cdd 50 #define DW1000_WRITE_FLAG 0x80 // First Bit of the address has to be 1 to indicate we want to write
bhepp 0:2c8820705cdd 51 #define DW1000_SUBADDRESS_FLAG 0x40 // if we have a sub address second Bit has to be 1
bhepp 0:2c8820705cdd 52 #define DW1000_2_SUBADDRESS_FLAG 0x80 // if we have a long sub adress (more than 7 Bit) we set this Bit in the first part
bhepp 0:2c8820705cdd 53
bhepp 2:12a2907957b8 54 class DW1000
bhepp 2:12a2907957b8 55 {
bhepp 2:12a2907957b8 56 public:
bhepp 2:12a2907957b8 57 const static float TIMEUNITS_TO_US = (1/(128*499.2f)); // conversion between the decawave timeunits (ca 15.65ps) to microseconds.
bhepp 2:12a2907957b8 58 const static float US_TO_TIMEUNITS = (128*499.2f); // conversion between microseconds to the decawave timeunits (ca 15.65ps).
bhepp 2:12a2907957b8 59 const static uint64_t CONST_2POWER40 = 1099511627776; // Time register in DW1000 is 40 bit so this is needed to detect overflows.
bhepp 2:12a2907957b8 60
bhepp 5:c34ebc7f650c 61 DW1000(SPI& spi, InterruptIn* irq, PinName CS, PinName RESET = NC); // constructor, uses SPI class
bhepp 0:2c8820705cdd 62
bhepp 0:2c8820705cdd 63 void setCallbacks(void (*callbackRX)(void), void (*callbackTX)(void)); // setter for callback functions, automatically enables interrupt, if NULL is passed the coresponding interrupt gets disabled
bhepp 0:2c8820705cdd 64 template<typename T>
bhepp 2:12a2907957b8 65 void setCallbacks(T* tptr, void (T::*mptrRX)(void), void (T::*mptrTX)(void))
bhepp 2:12a2907957b8 66 { // overloaded setter to treat member function pointers of objects
bhepp 0:2c8820705cdd 67 callbackRX.attach(tptr, mptrRX); // possible client code: dw.setCallbacks(this, &A::callbackRX, &A::callbackTX);
bhepp 0:2c8820705cdd 68 callbackTX.attach(tptr, mptrTX); // concept seen in line 100 of http://developer.mbed.org/users/mbed_official/code/mbed/docs/4fc01daae5a5/InterruptIn_8h_source.html
bhepp 0:2c8820705cdd 69 setInterrupt(true,true);
bhepp 0:2c8820705cdd 70 }
bhepp 0:2c8820705cdd 71
bhepp 0:2c8820705cdd 72 // Device API
bhepp 0:2c8820705cdd 73 uint32_t getDeviceID(); // gets the Device ID which should be 0xDECA0130 (good for testing SPI!)
bhepp 0:2c8820705cdd 74 uint64_t getEUI(); // gets 64 bit Extended Unique Identifier according to IEEE standard
bhepp 0:2c8820705cdd 75 void setEUI(uint64_t EUI); // sets 64 bit Extended Unique Identifier according to IEEE standard
bhepp 0:2c8820705cdd 76 float getVoltage(); // gets the current chip voltage measurement form the A/D converter
bhepp 0:2c8820705cdd 77 uint64_t getStatus(); // get the 40 bit device status
bhepp 4:faf802b4af85 78 bool hasTransmissionStarted(); // check if frame transmission has started
bhepp 4:faf802b4af85 79 bool hasSentPreamble(); // check if preamble has been sent
bhepp 4:faf802b4af85 80 bool hasSentPHYHeader(); // check if PHY header has been sent
bhepp 4:faf802b4af85 81 bool hasSentFrame(); // check if frame has been sent completely
bhepp 0:2c8820705cdd 82 bool hasReceivedFrame();
bhepp 0:2c8820705cdd 83 void clearReceivedFlag();
bhepp 0:2c8820705cdd 84 void clearSentFlag();
bhepp 2:12a2907957b8 85 uint64_t getSYSTimestamp();
bhepp 0:2c8820705cdd 86 uint64_t getRXTimestamp();
bhepp 0:2c8820705cdd 87 uint64_t getTXTimestamp();
bhepp 2:12a2907957b8 88 float getSYSTimestampUS();
bhepp 2:12a2907957b8 89 float getRXTimestampUS();
bhepp 2:12a2907957b8 90 float getTXTimestampUS();
bhepp 0:2c8820705cdd 91
bhepp 2:12a2907957b8 92 uint16_t getStdNoise();
bhepp 2:12a2907957b8 93 uint16_t getPACC();
bhepp 2:12a2907957b8 94 uint16_t getFPINDEX();
bhepp 2:12a2907957b8 95 uint16_t getFPAMPL1();
bhepp 2:12a2907957b8 96 uint16_t getFPAMPL2();
bhepp 2:12a2907957b8 97 uint16_t getFPAMPL3();
bhepp 2:12a2907957b8 98 uint16_t getCIRPWR();
bhepp 2:12a2907957b8 99 uint8_t getPRF();
bhepp 0:2c8820705cdd 100
bhepp 0:2c8820705cdd 101 void sendString(char* message); // to send String with arbitrary length
bhepp 0:2c8820705cdd 102 void receiveString(char* message); // to receive char string (length of the buffer must be 1021 to be safe)
bhepp 0:2c8820705cdd 103 void sendFrame(uint8_t* message, uint16_t length); // send a raw frame (length in bytes)
bhepp 0:2c8820705cdd 104 void sendDelayedFrame(uint8_t* message, uint16_t length, uint64_t TxTimestamp);
bhepp 5:c34ebc7f650c 105 uint16_t getFramelength(); // to get the framelength of the received frame from the PHY header
bhepp 0:2c8820705cdd 106 void startRX(); // start listening for frames
bhepp 0:2c8820705cdd 107 void stopTRX(); // disable tranceiver go back to idle mode
bhepp 0:2c8820705cdd 108
bhepp 5:c34ebc7f650c 109 static void hardwareReset(PinName reset_pin);
bhepp 5:c34ebc7f650c 110 static void hardwareReset(DigitalInOut& reset_pin);
bhepp 5:c34ebc7f650c 111 void softwareReset();
bhepp 5:c34ebc7f650c 112
bhepp 0:2c8820705cdd 113 uint8_t readRegister8(uint8_t reg, uint16_t subaddress); // expressive methods to read or write the number of bits written in the name
bhepp 0:2c8820705cdd 114 uint16_t readRegister16(uint8_t reg, uint16_t subaddress);
bhepp 0:2c8820705cdd 115 uint32_t readRegister32(uint8_t reg, uint16_t subaddress);
bhepp 0:2c8820705cdd 116 uint64_t readRegister40(uint8_t reg, uint16_t subaddress);
bhepp 0:2c8820705cdd 117 void writeRegister8(uint8_t reg, uint16_t subaddress, uint8_t buffer);
bhepp 0:2c8820705cdd 118 void writeRegister16(uint8_t reg, uint16_t subaddress, uint16_t buffer);
bhepp 0:2c8820705cdd 119 void writeRegister32(uint8_t reg, uint16_t subaddress, uint32_t buffer);
bhepp 0:2c8820705cdd 120 void writeRegister40(uint8_t reg, uint16_t subaddress, uint64_t buffer);
bhepp 0:2c8820705cdd 121 void readRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length); // reads the selected part of a slave register into the buffer memory
bhepp 0:2c8820705cdd 122 void writeRegister(uint8_t reg, uint16_t subaddress, uint8_t *buffer, int length); // writes the buffer memory to the selected slave register
bhepp 5:c34ebc7f650c 123
bhepp 5:c34ebc7f650c 124 private:
bhepp 5:c34ebc7f650c 125 void loadLDE(); // load the leading edge detection algorithm to RAM, [IMPORTANT because receiving malfunction may occur] see User Manual LDELOAD on p22 & p158
bhepp 5:c34ebc7f650c 126 void resetRX(); // soft reset only the tranciever part of DW1000
bhepp 5:c34ebc7f650c 127 void resetAll(); // soft reset the entire DW1000 (some registers stay as they were see User Manual)
bhepp 5:c34ebc7f650c 128
bhepp 5:c34ebc7f650c 129 // Interrupt
bhepp 5:c34ebc7f650c 130 InterruptIn* irq;
bhepp 5:c34ebc7f650c 131 FunctionPointer callbackRX; // function pointer to callback which is called when successfull RX took place
bhepp 5:c34ebc7f650c 132 FunctionPointer callbackTX; // function pointer to callback which is called when successfull TX took place
bhepp 5:c34ebc7f650c 133 void setInterrupt(bool RX, bool TX); // set Interrupt for received a good frame (CRC ok) or transmission done
bhepp 5:c34ebc7f650c 134 void ISR(); // interrupt handling method (also calls according callback methods)
bhepp 5:c34ebc7f650c 135
bhepp 5:c34ebc7f650c 136 // SPI Inteface
bhepp 5:c34ebc7f650c 137 SPI& spi; // SPI Bus
bhepp 5:c34ebc7f650c 138 DigitalOut cs; // Slave selector for SPI-Bus (here explicitly needed to start and end SPI transactions also usable to wake up DW1000)
bhepp 5:c34ebc7f650c 139 DigitalInOut reset;
bhepp 5:c34ebc7f650c 140
bhepp 0:2c8820705cdd 141 void setupTransaction(uint8_t reg, uint16_t subaddress, bool write); // sets up an SPI read or write transaction with correct register address and offset
bhepp 0:2c8820705cdd 142 void select(); // selects the only slave for a transaction
bhepp 0:2c8820705cdd 143 void deselect();
bhepp 0:2c8820705cdd 144 };
bhepp 0:2c8820705cdd 145
bhepp 1:19b5bef7ecf4 146 #endif