mbed-dev-f303 - mbed library sources. Supersedes mbed-src.

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mbed library sources. Supersedes mbed-src.

Dependents: Hobbyking_Cheetah_Compact Hobbyking_Cheetah_Compact_DRV8323_14bit Hobbyking_Cheetah_Compact_DRV8323_V51_201907 HKC_MiniCheetah ... more

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cmsis/core_sc300.h@181:36facd806e4a, 2018-07-30 (annotated)

Committer:: benkatz
Date:: Mon Jul 30 20:31:44 2018 +0000
Revision:: 181:36facd806e4a
Parent:: 167:e84263d55307

going on the robot.  fixed a dumb bug in float_to_uint

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	25:ac5b0a371348	1	/************************************************************************//
mbed_official	25:ac5b0a371348	2	* @file core_sc300.h
mbed_official	25:ac5b0a371348	3	* @brief CMSIS SC300 Core Peripheral Access Layer Header File
AnnaBridge	167:e84263d55307	4	* @version V5.0.2
AnnaBridge	167:e84263d55307	5	* @date 13. February 2017
AnnaBridge	167:e84263d55307	6	******************************************************************************/
AnnaBridge	167:e84263d55307	7	/*
AnnaBridge	167:e84263d55307	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	167:e84263d55307	9	*
AnnaBridge	167:e84263d55307	10	* SPDX-License-Identifier: Apache-2.0
mbed_official	25:ac5b0a371348	11	*
AnnaBridge	167:e84263d55307	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	167:e84263d55307	13	* not use this file except in compliance with the License.
AnnaBridge	167:e84263d55307	14	* You may obtain a copy of the License at
AnnaBridge	167:e84263d55307	15	*
AnnaBridge	167:e84263d55307	16	* www.apache.org/licenses/LICENSE-2.0
mbed_official	25:ac5b0a371348	17	*
AnnaBridge	167:e84263d55307	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	167:e84263d55307	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	167:e84263d55307	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	167:e84263d55307	21	* See the License for the specific language governing permissions and
AnnaBridge	167:e84263d55307	22	* limitations under the License.
AnnaBridge	167:e84263d55307	23	*/
mbed_official	25:ac5b0a371348	24
AnnaBridge	167:e84263d55307	25	#if defined ( __ICCARM__ )
AnnaBridge	167:e84263d55307	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	167:e84263d55307	27	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	167:e84263d55307	28	#pragma clang system_header /* treat file as system include file */
mbed_official	25:ac5b0a371348	29	#endif
mbed_official	25:ac5b0a371348	30
mbed_official	25:ac5b0a371348	31	#ifndef __CORE_SC300_H_GENERIC
mbed_official	25:ac5b0a371348	32	#define __CORE_SC300_H_GENERIC
mbed_official	25:ac5b0a371348	33
AnnaBridge	167:e84263d55307	34	#include <stdint.h>
AnnaBridge	167:e84263d55307	35
mbed_official	25:ac5b0a371348	36	#ifdef __cplusplus
mbed_official	25:ac5b0a371348	37	extern "C" {
mbed_official	25:ac5b0a371348	38	#endif
mbed_official	25:ac5b0a371348	39
AnnaBridge	167:e84263d55307	40	/**
AnnaBridge	167:e84263d55307	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbed_official	25:ac5b0a371348	42	CMSIS violates the following MISRA-C:2004 rules:
mbed_official	25:ac5b0a371348	43
mbed_official	25:ac5b0a371348	44	\li Required Rule 8.5, object/function definition in header file.<br>
mbed_official	25:ac5b0a371348	45	Function definitions in header files are used to allow 'inlining'.
mbed_official	25:ac5b0a371348	46
mbed_official	25:ac5b0a371348	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbed_official	25:ac5b0a371348	48	Unions are used for effective representation of core registers.
mbed_official	25:ac5b0a371348	49
mbed_official	25:ac5b0a371348	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
mbed_official	25:ac5b0a371348	51	Function-like macros are used to allow more efficient code.
mbed_official	25:ac5b0a371348	52	*/
mbed_official	25:ac5b0a371348	53
mbed_official	25:ac5b0a371348	54
mbed_official	25:ac5b0a371348	55	/*******************************************************************************
mbed_official	25:ac5b0a371348	56	* CMSIS definitions
mbed_official	25:ac5b0a371348	57	******************************************************************************/
AnnaBridge	167:e84263d55307	58	/**
AnnaBridge	167:e84263d55307	59	\ingroup SC3000
mbed_official	25:ac5b0a371348	60	@{
mbed_official	25:ac5b0a371348	61	*/
mbed_official	25:ac5b0a371348	62
mbed_official	25:ac5b0a371348	63	/* CMSIS SC300 definitions */
AnnaBridge	167:e84263d55307	64	#define __SC300_CMSIS_VERSION_MAIN ( 5U) /!< [31:16] CMSIS HAL main version /
AnnaBridge	167:e84263d55307	65	#define __SC300_CMSIS_VERSION_SUB ( 0U) /!< [15:0] CMSIS HAL sub version /
AnnaBridge	167:e84263d55307	66	#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	167:e84263d55307	67	__SC300_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
mbed_official	25:ac5b0a371348	68
AnnaBridge	167:e84263d55307	69	#define __CORTEX_SC (300U) /!< Cortex secure core /
mbed_official	25:ac5b0a371348	70
mbed_official	25:ac5b0a371348	71	/** __FPU_USED indicates whether an FPU is used or not.
mbed_official	25:ac5b0a371348	72	This core does not support an FPU at all
mbed_official	25:ac5b0a371348	73	*/
AnnaBridge	167:e84263d55307	74	#define __FPU_USED 0U
mbed_official	25:ac5b0a371348	75
mbed_official	25:ac5b0a371348	76	#if defined ( __CC_ARM )
mbed_official	25:ac5b0a371348	77	#if defined __TARGET_FPU_VFP
AnnaBridge	167:e84263d55307	78	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	79	#endif
AnnaBridge	167:e84263d55307	80
AnnaBridge	167:e84263d55307	81	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge	167:e84263d55307	82	#if defined __ARM_PCS_VFP
AnnaBridge	167:e84263d55307	83	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	25:ac5b0a371348	84	#endif
mbed_official	25:ac5b0a371348	85
mbed_official	25:ac5b0a371348	86	#elif defined ( __GNUC__ )
mbed_official	25:ac5b0a371348	87	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	167:e84263d55307	88	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	25:ac5b0a371348	89	#endif
mbed_official	25:ac5b0a371348	90
mbed_official	25:ac5b0a371348	91	#elif defined ( __ICCARM__ )
mbed_official	25:ac5b0a371348	92	#if defined __ARMVFP__
AnnaBridge	167:e84263d55307	93	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	25:ac5b0a371348	94	#endif
mbed_official	25:ac5b0a371348	95
AnnaBridge	167:e84263d55307	96	#elif defined ( __TI_ARM__ )
AnnaBridge	167:e84263d55307	97	#if defined __TI_VFP_SUPPORT__
AnnaBridge	167:e84263d55307	98	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	25:ac5b0a371348	99	#endif
mbed_official	25:ac5b0a371348	100
mbed_official	25:ac5b0a371348	101	#elif defined ( __TASKING__ )
mbed_official	25:ac5b0a371348	102	#if defined __FPU_VFP__
mbed_official	25:ac5b0a371348	103	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	25:ac5b0a371348	104	#endif
mbed_official	25:ac5b0a371348	105
AnnaBridge	167:e84263d55307	106	#elif defined ( __CSMC__ )
AnnaBridge	167:e84263d55307	107	#if ( __CSMC__ & 0x400U)
mbed_official	25:ac5b0a371348	108	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official	25:ac5b0a371348	109	#endif
AnnaBridge	167:e84263d55307	110
mbed_official	25:ac5b0a371348	111	#endif
mbed_official	25:ac5b0a371348	112
AnnaBridge	167:e84263d55307	113	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	167:e84263d55307	114
mbed_official	25:ac5b0a371348	115
mbed_official	25:ac5b0a371348	116	#ifdef __cplusplus
mbed_official	25:ac5b0a371348	117	}
mbed_official	25:ac5b0a371348	118	#endif
mbed_official	25:ac5b0a371348	119
mbed_official	25:ac5b0a371348	120	#endif /* __CORE_SC300_H_GENERIC */
mbed_official	25:ac5b0a371348	121
mbed_official	25:ac5b0a371348	122	#ifndef __CMSIS_GENERIC
mbed_official	25:ac5b0a371348	123
mbed_official	25:ac5b0a371348	124	#ifndef __CORE_SC300_H_DEPENDANT
mbed_official	25:ac5b0a371348	125	#define __CORE_SC300_H_DEPENDANT
mbed_official	25:ac5b0a371348	126
mbed_official	25:ac5b0a371348	127	#ifdef __cplusplus
mbed_official	25:ac5b0a371348	128	extern "C" {
mbed_official	25:ac5b0a371348	129	#endif
mbed_official	25:ac5b0a371348	130
mbed_official	25:ac5b0a371348	131	/* check device defines and use defaults */
mbed_official	25:ac5b0a371348	132	#if defined __CHECK_DEVICE_DEFINES
mbed_official	25:ac5b0a371348	133	#ifndef __SC300_REV
AnnaBridge	167:e84263d55307	134	#define __SC300_REV 0x0000U
mbed_official	25:ac5b0a371348	135	#warning "__SC300_REV not defined in device header file; using default!"
mbed_official	25:ac5b0a371348	136	#endif
mbed_official	25:ac5b0a371348	137
mbed_official	25:ac5b0a371348	138	#ifndef __MPU_PRESENT
AnnaBridge	167:e84263d55307	139	#define __MPU_PRESENT 0U
mbed_official	25:ac5b0a371348	140	#warning "__MPU_PRESENT not defined in device header file; using default!"
mbed_official	25:ac5b0a371348	141	#endif
mbed_official	25:ac5b0a371348	142
mbed_official	25:ac5b0a371348	143	#ifndef __NVIC_PRIO_BITS
AnnaBridge	167:e84263d55307	144	#define __NVIC_PRIO_BITS 3U
mbed_official	25:ac5b0a371348	145	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbed_official	25:ac5b0a371348	146	#endif
mbed_official	25:ac5b0a371348	147
mbed_official	25:ac5b0a371348	148	#ifndef __Vendor_SysTickConfig
AnnaBridge	167:e84263d55307	149	#define __Vendor_SysTickConfig 0U
mbed_official	25:ac5b0a371348	150	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbed_official	25:ac5b0a371348	151	#endif
mbed_official	25:ac5b0a371348	152	#endif
mbed_official	25:ac5b0a371348	153
mbed_official	25:ac5b0a371348	154	/* IO definitions (access restrictions to peripheral registers) */
mbed_official	25:ac5b0a371348	155	/**
mbed_official	25:ac5b0a371348	156	\defgroup CMSIS_glob_defs CMSIS Global Defines
mbed_official	25:ac5b0a371348	157
mbed_official	25:ac5b0a371348	158	<strong>IO Type Qualifiers</strong> are used
mbed_official	25:ac5b0a371348	159	\li to specify the access to peripheral variables.
mbed_official	25:ac5b0a371348	160	\li for automatic generation of peripheral register debug information.
mbed_official	25:ac5b0a371348	161	*/
mbed_official	25:ac5b0a371348	162	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	163	#define __I volatile /!< Defines 'read only' permissions /
mbed_official	25:ac5b0a371348	164	#else
AnnaBridge	167:e84263d55307	165	#define __I volatile const /!< Defines 'read only' permissions /
mbed_official	25:ac5b0a371348	166	#endif
AnnaBridge	167:e84263d55307	167	#define __O volatile /!< Defines 'write only' permissions /
AnnaBridge	167:e84263d55307	168	#define __IO volatile /!< Defines 'read / write' permissions /
AnnaBridge	167:e84263d55307	169
AnnaBridge	167:e84263d55307	170	/* following defines should be used for structure members */
AnnaBridge	167:e84263d55307	171	#define __IM volatile const /! Defines 'read only' structure member permissions /
AnnaBridge	167:e84263d55307	172	#define __OM volatile /! Defines 'write only' structure member permissions /
AnnaBridge	167:e84263d55307	173	#define __IOM volatile /! Defines 'read / write' structure member permissions /
mbed_official	25:ac5b0a371348	174
mbed_official	25:ac5b0a371348	175	/@} end of group SC300 /
mbed_official	25:ac5b0a371348	176
mbed_official	25:ac5b0a371348	177
mbed_official	25:ac5b0a371348	178
mbed_official	25:ac5b0a371348	179	/*******************************************************************************
mbed_official	25:ac5b0a371348	180	* Register Abstraction
mbed_official	25:ac5b0a371348	181	Core Register contain:
mbed_official	25:ac5b0a371348	182	- Core Register
mbed_official	25:ac5b0a371348	183	- Core NVIC Register
mbed_official	25:ac5b0a371348	184	- Core SCB Register
mbed_official	25:ac5b0a371348	185	- Core SysTick Register
mbed_official	25:ac5b0a371348	186	- Core Debug Register
mbed_official	25:ac5b0a371348	187	- Core MPU Register
mbed_official	25:ac5b0a371348	188	******************************************************************************/
AnnaBridge	167:e84263d55307	189	/**
AnnaBridge	167:e84263d55307	190	\defgroup CMSIS_core_register Defines and Type Definitions
AnnaBridge	167:e84263d55307	191	\brief Type definitions and defines for Cortex-M processor based devices.
mbed_official	25:ac5b0a371348	192	*/
mbed_official	25:ac5b0a371348	193
AnnaBridge	167:e84263d55307	194	/**
AnnaBridge	167:e84263d55307	195	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	196	\defgroup CMSIS_CORE Status and Control Registers
AnnaBridge	167:e84263d55307	197	\brief Core Register type definitions.
mbed_official	25:ac5b0a371348	198	@{
mbed_official	25:ac5b0a371348	199	*/
mbed_official	25:ac5b0a371348	200
AnnaBridge	167:e84263d55307	201	/**
AnnaBridge	167:e84263d55307	202	\brief Union type to access the Application Program Status Register (APSR).
mbed_official	25:ac5b0a371348	203	*/
mbed_official	25:ac5b0a371348	204	typedef union
mbed_official	25:ac5b0a371348	205	{
mbed_official	25:ac5b0a371348	206	struct
mbed_official	25:ac5b0a371348	207	{
AnnaBridge	167:e84263d55307	208	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
AnnaBridge	167:e84263d55307	209	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	167:e84263d55307	210	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:e84263d55307	211	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:e84263d55307	212	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:e84263d55307	213	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:e84263d55307	214	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	215	uint32_t w; /!< Type used for word access /
mbed_official	25:ac5b0a371348	216	} APSR_Type;
mbed_official	25:ac5b0a371348	217
mbed_official	25:ac5b0a371348	218	/* APSR Register Definitions */
AnnaBridge	167:e84263d55307	219	#define APSR_N_Pos 31U /!< APSR: N Position /
mbed_official	25:ac5b0a371348	220	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
mbed_official	25:ac5b0a371348	221
AnnaBridge	167:e84263d55307	222	#define APSR_Z_Pos 30U /!< APSR: Z Position /
mbed_official	25:ac5b0a371348	223	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
mbed_official	25:ac5b0a371348	224
AnnaBridge	167:e84263d55307	225	#define APSR_C_Pos 29U /!< APSR: C Position /
mbed_official	25:ac5b0a371348	226	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
mbed_official	25:ac5b0a371348	227
AnnaBridge	167:e84263d55307	228	#define APSR_V_Pos 28U /!< APSR: V Position /
mbed_official	25:ac5b0a371348	229	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
mbed_official	25:ac5b0a371348	230
AnnaBridge	167:e84263d55307	231	#define APSR_Q_Pos 27U /!< APSR: Q Position /
mbed_official	25:ac5b0a371348	232	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
mbed_official	25:ac5b0a371348	233
mbed_official	25:ac5b0a371348	234
AnnaBridge	167:e84263d55307	235	/**
AnnaBridge	167:e84263d55307	236	\brief Union type to access the Interrupt Program Status Register (IPSR).
mbed_official	25:ac5b0a371348	237	*/
mbed_official	25:ac5b0a371348	238	typedef union
mbed_official	25:ac5b0a371348	239	{
mbed_official	25:ac5b0a371348	240	struct
mbed_official	25:ac5b0a371348	241	{
AnnaBridge	167:e84263d55307	242	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:e84263d55307	243	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
AnnaBridge	167:e84263d55307	244	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	245	uint32_t w; /!< Type used for word access /
mbed_official	25:ac5b0a371348	246	} IPSR_Type;
mbed_official	25:ac5b0a371348	247
mbed_official	25:ac5b0a371348	248	/* IPSR Register Definitions */
AnnaBridge	167:e84263d55307	249	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
mbed_official	25:ac5b0a371348	250	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
mbed_official	25:ac5b0a371348	251
mbed_official	25:ac5b0a371348	252
AnnaBridge	167:e84263d55307	253	/**
AnnaBridge	167:e84263d55307	254	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbed_official	25:ac5b0a371348	255	*/
mbed_official	25:ac5b0a371348	256	typedef union
mbed_official	25:ac5b0a371348	257	{
mbed_official	25:ac5b0a371348	258	struct
mbed_official	25:ac5b0a371348	259	{
AnnaBridge	167:e84263d55307	260	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
AnnaBridge	167:e84263d55307	261	uint32_t _reserved0:1; /!< bit: 9 Reserved /
AnnaBridge	167:e84263d55307	262	uint32_t ICI_IT_1:6; /!< bit: 10..15 ICI/IT part 1 /
AnnaBridge	167:e84263d55307	263	uint32_t _reserved1:8; /!< bit: 16..23 Reserved /
AnnaBridge	167:e84263d55307	264	uint32_t T:1; /!< bit: 24 Thumb bit /
AnnaBridge	167:e84263d55307	265	uint32_t ICI_IT_2:2; /!< bit: 25..26 ICI/IT part 2 /
AnnaBridge	167:e84263d55307	266	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
AnnaBridge	167:e84263d55307	267	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
AnnaBridge	167:e84263d55307	268	uint32_t C:1; /!< bit: 29 Carry condition code flag /
AnnaBridge	167:e84263d55307	269	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
AnnaBridge	167:e84263d55307	270	uint32_t N:1; /!< bit: 31 Negative condition code flag /
AnnaBridge	167:e84263d55307	271	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	272	uint32_t w; /!< Type used for word access /
mbed_official	25:ac5b0a371348	273	} xPSR_Type;
mbed_official	25:ac5b0a371348	274
mbed_official	25:ac5b0a371348	275	/* xPSR Register Definitions */
AnnaBridge	167:e84263d55307	276	#define xPSR_N_Pos 31U /!< xPSR: N Position /
mbed_official	25:ac5b0a371348	277	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
mbed_official	25:ac5b0a371348	278
AnnaBridge	167:e84263d55307	279	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
mbed_official	25:ac5b0a371348	280	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
mbed_official	25:ac5b0a371348	281
AnnaBridge	167:e84263d55307	282	#define xPSR_C_Pos 29U /!< xPSR: C Position /
mbed_official	25:ac5b0a371348	283	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
mbed_official	25:ac5b0a371348	284
AnnaBridge	167:e84263d55307	285	#define xPSR_V_Pos 28U /!< xPSR: V Position /
mbed_official	25:ac5b0a371348	286	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
mbed_official	25:ac5b0a371348	287
AnnaBridge	167:e84263d55307	288	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
mbed_official	25:ac5b0a371348	289	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
mbed_official	25:ac5b0a371348	290
AnnaBridge	167:e84263d55307	291	#define xPSR_ICI_IT_2_Pos 25U /!< xPSR: ICI/IT part 2 Position /
AnnaBridge	167:e84263d55307	292	#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /!< xPSR: ICI/IT part 2 Mask /
mbed_official	25:ac5b0a371348	293
AnnaBridge	167:e84263d55307	294	#define xPSR_T_Pos 24U /!< xPSR: T Position /
mbed_official	25:ac5b0a371348	295	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
mbed_official	25:ac5b0a371348	296
AnnaBridge	167:e84263d55307	297	#define xPSR_ICI_IT_1_Pos 10U /!< xPSR: ICI/IT part 1 Position /
AnnaBridge	167:e84263d55307	298	#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /!< xPSR: ICI/IT part 1 Mask /
AnnaBridge	167:e84263d55307	299
AnnaBridge	167:e84263d55307	300	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
mbed_official	25:ac5b0a371348	301	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
mbed_official	25:ac5b0a371348	302
mbed_official	25:ac5b0a371348	303
AnnaBridge	167:e84263d55307	304	/**
AnnaBridge	167:e84263d55307	305	\brief Union type to access the Control Registers (CONTROL).
mbed_official	25:ac5b0a371348	306	*/
mbed_official	25:ac5b0a371348	307	typedef union
mbed_official	25:ac5b0a371348	308	{
mbed_official	25:ac5b0a371348	309	struct
mbed_official	25:ac5b0a371348	310	{
mbed_official	25:ac5b0a371348	311	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
AnnaBridge	167:e84263d55307	312	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
AnnaBridge	167:e84263d55307	313	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
AnnaBridge	167:e84263d55307	314	} b; /!< Structure used for bit access /
AnnaBridge	167:e84263d55307	315	uint32_t w; /!< Type used for word access /
mbed_official	25:ac5b0a371348	316	} CONTROL_Type;
mbed_official	25:ac5b0a371348	317
mbed_official	25:ac5b0a371348	318	/* CONTROL Register Definitions */
AnnaBridge	167:e84263d55307	319	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
mbed_official	25:ac5b0a371348	320	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
mbed_official	25:ac5b0a371348	321
AnnaBridge	167:e84263d55307	322	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
mbed_official	25:ac5b0a371348	323	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
mbed_official	25:ac5b0a371348	324
mbed_official	25:ac5b0a371348	325	/@} end of group CMSIS_CORE /
mbed_official	25:ac5b0a371348	326
mbed_official	25:ac5b0a371348	327
AnnaBridge	167:e84263d55307	328	/**
AnnaBridge	167:e84263d55307	329	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	330	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
AnnaBridge	167:e84263d55307	331	\brief Type definitions for the NVIC Registers
mbed_official	25:ac5b0a371348	332	@{
mbed_official	25:ac5b0a371348	333	*/
mbed_official	25:ac5b0a371348	334
AnnaBridge	167:e84263d55307	335	/**
AnnaBridge	167:e84263d55307	336	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbed_official	25:ac5b0a371348	337	*/
mbed_official	25:ac5b0a371348	338	typedef struct
mbed_official	25:ac5b0a371348	339	{
AnnaBridge	167:e84263d55307	340	__IOM uint32_t ISER[8U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
AnnaBridge	167:e84263d55307	341	uint32_t RESERVED0[24U];
AnnaBridge	167:e84263d55307	342	__IOM uint32_t ICER[8U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
AnnaBridge	167:e84263d55307	343	uint32_t RSERVED1[24U];
AnnaBridge	167:e84263d55307	344	__IOM uint32_t ISPR[8U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
AnnaBridge	167:e84263d55307	345	uint32_t RESERVED2[24U];
AnnaBridge	167:e84263d55307	346	__IOM uint32_t ICPR[8U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
AnnaBridge	167:e84263d55307	347	uint32_t RESERVED3[24U];
AnnaBridge	167:e84263d55307	348	__IOM uint32_t IABR[8U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
AnnaBridge	167:e84263d55307	349	uint32_t RESERVED4[56U];
AnnaBridge	167:e84263d55307	350	__IOM uint8_t IP[240U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
AnnaBridge	167:e84263d55307	351	uint32_t RESERVED5[644U];
AnnaBridge	167:e84263d55307	352	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
mbed_official	25:ac5b0a371348	353	} NVIC_Type;
mbed_official	25:ac5b0a371348	354
mbed_official	25:ac5b0a371348	355	/* Software Triggered Interrupt Register Definitions */
AnnaBridge	167:e84263d55307	356	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
mbed_official	25:ac5b0a371348	357	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
mbed_official	25:ac5b0a371348	358
mbed_official	25:ac5b0a371348	359	/@} end of group CMSIS_NVIC /
mbed_official	25:ac5b0a371348	360
mbed_official	25:ac5b0a371348	361
AnnaBridge	167:e84263d55307	362	/**
AnnaBridge	167:e84263d55307	363	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	364	\defgroup CMSIS_SCB System Control Block (SCB)
AnnaBridge	167:e84263d55307	365	\brief Type definitions for the System Control Block Registers
mbed_official	25:ac5b0a371348	366	@{
mbed_official	25:ac5b0a371348	367	*/
mbed_official	25:ac5b0a371348	368
AnnaBridge	167:e84263d55307	369	/**
AnnaBridge	167:e84263d55307	370	\brief Structure type to access the System Control Block (SCB).
mbed_official	25:ac5b0a371348	371	*/
mbed_official	25:ac5b0a371348	372	typedef struct
mbed_official	25:ac5b0a371348	373	{
AnnaBridge	167:e84263d55307	374	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
AnnaBridge	167:e84263d55307	375	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
AnnaBridge	167:e84263d55307	376	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
AnnaBridge	167:e84263d55307	377	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
AnnaBridge	167:e84263d55307	378	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
AnnaBridge	167:e84263d55307	379	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
AnnaBridge	167:e84263d55307	380	__IOM uint8_t SHP[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
AnnaBridge	167:e84263d55307	381	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
AnnaBridge	167:e84263d55307	382	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
AnnaBridge	167:e84263d55307	383	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
AnnaBridge	167:e84263d55307	384	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
AnnaBridge	167:e84263d55307	385	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
AnnaBridge	167:e84263d55307	386	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
AnnaBridge	167:e84263d55307	387	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
AnnaBridge	167:e84263d55307	388	__IM uint32_t PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
AnnaBridge	167:e84263d55307	389	__IM uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
AnnaBridge	167:e84263d55307	390	__IM uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
AnnaBridge	167:e84263d55307	391	__IM uint32_t MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
AnnaBridge	167:e84263d55307	392	__IM uint32_t ISAR[5U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
AnnaBridge	167:e84263d55307	393	uint32_t RESERVED0[5U];
AnnaBridge	167:e84263d55307	394	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
AnnaBridge	167:e84263d55307	395	uint32_t RESERVED1[129U];
AnnaBridge	167:e84263d55307	396	__IOM uint32_t SFCR; /!< Offset: 0x290 (R/W) Security Features Control Register /
mbed_official	25:ac5b0a371348	397	} SCB_Type;
mbed_official	25:ac5b0a371348	398
mbed_official	25:ac5b0a371348	399	/* SCB CPUID Register Definitions */
AnnaBridge	167:e84263d55307	400	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
mbed_official	25:ac5b0a371348	401	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
mbed_official	25:ac5b0a371348	402
AnnaBridge	167:e84263d55307	403	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
mbed_official	25:ac5b0a371348	404	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
mbed_official	25:ac5b0a371348	405
AnnaBridge	167:e84263d55307	406	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
mbed_official	25:ac5b0a371348	407	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
mbed_official	25:ac5b0a371348	408
AnnaBridge	167:e84263d55307	409	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
mbed_official	25:ac5b0a371348	410	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
mbed_official	25:ac5b0a371348	411
AnnaBridge	167:e84263d55307	412	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
mbed_official	25:ac5b0a371348	413	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
mbed_official	25:ac5b0a371348	414
mbed_official	25:ac5b0a371348	415	/* SCB Interrupt Control State Register Definitions */
AnnaBridge	167:e84263d55307	416	#define SCB_ICSR_NMIPENDSET_Pos 31U /!< SCB ICSR: NMIPENDSET Position /
mbed_official	25:ac5b0a371348	417	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
mbed_official	25:ac5b0a371348	418
AnnaBridge	167:e84263d55307	419	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
mbed_official	25:ac5b0a371348	420	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
mbed_official	25:ac5b0a371348	421
AnnaBridge	167:e84263d55307	422	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
mbed_official	25:ac5b0a371348	423	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
mbed_official	25:ac5b0a371348	424
AnnaBridge	167:e84263d55307	425	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
mbed_official	25:ac5b0a371348	426	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
mbed_official	25:ac5b0a371348	427
AnnaBridge	167:e84263d55307	428	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
mbed_official	25:ac5b0a371348	429	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
mbed_official	25:ac5b0a371348	430
AnnaBridge	167:e84263d55307	431	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
mbed_official	25:ac5b0a371348	432	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
mbed_official	25:ac5b0a371348	433
AnnaBridge	167:e84263d55307	434	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
mbed_official	25:ac5b0a371348	435	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
mbed_official	25:ac5b0a371348	436
AnnaBridge	167:e84263d55307	437	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
mbed_official	25:ac5b0a371348	438	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
mbed_official	25:ac5b0a371348	439
AnnaBridge	167:e84263d55307	440	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
mbed_official	25:ac5b0a371348	441	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
mbed_official	25:ac5b0a371348	442
AnnaBridge	167:e84263d55307	443	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
mbed_official	25:ac5b0a371348	444	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
mbed_official	25:ac5b0a371348	445
mbed_official	25:ac5b0a371348	446	/* SCB Vector Table Offset Register Definitions */
AnnaBridge	167:e84263d55307	447	#define SCB_VTOR_TBLBASE_Pos 29U /!< SCB VTOR: TBLBASE Position /
mbed_official	25:ac5b0a371348	448	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
mbed_official	25:ac5b0a371348	449
AnnaBridge	167:e84263d55307	450	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
mbed_official	25:ac5b0a371348	451	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
mbed_official	25:ac5b0a371348	452
mbed_official	25:ac5b0a371348	453	/* SCB Application Interrupt and Reset Control Register Definitions */
AnnaBridge	167:e84263d55307	454	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
mbed_official	25:ac5b0a371348	455	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
mbed_official	25:ac5b0a371348	456
AnnaBridge	167:e84263d55307	457	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
mbed_official	25:ac5b0a371348	458	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
mbed_official	25:ac5b0a371348	459
AnnaBridge	167:e84263d55307	460	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
mbed_official	25:ac5b0a371348	461	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
mbed_official	25:ac5b0a371348	462
AnnaBridge	167:e84263d55307	463	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
mbed_official	25:ac5b0a371348	464	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
mbed_official	25:ac5b0a371348	465
AnnaBridge	167:e84263d55307	466	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
mbed_official	25:ac5b0a371348	467	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
mbed_official	25:ac5b0a371348	468
AnnaBridge	167:e84263d55307	469	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
mbed_official	25:ac5b0a371348	470	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
mbed_official	25:ac5b0a371348	471
AnnaBridge	167:e84263d55307	472	#define SCB_AIRCR_VECTRESET_Pos 0U /!< SCB AIRCR: VECTRESET Position /
mbed_official	25:ac5b0a371348	473	#define SCB_AIRCR_VECTRESET_Msk (1UL /<< SCB_AIRCR_VECTRESET_Pos/) /!< SCB AIRCR: VECTRESET Mask /
mbed_official	25:ac5b0a371348	474
mbed_official	25:ac5b0a371348	475	/* SCB System Control Register Definitions */
AnnaBridge	167:e84263d55307	476	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
mbed_official	25:ac5b0a371348	477	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
mbed_official	25:ac5b0a371348	478
AnnaBridge	167:e84263d55307	479	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
mbed_official	25:ac5b0a371348	480	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
mbed_official	25:ac5b0a371348	481
AnnaBridge	167:e84263d55307	482	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
mbed_official	25:ac5b0a371348	483	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
mbed_official	25:ac5b0a371348	484
mbed_official	25:ac5b0a371348	485	/* SCB Configuration Control Register Definitions */
AnnaBridge	167:e84263d55307	486	#define SCB_CCR_STKALIGN_Pos 9U /!< SCB CCR: STKALIGN Position /
mbed_official	25:ac5b0a371348	487	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
mbed_official	25:ac5b0a371348	488
AnnaBridge	167:e84263d55307	489	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
mbed_official	25:ac5b0a371348	490	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
mbed_official	25:ac5b0a371348	491
AnnaBridge	167:e84263d55307	492	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
mbed_official	25:ac5b0a371348	493	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
mbed_official	25:ac5b0a371348	494
AnnaBridge	167:e84263d55307	495	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
mbed_official	25:ac5b0a371348	496	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
mbed_official	25:ac5b0a371348	497
AnnaBridge	167:e84263d55307	498	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
mbed_official	25:ac5b0a371348	499	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
mbed_official	25:ac5b0a371348	500
AnnaBridge	167:e84263d55307	501	#define SCB_CCR_NONBASETHRDENA_Pos 0U /!< SCB CCR: NONBASETHRDENA Position /
mbed_official	25:ac5b0a371348	502	#define SCB_CCR_NONBASETHRDENA_Msk (1UL /<< SCB_CCR_NONBASETHRDENA_Pos/) /!< SCB CCR: NONBASETHRDENA Mask /
mbed_official	25:ac5b0a371348	503
mbed_official	25:ac5b0a371348	504	/* SCB System Handler Control and State Register Definitions */
AnnaBridge	167:e84263d55307	505	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
mbed_official	25:ac5b0a371348	506	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
mbed_official	25:ac5b0a371348	507
AnnaBridge	167:e84263d55307	508	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
mbed_official	25:ac5b0a371348	509	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
mbed_official	25:ac5b0a371348	510
AnnaBridge	167:e84263d55307	511	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
mbed_official	25:ac5b0a371348	512	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
mbed_official	25:ac5b0a371348	513
AnnaBridge	167:e84263d55307	514	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
mbed_official	25:ac5b0a371348	515	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
mbed_official	25:ac5b0a371348	516
AnnaBridge	167:e84263d55307	517	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
mbed_official	25:ac5b0a371348	518	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
mbed_official	25:ac5b0a371348	519
AnnaBridge	167:e84263d55307	520	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
mbed_official	25:ac5b0a371348	521	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
mbed_official	25:ac5b0a371348	522
AnnaBridge	167:e84263d55307	523	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
mbed_official	25:ac5b0a371348	524	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
mbed_official	25:ac5b0a371348	525
AnnaBridge	167:e84263d55307	526	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
mbed_official	25:ac5b0a371348	527	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
mbed_official	25:ac5b0a371348	528
AnnaBridge	167:e84263d55307	529	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
mbed_official	25:ac5b0a371348	530	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
mbed_official	25:ac5b0a371348	531
AnnaBridge	167:e84263d55307	532	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
mbed_official	25:ac5b0a371348	533	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
mbed_official	25:ac5b0a371348	534
AnnaBridge	167:e84263d55307	535	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
mbed_official	25:ac5b0a371348	536	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
mbed_official	25:ac5b0a371348	537
AnnaBridge	167:e84263d55307	538	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
mbed_official	25:ac5b0a371348	539	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
mbed_official	25:ac5b0a371348	540
AnnaBridge	167:e84263d55307	541	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
mbed_official	25:ac5b0a371348	542	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
mbed_official	25:ac5b0a371348	543
AnnaBridge	167:e84263d55307	544	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
mbed_official	25:ac5b0a371348	545	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
mbed_official	25:ac5b0a371348	546
AnnaBridge	167:e84263d55307	547	/* SCB Configurable Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	548	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
mbed_official	25:ac5b0a371348	549	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
mbed_official	25:ac5b0a371348	550
AnnaBridge	167:e84263d55307	551	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
mbed_official	25:ac5b0a371348	552	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
mbed_official	25:ac5b0a371348	553
AnnaBridge	167:e84263d55307	554	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
mbed_official	25:ac5b0a371348	555	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
mbed_official	25:ac5b0a371348	556
AnnaBridge	167:e84263d55307	557	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:e84263d55307	558	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
AnnaBridge	167:e84263d55307	559	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
AnnaBridge	167:e84263d55307	560
AnnaBridge	167:e84263d55307	561	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
AnnaBridge	167:e84263d55307	562	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
AnnaBridge	167:e84263d55307	563
AnnaBridge	167:e84263d55307	564	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
AnnaBridge	167:e84263d55307	565	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
AnnaBridge	167:e84263d55307	566
AnnaBridge	167:e84263d55307	567	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
AnnaBridge	167:e84263d55307	568	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
AnnaBridge	167:e84263d55307	569
AnnaBridge	167:e84263d55307	570	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
AnnaBridge	167:e84263d55307	571	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
AnnaBridge	167:e84263d55307	572
AnnaBridge	167:e84263d55307	573	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:e84263d55307	574	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
AnnaBridge	167:e84263d55307	575	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
AnnaBridge	167:e84263d55307	576
AnnaBridge	167:e84263d55307	577	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
AnnaBridge	167:e84263d55307	578	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
AnnaBridge	167:e84263d55307	579
AnnaBridge	167:e84263d55307	580	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
AnnaBridge	167:e84263d55307	581	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
AnnaBridge	167:e84263d55307	582
AnnaBridge	167:e84263d55307	583	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
AnnaBridge	167:e84263d55307	584	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
AnnaBridge	167:e84263d55307	585
AnnaBridge	167:e84263d55307	586	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
AnnaBridge	167:e84263d55307	587	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
AnnaBridge	167:e84263d55307	588
AnnaBridge	167:e84263d55307	589	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
AnnaBridge	167:e84263d55307	590	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
AnnaBridge	167:e84263d55307	591
AnnaBridge	167:e84263d55307	592	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
AnnaBridge	167:e84263d55307	593	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
AnnaBridge	167:e84263d55307	594	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
AnnaBridge	167:e84263d55307	595
AnnaBridge	167:e84263d55307	596	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
AnnaBridge	167:e84263d55307	597	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
AnnaBridge	167:e84263d55307	598
AnnaBridge	167:e84263d55307	599	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
AnnaBridge	167:e84263d55307	600	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
AnnaBridge	167:e84263d55307	601
AnnaBridge	167:e84263d55307	602	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
AnnaBridge	167:e84263d55307	603	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
AnnaBridge	167:e84263d55307	604
AnnaBridge	167:e84263d55307	605	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
AnnaBridge	167:e84263d55307	606	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
AnnaBridge	167:e84263d55307	607
AnnaBridge	167:e84263d55307	608	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
AnnaBridge	167:e84263d55307	609	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
AnnaBridge	167:e84263d55307	610
AnnaBridge	167:e84263d55307	611	/* SCB Hard Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	612	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
mbed_official	25:ac5b0a371348	613	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
mbed_official	25:ac5b0a371348	614
AnnaBridge	167:e84263d55307	615	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
mbed_official	25:ac5b0a371348	616	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
mbed_official	25:ac5b0a371348	617
AnnaBridge	167:e84263d55307	618	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
mbed_official	25:ac5b0a371348	619	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
mbed_official	25:ac5b0a371348	620
mbed_official	25:ac5b0a371348	621	/* SCB Debug Fault Status Register Definitions */
AnnaBridge	167:e84263d55307	622	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
mbed_official	25:ac5b0a371348	623	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
mbed_official	25:ac5b0a371348	624
AnnaBridge	167:e84263d55307	625	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
mbed_official	25:ac5b0a371348	626	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
mbed_official	25:ac5b0a371348	627
AnnaBridge	167:e84263d55307	628	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
mbed_official	25:ac5b0a371348	629	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
mbed_official	25:ac5b0a371348	630
AnnaBridge	167:e84263d55307	631	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
mbed_official	25:ac5b0a371348	632	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
mbed_official	25:ac5b0a371348	633
AnnaBridge	167:e84263d55307	634	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
mbed_official	25:ac5b0a371348	635	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
mbed_official	25:ac5b0a371348	636
mbed_official	25:ac5b0a371348	637	/@} end of group CMSIS_SCB /
mbed_official	25:ac5b0a371348	638
mbed_official	25:ac5b0a371348	639
AnnaBridge	167:e84263d55307	640	/**
AnnaBridge	167:e84263d55307	641	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	642	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
AnnaBridge	167:e84263d55307	643	\brief Type definitions for the System Control and ID Register not in the SCB
mbed_official	25:ac5b0a371348	644	@{
mbed_official	25:ac5b0a371348	645	*/
mbed_official	25:ac5b0a371348	646
AnnaBridge	167:e84263d55307	647	/**
AnnaBridge	167:e84263d55307	648	\brief Structure type to access the System Control and ID Register not in the SCB.
mbed_official	25:ac5b0a371348	649	*/
mbed_official	25:ac5b0a371348	650	typedef struct
mbed_official	25:ac5b0a371348	651	{
AnnaBridge	167:e84263d55307	652	uint32_t RESERVED0[1U];
AnnaBridge	167:e84263d55307	653	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
AnnaBridge	167:e84263d55307	654	uint32_t RESERVED1[1U];
mbed_official	25:ac5b0a371348	655	} SCnSCB_Type;
mbed_official	25:ac5b0a371348	656
mbed_official	25:ac5b0a371348	657	/* Interrupt Controller Type Register Definitions */
AnnaBridge	167:e84263d55307	658	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
mbed_official	25:ac5b0a371348	659	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
mbed_official	25:ac5b0a371348	660
mbed_official	25:ac5b0a371348	661	/@} end of group CMSIS_SCnotSCB /
mbed_official	25:ac5b0a371348	662
mbed_official	25:ac5b0a371348	663
AnnaBridge	167:e84263d55307	664	/**
AnnaBridge	167:e84263d55307	665	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	666	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
AnnaBridge	167:e84263d55307	667	\brief Type definitions for the System Timer Registers.
mbed_official	25:ac5b0a371348	668	@{
mbed_official	25:ac5b0a371348	669	*/
mbed_official	25:ac5b0a371348	670
AnnaBridge	167:e84263d55307	671	/**
AnnaBridge	167:e84263d55307	672	\brief Structure type to access the System Timer (SysTick).
mbed_official	25:ac5b0a371348	673	*/
mbed_official	25:ac5b0a371348	674	typedef struct
mbed_official	25:ac5b0a371348	675	{
AnnaBridge	167:e84263d55307	676	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
AnnaBridge	167:e84263d55307	677	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
AnnaBridge	167:e84263d55307	678	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
AnnaBridge	167:e84263d55307	679	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
mbed_official	25:ac5b0a371348	680	} SysTick_Type;
mbed_official	25:ac5b0a371348	681
mbed_official	25:ac5b0a371348	682	/* SysTick Control / Status Register Definitions */
AnnaBridge	167:e84263d55307	683	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
mbed_official	25:ac5b0a371348	684	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
mbed_official	25:ac5b0a371348	685
AnnaBridge	167:e84263d55307	686	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
mbed_official	25:ac5b0a371348	687	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
mbed_official	25:ac5b0a371348	688
AnnaBridge	167:e84263d55307	689	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
mbed_official	25:ac5b0a371348	690	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
mbed_official	25:ac5b0a371348	691
AnnaBridge	167:e84263d55307	692	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
mbed_official	25:ac5b0a371348	693	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
mbed_official	25:ac5b0a371348	694
mbed_official	25:ac5b0a371348	695	/* SysTick Reload Register Definitions */
AnnaBridge	167:e84263d55307	696	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
mbed_official	25:ac5b0a371348	697	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
mbed_official	25:ac5b0a371348	698
mbed_official	25:ac5b0a371348	699	/* SysTick Current Register Definitions */
AnnaBridge	167:e84263d55307	700	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
mbed_official	25:ac5b0a371348	701	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
mbed_official	25:ac5b0a371348	702
mbed_official	25:ac5b0a371348	703	/* SysTick Calibration Register Definitions */
AnnaBridge	167:e84263d55307	704	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
mbed_official	25:ac5b0a371348	705	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
mbed_official	25:ac5b0a371348	706
AnnaBridge	167:e84263d55307	707	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
mbed_official	25:ac5b0a371348	708	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
mbed_official	25:ac5b0a371348	709
AnnaBridge	167:e84263d55307	710	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
mbed_official	25:ac5b0a371348	711	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
mbed_official	25:ac5b0a371348	712
mbed_official	25:ac5b0a371348	713	/@} end of group CMSIS_SysTick /
mbed_official	25:ac5b0a371348	714
mbed_official	25:ac5b0a371348	715
AnnaBridge	167:e84263d55307	716	/**
AnnaBridge	167:e84263d55307	717	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	718	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
AnnaBridge	167:e84263d55307	719	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mbed_official	25:ac5b0a371348	720	@{
mbed_official	25:ac5b0a371348	721	*/
mbed_official	25:ac5b0a371348	722
AnnaBridge	167:e84263d55307	723	/**
AnnaBridge	167:e84263d55307	724	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mbed_official	25:ac5b0a371348	725	*/
mbed_official	25:ac5b0a371348	726	typedef struct
mbed_official	25:ac5b0a371348	727	{
AnnaBridge	167:e84263d55307	728	__OM union
mbed_official	25:ac5b0a371348	729	{
AnnaBridge	167:e84263d55307	730	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
AnnaBridge	167:e84263d55307	731	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
AnnaBridge	167:e84263d55307	732	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
AnnaBridge	167:e84263d55307	733	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
AnnaBridge	167:e84263d55307	734	uint32_t RESERVED0[864U];
AnnaBridge	167:e84263d55307	735	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
AnnaBridge	167:e84263d55307	736	uint32_t RESERVED1[15U];
AnnaBridge	167:e84263d55307	737	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
AnnaBridge	167:e84263d55307	738	uint32_t RESERVED2[15U];
AnnaBridge	167:e84263d55307	739	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
AnnaBridge	167:e84263d55307	740	uint32_t RESERVED3[29U];
AnnaBridge	167:e84263d55307	741	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
AnnaBridge	167:e84263d55307	742	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
AnnaBridge	167:e84263d55307	743	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
AnnaBridge	167:e84263d55307	744	uint32_t RESERVED4[43U];
AnnaBridge	167:e84263d55307	745	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
AnnaBridge	167:e84263d55307	746	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
AnnaBridge	167:e84263d55307	747	uint32_t RESERVED5[6U];
AnnaBridge	167:e84263d55307	748	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
AnnaBridge	167:e84263d55307	749	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
AnnaBridge	167:e84263d55307	750	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
AnnaBridge	167:e84263d55307	751	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
AnnaBridge	167:e84263d55307	752	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
AnnaBridge	167:e84263d55307	753	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
AnnaBridge	167:e84263d55307	754	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
AnnaBridge	167:e84263d55307	755	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
AnnaBridge	167:e84263d55307	756	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
AnnaBridge	167:e84263d55307	757	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
AnnaBridge	167:e84263d55307	758	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
AnnaBridge	167:e84263d55307	759	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
mbed_official	25:ac5b0a371348	760	} ITM_Type;
mbed_official	25:ac5b0a371348	761
mbed_official	25:ac5b0a371348	762	/* ITM Trace Privilege Register Definitions */
AnnaBridge	167:e84263d55307	763	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
mbed_official	25:ac5b0a371348	764	#define ITM_TPR_PRIVMASK_Msk (0xFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
mbed_official	25:ac5b0a371348	765
mbed_official	25:ac5b0a371348	766	/* ITM Trace Control Register Definitions */
AnnaBridge	167:e84263d55307	767	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
mbed_official	25:ac5b0a371348	768	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
mbed_official	25:ac5b0a371348	769
AnnaBridge	167:e84263d55307	770	#define ITM_TCR_TraceBusID_Pos 16U /!< ITM TCR: ATBID Position /
mbed_official	25:ac5b0a371348	771	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
mbed_official	25:ac5b0a371348	772
AnnaBridge	167:e84263d55307	773	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
mbed_official	25:ac5b0a371348	774	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
mbed_official	25:ac5b0a371348	775
AnnaBridge	167:e84263d55307	776	#define ITM_TCR_TSPrescale_Pos 8U /!< ITM TCR: TSPrescale Position /
mbed_official	25:ac5b0a371348	777	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
mbed_official	25:ac5b0a371348	778
AnnaBridge	167:e84263d55307	779	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
mbed_official	25:ac5b0a371348	780	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
mbed_official	25:ac5b0a371348	781
AnnaBridge	167:e84263d55307	782	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
mbed_official	25:ac5b0a371348	783	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
mbed_official	25:ac5b0a371348	784
AnnaBridge	167:e84263d55307	785	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
mbed_official	25:ac5b0a371348	786	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
mbed_official	25:ac5b0a371348	787
AnnaBridge	167:e84263d55307	788	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
mbed_official	25:ac5b0a371348	789	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
mbed_official	25:ac5b0a371348	790
AnnaBridge	167:e84263d55307	791	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
mbed_official	25:ac5b0a371348	792	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
mbed_official	25:ac5b0a371348	793
mbed_official	25:ac5b0a371348	794	/* ITM Integration Write Register Definitions */
AnnaBridge	167:e84263d55307	795	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
mbed_official	25:ac5b0a371348	796	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
mbed_official	25:ac5b0a371348	797
mbed_official	25:ac5b0a371348	798	/* ITM Integration Read Register Definitions */
AnnaBridge	167:e84263d55307	799	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
mbed_official	25:ac5b0a371348	800	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
mbed_official	25:ac5b0a371348	801
mbed_official	25:ac5b0a371348	802	/* ITM Integration Mode Control Register Definitions */
AnnaBridge	167:e84263d55307	803	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
mbed_official	25:ac5b0a371348	804	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
mbed_official	25:ac5b0a371348	805
mbed_official	25:ac5b0a371348	806	/* ITM Lock Status Register Definitions */
AnnaBridge	167:e84263d55307	807	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
mbed_official	25:ac5b0a371348	808	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
mbed_official	25:ac5b0a371348	809
AnnaBridge	167:e84263d55307	810	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
mbed_official	25:ac5b0a371348	811	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
mbed_official	25:ac5b0a371348	812
AnnaBridge	167:e84263d55307	813	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
mbed_official	25:ac5b0a371348	814	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
mbed_official	25:ac5b0a371348	815
mbed_official	25:ac5b0a371348	816	/@}/ /* end of group CMSIS_ITM */
mbed_official	25:ac5b0a371348	817
mbed_official	25:ac5b0a371348	818
AnnaBridge	167:e84263d55307	819	/**
AnnaBridge	167:e84263d55307	820	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	821	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
AnnaBridge	167:e84263d55307	822	\brief Type definitions for the Data Watchpoint and Trace (DWT)
mbed_official	25:ac5b0a371348	823	@{
mbed_official	25:ac5b0a371348	824	*/
mbed_official	25:ac5b0a371348	825
AnnaBridge	167:e84263d55307	826	/**
AnnaBridge	167:e84263d55307	827	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mbed_official	25:ac5b0a371348	828	*/
mbed_official	25:ac5b0a371348	829	typedef struct
mbed_official	25:ac5b0a371348	830	{
AnnaBridge	167:e84263d55307	831	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
AnnaBridge	167:e84263d55307	832	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
AnnaBridge	167:e84263d55307	833	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
AnnaBridge	167:e84263d55307	834	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
AnnaBridge	167:e84263d55307	835	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
AnnaBridge	167:e84263d55307	836	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
AnnaBridge	167:e84263d55307	837	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
AnnaBridge	167:e84263d55307	838	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
AnnaBridge	167:e84263d55307	839	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
AnnaBridge	167:e84263d55307	840	__IOM uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
AnnaBridge	167:e84263d55307	841	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
AnnaBridge	167:e84263d55307	842	uint32_t RESERVED0[1U];
AnnaBridge	167:e84263d55307	843	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
AnnaBridge	167:e84263d55307	844	__IOM uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
AnnaBridge	167:e84263d55307	845	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
AnnaBridge	167:e84263d55307	846	uint32_t RESERVED1[1U];
AnnaBridge	167:e84263d55307	847	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
AnnaBridge	167:e84263d55307	848	__IOM uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
AnnaBridge	167:e84263d55307	849	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
AnnaBridge	167:e84263d55307	850	uint32_t RESERVED2[1U];
AnnaBridge	167:e84263d55307	851	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
AnnaBridge	167:e84263d55307	852	__IOM uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
AnnaBridge	167:e84263d55307	853	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
mbed_official	25:ac5b0a371348	854	} DWT_Type;
mbed_official	25:ac5b0a371348	855
mbed_official	25:ac5b0a371348	856	/* DWT Control Register Definitions */
AnnaBridge	167:e84263d55307	857	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
mbed_official	25:ac5b0a371348	858	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
mbed_official	25:ac5b0a371348	859
AnnaBridge	167:e84263d55307	860	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
mbed_official	25:ac5b0a371348	861	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
mbed_official	25:ac5b0a371348	862
AnnaBridge	167:e84263d55307	863	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
mbed_official	25:ac5b0a371348	864	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
mbed_official	25:ac5b0a371348	865
AnnaBridge	167:e84263d55307	866	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
mbed_official	25:ac5b0a371348	867	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
mbed_official	25:ac5b0a371348	868
AnnaBridge	167:e84263d55307	869	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
mbed_official	25:ac5b0a371348	870	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
mbed_official	25:ac5b0a371348	871
AnnaBridge	167:e84263d55307	872	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
mbed_official	25:ac5b0a371348	873	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
mbed_official	25:ac5b0a371348	874
AnnaBridge	167:e84263d55307	875	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
mbed_official	25:ac5b0a371348	876	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
mbed_official	25:ac5b0a371348	877
AnnaBridge	167:e84263d55307	878	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
mbed_official	25:ac5b0a371348	879	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
mbed_official	25:ac5b0a371348	880
AnnaBridge	167:e84263d55307	881	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
mbed_official	25:ac5b0a371348	882	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
mbed_official	25:ac5b0a371348	883
AnnaBridge	167:e84263d55307	884	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
mbed_official	25:ac5b0a371348	885	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
mbed_official	25:ac5b0a371348	886
AnnaBridge	167:e84263d55307	887	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
mbed_official	25:ac5b0a371348	888	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
mbed_official	25:ac5b0a371348	889
AnnaBridge	167:e84263d55307	890	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
mbed_official	25:ac5b0a371348	891	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
mbed_official	25:ac5b0a371348	892
AnnaBridge	167:e84263d55307	893	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
mbed_official	25:ac5b0a371348	894	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
mbed_official	25:ac5b0a371348	895
AnnaBridge	167:e84263d55307	896	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
mbed_official	25:ac5b0a371348	897	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
mbed_official	25:ac5b0a371348	898
AnnaBridge	167:e84263d55307	899	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
mbed_official	25:ac5b0a371348	900	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
mbed_official	25:ac5b0a371348	901
AnnaBridge	167:e84263d55307	902	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
mbed_official	25:ac5b0a371348	903	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
mbed_official	25:ac5b0a371348	904
AnnaBridge	167:e84263d55307	905	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
mbed_official	25:ac5b0a371348	906	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
mbed_official	25:ac5b0a371348	907
AnnaBridge	167:e84263d55307	908	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
mbed_official	25:ac5b0a371348	909	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
mbed_official	25:ac5b0a371348	910
mbed_official	25:ac5b0a371348	911	/* DWT CPI Count Register Definitions */
AnnaBridge	167:e84263d55307	912	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
mbed_official	25:ac5b0a371348	913	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
mbed_official	25:ac5b0a371348	914
mbed_official	25:ac5b0a371348	915	/* DWT Exception Overhead Count Register Definitions */
AnnaBridge	167:e84263d55307	916	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
mbed_official	25:ac5b0a371348	917	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
mbed_official	25:ac5b0a371348	918
mbed_official	25:ac5b0a371348	919	/* DWT Sleep Count Register Definitions */
AnnaBridge	167:e84263d55307	920	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
mbed_official	25:ac5b0a371348	921	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
mbed_official	25:ac5b0a371348	922
mbed_official	25:ac5b0a371348	923	/* DWT LSU Count Register Definitions */
AnnaBridge	167:e84263d55307	924	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
mbed_official	25:ac5b0a371348	925	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
mbed_official	25:ac5b0a371348	926
mbed_official	25:ac5b0a371348	927	/* DWT Folded-instruction Count Register Definitions */
AnnaBridge	167:e84263d55307	928	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
mbed_official	25:ac5b0a371348	929	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
mbed_official	25:ac5b0a371348	930
mbed_official	25:ac5b0a371348	931	/* DWT Comparator Mask Register Definitions */
AnnaBridge	167:e84263d55307	932	#define DWT_MASK_MASK_Pos 0U /!< DWT MASK: MASK Position /
mbed_official	25:ac5b0a371348	933	#define DWT_MASK_MASK_Msk (0x1FUL /<< DWT_MASK_MASK_Pos/) /!< DWT MASK: MASK Mask /
mbed_official	25:ac5b0a371348	934
mbed_official	25:ac5b0a371348	935	/* DWT Comparator Function Register Definitions */
AnnaBridge	167:e84263d55307	936	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
mbed_official	25:ac5b0a371348	937	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
mbed_official	25:ac5b0a371348	938
AnnaBridge	167:e84263d55307	939	#define DWT_FUNCTION_DATAVADDR1_Pos 16U /!< DWT FUNCTION: DATAVADDR1 Position /
mbed_official	25:ac5b0a371348	940	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
mbed_official	25:ac5b0a371348	941
AnnaBridge	167:e84263d55307	942	#define DWT_FUNCTION_DATAVADDR0_Pos 12U /!< DWT FUNCTION: DATAVADDR0 Position /
mbed_official	25:ac5b0a371348	943	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
mbed_official	25:ac5b0a371348	944
AnnaBridge	167:e84263d55307	945	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
mbed_official	25:ac5b0a371348	946	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
mbed_official	25:ac5b0a371348	947
AnnaBridge	167:e84263d55307	948	#define DWT_FUNCTION_LNK1ENA_Pos 9U /!< DWT FUNCTION: LNK1ENA Position /
mbed_official	25:ac5b0a371348	949	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
mbed_official	25:ac5b0a371348	950
AnnaBridge	167:e84263d55307	951	#define DWT_FUNCTION_DATAVMATCH_Pos 8U /!< DWT FUNCTION: DATAVMATCH Position /
mbed_official	25:ac5b0a371348	952	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
mbed_official	25:ac5b0a371348	953
AnnaBridge	167:e84263d55307	954	#define DWT_FUNCTION_CYCMATCH_Pos 7U /!< DWT FUNCTION: CYCMATCH Position /
mbed_official	25:ac5b0a371348	955	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
mbed_official	25:ac5b0a371348	956
AnnaBridge	167:e84263d55307	957	#define DWT_FUNCTION_EMITRANGE_Pos 5U /!< DWT FUNCTION: EMITRANGE Position /
mbed_official	25:ac5b0a371348	958	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
mbed_official	25:ac5b0a371348	959
AnnaBridge	167:e84263d55307	960	#define DWT_FUNCTION_FUNCTION_Pos 0U /!< DWT FUNCTION: FUNCTION Position /
mbed_official	25:ac5b0a371348	961	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /<< DWT_FUNCTION_FUNCTION_Pos/) /!< DWT FUNCTION: FUNCTION Mask /
mbed_official	25:ac5b0a371348	962
mbed_official	25:ac5b0a371348	963	/@}/ /* end of group CMSIS_DWT */
mbed_official	25:ac5b0a371348	964
mbed_official	25:ac5b0a371348	965
AnnaBridge	167:e84263d55307	966	/**
AnnaBridge	167:e84263d55307	967	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	968	\defgroup CMSIS_TPI Trace Port Interface (TPI)
AnnaBridge	167:e84263d55307	969	\brief Type definitions for the Trace Port Interface (TPI)
mbed_official	25:ac5b0a371348	970	@{
mbed_official	25:ac5b0a371348	971	*/
mbed_official	25:ac5b0a371348	972
AnnaBridge	167:e84263d55307	973	/**
AnnaBridge	167:e84263d55307	974	\brief Structure type to access the Trace Port Interface Register (TPI).
mbed_official	25:ac5b0a371348	975	*/
mbed_official	25:ac5b0a371348	976	typedef struct
mbed_official	25:ac5b0a371348	977	{
AnnaBridge	167:e84263d55307	978	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
AnnaBridge	167:e84263d55307	979	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
AnnaBridge	167:e84263d55307	980	uint32_t RESERVED0[2U];
AnnaBridge	167:e84263d55307	981	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
AnnaBridge	167:e84263d55307	982	uint32_t RESERVED1[55U];
AnnaBridge	167:e84263d55307	983	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
AnnaBridge	167:e84263d55307	984	uint32_t RESERVED2[131U];
AnnaBridge	167:e84263d55307	985	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
AnnaBridge	167:e84263d55307	986	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
AnnaBridge	167:e84263d55307	987	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
AnnaBridge	167:e84263d55307	988	uint32_t RESERVED3[759U];
AnnaBridge	167:e84263d55307	989	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
AnnaBridge	167:e84263d55307	990	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
AnnaBridge	167:e84263d55307	991	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
AnnaBridge	167:e84263d55307	992	uint32_t RESERVED4[1U];
AnnaBridge	167:e84263d55307	993	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
AnnaBridge	167:e84263d55307	994	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
AnnaBridge	167:e84263d55307	995	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
AnnaBridge	167:e84263d55307	996	uint32_t RESERVED5[39U];
AnnaBridge	167:e84263d55307	997	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
AnnaBridge	167:e84263d55307	998	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
AnnaBridge	167:e84263d55307	999	uint32_t RESERVED7[8U];
AnnaBridge	167:e84263d55307	1000	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
AnnaBridge	167:e84263d55307	1001	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
mbed_official	25:ac5b0a371348	1002	} TPI_Type;
mbed_official	25:ac5b0a371348	1003
mbed_official	25:ac5b0a371348	1004	/* TPI Asynchronous Clock Prescaler Register Definitions */
AnnaBridge	167:e84263d55307	1005	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
mbed_official	25:ac5b0a371348	1006	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
mbed_official	25:ac5b0a371348	1007
mbed_official	25:ac5b0a371348	1008	/* TPI Selected Pin Protocol Register Definitions */
AnnaBridge	167:e84263d55307	1009	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
mbed_official	25:ac5b0a371348	1010	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
mbed_official	25:ac5b0a371348	1011
mbed_official	25:ac5b0a371348	1012	/* TPI Formatter and Flush Status Register Definitions */
AnnaBridge	167:e84263d55307	1013	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
mbed_official	25:ac5b0a371348	1014	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
mbed_official	25:ac5b0a371348	1015
AnnaBridge	167:e84263d55307	1016	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
mbed_official	25:ac5b0a371348	1017	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
mbed_official	25:ac5b0a371348	1018
AnnaBridge	167:e84263d55307	1019	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
mbed_official	25:ac5b0a371348	1020	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
mbed_official	25:ac5b0a371348	1021
AnnaBridge	167:e84263d55307	1022	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
mbed_official	25:ac5b0a371348	1023	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
mbed_official	25:ac5b0a371348	1024
mbed_official	25:ac5b0a371348	1025	/* TPI Formatter and Flush Control Register Definitions */
AnnaBridge	167:e84263d55307	1026	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
mbed_official	25:ac5b0a371348	1027	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
mbed_official	25:ac5b0a371348	1028
AnnaBridge	167:e84263d55307	1029	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
mbed_official	25:ac5b0a371348	1030	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
mbed_official	25:ac5b0a371348	1031
mbed_official	25:ac5b0a371348	1032	/* TPI TRIGGER Register Definitions */
AnnaBridge	167:e84263d55307	1033	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
mbed_official	25:ac5b0a371348	1034	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
mbed_official	25:ac5b0a371348	1035
mbed_official	25:ac5b0a371348	1036	/* TPI Integration ETM Data Register Definitions (FIFO0) */
AnnaBridge	167:e84263d55307	1037	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
mbed_official	25:ac5b0a371348	1038	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
mbed_official	25:ac5b0a371348	1039
AnnaBridge	167:e84263d55307	1040	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
mbed_official	25:ac5b0a371348	1041	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
mbed_official	25:ac5b0a371348	1042
AnnaBridge	167:e84263d55307	1043	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
mbed_official	25:ac5b0a371348	1044	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
mbed_official	25:ac5b0a371348	1045
AnnaBridge	167:e84263d55307	1046	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
mbed_official	25:ac5b0a371348	1047	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
mbed_official	25:ac5b0a371348	1048
AnnaBridge	167:e84263d55307	1049	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
mbed_official	25:ac5b0a371348	1050	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
mbed_official	25:ac5b0a371348	1051
AnnaBridge	167:e84263d55307	1052	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
mbed_official	25:ac5b0a371348	1053	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
mbed_official	25:ac5b0a371348	1054
AnnaBridge	167:e84263d55307	1055	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
mbed_official	25:ac5b0a371348	1056	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
mbed_official	25:ac5b0a371348	1057
mbed_official	25:ac5b0a371348	1058	/* TPI ITATBCTR2 Register Definitions */
AnnaBridge	167:e84263d55307	1059	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
mbed_official	25:ac5b0a371348	1060	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
mbed_official	25:ac5b0a371348	1061
mbed_official	25:ac5b0a371348	1062	/* TPI Integration ITM Data Register Definitions (FIFO1) */
AnnaBridge	167:e84263d55307	1063	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
mbed_official	25:ac5b0a371348	1064	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
mbed_official	25:ac5b0a371348	1065
AnnaBridge	167:e84263d55307	1066	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
mbed_official	25:ac5b0a371348	1067	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
mbed_official	25:ac5b0a371348	1068
AnnaBridge	167:e84263d55307	1069	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
mbed_official	25:ac5b0a371348	1070	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
mbed_official	25:ac5b0a371348	1071
AnnaBridge	167:e84263d55307	1072	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
mbed_official	25:ac5b0a371348	1073	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
mbed_official	25:ac5b0a371348	1074
AnnaBridge	167:e84263d55307	1075	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
mbed_official	25:ac5b0a371348	1076	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
mbed_official	25:ac5b0a371348	1077
AnnaBridge	167:e84263d55307	1078	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
mbed_official	25:ac5b0a371348	1079	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
mbed_official	25:ac5b0a371348	1080
AnnaBridge	167:e84263d55307	1081	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
mbed_official	25:ac5b0a371348	1082	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
mbed_official	25:ac5b0a371348	1083
mbed_official	25:ac5b0a371348	1084	/* TPI ITATBCTR0 Register Definitions */
AnnaBridge	167:e84263d55307	1085	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
mbed_official	25:ac5b0a371348	1086	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
mbed_official	25:ac5b0a371348	1087
mbed_official	25:ac5b0a371348	1088	/* TPI Integration Mode Control Register Definitions */
AnnaBridge	167:e84263d55307	1089	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
mbed_official	25:ac5b0a371348	1090	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
mbed_official	25:ac5b0a371348	1091
mbed_official	25:ac5b0a371348	1092	/* TPI DEVID Register Definitions */
AnnaBridge	167:e84263d55307	1093	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
mbed_official	25:ac5b0a371348	1094	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
mbed_official	25:ac5b0a371348	1095
AnnaBridge	167:e84263d55307	1096	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
mbed_official	25:ac5b0a371348	1097	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
mbed_official	25:ac5b0a371348	1098
AnnaBridge	167:e84263d55307	1099	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
mbed_official	25:ac5b0a371348	1100	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
mbed_official	25:ac5b0a371348	1101
AnnaBridge	167:e84263d55307	1102	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
mbed_official	25:ac5b0a371348	1103	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
mbed_official	25:ac5b0a371348	1104
AnnaBridge	167:e84263d55307	1105	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
mbed_official	25:ac5b0a371348	1106	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
mbed_official	25:ac5b0a371348	1107
AnnaBridge	167:e84263d55307	1108	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
mbed_official	25:ac5b0a371348	1109	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
mbed_official	25:ac5b0a371348	1110
mbed_official	25:ac5b0a371348	1111	/* TPI DEVTYPE Register Definitions */
AnnaBridge	167:e84263d55307	1112	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
mbed_official	25:ac5b0a371348	1113	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
mbed_official	25:ac5b0a371348	1114
AnnaBridge	167:e84263d55307	1115	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
mbed_official	25:ac5b0a371348	1116	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
mbed_official	25:ac5b0a371348	1117
mbed_official	25:ac5b0a371348	1118	/@}/ /* end of group CMSIS_TPI */
mbed_official	25:ac5b0a371348	1119
mbed_official	25:ac5b0a371348	1120
AnnaBridge	167:e84263d55307	1121	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1122	/**
AnnaBridge	167:e84263d55307	1123	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1124	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
AnnaBridge	167:e84263d55307	1125	\brief Type definitions for the Memory Protection Unit (MPU)
mbed_official	25:ac5b0a371348	1126	@{
mbed_official	25:ac5b0a371348	1127	*/
mbed_official	25:ac5b0a371348	1128
AnnaBridge	167:e84263d55307	1129	/**
AnnaBridge	167:e84263d55307	1130	\brief Structure type to access the Memory Protection Unit (MPU).
mbed_official	25:ac5b0a371348	1131	*/
mbed_official	25:ac5b0a371348	1132	typedef struct
mbed_official	25:ac5b0a371348	1133	{
AnnaBridge	167:e84263d55307	1134	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
AnnaBridge	167:e84263d55307	1135	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
AnnaBridge	167:e84263d55307	1136	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
AnnaBridge	167:e84263d55307	1137	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
AnnaBridge	167:e84263d55307	1138	__IOM uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
AnnaBridge	167:e84263d55307	1139	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
AnnaBridge	167:e84263d55307	1140	__IOM uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
AnnaBridge	167:e84263d55307	1141	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
AnnaBridge	167:e84263d55307	1142	__IOM uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
AnnaBridge	167:e84263d55307	1143	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
AnnaBridge	167:e84263d55307	1144	__IOM uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
mbed_official	25:ac5b0a371348	1145	} MPU_Type;
mbed_official	25:ac5b0a371348	1146
AnnaBridge	167:e84263d55307	1147	/* MPU Type Register Definitions */
AnnaBridge	167:e84263d55307	1148	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
mbed_official	25:ac5b0a371348	1149	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
mbed_official	25:ac5b0a371348	1150
AnnaBridge	167:e84263d55307	1151	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
mbed_official	25:ac5b0a371348	1152	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
mbed_official	25:ac5b0a371348	1153
AnnaBridge	167:e84263d55307	1154	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
mbed_official	25:ac5b0a371348	1155	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
mbed_official	25:ac5b0a371348	1156
AnnaBridge	167:e84263d55307	1157	/* MPU Control Register Definitions */
AnnaBridge	167:e84263d55307	1158	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
mbed_official	25:ac5b0a371348	1159	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
mbed_official	25:ac5b0a371348	1160
AnnaBridge	167:e84263d55307	1161	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
mbed_official	25:ac5b0a371348	1162	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
mbed_official	25:ac5b0a371348	1163
AnnaBridge	167:e84263d55307	1164	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
mbed_official	25:ac5b0a371348	1165	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
mbed_official	25:ac5b0a371348	1166
AnnaBridge	167:e84263d55307	1167	/* MPU Region Number Register Definitions */
AnnaBridge	167:e84263d55307	1168	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
mbed_official	25:ac5b0a371348	1169	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
mbed_official	25:ac5b0a371348	1170
AnnaBridge	167:e84263d55307	1171	/* MPU Region Base Address Register Definitions */
AnnaBridge	167:e84263d55307	1172	#define MPU_RBAR_ADDR_Pos 5U /!< MPU RBAR: ADDR Position /
mbed_official	25:ac5b0a371348	1173	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
mbed_official	25:ac5b0a371348	1174
AnnaBridge	167:e84263d55307	1175	#define MPU_RBAR_VALID_Pos 4U /!< MPU RBAR: VALID Position /
mbed_official	25:ac5b0a371348	1176	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
mbed_official	25:ac5b0a371348	1177
AnnaBridge	167:e84263d55307	1178	#define MPU_RBAR_REGION_Pos 0U /!< MPU RBAR: REGION Position /
mbed_official	25:ac5b0a371348	1179	#define MPU_RBAR_REGION_Msk (0xFUL /<< MPU_RBAR_REGION_Pos/) /!< MPU RBAR: REGION Mask /
mbed_official	25:ac5b0a371348	1180
AnnaBridge	167:e84263d55307	1181	/* MPU Region Attribute and Size Register Definitions */
AnnaBridge	167:e84263d55307	1182	#define MPU_RASR_ATTRS_Pos 16U /!< MPU RASR: MPU Region Attribute field Position /
mbed_official	25:ac5b0a371348	1183	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
mbed_official	25:ac5b0a371348	1184
AnnaBridge	167:e84263d55307	1185	#define MPU_RASR_XN_Pos 28U /!< MPU RASR: ATTRS.XN Position /
mbed_official	25:ac5b0a371348	1186	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
mbed_official	25:ac5b0a371348	1187
AnnaBridge	167:e84263d55307	1188	#define MPU_RASR_AP_Pos 24U /!< MPU RASR: ATTRS.AP Position /
mbed_official	25:ac5b0a371348	1189	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
mbed_official	25:ac5b0a371348	1190
AnnaBridge	167:e84263d55307	1191	#define MPU_RASR_TEX_Pos 19U /!< MPU RASR: ATTRS.TEX Position /
mbed_official	25:ac5b0a371348	1192	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
mbed_official	25:ac5b0a371348	1193
AnnaBridge	167:e84263d55307	1194	#define MPU_RASR_S_Pos 18U /!< MPU RASR: ATTRS.S Position /
mbed_official	25:ac5b0a371348	1195	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
mbed_official	25:ac5b0a371348	1196
AnnaBridge	167:e84263d55307	1197	#define MPU_RASR_C_Pos 17U /!< MPU RASR: ATTRS.C Position /
mbed_official	25:ac5b0a371348	1198	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
mbed_official	25:ac5b0a371348	1199
AnnaBridge	167:e84263d55307	1200	#define MPU_RASR_B_Pos 16U /!< MPU RASR: ATTRS.B Position /
mbed_official	25:ac5b0a371348	1201	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
mbed_official	25:ac5b0a371348	1202
AnnaBridge	167:e84263d55307	1203	#define MPU_RASR_SRD_Pos 8U /!< MPU RASR: Sub-Region Disable Position /
mbed_official	25:ac5b0a371348	1204	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
mbed_official	25:ac5b0a371348	1205
AnnaBridge	167:e84263d55307	1206	#define MPU_RASR_SIZE_Pos 1U /!< MPU RASR: Region Size Field Position /
mbed_official	25:ac5b0a371348	1207	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
mbed_official	25:ac5b0a371348	1208
AnnaBridge	167:e84263d55307	1209	#define MPU_RASR_ENABLE_Pos 0U /!< MPU RASR: Region enable bit Position /
mbed_official	25:ac5b0a371348	1210	#define MPU_RASR_ENABLE_Msk (1UL /<< MPU_RASR_ENABLE_Pos/) /!< MPU RASR: Region enable bit Disable Mask /
mbed_official	25:ac5b0a371348	1211
mbed_official	25:ac5b0a371348	1212	/@} end of group CMSIS_MPU /
mbed_official	25:ac5b0a371348	1213	#endif
mbed_official	25:ac5b0a371348	1214
mbed_official	25:ac5b0a371348	1215
AnnaBridge	167:e84263d55307	1216	/**
AnnaBridge	167:e84263d55307	1217	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1218	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
AnnaBridge	167:e84263d55307	1219	\brief Type definitions for the Core Debug Registers
mbed_official	25:ac5b0a371348	1220	@{
mbed_official	25:ac5b0a371348	1221	*/
mbed_official	25:ac5b0a371348	1222
AnnaBridge	167:e84263d55307	1223	/**
AnnaBridge	167:e84263d55307	1224	\brief Structure type to access the Core Debug Register (CoreDebug).
mbed_official	25:ac5b0a371348	1225	*/
mbed_official	25:ac5b0a371348	1226	typedef struct
mbed_official	25:ac5b0a371348	1227	{
AnnaBridge	167:e84263d55307	1228	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
AnnaBridge	167:e84263d55307	1229	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
AnnaBridge	167:e84263d55307	1230	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
AnnaBridge	167:e84263d55307	1231	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
mbed_official	25:ac5b0a371348	1232	} CoreDebug_Type;
mbed_official	25:ac5b0a371348	1233
AnnaBridge	167:e84263d55307	1234	/* Debug Halting Control and Status Register Definitions */
AnnaBridge	167:e84263d55307	1235	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
mbed_official	25:ac5b0a371348	1236	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
mbed_official	25:ac5b0a371348	1237
AnnaBridge	167:e84263d55307	1238	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
mbed_official	25:ac5b0a371348	1239	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
mbed_official	25:ac5b0a371348	1240
AnnaBridge	167:e84263d55307	1241	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
mbed_official	25:ac5b0a371348	1242	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
mbed_official	25:ac5b0a371348	1243
AnnaBridge	167:e84263d55307	1244	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
mbed_official	25:ac5b0a371348	1245	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
mbed_official	25:ac5b0a371348	1246
AnnaBridge	167:e84263d55307	1247	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
mbed_official	25:ac5b0a371348	1248	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
mbed_official	25:ac5b0a371348	1249
AnnaBridge	167:e84263d55307	1250	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
mbed_official	25:ac5b0a371348	1251	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
mbed_official	25:ac5b0a371348	1252
AnnaBridge	167:e84263d55307	1253	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
mbed_official	25:ac5b0a371348	1254	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
mbed_official	25:ac5b0a371348	1255
AnnaBridge	167:e84263d55307	1256	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
mbed_official	25:ac5b0a371348	1257	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
mbed_official	25:ac5b0a371348	1258
AnnaBridge	167:e84263d55307	1259	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
mbed_official	25:ac5b0a371348	1260	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
mbed_official	25:ac5b0a371348	1261
AnnaBridge	167:e84263d55307	1262	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
mbed_official	25:ac5b0a371348	1263	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
mbed_official	25:ac5b0a371348	1264
AnnaBridge	167:e84263d55307	1265	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
mbed_official	25:ac5b0a371348	1266	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
mbed_official	25:ac5b0a371348	1267
AnnaBridge	167:e84263d55307	1268	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
mbed_official	25:ac5b0a371348	1269	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
mbed_official	25:ac5b0a371348	1270
AnnaBridge	167:e84263d55307	1271	/* Debug Core Register Selector Register Definitions */
AnnaBridge	167:e84263d55307	1272	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
mbed_official	25:ac5b0a371348	1273	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
mbed_official	25:ac5b0a371348	1274
AnnaBridge	167:e84263d55307	1275	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
mbed_official	25:ac5b0a371348	1276	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
mbed_official	25:ac5b0a371348	1277
AnnaBridge	167:e84263d55307	1278	/* Debug Exception and Monitor Control Register Definitions */
AnnaBridge	167:e84263d55307	1279	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
mbed_official	25:ac5b0a371348	1280	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
mbed_official	25:ac5b0a371348	1281
AnnaBridge	167:e84263d55307	1282	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
mbed_official	25:ac5b0a371348	1283	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
mbed_official	25:ac5b0a371348	1284
AnnaBridge	167:e84263d55307	1285	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
mbed_official	25:ac5b0a371348	1286	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
mbed_official	25:ac5b0a371348	1287
AnnaBridge	167:e84263d55307	1288	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
mbed_official	25:ac5b0a371348	1289	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
mbed_official	25:ac5b0a371348	1290
AnnaBridge	167:e84263d55307	1291	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
mbed_official	25:ac5b0a371348	1292	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
mbed_official	25:ac5b0a371348	1293
AnnaBridge	167:e84263d55307	1294	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
mbed_official	25:ac5b0a371348	1295	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
mbed_official	25:ac5b0a371348	1296
AnnaBridge	167:e84263d55307	1297	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
mbed_official	25:ac5b0a371348	1298	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
mbed_official	25:ac5b0a371348	1299
AnnaBridge	167:e84263d55307	1300	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
mbed_official	25:ac5b0a371348	1301	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
mbed_official	25:ac5b0a371348	1302
AnnaBridge	167:e84263d55307	1303	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
mbed_official	25:ac5b0a371348	1304	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
mbed_official	25:ac5b0a371348	1305
AnnaBridge	167:e84263d55307	1306	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
mbed_official	25:ac5b0a371348	1307	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
mbed_official	25:ac5b0a371348	1308
AnnaBridge	167:e84263d55307	1309	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
mbed_official	25:ac5b0a371348	1310	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
mbed_official	25:ac5b0a371348	1311
AnnaBridge	167:e84263d55307	1312	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
mbed_official	25:ac5b0a371348	1313	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
mbed_official	25:ac5b0a371348	1314
AnnaBridge	167:e84263d55307	1315	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
mbed_official	25:ac5b0a371348	1316	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
mbed_official	25:ac5b0a371348	1317
mbed_official	25:ac5b0a371348	1318	/@} end of group CMSIS_CoreDebug /
mbed_official	25:ac5b0a371348	1319
mbed_official	25:ac5b0a371348	1320
AnnaBridge	167:e84263d55307	1321	/**
AnnaBridge	167:e84263d55307	1322	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1323	\defgroup CMSIS_core_bitfield Core register bit field macros
AnnaBridge	167:e84263d55307	1324	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
mbed_official	25:ac5b0a371348	1325	@{
mbed_official	25:ac5b0a371348	1326	*/
mbed_official	25:ac5b0a371348	1327
AnnaBridge	167:e84263d55307	1328	/**
AnnaBridge	167:e84263d55307	1329	\brief Mask and shift a bit field value for use in a register bit range.
AnnaBridge	167:e84263d55307	1330	\param[in] field Name of the register bit field.
AnnaBridge	167:e84263d55307	1331	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:e84263d55307	1332	\return Masked and shifted value.
AnnaBridge	167:e84263d55307	1333	*/
AnnaBridge	167:e84263d55307	1334	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
AnnaBridge	167:e84263d55307	1335
AnnaBridge	167:e84263d55307	1336	/**
AnnaBridge	167:e84263d55307	1337	\brief Mask and shift a register value to extract a bit filed value.
AnnaBridge	167:e84263d55307	1338	\param[in] field Name of the register bit field.
AnnaBridge	167:e84263d55307	1339	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
AnnaBridge	167:e84263d55307	1340	\return Masked and shifted bit field value.
AnnaBridge	167:e84263d55307	1341	*/
AnnaBridge	167:e84263d55307	1342	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
AnnaBridge	167:e84263d55307	1343
AnnaBridge	167:e84263d55307	1344	/@} end of group CMSIS_core_bitfield /
AnnaBridge	167:e84263d55307	1345
AnnaBridge	167:e84263d55307	1346
AnnaBridge	167:e84263d55307	1347	/**
AnnaBridge	167:e84263d55307	1348	\ingroup CMSIS_core_register
AnnaBridge	167:e84263d55307	1349	\defgroup CMSIS_core_base Core Definitions
AnnaBridge	167:e84263d55307	1350	\brief Definitions for base addresses, unions, and structures.
AnnaBridge	167:e84263d55307	1351	@{
AnnaBridge	167:e84263d55307	1352	*/
AnnaBridge	167:e84263d55307	1353
AnnaBridge	167:e84263d55307	1354	/* Memory mapping of Core Hardware */
AnnaBridge	167:e84263d55307	1355	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
AnnaBridge	167:e84263d55307	1356	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
AnnaBridge	167:e84263d55307	1357	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
AnnaBridge	167:e84263d55307	1358	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
AnnaBridge	167:e84263d55307	1359	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
AnnaBridge	167:e84263d55307	1360	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
AnnaBridge	167:e84263d55307	1361	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
AnnaBridge	167:e84263d55307	1362	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
mbed_official	25:ac5b0a371348	1363
mbed_official	25:ac5b0a371348	1364	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
AnnaBridge	167:e84263d55307	1365	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
AnnaBridge	167:e84263d55307	1366	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
AnnaBridge	167:e84263d55307	1367	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
AnnaBridge	167:e84263d55307	1368	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
AnnaBridge	167:e84263d55307	1369	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
AnnaBridge	167:e84263d55307	1370	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
AnnaBridge	167:e84263d55307	1371	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
mbed_official	25:ac5b0a371348	1372
AnnaBridge	167:e84263d55307	1373	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1374	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
AnnaBridge	167:e84263d55307	1375	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
mbed_official	25:ac5b0a371348	1376	#endif
mbed_official	25:ac5b0a371348	1377
mbed_official	25:ac5b0a371348	1378	/@} /
mbed_official	25:ac5b0a371348	1379
mbed_official	25:ac5b0a371348	1380
mbed_official	25:ac5b0a371348	1381
mbed_official	25:ac5b0a371348	1382	/*******************************************************************************
mbed_official	25:ac5b0a371348	1383	* Hardware Abstraction Layer
mbed_official	25:ac5b0a371348	1384	Core Function Interface contains:
mbed_official	25:ac5b0a371348	1385	- Core NVIC Functions
mbed_official	25:ac5b0a371348	1386	- Core SysTick Functions
mbed_official	25:ac5b0a371348	1387	- Core Debug Functions
mbed_official	25:ac5b0a371348	1388	- Core Register Access Functions
mbed_official	25:ac5b0a371348	1389	******************************************************************************/
AnnaBridge	167:e84263d55307	1390	/**
AnnaBridge	167:e84263d55307	1391	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbed_official	25:ac5b0a371348	1392	*/
mbed_official	25:ac5b0a371348	1393
mbed_official	25:ac5b0a371348	1394
mbed_official	25:ac5b0a371348	1395
mbed_official	25:ac5b0a371348	1396	/* ########################## NVIC functions #################################### */
AnnaBridge	167:e84263d55307	1397	/**
AnnaBridge	167:e84263d55307	1398	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	1399	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
AnnaBridge	167:e84263d55307	1400	\brief Functions that manage interrupts and exceptions via the NVIC.
AnnaBridge	167:e84263d55307	1401	@{
mbed_official	25:ac5b0a371348	1402	*/
mbed_official	25:ac5b0a371348	1403
AnnaBridge	167:e84263d55307	1404	#ifdef CMSIS_NVIC_VIRTUAL
AnnaBridge	167:e84263d55307	1405	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1406	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
AnnaBridge	167:e84263d55307	1407	#endif
AnnaBridge	167:e84263d55307	1408	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1409	#else
AnnaBridge	167:e84263d55307	1410	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
AnnaBridge	167:e84263d55307	1411	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
AnnaBridge	167:e84263d55307	1412	#define NVIC_EnableIRQ __NVIC_EnableIRQ
AnnaBridge	167:e84263d55307	1413	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
AnnaBridge	167:e84263d55307	1414	#define NVIC_DisableIRQ __NVIC_DisableIRQ
AnnaBridge	167:e84263d55307	1415	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
AnnaBridge	167:e84263d55307	1416	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
AnnaBridge	167:e84263d55307	1417	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
AnnaBridge	167:e84263d55307	1418	#define NVIC_GetActive __NVIC_GetActive
AnnaBridge	167:e84263d55307	1419	#define NVIC_SetPriority __NVIC_SetPriority
AnnaBridge	167:e84263d55307	1420	#define NVIC_GetPriority __NVIC_GetPriority
AnnaBridge	167:e84263d55307	1421	#define NVIC_SystemReset __NVIC_SystemReset
AnnaBridge	167:e84263d55307	1422	#endif /* CMSIS_NVIC_VIRTUAL */
mbed_official	25:ac5b0a371348	1423
AnnaBridge	167:e84263d55307	1424	#ifdef CMSIS_VECTAB_VIRTUAL
AnnaBridge	167:e84263d55307	1425	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1426	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
AnnaBridge	167:e84263d55307	1427	#endif
AnnaBridge	167:e84263d55307	1428	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
AnnaBridge	167:e84263d55307	1429	#else
AnnaBridge	167:e84263d55307	1430	#define NVIC_SetVector __NVIC_SetVector
AnnaBridge	167:e84263d55307	1431	#define NVIC_GetVector __NVIC_GetVector
AnnaBridge	167:e84263d55307	1432	#endif /* (CMSIS_VECTAB_VIRTUAL) */
AnnaBridge	167:e84263d55307	1433
AnnaBridge	167:e84263d55307	1434	#define NVIC_USER_IRQ_OFFSET 16
mbed_official	25:ac5b0a371348	1435
AnnaBridge	167:e84263d55307	1436
AnnaBridge	167:e84263d55307	1437
AnnaBridge	167:e84263d55307	1438	/**
AnnaBridge	167:e84263d55307	1439	\brief Set Priority Grouping
AnnaBridge	167:e84263d55307	1440	\details Sets the priority grouping field using the required unlock sequence.
AnnaBridge	167:e84263d55307	1441	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
AnnaBridge	167:e84263d55307	1442	Only values from 0..7 are used.
AnnaBridge	167:e84263d55307	1443	In case of a conflict between priority grouping and available
AnnaBridge	167:e84263d55307	1444	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:e84263d55307	1445	\param [in] PriorityGroup Priority grouping field.
mbed_official	25:ac5b0a371348	1446	*/
AnnaBridge	167:e84263d55307	1447	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mbed_official	25:ac5b0a371348	1448	{
mbed_official	25:ac5b0a371348	1449	uint32_t reg_value;
mbed_official	25:ac5b0a371348	1450	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official	25:ac5b0a371348	1451
mbed_official	25:ac5b0a371348	1452	reg_value = SCB->AIRCR; /* read old register configuration */
AnnaBridge	167:e84263d55307	1453	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
mbed_official	25:ac5b0a371348	1454	reg_value = (reg_value \|
mbed_official	25:ac5b0a371348	1455	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
AnnaBridge	167:e84263d55307	1456	(PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
mbed_official	25:ac5b0a371348	1457	SCB->AIRCR = reg_value;
mbed_official	25:ac5b0a371348	1458	}
mbed_official	25:ac5b0a371348	1459
mbed_official	25:ac5b0a371348	1460
AnnaBridge	167:e84263d55307	1461	/**
AnnaBridge	167:e84263d55307	1462	\brief Get Priority Grouping
AnnaBridge	167:e84263d55307	1463	\details Reads the priority grouping field from the NVIC Interrupt Controller.
AnnaBridge	167:e84263d55307	1464	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mbed_official	25:ac5b0a371348	1465	*/
AnnaBridge	167:e84263d55307	1466	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
mbed_official	25:ac5b0a371348	1467	{
mbed_official	25:ac5b0a371348	1468	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
mbed_official	25:ac5b0a371348	1469	}
mbed_official	25:ac5b0a371348	1470
mbed_official	25:ac5b0a371348	1471
AnnaBridge	167:e84263d55307	1472	/**
AnnaBridge	167:e84263d55307	1473	\brief Enable Interrupt
AnnaBridge	167:e84263d55307	1474	\details Enables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	1475	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1476	\note IRQn must not be negative.
mbed_official	25:ac5b0a371348	1477	*/
AnnaBridge	167:e84263d55307	1478	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
mbed_official	25:ac5b0a371348	1479	{
AnnaBridge	167:e84263d55307	1480	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1481	{
AnnaBridge	167:e84263d55307	1482	NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1483	}
mbed_official	25:ac5b0a371348	1484	}
mbed_official	25:ac5b0a371348	1485
mbed_official	25:ac5b0a371348	1486
AnnaBridge	167:e84263d55307	1487	/**
AnnaBridge	167:e84263d55307	1488	\brief Get Interrupt Enable status
AnnaBridge	167:e84263d55307	1489	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	1490	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1491	\return 0 Interrupt is not enabled.
AnnaBridge	167:e84263d55307	1492	\return 1 Interrupt is enabled.
AnnaBridge	167:e84263d55307	1493	\note IRQn must not be negative.
mbed_official	25:ac5b0a371348	1494	*/
AnnaBridge	167:e84263d55307	1495	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
mbed_official	25:ac5b0a371348	1496	{
AnnaBridge	167:e84263d55307	1497	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1498	{
AnnaBridge	167:e84263d55307	1499	return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1500	}
AnnaBridge	167:e84263d55307	1501	else
AnnaBridge	167:e84263d55307	1502	{
AnnaBridge	167:e84263d55307	1503	return(0U);
AnnaBridge	167:e84263d55307	1504	}
mbed_official	25:ac5b0a371348	1505	}
mbed_official	25:ac5b0a371348	1506
mbed_official	25:ac5b0a371348	1507
AnnaBridge	167:e84263d55307	1508	/**
AnnaBridge	167:e84263d55307	1509	\brief Disable Interrupt
AnnaBridge	167:e84263d55307	1510	\details Disables a device specific interrupt in the NVIC interrupt controller.
AnnaBridge	167:e84263d55307	1511	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1512	\note IRQn must not be negative.
mbed_official	25:ac5b0a371348	1513	*/
AnnaBridge	167:e84263d55307	1514	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
mbed_official	25:ac5b0a371348	1515	{
AnnaBridge	167:e84263d55307	1516	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1517	{
AnnaBridge	167:e84263d55307	1518	NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1519	__DSB();
AnnaBridge	167:e84263d55307	1520	__ISB();
AnnaBridge	167:e84263d55307	1521	}
mbed_official	25:ac5b0a371348	1522	}
mbed_official	25:ac5b0a371348	1523
mbed_official	25:ac5b0a371348	1524
AnnaBridge	167:e84263d55307	1525	/**
AnnaBridge	167:e84263d55307	1526	\brief Get Pending Interrupt
AnnaBridge	167:e84263d55307	1527	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
AnnaBridge	167:e84263d55307	1528	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1529	\return 0 Interrupt status is not pending.
AnnaBridge	167:e84263d55307	1530	\return 1 Interrupt status is pending.
AnnaBridge	167:e84263d55307	1531	\note IRQn must not be negative.
mbed_official	25:ac5b0a371348	1532	*/
AnnaBridge	167:e84263d55307	1533	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbed_official	25:ac5b0a371348	1534	{
AnnaBridge	167:e84263d55307	1535	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1536	{
AnnaBridge	167:e84263d55307	1537	return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
AnnaBridge	167:e84263d55307	1538	}
AnnaBridge	167:e84263d55307	1539	else
AnnaBridge	167:e84263d55307	1540	{
AnnaBridge	167:e84263d55307	1541	return(0U);
AnnaBridge	167:e84263d55307	1542	}
mbed_official	25:ac5b0a371348	1543	}
mbed_official	25:ac5b0a371348	1544
mbed_official	25:ac5b0a371348	1545
AnnaBridge	167:e84263d55307	1546	/**
AnnaBridge	167:e84263d55307	1547	\brief Set Pending Interrupt
AnnaBridge	167:e84263d55307	1548	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:e84263d55307	1549	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1550	\note IRQn must not be negative.
mbed_official	25:ac5b0a371348	1551	*/
AnnaBridge	167:e84263d55307	1552	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official	25:ac5b0a371348	1553	{
AnnaBridge	167:e84263d55307	1554	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1555	{
AnnaBridge	167:e84263d55307	1556	NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official	25:ac5b0a371348	1557	}
mbed_official	25:ac5b0a371348	1558	}
mbed_official	25:ac5b0a371348	1559
mbed_official	25:ac5b0a371348	1560
AnnaBridge	167:e84263d55307	1561	/**
AnnaBridge	167:e84263d55307	1562	\brief Clear Pending Interrupt
AnnaBridge	167:e84263d55307	1563	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
AnnaBridge	167:e84263d55307	1564	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1565	\note IRQn must not be negative.
AnnaBridge	167:e84263d55307	1566	*/
AnnaBridge	167:e84263d55307	1567	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1568	{
AnnaBridge	167:e84263d55307	1569	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1570	{
AnnaBridge	167:e84263d55307	1571	NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
AnnaBridge	167:e84263d55307	1572	}
AnnaBridge	167:e84263d55307	1573	}
mbed_official	25:ac5b0a371348	1574
mbed_official	25:ac5b0a371348	1575
AnnaBridge	167:e84263d55307	1576	/**
AnnaBridge	167:e84263d55307	1577	\brief Get Active Interrupt
AnnaBridge	167:e84263d55307	1578	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
AnnaBridge	167:e84263d55307	1579	\param [in] IRQn Device specific interrupt number.
AnnaBridge	167:e84263d55307	1580	\return 0 Interrupt status is not active.
AnnaBridge	167:e84263d55307	1581	\return 1 Interrupt status is active.
AnnaBridge	167:e84263d55307	1582	\note IRQn must not be negative.
mbed_official	25:ac5b0a371348	1583	*/
AnnaBridge	167:e84263d55307	1584	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
mbed_official	25:ac5b0a371348	1585	{
AnnaBridge	167:e84263d55307	1586	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1587	{
AnnaBridge	167:e84263d55307	1588	return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official	25:ac5b0a371348	1589	}
AnnaBridge	167:e84263d55307	1590	else
AnnaBridge	167:e84263d55307	1591	{
AnnaBridge	167:e84263d55307	1592	return(0U);
mbed_official	25:ac5b0a371348	1593	}
mbed_official	25:ac5b0a371348	1594	}
mbed_official	25:ac5b0a371348	1595
mbed_official	25:ac5b0a371348	1596
AnnaBridge	167:e84263d55307	1597	/**
AnnaBridge	167:e84263d55307	1598	\brief Set Interrupt Priority
AnnaBridge	167:e84263d55307	1599	\details Sets the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:e84263d55307	1600	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	1601	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	1602	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	1603	\param [in] priority Priority to set.
AnnaBridge	167:e84263d55307	1604	\note The priority cannot be set for every processor exception.
AnnaBridge	167:e84263d55307	1605	*/
AnnaBridge	167:e84263d55307	1606	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	167:e84263d55307	1607	{
AnnaBridge	167:e84263d55307	1608	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1609	{
AnnaBridge	167:e84263d55307	1610	NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:e84263d55307	1611	}
AnnaBridge	167:e84263d55307	1612	else
AnnaBridge	167:e84263d55307	1613	{
AnnaBridge	167:e84263d55307	1614	SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
AnnaBridge	167:e84263d55307	1615	}
AnnaBridge	167:e84263d55307	1616	}
AnnaBridge	167:e84263d55307	1617
mbed_official	25:ac5b0a371348	1618
AnnaBridge	167:e84263d55307	1619	/**
AnnaBridge	167:e84263d55307	1620	\brief Get Interrupt Priority
AnnaBridge	167:e84263d55307	1621	\details Reads the priority of a device specific interrupt or a processor exception.
AnnaBridge	167:e84263d55307	1622	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	1623	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	1624	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	1625	\return Interrupt Priority.
AnnaBridge	167:e84263d55307	1626	Value is aligned automatically to the implemented priority bits of the microcontroller.
AnnaBridge	167:e84263d55307	1627	*/
AnnaBridge	167:e84263d55307	1628	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1629	{
mbed_official	25:ac5b0a371348	1630
AnnaBridge	167:e84263d55307	1631	if ((int32_t)(IRQn) >= 0)
AnnaBridge	167:e84263d55307	1632	{
AnnaBridge	167:e84263d55307	1633	return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	1634	}
AnnaBridge	167:e84263d55307	1635	else
AnnaBridge	167:e84263d55307	1636	{
AnnaBridge	167:e84263d55307	1637	return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
AnnaBridge	167:e84263d55307	1638	}
AnnaBridge	167:e84263d55307	1639	}
AnnaBridge	167:e84263d55307	1640
AnnaBridge	167:e84263d55307	1641
AnnaBridge	167:e84263d55307	1642	/**
AnnaBridge	167:e84263d55307	1643	\brief Encode Priority
AnnaBridge	167:e84263d55307	1644	\details Encodes the priority for an interrupt with the given priority group,
AnnaBridge	167:e84263d55307	1645	preemptive priority value, and subpriority value.
AnnaBridge	167:e84263d55307	1646	In case of a conflict between priority grouping and available
AnnaBridge	167:e84263d55307	1647	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
AnnaBridge	167:e84263d55307	1648	\param [in] PriorityGroup Used priority group.
AnnaBridge	167:e84263d55307	1649	\param [in] PreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	167:e84263d55307	1650	\param [in] SubPriority Subpriority value (starting from 0).
AnnaBridge	167:e84263d55307	1651	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mbed_official	25:ac5b0a371348	1652	*/
mbed_official	25:ac5b0a371348	1653	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mbed_official	25:ac5b0a371348	1654	{
mbed_official	25:ac5b0a371348	1655	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official	25:ac5b0a371348	1656	uint32_t PreemptPriorityBits;
mbed_official	25:ac5b0a371348	1657	uint32_t SubPriorityBits;
mbed_official	25:ac5b0a371348	1658
mbed_official	25:ac5b0a371348	1659	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official	25:ac5b0a371348	1660	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mbed_official	25:ac5b0a371348	1661
mbed_official	25:ac5b0a371348	1662	return (
mbed_official	25:ac5b0a371348	1663	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
mbed_official	25:ac5b0a371348	1664	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
mbed_official	25:ac5b0a371348	1665	);
mbed_official	25:ac5b0a371348	1666	}
mbed_official	25:ac5b0a371348	1667
mbed_official	25:ac5b0a371348	1668
AnnaBridge	167:e84263d55307	1669	/**
AnnaBridge	167:e84263d55307	1670	\brief Decode Priority
AnnaBridge	167:e84263d55307	1671	\details Decodes an interrupt priority value with a given priority group to
AnnaBridge	167:e84263d55307	1672	preemptive priority value and subpriority value.
AnnaBridge	167:e84263d55307	1673	In case of a conflict between priority grouping and available
AnnaBridge	167:e84263d55307	1674	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
AnnaBridge	167:e84263d55307	1675	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
AnnaBridge	167:e84263d55307	1676	\param [in] PriorityGroup Used priority group.
AnnaBridge	167:e84263d55307	1677	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
AnnaBridge	167:e84263d55307	1678	\param [out] pSubPriority Subpriority value (starting from 0).
mbed_official	25:ac5b0a371348	1679	*/
AnnaBridge	167:e84263d55307	1680	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
mbed_official	25:ac5b0a371348	1681	{
mbed_official	25:ac5b0a371348	1682	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official	25:ac5b0a371348	1683	uint32_t PreemptPriorityBits;
mbed_official	25:ac5b0a371348	1684	uint32_t SubPriorityBits;
mbed_official	25:ac5b0a371348	1685
mbed_official	25:ac5b0a371348	1686	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official	25:ac5b0a371348	1687	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mbed_official	25:ac5b0a371348	1688
mbed_official	25:ac5b0a371348	1689	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
mbed_official	25:ac5b0a371348	1690	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
mbed_official	25:ac5b0a371348	1691	}
mbed_official	25:ac5b0a371348	1692
mbed_official	25:ac5b0a371348	1693
AnnaBridge	167:e84263d55307	1694	/**
AnnaBridge	167:e84263d55307	1695	\brief Set Interrupt Vector
AnnaBridge	167:e84263d55307	1696	\details Sets an interrupt vector in SRAM based interrupt vector table.
AnnaBridge	167:e84263d55307	1697	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	1698	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	1699	VTOR must been relocated to SRAM before.
AnnaBridge	167:e84263d55307	1700	\param [in] IRQn Interrupt number
AnnaBridge	167:e84263d55307	1701	\param [in] vector Address of interrupt handler function
AnnaBridge	167:e84263d55307	1702	*/
AnnaBridge	167:e84263d55307	1703	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
AnnaBridge	167:e84263d55307	1704	{
AnnaBridge	167:e84263d55307	1705	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:e84263d55307	1706	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
AnnaBridge	167:e84263d55307	1707	}
AnnaBridge	167:e84263d55307	1708
mbed_official	25:ac5b0a371348	1709
AnnaBridge	167:e84263d55307	1710	/**
AnnaBridge	167:e84263d55307	1711	\brief Get Interrupt Vector
AnnaBridge	167:e84263d55307	1712	\details Reads an interrupt vector from interrupt vector table.
AnnaBridge	167:e84263d55307	1713	The interrupt number can be positive to specify a device specific interrupt,
AnnaBridge	167:e84263d55307	1714	or negative to specify a processor exception.
AnnaBridge	167:e84263d55307	1715	\param [in] IRQn Interrupt number.
AnnaBridge	167:e84263d55307	1716	\return Address of interrupt handler function
mbed_official	25:ac5b0a371348	1717	*/
AnnaBridge	167:e84263d55307	1718	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	1719	{
AnnaBridge	167:e84263d55307	1720	uint32_t vectors = (uint32_t )SCB->VTOR;
AnnaBridge	167:e84263d55307	1721	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
AnnaBridge	167:e84263d55307	1722	}
AnnaBridge	167:e84263d55307	1723
AnnaBridge	167:e84263d55307	1724
AnnaBridge	167:e84263d55307	1725	/**
AnnaBridge	167:e84263d55307	1726	\brief System Reset
AnnaBridge	167:e84263d55307	1727	\details Initiates a system reset request to reset the MCU.
AnnaBridge	167:e84263d55307	1728	*/
AnnaBridge	167:e84263d55307	1729	__STATIC_INLINE void __NVIC_SystemReset(void)
mbed_official	25:ac5b0a371348	1730	{
mbed_official	25:ac5b0a371348	1731	__DSB(); /* Ensure all outstanding memory accesses included
mbed_official	25:ac5b0a371348	1732	buffered write are completed before reset */
mbed_official	25:ac5b0a371348	1733	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
mbed_official	25:ac5b0a371348	1734	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
mbed_official	25:ac5b0a371348	1735	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
mbed_official	25:ac5b0a371348	1736	__DSB(); /* Ensure completion of memory access */
AnnaBridge	167:e84263d55307	1737
AnnaBridge	167:e84263d55307	1738	for(;;) /* wait until reset */
AnnaBridge	167:e84263d55307	1739	{
AnnaBridge	167:e84263d55307	1740	__NOP();
AnnaBridge	167:e84263d55307	1741	}
mbed_official	25:ac5b0a371348	1742	}
mbed_official	25:ac5b0a371348	1743
mbed_official	25:ac5b0a371348	1744	/@} end of CMSIS_Core_NVICFunctions /
mbed_official	25:ac5b0a371348	1745
mbed_official	25:ac5b0a371348	1746
AnnaBridge	167:e84263d55307	1747	/* ########################## FPU functions #################################### */
AnnaBridge	167:e84263d55307	1748	/**
AnnaBridge	167:e84263d55307	1749	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	1750	\defgroup CMSIS_Core_FpuFunctions FPU Functions
AnnaBridge	167:e84263d55307	1751	\brief Function that provides FPU type.
mbed_official	25:ac5b0a371348	1752	@{
mbed_official	25:ac5b0a371348	1753	*/
mbed_official	25:ac5b0a371348	1754
AnnaBridge	167:e84263d55307	1755	/**
AnnaBridge	167:e84263d55307	1756	\brief get FPU type
AnnaBridge	167:e84263d55307	1757	\details returns the FPU type
AnnaBridge	167:e84263d55307	1758	\returns
AnnaBridge	167:e84263d55307	1759	- \b 0: No FPU
AnnaBridge	167:e84263d55307	1760	- \b 1: Single precision FPU
AnnaBridge	167:e84263d55307	1761	- \b 2: Double + Single precision FPU
AnnaBridge	167:e84263d55307	1762	*/
AnnaBridge	167:e84263d55307	1763	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
AnnaBridge	167:e84263d55307	1764	{
AnnaBridge	167:e84263d55307	1765	return 0U; /* No FPU */
AnnaBridge	167:e84263d55307	1766	}
mbed_official	25:ac5b0a371348	1767
mbed_official	25:ac5b0a371348	1768
AnnaBridge	167:e84263d55307	1769	/@} end of CMSIS_Core_FpuFunctions /
AnnaBridge	167:e84263d55307	1770
AnnaBridge	167:e84263d55307	1771
mbed_official	25:ac5b0a371348	1772
AnnaBridge	167:e84263d55307	1773	/* ################################## SysTick function ############################################ */
AnnaBridge	167:e84263d55307	1774	/**
AnnaBridge	167:e84263d55307	1775	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	1776	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
AnnaBridge	167:e84263d55307	1777	\brief Functions that configure the System.
AnnaBridge	167:e84263d55307	1778	@{
AnnaBridge	167:e84263d55307	1779	*/
mbed_official	25:ac5b0a371348	1780
AnnaBridge	167:e84263d55307	1781	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
mbed_official	25:ac5b0a371348	1782
AnnaBridge	167:e84263d55307	1783	/**
AnnaBridge	167:e84263d55307	1784	\brief System Tick Configuration
AnnaBridge	167:e84263d55307	1785	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
AnnaBridge	167:e84263d55307	1786	Counter is in free running mode to generate periodic interrupts.
AnnaBridge	167:e84263d55307	1787	\param [in] ticks Number of ticks between two interrupts.
AnnaBridge	167:e84263d55307	1788	\return 0 Function succeeded.
AnnaBridge	167:e84263d55307	1789	\return 1 Function failed.
AnnaBridge	167:e84263d55307	1790	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
AnnaBridge	167:e84263d55307	1791	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
AnnaBridge	167:e84263d55307	1792	must contain a vendor-specific implementation of this function.
mbed_official	25:ac5b0a371348	1793	*/
mbed_official	25:ac5b0a371348	1794	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbed_official	25:ac5b0a371348	1795	{
AnnaBridge	167:e84263d55307	1796	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
AnnaBridge	167:e84263d55307	1797	{
AnnaBridge	167:e84263d55307	1798	return (1UL); /* Reload value impossible */
AnnaBridge	167:e84263d55307	1799	}
mbed_official	25:ac5b0a371348	1800
mbed_official	25:ac5b0a371348	1801	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official	25:ac5b0a371348	1802	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official	25:ac5b0a371348	1803	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official	25:ac5b0a371348	1804	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
mbed_official	25:ac5b0a371348	1805	SysTick_CTRL_TICKINT_Msk \|
mbed_official	25:ac5b0a371348	1806	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official	25:ac5b0a371348	1807	return (0UL); /* Function successful */
mbed_official	25:ac5b0a371348	1808	}
mbed_official	25:ac5b0a371348	1809
mbed_official	25:ac5b0a371348	1810	#endif
mbed_official	25:ac5b0a371348	1811
mbed_official	25:ac5b0a371348	1812	/@} end of CMSIS_Core_SysTickFunctions /
mbed_official	25:ac5b0a371348	1813
mbed_official	25:ac5b0a371348	1814
mbed_official	25:ac5b0a371348	1815
mbed_official	25:ac5b0a371348	1816	/* ##################################### Debug In/Output function ########################################### */
AnnaBridge	167:e84263d55307	1817	/**
AnnaBridge	167:e84263d55307	1818	\ingroup CMSIS_Core_FunctionInterface
AnnaBridge	167:e84263d55307	1819	\defgroup CMSIS_core_DebugFunctions ITM Functions
AnnaBridge	167:e84263d55307	1820	\brief Functions that access the ITM debug interface.
mbed_official	25:ac5b0a371348	1821	@{
mbed_official	25:ac5b0a371348	1822	*/
mbed_official	25:ac5b0a371348	1823
AnnaBridge	167:e84263d55307	1824	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
AnnaBridge	167:e84263d55307	1825	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
mbed_official	25:ac5b0a371348	1826
mbed_official	25:ac5b0a371348	1827
AnnaBridge	167:e84263d55307	1828	/**
AnnaBridge	167:e84263d55307	1829	\brief ITM Send Character
AnnaBridge	167:e84263d55307	1830	\details Transmits a character via the ITM channel 0, and
AnnaBridge	167:e84263d55307	1831	\li Just returns when no debugger is connected that has booked the output.
AnnaBridge	167:e84263d55307	1832	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
AnnaBridge	167:e84263d55307	1833	\param [in] ch Character to transmit.
AnnaBridge	167:e84263d55307	1834	\returns Character to transmit.
mbed_official	25:ac5b0a371348	1835	*/
mbed_official	25:ac5b0a371348	1836	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mbed_official	25:ac5b0a371348	1837	{
mbed_official	25:ac5b0a371348	1838	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
mbed_official	25:ac5b0a371348	1839	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
mbed_official	25:ac5b0a371348	1840	{
AnnaBridge	167:e84263d55307	1841	while (ITM->PORT[0U].u32 == 0UL)
AnnaBridge	167:e84263d55307	1842	{
AnnaBridge	167:e84263d55307	1843	__NOP();
AnnaBridge	167:e84263d55307	1844	}
AnnaBridge	167:e84263d55307	1845	ITM->PORT[0U].u8 = (uint8_t)ch;
mbed_official	25:ac5b0a371348	1846	}
mbed_official	25:ac5b0a371348	1847	return (ch);
mbed_official	25:ac5b0a371348	1848	}
mbed_official	25:ac5b0a371348	1849
mbed_official	25:ac5b0a371348	1850
AnnaBridge	167:e84263d55307	1851	/**
AnnaBridge	167:e84263d55307	1852	\brief ITM Receive Character
AnnaBridge	167:e84263d55307	1853	\details Inputs a character via the external variable \ref ITM_RxBuffer.
AnnaBridge	167:e84263d55307	1854	\return Received character.
AnnaBridge	167:e84263d55307	1855	\return -1 No character pending.
mbed_official	25:ac5b0a371348	1856	*/
AnnaBridge	167:e84263d55307	1857	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
AnnaBridge	167:e84263d55307	1858	{
mbed_official	25:ac5b0a371348	1859	int32_t ch = -1; /* no character available */
mbed_official	25:ac5b0a371348	1860
AnnaBridge	167:e84263d55307	1861	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
AnnaBridge	167:e84263d55307	1862	{
mbed_official	25:ac5b0a371348	1863	ch = ITM_RxBuffer;
mbed_official	25:ac5b0a371348	1864	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mbed_official	25:ac5b0a371348	1865	}
mbed_official	25:ac5b0a371348	1866
mbed_official	25:ac5b0a371348	1867	return (ch);
mbed_official	25:ac5b0a371348	1868	}
mbed_official	25:ac5b0a371348	1869
mbed_official	25:ac5b0a371348	1870
AnnaBridge	167:e84263d55307	1871	/**
AnnaBridge	167:e84263d55307	1872	\brief ITM Check Character
AnnaBridge	167:e84263d55307	1873	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
AnnaBridge	167:e84263d55307	1874	\return 0 No character available.
AnnaBridge	167:e84263d55307	1875	\return 1 Character available.
mbed_official	25:ac5b0a371348	1876	*/
AnnaBridge	167:e84263d55307	1877	__STATIC_INLINE int32_t ITM_CheckChar (void)
AnnaBridge	167:e84263d55307	1878	{
mbed_official	25:ac5b0a371348	1879
AnnaBridge	167:e84263d55307	1880	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
AnnaBridge	167:e84263d55307	1881	{
AnnaBridge	167:e84263d55307	1882	return (0); /* no character available */
AnnaBridge	167:e84263d55307	1883	}
AnnaBridge	167:e84263d55307	1884	else
AnnaBridge	167:e84263d55307	1885	{
AnnaBridge	167:e84263d55307	1886	return (1); /* character available */
mbed_official	25:ac5b0a371348	1887	}
mbed_official	25:ac5b0a371348	1888	}
mbed_official	25:ac5b0a371348	1889
mbed_official	25:ac5b0a371348	1890	/@} end of CMSIS_core_DebugFunctions /
mbed_official	25:ac5b0a371348	1891
mbed_official	25:ac5b0a371348	1892
mbed_official	25:ac5b0a371348	1893
mbed_official	25:ac5b0a371348	1894
mbed_official	25:ac5b0a371348	1895	#ifdef __cplusplus
mbed_official	25:ac5b0a371348	1896	}
mbed_official	25:ac5b0a371348	1897	#endif
mbed_official	25:ac5b0a371348	1898
mbed_official	25:ac5b0a371348	1899	#endif /* __CORE_SC300_H_DEPENDANT */
mbed_official	25:ac5b0a371348	1900
mbed_official	25:ac5b0a371348	1901	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	27 Oct 2017
Imports:	56
Forks:	0
Commits:	182
Dependents:	41
Dependencies:	0
Followers:	12

This repository is Public (Unlisted).

cmsis/core_sc300.h@181:36facd806e4a, 2018-07-30 (annotated)

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