mbed-dev-f303 - mbed library sources. Supersedes mbed-src.

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mbed library sources. Supersedes mbed-src.

Dependents: Hobbyking_Cheetah_Compact Hobbyking_Cheetah_Compact_DRV8323_14bit Hobbyking_Cheetah_Compact_DRV8323_V51_201907 HKC_MiniCheetah ... more

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cmsis/core_ca.h@181:36facd806e4a, 2018-07-30 (annotated)

Committer:: benkatz
Date:: Mon Jul 30 20:31:44 2018 +0000
Revision:: 181:36facd806e4a
Parent:: 167:e84263d55307

going on the robot.  fixed a dumb bug in float_to_uint

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:e84263d55307	1	/************************************************************************//
AnnaBridge	167:e84263d55307	2	* @file core_ca.h
AnnaBridge	167:e84263d55307	3	* @brief CMSIS Cortex-A Core Peripheral Access Layer Header File
AnnaBridge	167:e84263d55307	4	* @version V1.00
AnnaBridge	167:e84263d55307	5	* @date 22. Feb 2017
AnnaBridge	167:e84263d55307	6	******************************************************************************/
AnnaBridge	167:e84263d55307	7	/*
AnnaBridge	167:e84263d55307	8	* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge	167:e84263d55307	9	*
AnnaBridge	167:e84263d55307	10	* SPDX-License-Identifier: Apache-2.0
AnnaBridge	167:e84263d55307	11	*
AnnaBridge	167:e84263d55307	12	* Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge	167:e84263d55307	13	* not use this file except in compliance with the License.
AnnaBridge	167:e84263d55307	14	* You may obtain a copy of the License at
AnnaBridge	167:e84263d55307	15	*
AnnaBridge	167:e84263d55307	16	* www.apache.org/licenses/LICENSE-2.0
AnnaBridge	167:e84263d55307	17	*
AnnaBridge	167:e84263d55307	18	* Unless required by applicable law or agreed to in writing, software
AnnaBridge	167:e84263d55307	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge	167:e84263d55307	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge	167:e84263d55307	21	* See the License for the specific language governing permissions and
AnnaBridge	167:e84263d55307	22	* limitations under the License.
AnnaBridge	167:e84263d55307	23	*/
AnnaBridge	167:e84263d55307	24
AnnaBridge	167:e84263d55307	25	#if defined ( __ICCARM__ )
AnnaBridge	167:e84263d55307	26	#pragma system_include /* treat file as system include file for MISRA check */
AnnaBridge	167:e84263d55307	27	#endif
AnnaBridge	167:e84263d55307	28
AnnaBridge	167:e84263d55307	29	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	30	extern "C" {
AnnaBridge	167:e84263d55307	31	#endif
AnnaBridge	167:e84263d55307	32
AnnaBridge	167:e84263d55307	33	#ifndef __CORE_CA_H_GENERIC
AnnaBridge	167:e84263d55307	34	#define __CORE_CA_H_GENERIC
AnnaBridge	167:e84263d55307	35
AnnaBridge	167:e84263d55307	36
AnnaBridge	167:e84263d55307	37	/*******************************************************************************
AnnaBridge	167:e84263d55307	38	* CMSIS definitions
AnnaBridge	167:e84263d55307	39	******************************************************************************/
AnnaBridge	167:e84263d55307	40
AnnaBridge	167:e84263d55307	41	/* CMSIS CA definitions */
AnnaBridge	167:e84263d55307	42	#define __CA_CMSIS_VERSION_MAIN (1U) /!< \brief [31:16] CMSIS HAL main version /
AnnaBridge	167:e84263d55307	43	#define __CA_CMSIS_VERSION_SUB (0U) /!< \brief [15:0] CMSIS HAL sub version /
AnnaBridge	167:e84263d55307	44	#define __CA_CMSIS_VERSION ((__CA_CMSIS_VERSION_MAIN << 16U) \| \
AnnaBridge	167:e84263d55307	45	__CA_CMSIS_VERSION_SUB ) /!< \brief CMSIS HAL version number /
AnnaBridge	167:e84263d55307	46
AnnaBridge	167:e84263d55307	47	#if defined ( __CC_ARM )
AnnaBridge	167:e84263d55307	48	#if defined __TARGET_FPU_VFP
AnnaBridge	167:e84263d55307	49	#if (__FPU_PRESENT == 1)
AnnaBridge	167:e84263d55307	50	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	51	#else
AnnaBridge	167:e84263d55307	52	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	53	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	54	#endif
AnnaBridge	167:e84263d55307	55	#else
AnnaBridge	167:e84263d55307	56	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	57	#endif
AnnaBridge	167:e84263d55307	58
AnnaBridge	167:e84263d55307	59	#elif defined ( __ICCARM__ )
AnnaBridge	167:e84263d55307	60	#if defined __ARMVFP__
AnnaBridge	167:e84263d55307	61	#if (__FPU_PRESENT == 1)
AnnaBridge	167:e84263d55307	62	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	63	#else
AnnaBridge	167:e84263d55307	64	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	65	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	66	#endif
AnnaBridge	167:e84263d55307	67	#else
AnnaBridge	167:e84263d55307	68	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	69	#endif
AnnaBridge	167:e84263d55307	70
AnnaBridge	167:e84263d55307	71	#elif defined ( __TMS470__ )
AnnaBridge	167:e84263d55307	72	#if defined __TI_VFP_SUPPORT__
AnnaBridge	167:e84263d55307	73	#if (__FPU_PRESENT == 1)
AnnaBridge	167:e84263d55307	74	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	75	#else
AnnaBridge	167:e84263d55307	76	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	77	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	78	#endif
AnnaBridge	167:e84263d55307	79	#else
AnnaBridge	167:e84263d55307	80	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	81	#endif
AnnaBridge	167:e84263d55307	82
AnnaBridge	167:e84263d55307	83	#elif defined ( __GNUC__ )
AnnaBridge	167:e84263d55307	84	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
AnnaBridge	167:e84263d55307	85	#if (__FPU_PRESENT == 1)
AnnaBridge	167:e84263d55307	86	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	87	#else
AnnaBridge	167:e84263d55307	88	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	89	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	90	#endif
AnnaBridge	167:e84263d55307	91	#else
AnnaBridge	167:e84263d55307	92	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	93	#endif
AnnaBridge	167:e84263d55307	94
AnnaBridge	167:e84263d55307	95	#elif defined ( __TASKING__ )
AnnaBridge	167:e84263d55307	96	#if defined __FPU_VFP__
AnnaBridge	167:e84263d55307	97	#if (__FPU_PRESENT == 1)
AnnaBridge	167:e84263d55307	98	#define __FPU_USED 1U
AnnaBridge	167:e84263d55307	99	#else
AnnaBridge	167:e84263d55307	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
AnnaBridge	167:e84263d55307	101	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	102	#endif
AnnaBridge	167:e84263d55307	103	#else
AnnaBridge	167:e84263d55307	104	#define __FPU_USED 0U
AnnaBridge	167:e84263d55307	105	#endif
AnnaBridge	167:e84263d55307	106	#endif
AnnaBridge	167:e84263d55307	107
AnnaBridge	167:e84263d55307	108	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
AnnaBridge	167:e84263d55307	109
AnnaBridge	167:e84263d55307	110	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	111	}
AnnaBridge	167:e84263d55307	112	#endif
AnnaBridge	167:e84263d55307	113
AnnaBridge	167:e84263d55307	114	#endif /* __CORE_CA_H_GENERIC */
AnnaBridge	167:e84263d55307	115
AnnaBridge	167:e84263d55307	116	#ifndef __CMSIS_GENERIC
AnnaBridge	167:e84263d55307	117
AnnaBridge	167:e84263d55307	118	#ifndef __CORE_CA_H_DEPENDANT
AnnaBridge	167:e84263d55307	119	#define __CORE_CA_H_DEPENDANT
AnnaBridge	167:e84263d55307	120
AnnaBridge	167:e84263d55307	121	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	122	extern "C" {
AnnaBridge	167:e84263d55307	123	#endif
AnnaBridge	167:e84263d55307	124
AnnaBridge	167:e84263d55307	125	/* check device defines and use defaults */
AnnaBridge	167:e84263d55307	126	#if defined __CHECK_DEVICE_DEFINES
AnnaBridge	167:e84263d55307	127	#ifndef __CA_REV
AnnaBridge	167:e84263d55307	128	#define __CA_REV 0x0000U
AnnaBridge	167:e84263d55307	129	#warning "__CA_REV not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	130	#endif
AnnaBridge	167:e84263d55307	131
AnnaBridge	167:e84263d55307	132	#ifndef __FPU_PRESENT
AnnaBridge	167:e84263d55307	133	#define __FPU_PRESENT 0U
AnnaBridge	167:e84263d55307	134	#warning "__FPU_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	135	#endif
AnnaBridge	167:e84263d55307	136
AnnaBridge	167:e84263d55307	137	#ifndef __MPU_PRESENT
AnnaBridge	167:e84263d55307	138	#define __MPU_PRESENT 0U
AnnaBridge	167:e84263d55307	139	#warning "__MPU_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	140	#endif
AnnaBridge	167:e84263d55307	141
AnnaBridge	167:e84263d55307	142	#ifndef __GIC_PRESENT
AnnaBridge	167:e84263d55307	143	#define __GIC_PRESENT 1U
AnnaBridge	167:e84263d55307	144	#warning "__GIC_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	145	#endif
AnnaBridge	167:e84263d55307	146
AnnaBridge	167:e84263d55307	147	#ifndef __TIM_PRESENT
AnnaBridge	167:e84263d55307	148	#define __TIM_PRESENT 1U
AnnaBridge	167:e84263d55307	149	#warning "__TIM_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	150	#endif
AnnaBridge	167:e84263d55307	151
AnnaBridge	167:e84263d55307	152	#ifndef __L2C_PRESENT
AnnaBridge	167:e84263d55307	153	#define __L2C_PRESENT 0U
AnnaBridge	167:e84263d55307	154	#warning "__L2C_PRESENT not defined in device header file; using default!"
AnnaBridge	167:e84263d55307	155	#endif
AnnaBridge	167:e84263d55307	156	#endif
AnnaBridge	167:e84263d55307	157
AnnaBridge	167:e84263d55307	158	/* IO definitions (access restrictions to peripheral registers) */
AnnaBridge	167:e84263d55307	159	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	160	#define __I volatile /!< \brief Defines 'read only' permissions /
AnnaBridge	167:e84263d55307	161	#else
AnnaBridge	167:e84263d55307	162	#define __I volatile const /!< \brief Defines 'read only' permissions /
AnnaBridge	167:e84263d55307	163	#endif
AnnaBridge	167:e84263d55307	164	#define __O volatile /!< \brief Defines 'write only' permissions /
AnnaBridge	167:e84263d55307	165	#define __IO volatile /!< \brief Defines 'read / write' permissions /
AnnaBridge	167:e84263d55307	166
AnnaBridge	167:e84263d55307	167	/* following defines should be used for structure members */
AnnaBridge	167:e84263d55307	168	#define __IM volatile const /!< \brief Defines 'read only' structure member permissions /
AnnaBridge	167:e84263d55307	169	#define __OM volatile /!< \brief Defines 'write only' structure member permissions /
AnnaBridge	167:e84263d55307	170	#define __IOM volatile /!< \brief Defines 'read / write' structure member permissions /
AnnaBridge	167:e84263d55307	171
AnnaBridge	167:e84263d55307	172
AnnaBridge	167:e84263d55307	173	/*******************************************************************************
AnnaBridge	167:e84263d55307	174	* Register Abstraction
AnnaBridge	167:e84263d55307	175	Core Register contain:
AnnaBridge	167:e84263d55307	176	- CPSR
AnnaBridge	167:e84263d55307	177	- CP15 Registers
AnnaBridge	167:e84263d55307	178	- L2C-310 Cache Controller
AnnaBridge	167:e84263d55307	179	- Generic Interrupt Controller Distributor
AnnaBridge	167:e84263d55307	180	- Generic Interrupt Controller Interface
AnnaBridge	167:e84263d55307	181	******************************************************************************/
AnnaBridge	167:e84263d55307	182
AnnaBridge	167:e84263d55307	183	/* Core Register CPSR */
AnnaBridge	167:e84263d55307	184	typedef union
AnnaBridge	167:e84263d55307	185	{
AnnaBridge	167:e84263d55307	186	struct
AnnaBridge	167:e84263d55307	187	{
AnnaBridge	167:e84263d55307	188	uint32_t M:5; /!< \brief bit: 0.. 4 Mode field /
AnnaBridge	167:e84263d55307	189	uint32_t T:1; /!< \brief bit: 5 Thumb execution state bit /
AnnaBridge	167:e84263d55307	190	uint32_t F:1; /!< \brief bit: 6 FIQ mask bit /
AnnaBridge	167:e84263d55307	191	uint32_t I:1; /!< \brief bit: 7 IRQ mask bit /
AnnaBridge	167:e84263d55307	192	uint32_t A:1; /!< \brief bit: 8 Asynchronous abort mask bit /
AnnaBridge	167:e84263d55307	193	uint32_t E:1; /!< \brief bit: 9 Endianness execution state bit /
AnnaBridge	167:e84263d55307	194	uint32_t IT1:6; /!< \brief bit: 10..15 If-Then execution state bits 2-7 /
AnnaBridge	167:e84263d55307	195	uint32_t GE:4; /!< \brief bit: 16..19 Greater than or Equal flags /
AnnaBridge	167:e84263d55307	196	uint32_t _reserved0:4; /!< \brief bit: 20..23 Reserved /
AnnaBridge	167:e84263d55307	197	uint32_t J:1; /!< \brief bit: 24 Jazelle bit /
AnnaBridge	167:e84263d55307	198	uint32_t IT0:2; /!< \brief bit: 25..26 If-Then execution state bits 0-1 /
AnnaBridge	167:e84263d55307	199	uint32_t Q:1; /!< \brief bit: 27 Saturation condition flag /
AnnaBridge	167:e84263d55307	200	uint32_t V:1; /!< \brief bit: 28 Overflow condition code flag /
AnnaBridge	167:e84263d55307	201	uint32_t C:1; /!< \brief bit: 29 Carry condition code flag /
AnnaBridge	167:e84263d55307	202	uint32_t Z:1; /!< \brief bit: 30 Zero condition code flag /
AnnaBridge	167:e84263d55307	203	uint32_t N:1; /!< \brief bit: 31 Negative condition code flag /
AnnaBridge	167:e84263d55307	204	} b; /!< \brief Structure used for bit access /
AnnaBridge	167:e84263d55307	205	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	167:e84263d55307	206	} CPSR_Type;
AnnaBridge	167:e84263d55307	207
AnnaBridge	167:e84263d55307	208	/* CPSR Register Definitions */
AnnaBridge	167:e84263d55307	209	#define CPSR_N_Pos 31U /!< \brief CPSR: N Position /
AnnaBridge	167:e84263d55307	210	#define CPSR_N_Msk (1UL << CPSR_N_Pos) /!< \brief CPSR: N Mask /
AnnaBridge	167:e84263d55307	211
AnnaBridge	167:e84263d55307	212	#define CPSR_Z_Pos 30U /!< \brief CPSR: Z Position /
AnnaBridge	167:e84263d55307	213	#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /!< \brief CPSR: Z Mask /
AnnaBridge	167:e84263d55307	214
AnnaBridge	167:e84263d55307	215	#define CPSR_C_Pos 29U /!< \brief CPSR: C Position /
AnnaBridge	167:e84263d55307	216	#define CPSR_C_Msk (1UL << CPSR_C_Pos) /!< \brief CPSR: C Mask /
AnnaBridge	167:e84263d55307	217
AnnaBridge	167:e84263d55307	218	#define CPSR_V_Pos 28U /!< \brief CPSR: V Position /
AnnaBridge	167:e84263d55307	219	#define CPSR_V_Msk (1UL << CPSR_V_Pos) /!< \brief CPSR: V Mask /
AnnaBridge	167:e84263d55307	220
AnnaBridge	167:e84263d55307	221	#define CPSR_Q_Pos 27U /!< \brief CPSR: Q Position /
AnnaBridge	167:e84263d55307	222	#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /!< \brief CPSR: Q Mask /
AnnaBridge	167:e84263d55307	223
AnnaBridge	167:e84263d55307	224	#define CPSR_IT0_Pos 25U /!< \brief CPSR: IT0 Position /
AnnaBridge	167:e84263d55307	225	#define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /!< \brief CPSR: IT0 Mask /
AnnaBridge	167:e84263d55307	226
AnnaBridge	167:e84263d55307	227	#define CPSR_J_Pos 24U /!< \brief CPSR: J Position /
AnnaBridge	167:e84263d55307	228	#define CPSR_J_Msk (1UL << CPSR_J_Pos) /!< \brief CPSR: J Mask /
AnnaBridge	167:e84263d55307	229
AnnaBridge	167:e84263d55307	230	#define CPSR_GE_Pos 16U /!< \brief CPSR: GE Position /
AnnaBridge	167:e84263d55307	231	#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /!< \brief CPSR: GE Mask /
AnnaBridge	167:e84263d55307	232
AnnaBridge	167:e84263d55307	233	#define CPSR_IT1_Pos 10U /!< \brief CPSR: IT1 Position /
AnnaBridge	167:e84263d55307	234	#define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /!< \brief CPSR: IT1 Mask /
AnnaBridge	167:e84263d55307	235
AnnaBridge	167:e84263d55307	236	#define CPSR_E_Pos 9U /!< \brief CPSR: E Position /
AnnaBridge	167:e84263d55307	237	#define CPSR_E_Msk (1UL << CPSR_E_Pos) /!< \brief CPSR: E Mask /
AnnaBridge	167:e84263d55307	238
AnnaBridge	167:e84263d55307	239	#define CPSR_A_Pos 8U /!< \brief CPSR: A Position /
AnnaBridge	167:e84263d55307	240	#define CPSR_A_Msk (1UL << CPSR_A_Pos) /!< \brief CPSR: A Mask /
AnnaBridge	167:e84263d55307	241
AnnaBridge	167:e84263d55307	242	#define CPSR_I_Pos 7U /!< \brief CPSR: I Position /
AnnaBridge	167:e84263d55307	243	#define CPSR_I_Msk (1UL << CPSR_I_Pos) /!< \brief CPSR: I Mask /
AnnaBridge	167:e84263d55307	244
AnnaBridge	167:e84263d55307	245	#define CPSR_F_Pos 6U /!< \brief CPSR: F Position /
AnnaBridge	167:e84263d55307	246	#define CPSR_F_Msk (1UL << CPSR_F_Pos) /!< \brief CPSR: F Mask /
AnnaBridge	167:e84263d55307	247
AnnaBridge	167:e84263d55307	248	#define CPSR_T_Pos 5U /!< \brief CPSR: T Position /
AnnaBridge	167:e84263d55307	249	#define CPSR_T_Msk (1UL << CPSR_T_Pos) /!< \brief CPSR: T Mask /
AnnaBridge	167:e84263d55307	250
AnnaBridge	167:e84263d55307	251	#define CPSR_M_Pos 0U /!< \brief CPSR: M Position /
AnnaBridge	167:e84263d55307	252	#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /!< \brief CPSR: M Mask /
AnnaBridge	167:e84263d55307	253
AnnaBridge	167:e84263d55307	254	/* CP15 Register SCTLR */
AnnaBridge	167:e84263d55307	255	typedef union
AnnaBridge	167:e84263d55307	256	{
AnnaBridge	167:e84263d55307	257	struct
AnnaBridge	167:e84263d55307	258	{
AnnaBridge	167:e84263d55307	259	uint32_t M:1; /!< \brief bit: 0 MMU enable /
AnnaBridge	167:e84263d55307	260	uint32_t A:1; /!< \brief bit: 1 Alignment check enable /
AnnaBridge	167:e84263d55307	261	uint32_t C:1; /!< \brief bit: 2 Cache enable /
AnnaBridge	167:e84263d55307	262	uint32_t _reserved0:2; /!< \brief bit: 3.. 4 Reserved /
AnnaBridge	167:e84263d55307	263	uint32_t CP15BEN:1; /!< \brief bit: 5 CP15 barrier enable /
AnnaBridge	167:e84263d55307	264	uint32_t _reserved1:1; /!< \brief bit: 6 Reserved /
AnnaBridge	167:e84263d55307	265	uint32_t B:1; /!< \brief bit: 7 Endianness model /
AnnaBridge	167:e84263d55307	266	uint32_t _reserved2:2; /!< \brief bit: 8.. 9 Reserved /
AnnaBridge	167:e84263d55307	267	uint32_t SW:1; /!< \brief bit: 10 SWP and SWPB enable /
AnnaBridge	167:e84263d55307	268	uint32_t Z:1; /!< \brief bit: 11 Branch prediction enable /
AnnaBridge	167:e84263d55307	269	uint32_t I:1; /!< \brief bit: 12 Instruction cache enable /
AnnaBridge	167:e84263d55307	270	uint32_t V:1; /!< \brief bit: 13 Vectors bit /
AnnaBridge	167:e84263d55307	271	uint32_t RR:1; /!< \brief bit: 14 Round Robin select /
AnnaBridge	167:e84263d55307	272	uint32_t _reserved3:2; /!< \brief bit:15..16 Reserved /
AnnaBridge	167:e84263d55307	273	uint32_t HA:1; /!< \brief bit: 17 Hardware Access flag enable /
AnnaBridge	167:e84263d55307	274	uint32_t _reserved4:1; /!< \brief bit: 18 Reserved /
AnnaBridge	167:e84263d55307	275	uint32_t WXN:1; /!< \brief bit: 19 Write permission implies XN /
AnnaBridge	167:e84263d55307	276	uint32_t UWXN:1; /!< \brief bit: 20 Unprivileged write permission implies PL1 XN /
AnnaBridge	167:e84263d55307	277	uint32_t FI:1; /!< \brief bit: 21 Fast interrupts configuration enable /
AnnaBridge	167:e84263d55307	278	uint32_t U:1; /!< \brief bit: 22 Alignment model /
AnnaBridge	167:e84263d55307	279	uint32_t _reserved5:1; /!< \brief bit: 23 Reserved /
AnnaBridge	167:e84263d55307	280	uint32_t VE:1; /!< \brief bit: 24 Interrupt Vectors Enable /
AnnaBridge	167:e84263d55307	281	uint32_t EE:1; /!< \brief bit: 25 Exception Endianness /
AnnaBridge	167:e84263d55307	282	uint32_t _reserved6:1; /!< \brief bit: 26 Reserved /
AnnaBridge	167:e84263d55307	283	uint32_t NMFI:1; /!< \brief bit: 27 Non-maskable FIQ (NMFI) support /
AnnaBridge	167:e84263d55307	284	uint32_t TRE:1; /!< \brief bit: 28 TEX remap enable. /
AnnaBridge	167:e84263d55307	285	uint32_t AFE:1; /!< \brief bit: 29 Access flag enable /
AnnaBridge	167:e84263d55307	286	uint32_t TE:1; /!< \brief bit: 30 Thumb Exception enable /
AnnaBridge	167:e84263d55307	287	uint32_t _reserved7:1; /!< \brief bit: 31 Reserved /
AnnaBridge	167:e84263d55307	288	} b; /!< \brief Structure used for bit access /
AnnaBridge	167:e84263d55307	289	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	167:e84263d55307	290	} SCTLR_Type;
AnnaBridge	167:e84263d55307	291
AnnaBridge	167:e84263d55307	292	#define SCTLR_TE_Pos 30U /!< \brief SCTLR: TE Position /
AnnaBridge	167:e84263d55307	293	#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /!< \brief SCTLR: TE Mask /
AnnaBridge	167:e84263d55307	294
AnnaBridge	167:e84263d55307	295	#define SCTLR_AFE_Pos 29U /!< \brief SCTLR: AFE Position /
AnnaBridge	167:e84263d55307	296	#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /!< \brief SCTLR: AFE Mask /
AnnaBridge	167:e84263d55307	297
AnnaBridge	167:e84263d55307	298	#define SCTLR_TRE_Pos 28U /!< \brief SCTLR: TRE Position /
AnnaBridge	167:e84263d55307	299	#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /!< \brief SCTLR: TRE Mask /
AnnaBridge	167:e84263d55307	300
AnnaBridge	167:e84263d55307	301	#define SCTLR_NMFI_Pos 27U /!< \brief SCTLR: NMFI Position /
AnnaBridge	167:e84263d55307	302	#define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /!< \brief SCTLR: NMFI Mask /
AnnaBridge	167:e84263d55307	303
AnnaBridge	167:e84263d55307	304	#define SCTLR_EE_Pos 25U /!< \brief SCTLR: EE Position /
AnnaBridge	167:e84263d55307	305	#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /!< \brief SCTLR: EE Mask /
AnnaBridge	167:e84263d55307	306
AnnaBridge	167:e84263d55307	307	#define SCTLR_VE_Pos 24U /!< \brief SCTLR: VE Position /
AnnaBridge	167:e84263d55307	308	#define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /!< \brief SCTLR: VE Mask /
AnnaBridge	167:e84263d55307	309
AnnaBridge	167:e84263d55307	310	#define SCTLR_U_Pos 22U /!< \brief SCTLR: U Position /
AnnaBridge	167:e84263d55307	311	#define SCTLR_U_Msk (1UL << SCTLR_U_Pos) /!< \brief SCTLR: U Mask /
AnnaBridge	167:e84263d55307	312
AnnaBridge	167:e84263d55307	313	#define SCTLR_FI_Pos 21U /!< \brief SCTLR: FI Position /
AnnaBridge	167:e84263d55307	314	#define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /!< \brief SCTLR: FI Mask /
AnnaBridge	167:e84263d55307	315
AnnaBridge	167:e84263d55307	316	#define SCTLR_UWXN_Pos 20U /!< \brief SCTLR: UWXN Position /
AnnaBridge	167:e84263d55307	317	#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /!< \brief SCTLR: UWXN Mask /
AnnaBridge	167:e84263d55307	318
AnnaBridge	167:e84263d55307	319	#define SCTLR_WXN_Pos 19U /!< \brief SCTLR: WXN Position /
AnnaBridge	167:e84263d55307	320	#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /!< \brief SCTLR: WXN Mask /
AnnaBridge	167:e84263d55307	321
AnnaBridge	167:e84263d55307	322	#define SCTLR_HA_Pos 17U /!< \brief SCTLR: HA Position /
AnnaBridge	167:e84263d55307	323	#define SCTLR_HA_Msk (1UL << SCTLR_HA_Pos) /!< \brief SCTLR: HA Mask /
AnnaBridge	167:e84263d55307	324
AnnaBridge	167:e84263d55307	325	#define SCTLR_RR_Pos 14U /!< \brief SCTLR: RR Position /
AnnaBridge	167:e84263d55307	326	#define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /!< \brief SCTLR: RR Mask /
AnnaBridge	167:e84263d55307	327
AnnaBridge	167:e84263d55307	328	#define SCTLR_V_Pos 13U /!< \brief SCTLR: V Position /
AnnaBridge	167:e84263d55307	329	#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /!< \brief SCTLR: V Mask /
AnnaBridge	167:e84263d55307	330
AnnaBridge	167:e84263d55307	331	#define SCTLR_I_Pos 12U /!< \brief SCTLR: I Position /
AnnaBridge	167:e84263d55307	332	#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /!< \brief SCTLR: I Mask /
AnnaBridge	167:e84263d55307	333
AnnaBridge	167:e84263d55307	334	#define SCTLR_Z_Pos 11U /!< \brief SCTLR: Z Position /
AnnaBridge	167:e84263d55307	335	#define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /!< \brief SCTLR: Z Mask /
AnnaBridge	167:e84263d55307	336
AnnaBridge	167:e84263d55307	337	#define SCTLR_SW_Pos 10U /!< \brief SCTLR: SW Position /
AnnaBridge	167:e84263d55307	338	#define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /!< \brief SCTLR: SW Mask /
AnnaBridge	167:e84263d55307	339
AnnaBridge	167:e84263d55307	340	#define SCTLR_B_Pos 7U /!< \brief SCTLR: B Position /
AnnaBridge	167:e84263d55307	341	#define SCTLR_B_Msk (1UL << SCTLR_B_Pos) /!< \brief SCTLR: B Mask /
AnnaBridge	167:e84263d55307	342
AnnaBridge	167:e84263d55307	343	#define SCTLR_CP15BEN_Pos 5U /!< \brief SCTLR: CP15BEN Position /
AnnaBridge	167:e84263d55307	344	#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /!< \brief SCTLR: CP15BEN Mask /
AnnaBridge	167:e84263d55307	345
AnnaBridge	167:e84263d55307	346	#define SCTLR_C_Pos 2U /!< \brief SCTLR: C Position /
AnnaBridge	167:e84263d55307	347	#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /!< \brief SCTLR: C Mask /
AnnaBridge	167:e84263d55307	348
AnnaBridge	167:e84263d55307	349	#define SCTLR_A_Pos 1U /!< \brief SCTLR: A Position /
AnnaBridge	167:e84263d55307	350	#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /!< \brief SCTLR: A Mask /
AnnaBridge	167:e84263d55307	351
AnnaBridge	167:e84263d55307	352	#define SCTLR_M_Pos 0U /!< \brief SCTLR: M Position /
AnnaBridge	167:e84263d55307	353	#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /!< \brief SCTLR: M Mask /
AnnaBridge	167:e84263d55307	354
AnnaBridge	167:e84263d55307	355	/* CP15 Register CPACR */
AnnaBridge	167:e84263d55307	356	typedef union
AnnaBridge	167:e84263d55307	357	{
AnnaBridge	167:e84263d55307	358	struct
AnnaBridge	167:e84263d55307	359	{
AnnaBridge	167:e84263d55307	360	uint32_t _reserved0:20; /!< \brief bit: 0..19 Reserved /
AnnaBridge	167:e84263d55307	361	uint32_t cp10:2; /!< \brief bit:20..21 Access rights for coprocessor 10 /
AnnaBridge	167:e84263d55307	362	uint32_t cp11:2; /!< \brief bit:22..23 Access rights for coprocessor 11 /
AnnaBridge	167:e84263d55307	363	uint32_t _reserved1:6; /!< \brief bit:24..29 Reserved /
AnnaBridge	167:e84263d55307	364	uint32_t D32DIS:1; /!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file /
AnnaBridge	167:e84263d55307	365	uint32_t ASEDIS:1; /!< \brief bit: 31 Disable Advanced SIMD Functionality /
AnnaBridge	167:e84263d55307	366	} b; /!< \brief Structure used for bit access /
AnnaBridge	167:e84263d55307	367	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	167:e84263d55307	368	} CPACR_Type;
AnnaBridge	167:e84263d55307	369
AnnaBridge	167:e84263d55307	370	#define CPACR_ASEDIS_Pos 31U /!< \brief CPACR: ASEDIS Position /
AnnaBridge	167:e84263d55307	371	#define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /!< \brief CPACR: ASEDIS Mask /
AnnaBridge	167:e84263d55307	372
AnnaBridge	167:e84263d55307	373	#define CPACR_D32DIS_Pos 30U /!< \brief CPACR: D32DIS Position /
AnnaBridge	167:e84263d55307	374	#define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /!< \brief CPACR: D32DIS Mask /
AnnaBridge	167:e84263d55307	375
AnnaBridge	167:e84263d55307	376	#define CPACR_cp11_Pos 22U /!< \brief CPACR: cp11 Position /
AnnaBridge	167:e84263d55307	377	#define CPACR_cp11_Msk (3UL << CPACR_cp11_Pos) /!< \brief CPACR: cp11 Mask /
AnnaBridge	167:e84263d55307	378
AnnaBridge	167:e84263d55307	379	#define CPACR_cp10_Pos 20U /!< \brief CPACR: cp10 Position /
AnnaBridge	167:e84263d55307	380	#define CPACR_cp10_Msk (3UL << CPACR_cp10_Pos) /!< \brief CPACR: cp10 Mask /
AnnaBridge	167:e84263d55307	381
AnnaBridge	167:e84263d55307	382	/* CP15 Register DFSR */
AnnaBridge	167:e84263d55307	383	typedef union
AnnaBridge	167:e84263d55307	384	{
AnnaBridge	167:e84263d55307	385	struct
AnnaBridge	167:e84263d55307	386	{
AnnaBridge	167:e84263d55307	387	uint32_t FS0:4; /!< \brief bit: 0.. 3 Fault Status bits bit 0-3 /
AnnaBridge	167:e84263d55307	388	uint32_t Domain:4; /!< \brief bit: 4.. 7 Fault on which domain /
AnnaBridge	167:e84263d55307	389	uint32_t _reserved0:2; /!< \brief bit: 8.. 9 Reserved /
AnnaBridge	167:e84263d55307	390	uint32_t FS1:1; /!< \brief bit: 10 Fault Status bits bit 4 /
AnnaBridge	167:e84263d55307	391	uint32_t WnR:1; /!< \brief bit: 11 Write not Read bit /
AnnaBridge	167:e84263d55307	392	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
AnnaBridge	167:e84263d55307	393	uint32_t CM:1; /!< \brief bit: 13 Cache maintenance fault /
AnnaBridge	167:e84263d55307	394	uint32_t _reserved1:18; /!< \brief bit:14..31 Reserved /
AnnaBridge	167:e84263d55307	395	} b; /!< \brief Structure used for bit access /
AnnaBridge	167:e84263d55307	396	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	167:e84263d55307	397	} DFSR_Type;
AnnaBridge	167:e84263d55307	398
AnnaBridge	167:e84263d55307	399	#define DFSR_CM_Pos 13U /!< \brief DFSR: CM Position /
AnnaBridge	167:e84263d55307	400	#define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /!< \brief DFSR: CM Mask /
AnnaBridge	167:e84263d55307	401
AnnaBridge	167:e84263d55307	402	#define DFSR_Ext_Pos 12U /!< \brief DFSR: Ext Position /
AnnaBridge	167:e84263d55307	403	#define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /!< \brief DFSR: Ext Mask /
AnnaBridge	167:e84263d55307	404
AnnaBridge	167:e84263d55307	405	#define DFSR_WnR_Pos 11U /!< \brief DFSR: WnR Position /
AnnaBridge	167:e84263d55307	406	#define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /!< \brief DFSR: WnR Mask /
AnnaBridge	167:e84263d55307	407
AnnaBridge	167:e84263d55307	408	#define DFSR_FS1_Pos 10U /!< \brief DFSR: FS1 Position /
AnnaBridge	167:e84263d55307	409	#define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /!< \brief DFSR: FS1 Mask /
AnnaBridge	167:e84263d55307	410
AnnaBridge	167:e84263d55307	411	#define DFSR_Domain_Pos 4U /!< \brief DFSR: Domain Position /
AnnaBridge	167:e84263d55307	412	#define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /!< \brief DFSR: Domain Mask /
AnnaBridge	167:e84263d55307	413
AnnaBridge	167:e84263d55307	414	#define DFSR_FS0_Pos 0U /!< \brief DFSR: FS0 Position /
AnnaBridge	167:e84263d55307	415	#define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /!< \brief DFSR: FS0 Mask /
AnnaBridge	167:e84263d55307	416
AnnaBridge	167:e84263d55307	417	/* CP15 Register IFSR */
AnnaBridge	167:e84263d55307	418	typedef union
AnnaBridge	167:e84263d55307	419	{
AnnaBridge	167:e84263d55307	420	struct
AnnaBridge	167:e84263d55307	421	{
AnnaBridge	167:e84263d55307	422	uint32_t FS0:4; /!< \brief bit: 0.. 3 Fault Status bits bit 0-3 /
AnnaBridge	167:e84263d55307	423	uint32_t _reserved0:6; /!< \brief bit: 4.. 9 Reserved /
AnnaBridge	167:e84263d55307	424	uint32_t FS1:1; /!< \brief bit: 10 Fault Status bits bit 4 /
AnnaBridge	167:e84263d55307	425	uint32_t _reserved1:1; /!< \brief bit: 11 Reserved /
AnnaBridge	167:e84263d55307	426	uint32_t ExT:1; /!< \brief bit: 12 External abort type /
AnnaBridge	167:e84263d55307	427	uint32_t _reserved2:19; /!< \brief bit:13..31 Reserved /
AnnaBridge	167:e84263d55307	428	} b; /!< \brief Structure used for bit access /
AnnaBridge	167:e84263d55307	429	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	167:e84263d55307	430	} IFSR_Type;
AnnaBridge	167:e84263d55307	431
AnnaBridge	167:e84263d55307	432	#define IFSR_ExT_Pos 12U /!< \brief IFSR: ExT Position /
AnnaBridge	167:e84263d55307	433	#define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /!< \brief IFSR: ExT Mask /
AnnaBridge	167:e84263d55307	434
AnnaBridge	167:e84263d55307	435	#define IFSR_FS1_Pos 10U /!< \brief IFSR: FS1 Position /
AnnaBridge	167:e84263d55307	436	#define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /!< \brief IFSR: FS1 Mask /
AnnaBridge	167:e84263d55307	437
AnnaBridge	167:e84263d55307	438	#define IFSR_FS0_Pos 0U /!< \brief IFSR: FS0 Position /
AnnaBridge	167:e84263d55307	439	#define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /!< \brief IFSR: FS0 Mask /
AnnaBridge	167:e84263d55307	440
AnnaBridge	167:e84263d55307	441	/* CP15 Register ISR */
AnnaBridge	167:e84263d55307	442	typedef union
AnnaBridge	167:e84263d55307	443	{
AnnaBridge	167:e84263d55307	444	struct
AnnaBridge	167:e84263d55307	445	{
AnnaBridge	167:e84263d55307	446	uint32_t _reserved0:6; /!< \brief bit: 0.. 5 Reserved /
AnnaBridge	167:e84263d55307	447	uint32_t F:1; /!< \brief bit: 6 FIQ pending bit /
AnnaBridge	167:e84263d55307	448	uint32_t I:1; /!< \brief bit: 7 IRQ pending bit /
AnnaBridge	167:e84263d55307	449	uint32_t A:1; /!< \brief bit: 8 External abort pending bit /
AnnaBridge	167:e84263d55307	450	uint32_t _reserved1:23; /!< \brief bit:14..31 Reserved /
AnnaBridge	167:e84263d55307	451	} b; /!< \brief Structure used for bit access /
AnnaBridge	167:e84263d55307	452	uint32_t w; /!< \brief Type used for word access /
AnnaBridge	167:e84263d55307	453	} ISR_Type;
AnnaBridge	167:e84263d55307	454
AnnaBridge	167:e84263d55307	455	#define ISR_A_Pos 13U /!< \brief ISR: A Position /
AnnaBridge	167:e84263d55307	456	#define ISR_A_Msk (1UL << ISR_A_Pos) /!< \brief ISR: A Mask /
AnnaBridge	167:e84263d55307	457
AnnaBridge	167:e84263d55307	458	#define ISR_I_Pos 12U /!< \brief ISR: I Position /
AnnaBridge	167:e84263d55307	459	#define ISR_I_Msk (1UL << ISR_I_Pos) /!< \brief ISR: I Mask /
AnnaBridge	167:e84263d55307	460
AnnaBridge	167:e84263d55307	461	#define ISR_F_Pos 11U /!< \brief ISR: F Position /
AnnaBridge	167:e84263d55307	462	#define ISR_F_Msk (1UL << ISR_F_Pos) /!< \brief ISR: F Mask /
AnnaBridge	167:e84263d55307	463
AnnaBridge	167:e84263d55307	464
AnnaBridge	167:e84263d55307	465	/**
AnnaBridge	167:e84263d55307	466	\brief Union type to access the L2C_310 Cache Controller.
AnnaBridge	167:e84263d55307	467	*/
AnnaBridge	167:e84263d55307	468	#if (__L2C_PRESENT == 1U)
AnnaBridge	167:e84263d55307	469	typedef struct
AnnaBridge	167:e84263d55307	470	{
AnnaBridge	167:e84263d55307	471	__I uint32_t CACHE_ID; /!< \brief Offset: 0x0000 Cache ID Register /
AnnaBridge	167:e84263d55307	472	__I uint32_t CACHE_TYPE; /!< \brief Offset: 0x0004 Cache Type Register /
AnnaBridge	167:e84263d55307	473	uint32_t RESERVED0[0x3e];
AnnaBridge	167:e84263d55307	474	__IO uint32_t CONTROL; /!< \brief Offset: 0x0100 Control Register /
AnnaBridge	167:e84263d55307	475	__IO uint32_t AUX_CNT; /!< \brief Offset: 0x0104 Auxiliary Control /
AnnaBridge	167:e84263d55307	476	uint32_t RESERVED1[0x3e];
AnnaBridge	167:e84263d55307	477	__IO uint32_t EVENT_CONTROL; /!< \brief Offset: 0x0200 Event Counter Control /
AnnaBridge	167:e84263d55307	478	__IO uint32_t EVENT_COUNTER1_CONF; /!< \brief Offset: 0x0204 Event Counter 1 Configuration /
AnnaBridge	167:e84263d55307	479	__IO uint32_t EVENT_COUNTER0_CONF; /!< \brief Offset: 0x0208 Event Counter 1 Configuration /
AnnaBridge	167:e84263d55307	480	uint32_t RESERVED2[0x2];
AnnaBridge	167:e84263d55307	481	__IO uint32_t INTERRUPT_MASK; /!< \brief Offset: 0x0214 Interrupt Mask /
AnnaBridge	167:e84263d55307	482	__I uint32_t MASKED_INT_STATUS; /!< \brief Offset: 0x0218 Masked Interrupt Status /
AnnaBridge	167:e84263d55307	483	__I uint32_t RAW_INT_STATUS; /!< \brief Offset: 0x021c Raw Interrupt Status /
AnnaBridge	167:e84263d55307	484	__O uint32_t INTERRUPT_CLEAR; /!< \brief Offset: 0x0220 Interrupt Clear /
AnnaBridge	167:e84263d55307	485	uint32_t RESERVED3[0x143];
AnnaBridge	167:e84263d55307	486	__IO uint32_t CACHE_SYNC; /!< \brief Offset: 0x0730 Cache Sync /
AnnaBridge	167:e84263d55307	487	uint32_t RESERVED4[0xf];
AnnaBridge	167:e84263d55307	488	__IO uint32_t INV_LINE_PA; /!< \brief Offset: 0x0770 Invalidate Line By PA /
AnnaBridge	167:e84263d55307	489	uint32_t RESERVED6[2];
AnnaBridge	167:e84263d55307	490	__IO uint32_t INV_WAY; /!< \brief Offset: 0x077c Invalidate by Way /
AnnaBridge	167:e84263d55307	491	uint32_t RESERVED5[0xc];
AnnaBridge	167:e84263d55307	492	__IO uint32_t CLEAN_LINE_PA; /!< \brief Offset: 0x07b0 Clean Line by PA /
AnnaBridge	167:e84263d55307	493	uint32_t RESERVED7[1];
AnnaBridge	167:e84263d55307	494	__IO uint32_t CLEAN_LINE_INDEX_WAY; /!< \brief Offset: 0x07b8 Clean Line by Index/Way /
AnnaBridge	167:e84263d55307	495	__IO uint32_t CLEAN_WAY; /!< \brief Offset: 0x07bc Clean by Way /
AnnaBridge	167:e84263d55307	496	uint32_t RESERVED8[0xc];
AnnaBridge	167:e84263d55307	497	__IO uint32_t CLEAN_INV_LINE_PA; /!< \brief Offset: 0x07f0 Clean and Invalidate Line by PA /
AnnaBridge	167:e84263d55307	498	uint32_t RESERVED9[1];
AnnaBridge	167:e84263d55307	499	__IO uint32_t CLEAN_INV_LINE_INDEX_WAY; /!< \brief Offset: 0x07f8 Clean and Invalidate Line by Index/Way /
AnnaBridge	167:e84263d55307	500	__IO uint32_t CLEAN_INV_WAY; /!< \brief Offset: 0x07fc Clean and Invalidate by Way /
AnnaBridge	167:e84263d55307	501	uint32_t RESERVED10[0x40];
AnnaBridge	167:e84263d55307	502	__IO uint32_t DATA_LOCK_0_WAY; /!< \brief Offset: 0x0900 Data Lockdown 0 by Way /
AnnaBridge	167:e84263d55307	503	__IO uint32_t INST_LOCK_0_WAY; /!< \brief Offset: 0x0904 Instruction Lockdown 0 by Way /
AnnaBridge	167:e84263d55307	504	__IO uint32_t DATA_LOCK_1_WAY; /!< \brief Offset: 0x0908 Data Lockdown 1 by Way /
AnnaBridge	167:e84263d55307	505	__IO uint32_t INST_LOCK_1_WAY; /!< \brief Offset: 0x090c Instruction Lockdown 1 by Way /
AnnaBridge	167:e84263d55307	506	__IO uint32_t DATA_LOCK_2_WAY; /!< \brief Offset: 0x0910 Data Lockdown 2 by Way /
AnnaBridge	167:e84263d55307	507	__IO uint32_t INST_LOCK_2_WAY; /!< \brief Offset: 0x0914 Instruction Lockdown 2 by Way /
AnnaBridge	167:e84263d55307	508	__IO uint32_t DATA_LOCK_3_WAY; /!< \brief Offset: 0x0918 Data Lockdown 3 by Way /
AnnaBridge	167:e84263d55307	509	__IO uint32_t INST_LOCK_3_WAY; /!< \brief Offset: 0x091c Instruction Lockdown 3 by Way /
AnnaBridge	167:e84263d55307	510	__IO uint32_t DATA_LOCK_4_WAY; /!< \brief Offset: 0x0920 Data Lockdown 4 by Way /
AnnaBridge	167:e84263d55307	511	__IO uint32_t INST_LOCK_4_WAY; /!< \brief Offset: 0x0924 Instruction Lockdown 4 by Way /
AnnaBridge	167:e84263d55307	512	__IO uint32_t DATA_LOCK_5_WAY; /!< \brief Offset: 0x0928 Data Lockdown 5 by Way /
AnnaBridge	167:e84263d55307	513	__IO uint32_t INST_LOCK_5_WAY; /!< \brief Offset: 0x092c Instruction Lockdown 5 by Way /
AnnaBridge	167:e84263d55307	514	__IO uint32_t DATA_LOCK_6_WAY; /!< \brief Offset: 0x0930 Data Lockdown 5 by Way /
AnnaBridge	167:e84263d55307	515	__IO uint32_t INST_LOCK_6_WAY; /!< \brief Offset: 0x0934 Instruction Lockdown 5 by Way /
AnnaBridge	167:e84263d55307	516	__IO uint32_t DATA_LOCK_7_WAY; /!< \brief Offset: 0x0938 Data Lockdown 6 by Way /
AnnaBridge	167:e84263d55307	517	__IO uint32_t INST_LOCK_7_WAY; /!< \brief Offset: 0x093c Instruction Lockdown 6 by Way /
AnnaBridge	167:e84263d55307	518	uint32_t RESERVED11[0x4];
AnnaBridge	167:e84263d55307	519	__IO uint32_t LOCK_LINE_EN; /!< \brief Offset: 0x0950 Lockdown by Line Enable /
AnnaBridge	167:e84263d55307	520	__IO uint32_t UNLOCK_ALL_BY_WAY; /!< \brief Offset: 0x0954 Unlock All Lines by Way /
AnnaBridge	167:e84263d55307	521	uint32_t RESERVED12[0xaa];
AnnaBridge	167:e84263d55307	522	__IO uint32_t ADDRESS_FILTER_START; /!< \brief Offset: 0x0c00 Address Filtering Start /
AnnaBridge	167:e84263d55307	523	__IO uint32_t ADDRESS_FILTER_END; /!< \brief Offset: 0x0c04 Address Filtering End /
AnnaBridge	167:e84263d55307	524	uint32_t RESERVED13[0xce];
AnnaBridge	167:e84263d55307	525	__IO uint32_t DEBUG_CONTROL; /!< \brief Offset: 0x0f40 Debug Control Register /
AnnaBridge	167:e84263d55307	526	} L2C_310_TypeDef;
AnnaBridge	167:e84263d55307	527
AnnaBridge	167:e84263d55307	528	#define L2C_310 ((L2C_310_TypeDef )L2C_310_BASE) /!< \brief L2C_310 Declaration */
AnnaBridge	167:e84263d55307	529	#endif
AnnaBridge	167:e84263d55307	530
AnnaBridge	167:e84263d55307	531	#if (__GIC_PRESENT == 1U)
AnnaBridge	167:e84263d55307	532	/** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
AnnaBridge	167:e84263d55307	533	*/
AnnaBridge	167:e84263d55307	534	typedef struct
AnnaBridge	167:e84263d55307	535	{
AnnaBridge	167:e84263d55307	536	__IO uint32_t ICDDCR;
AnnaBridge	167:e84263d55307	537	__I uint32_t ICDICTR;
AnnaBridge	167:e84263d55307	538	__I uint32_t ICDIIDR;
AnnaBridge	167:e84263d55307	539	uint32_t RESERVED0[29];
AnnaBridge	167:e84263d55307	540	__IO uint32_t ICDISR[32];
AnnaBridge	167:e84263d55307	541	__IO uint32_t ICDISER[32];
AnnaBridge	167:e84263d55307	542	__IO uint32_t ICDICER[32];
AnnaBridge	167:e84263d55307	543	__IO uint32_t ICDISPR[32];
AnnaBridge	167:e84263d55307	544	__IO uint32_t ICDICPR[32];
AnnaBridge	167:e84263d55307	545	__I uint32_t ICDABR[32];
AnnaBridge	167:e84263d55307	546	uint32_t RESERVED1[32];
AnnaBridge	167:e84263d55307	547	__IO uint32_t ICDIPR[256];
AnnaBridge	167:e84263d55307	548	__IO uint32_t ICDIPTR[256];
AnnaBridge	167:e84263d55307	549	__IO uint32_t ICDICFR[64];
AnnaBridge	167:e84263d55307	550	uint32_t RESERVED2[128];
AnnaBridge	167:e84263d55307	551	__IO uint32_t ICDSGIR;
AnnaBridge	167:e84263d55307	552	} GICDistributor_Type;
AnnaBridge	167:e84263d55307	553
AnnaBridge	167:e84263d55307	554	#define GICDistributor ((GICDistributor_Type ) GIC_DISTRIBUTOR_BASE ) /!< GIC Distributor configuration struct */
AnnaBridge	167:e84263d55307	555
AnnaBridge	167:e84263d55307	556	/** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
AnnaBridge	167:e84263d55307	557	*/
AnnaBridge	167:e84263d55307	558	typedef struct
AnnaBridge	167:e84263d55307	559	{
AnnaBridge	167:e84263d55307	560	__IO uint32_t ICCICR; //!< \brief +0x000 - RW - CPU Interface Control Register
AnnaBridge	167:e84263d55307	561	__IO uint32_t ICCPMR; //!< \brief +0x004 - RW - Interrupt Priority Mask Register
AnnaBridge	167:e84263d55307	562	__IO uint32_t ICCBPR; //!< \brief +0x008 - RW - Binary Point Register
AnnaBridge	167:e84263d55307	563	__I uint32_t ICCIAR; //!< \brief +0x00C - RO - Interrupt Acknowledge Register
AnnaBridge	167:e84263d55307	564	__IO uint32_t ICCEOIR; //!< \brief +0x010 - WO - End of Interrupt Register
AnnaBridge	167:e84263d55307	565	__I uint32_t ICCRPR; //!< \brief +0x014 - RO - Running Priority Register
AnnaBridge	167:e84263d55307	566	__I uint32_t ICCHPIR; //!< \brief +0x018 - RO - Highest Pending Interrupt Register
AnnaBridge	167:e84263d55307	567	__IO uint32_t ICCABPR; //!< \brief +0x01C - RW - Aliased Binary Point Register
AnnaBridge	167:e84263d55307	568	uint32_t RESERVED[55];
AnnaBridge	167:e84263d55307	569	__I uint32_t ICCIIDR; //!< \brief +0x0FC - RO - CPU Interface Identification Register
AnnaBridge	167:e84263d55307	570	} GICInterface_Type;
AnnaBridge	167:e84263d55307	571
AnnaBridge	167:e84263d55307	572	#define GICInterface ((GICInterface_Type ) GIC_INTERFACE_BASE ) /!< GIC Interface configuration struct */
AnnaBridge	167:e84263d55307	573	#endif
AnnaBridge	167:e84263d55307	574
AnnaBridge	167:e84263d55307	575	#if (__TIM_PRESENT == 1U)
AnnaBridge	167:e84263d55307	576	#if ((__CORTEX_A == 5U)\|\|(__CORTEX_A == 9U))
AnnaBridge	167:e84263d55307	577	/** \brief Structure type to access the Private Timer
AnnaBridge	167:e84263d55307	578	*/
AnnaBridge	167:e84263d55307	579	typedef struct
AnnaBridge	167:e84263d55307	580	{
AnnaBridge	167:e84263d55307	581	__IO uint32_t LOAD; //!< \brief +0x000 - RW - Private Timer Load Register
AnnaBridge	167:e84263d55307	582	__IO uint32_t COUNTER; //!< \brief +0x004 - RW - Private Timer Counter Register
AnnaBridge	167:e84263d55307	583	__IO uint32_t CONTROL; //!< \brief +0x008 - RW - Private Timer Control Register
AnnaBridge	167:e84263d55307	584	__IO uint32_t ISR; //!< \brief +0x00C - RO - Private Timer Interrupt Status Register
AnnaBridge	167:e84263d55307	585	uint32_t RESERVED[8];
AnnaBridge	167:e84263d55307	586	__IO uint32_t WLOAD; //!< \brief +0x020 - RW - Watchdog Load Register
AnnaBridge	167:e84263d55307	587	__IO uint32_t WCOUNTER; //!< \brief +0x024 - RW - Watchdog Counter Register
AnnaBridge	167:e84263d55307	588	__IO uint32_t WCONTROL; //!< \brief +0x028 - RW - Watchdog Control Register
AnnaBridge	167:e84263d55307	589	__IO uint32_t WISR; //!< \brief +0x02C - RW - Watchdog Interrupt Status Register
AnnaBridge	167:e84263d55307	590	__IO uint32_t WRESET; //!< \brief +0x030 - RW - Watchdog Reset Status Register
AnnaBridge	167:e84263d55307	591	__I uint32_t WDISABLE; //!< \brief +0x0FC - RO - Watchdog Disable Register
AnnaBridge	167:e84263d55307	592	} Timer_Type;
AnnaBridge	167:e84263d55307	593	#define PTIM ((Timer_Type ) TIMER_BASE ) /!< \brief Timer configuration struct */
AnnaBridge	167:e84263d55307	594	#endif
AnnaBridge	167:e84263d55307	595	#endif
AnnaBridge	167:e84263d55307	596
AnnaBridge	167:e84263d55307	597	/*******************************************************************************
AnnaBridge	167:e84263d55307	598	* Hardware Abstraction Layer
AnnaBridge	167:e84263d55307	599	Core Function Interface contains:
AnnaBridge	167:e84263d55307	600	- L1 Cache Functions
AnnaBridge	167:e84263d55307	601	- L2C-310 Cache Controller Functions
AnnaBridge	167:e84263d55307	602	- PL1 Timer Functions
AnnaBridge	167:e84263d55307	603	- GIC Functions
AnnaBridge	167:e84263d55307	604	- MMU Functions
AnnaBridge	167:e84263d55307	605	******************************************************************************/
AnnaBridge	167:e84263d55307	606
AnnaBridge	167:e84263d55307	607	/* ########################## L1 Cache functions ################################# */
AnnaBridge	167:e84263d55307	608
AnnaBridge	167:e84263d55307	609	/** \brief Enable Caches
AnnaBridge	167:e84263d55307	610
AnnaBridge	167:e84263d55307	611	Enable Caches
AnnaBridge	167:e84263d55307	612	*/
AnnaBridge	167:e84263d55307	613	__STATIC_INLINE void L1C_EnableCaches(void) {
AnnaBridge	167:e84263d55307	614	// Set I bit 12 to enable I Cache
AnnaBridge	167:e84263d55307	615	// Set C bit 2 to enable D Cache
AnnaBridge	167:e84263d55307	616	__set_SCTLR( __get_SCTLR() \| (1 << 12) \| (1 << 2));
AnnaBridge	167:e84263d55307	617	}
AnnaBridge	167:e84263d55307	618
AnnaBridge	167:e84263d55307	619	/** \brief Disable Caches
AnnaBridge	167:e84263d55307	620
AnnaBridge	167:e84263d55307	621	Disable Caches
AnnaBridge	167:e84263d55307	622	*/
AnnaBridge	167:e84263d55307	623	__STATIC_INLINE void L1C_DisableCaches(void) {
AnnaBridge	167:e84263d55307	624	// Clear I bit 12 to disable I Cache
AnnaBridge	167:e84263d55307	625	// Clear C bit 2 to disable D Cache
AnnaBridge	167:e84263d55307	626	__set_SCTLR( __get_SCTLR() & ~(1 << 12) & ~(1 << 2));
AnnaBridge	167:e84263d55307	627	__ISB();
AnnaBridge	167:e84263d55307	628	}
AnnaBridge	167:e84263d55307	629
AnnaBridge	167:e84263d55307	630	/** \brief Enable BTAC
AnnaBridge	167:e84263d55307	631
AnnaBridge	167:e84263d55307	632	Enable BTAC
AnnaBridge	167:e84263d55307	633	*/
AnnaBridge	167:e84263d55307	634	__STATIC_INLINE void L1C_EnableBTAC(void) {
AnnaBridge	167:e84263d55307	635	// Set Z bit 11 to enable branch prediction
AnnaBridge	167:e84263d55307	636	__set_SCTLR( __get_SCTLR() \| (1 << 11));
AnnaBridge	167:e84263d55307	637	__ISB();
AnnaBridge	167:e84263d55307	638	}
AnnaBridge	167:e84263d55307	639
AnnaBridge	167:e84263d55307	640	/** \brief Disable BTAC
AnnaBridge	167:e84263d55307	641
AnnaBridge	167:e84263d55307	642	Disable BTAC
AnnaBridge	167:e84263d55307	643	*/
AnnaBridge	167:e84263d55307	644	__STATIC_INLINE void L1C_DisableBTAC(void) {
AnnaBridge	167:e84263d55307	645	// Clear Z bit 11 to disable branch prediction
AnnaBridge	167:e84263d55307	646	__set_SCTLR( __get_SCTLR() & ~(1 << 11));
AnnaBridge	167:e84263d55307	647	}
AnnaBridge	167:e84263d55307	648
AnnaBridge	167:e84263d55307	649	/** \brief Invalidate entire branch predictor array
AnnaBridge	167:e84263d55307	650
AnnaBridge	167:e84263d55307	651	BPIALL. Branch Predictor Invalidate All.
AnnaBridge	167:e84263d55307	652	*/
AnnaBridge	167:e84263d55307	653
AnnaBridge	167:e84263d55307	654	__STATIC_INLINE void L1C_InvalidateBTAC(void) {
AnnaBridge	167:e84263d55307	655	__set_BPIALL(0);
AnnaBridge	167:e84263d55307	656	__DSB(); //ensure completion of the invalidation
AnnaBridge	167:e84263d55307	657	__ISB(); //ensure instruction fetch path sees new state
AnnaBridge	167:e84263d55307	658	}
AnnaBridge	167:e84263d55307	659
AnnaBridge	167:e84263d55307	660	/** \brief Invalidate the whole I$
AnnaBridge	167:e84263d55307	661
AnnaBridge	167:e84263d55307	662	ICIALLU. Instruction Cache Invalidate All to PoU
AnnaBridge	167:e84263d55307	663	*/
AnnaBridge	167:e84263d55307	664	__STATIC_INLINE void L1C_InvalidateICacheAll(void) {
AnnaBridge	167:e84263d55307	665	__set_ICIALLU(0);
AnnaBridge	167:e84263d55307	666	__DSB(); //ensure completion of the invalidation
AnnaBridge	167:e84263d55307	667	__ISB(); //ensure instruction fetch path sees new I cache state
AnnaBridge	167:e84263d55307	668	}
AnnaBridge	167:e84263d55307	669
AnnaBridge	167:e84263d55307	670	/** \brief Clean D$ by MVA
AnnaBridge	167:e84263d55307	671
AnnaBridge	167:e84263d55307	672	DCCMVAC. Data cache clean by MVA to PoC
AnnaBridge	167:e84263d55307	673	*/
AnnaBridge	167:e84263d55307	674	__STATIC_INLINE void L1C_CleanDCacheMVA(void *va) {
AnnaBridge	167:e84263d55307	675	__set_DCCMVAC((uint32_t)va);
AnnaBridge	167:e84263d55307	676	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge	167:e84263d55307	677	}
AnnaBridge	167:e84263d55307	678
AnnaBridge	167:e84263d55307	679	/** \brief Invalidate D$ by MVA
AnnaBridge	167:e84263d55307	680
AnnaBridge	167:e84263d55307	681	DCIMVAC. Data cache invalidate by MVA to PoC
AnnaBridge	167:e84263d55307	682	*/
AnnaBridge	167:e84263d55307	683	__STATIC_INLINE void L1C_InvalidateDCacheMVA(void *va) {
AnnaBridge	167:e84263d55307	684	__set_DCIMVAC((uint32_t)va);
AnnaBridge	167:e84263d55307	685	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge	167:e84263d55307	686	}
AnnaBridge	167:e84263d55307	687
AnnaBridge	167:e84263d55307	688	/** \brief Clean and Invalidate D$ by MVA
AnnaBridge	167:e84263d55307	689
AnnaBridge	167:e84263d55307	690	DCCIMVAC. Data cache clean and invalidate by MVA to PoC
AnnaBridge	167:e84263d55307	691	*/
AnnaBridge	167:e84263d55307	692	__STATIC_INLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
AnnaBridge	167:e84263d55307	693	__set_DCCIMVAC((uint32_t)va);
AnnaBridge	167:e84263d55307	694	__DMB(); //ensure the ordering of data cache maintenance operations and their effects
AnnaBridge	167:e84263d55307	695	}
AnnaBridge	167:e84263d55307	696
AnnaBridge	167:e84263d55307	697	/** \brief Clean and Invalidate the entire data or unified cache
AnnaBridge	167:e84263d55307	698
AnnaBridge	167:e84263d55307	699	Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency.
AnnaBridge	167:e84263d55307	700	*/
AnnaBridge	167:e84263d55307	701	__STATIC_INLINE void L1C_CleanInvalidateCache(uint32_t op) {
AnnaBridge	167:e84263d55307	702	__L1C_CleanInvalidateCache(op); // compiler specific call
AnnaBridge	167:e84263d55307	703	}
AnnaBridge	167:e84263d55307	704
AnnaBridge	167:e84263d55307	705
AnnaBridge	167:e84263d55307	706	/** \brief Invalidate the whole D$
AnnaBridge	167:e84263d55307	707
AnnaBridge	167:e84263d55307	708	DCISW. Invalidate by Set/Way
AnnaBridge	167:e84263d55307	709	*/
AnnaBridge	167:e84263d55307	710
AnnaBridge	167:e84263d55307	711	__STATIC_INLINE void L1C_InvalidateDCacheAll(void) {
AnnaBridge	167:e84263d55307	712	L1C_CleanInvalidateCache(0);
AnnaBridge	167:e84263d55307	713	}
AnnaBridge	167:e84263d55307	714
AnnaBridge	167:e84263d55307	715	/** \brief Clean the whole D$
AnnaBridge	167:e84263d55307	716
AnnaBridge	167:e84263d55307	717	DCCSW. Clean by Set/Way
AnnaBridge	167:e84263d55307	718	*/
AnnaBridge	167:e84263d55307	719
AnnaBridge	167:e84263d55307	720	__STATIC_INLINE void L1C_CleanDCacheAll(void) {
AnnaBridge	167:e84263d55307	721	L1C_CleanInvalidateCache(1);
AnnaBridge	167:e84263d55307	722	}
AnnaBridge	167:e84263d55307	723
AnnaBridge	167:e84263d55307	724	/** \brief Clean and invalidate the whole D$
AnnaBridge	167:e84263d55307	725
AnnaBridge	167:e84263d55307	726	DCCISW. Clean and Invalidate by Set/Way
AnnaBridge	167:e84263d55307	727	*/
AnnaBridge	167:e84263d55307	728
AnnaBridge	167:e84263d55307	729	__STATIC_INLINE void L1C_CleanInvalidateDCacheAll(void) {
AnnaBridge	167:e84263d55307	730	L1C_CleanInvalidateCache(2);
AnnaBridge	167:e84263d55307	731	}
AnnaBridge	167:e84263d55307	732
AnnaBridge	167:e84263d55307	733
AnnaBridge	167:e84263d55307	734	/* ########################## L2 Cache functions ################################# */
AnnaBridge	167:e84263d55307	735	#if (__L2C_PRESENT == 1U)
AnnaBridge	167:e84263d55307	736	//Cache Sync operation
AnnaBridge	167:e84263d55307	737	__STATIC_INLINE void L2C_Sync(void)
AnnaBridge	167:e84263d55307	738	{
AnnaBridge	167:e84263d55307	739	L2C_310->CACHE_SYNC = 0x0;
AnnaBridge	167:e84263d55307	740	}
AnnaBridge	167:e84263d55307	741
AnnaBridge	167:e84263d55307	742	//return Cache controller cache ID
AnnaBridge	167:e84263d55307	743	__STATIC_INLINE int L2C_GetID (void)
AnnaBridge	167:e84263d55307	744	{
AnnaBridge	167:e84263d55307	745	return L2C_310->CACHE_ID;
AnnaBridge	167:e84263d55307	746	}
AnnaBridge	167:e84263d55307	747
AnnaBridge	167:e84263d55307	748	//return Cache controller cache Type
AnnaBridge	167:e84263d55307	749	__STATIC_INLINE int L2C_GetType (void)
AnnaBridge	167:e84263d55307	750	{
AnnaBridge	167:e84263d55307	751	return L2C_310->CACHE_TYPE;
AnnaBridge	167:e84263d55307	752	}
AnnaBridge	167:e84263d55307	753
AnnaBridge	167:e84263d55307	754	//Invalidate all cache by way
AnnaBridge	167:e84263d55307	755	__STATIC_INLINE void L2C_InvAllByWay (void)
AnnaBridge	167:e84263d55307	756	{
AnnaBridge	167:e84263d55307	757	unsigned int assoc;
AnnaBridge	167:e84263d55307	758
AnnaBridge	167:e84263d55307	759	if (L2C_310->AUX_CNT & (1<<16))
AnnaBridge	167:e84263d55307	760	assoc = 16;
AnnaBridge	167:e84263d55307	761	else
AnnaBridge	167:e84263d55307	762	assoc = 8;
AnnaBridge	167:e84263d55307	763
AnnaBridge	167:e84263d55307	764	L2C_310->INV_WAY = (1 << assoc) - 1;
AnnaBridge	167:e84263d55307	765	while(L2C_310->INV_WAY & ((1 << assoc) - 1)); //poll invalidate
AnnaBridge	167:e84263d55307	766
AnnaBridge	167:e84263d55307	767	L2C_Sync();
AnnaBridge	167:e84263d55307	768	}
AnnaBridge	167:e84263d55307	769
AnnaBridge	167:e84263d55307	770	//Clean and Invalidate all cache by way
AnnaBridge	167:e84263d55307	771	__STATIC_INLINE void L2C_CleanInvAllByWay (void)
AnnaBridge	167:e84263d55307	772	{
AnnaBridge	167:e84263d55307	773	unsigned int assoc;
AnnaBridge	167:e84263d55307	774
AnnaBridge	167:e84263d55307	775	if (L2C_310->AUX_CNT & (1<<16))
AnnaBridge	167:e84263d55307	776	assoc = 16;
AnnaBridge	167:e84263d55307	777	else
AnnaBridge	167:e84263d55307	778	assoc = 8;
AnnaBridge	167:e84263d55307	779
AnnaBridge	167:e84263d55307	780	L2C_310->CLEAN_INV_WAY = (1 << assoc) - 1;
AnnaBridge	167:e84263d55307	781	while(L2C_310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
AnnaBridge	167:e84263d55307	782
AnnaBridge	167:e84263d55307	783	L2C_Sync();
AnnaBridge	167:e84263d55307	784	}
AnnaBridge	167:e84263d55307	785
AnnaBridge	167:e84263d55307	786	//Enable Cache
AnnaBridge	167:e84263d55307	787	__STATIC_INLINE void L2C_Enable(void)
AnnaBridge	167:e84263d55307	788	{
AnnaBridge	167:e84263d55307	789	L2C_310->CONTROL = 0;
AnnaBridge	167:e84263d55307	790	L2C_310->INTERRUPT_CLEAR = 0x000001FFuL;
AnnaBridge	167:e84263d55307	791	L2C_310->DEBUG_CONTROL = 0;
AnnaBridge	167:e84263d55307	792	L2C_310->DATA_LOCK_0_WAY = 0;
AnnaBridge	167:e84263d55307	793	L2C_310->CACHE_SYNC = 0;
AnnaBridge	167:e84263d55307	794	L2C_310->CONTROL = 0x01;
AnnaBridge	167:e84263d55307	795	L2C_Sync();
AnnaBridge	167:e84263d55307	796	}
AnnaBridge	167:e84263d55307	797	//Disable Cache
AnnaBridge	167:e84263d55307	798	__STATIC_INLINE void L2C_Disable(void)
AnnaBridge	167:e84263d55307	799	{
AnnaBridge	167:e84263d55307	800	L2C_310->CONTROL = 0x00;
AnnaBridge	167:e84263d55307	801	L2C_Sync();
AnnaBridge	167:e84263d55307	802	}
AnnaBridge	167:e84263d55307	803
AnnaBridge	167:e84263d55307	804	//Invalidate cache by physical address
AnnaBridge	167:e84263d55307	805	__STATIC_INLINE void L2C_InvPa (void *pa)
AnnaBridge	167:e84263d55307	806	{
AnnaBridge	167:e84263d55307	807	L2C_310->INV_LINE_PA = (unsigned int)pa;
AnnaBridge	167:e84263d55307	808	L2C_Sync();
AnnaBridge	167:e84263d55307	809	}
AnnaBridge	167:e84263d55307	810
AnnaBridge	167:e84263d55307	811	//Clean cache by physical address
AnnaBridge	167:e84263d55307	812	__STATIC_INLINE void L2C_CleanPa (void *pa)
AnnaBridge	167:e84263d55307	813	{
AnnaBridge	167:e84263d55307	814	L2C_310->CLEAN_LINE_PA = (unsigned int)pa;
AnnaBridge	167:e84263d55307	815	L2C_Sync();
AnnaBridge	167:e84263d55307	816	}
AnnaBridge	167:e84263d55307	817
AnnaBridge	167:e84263d55307	818	//Clean and invalidate cache by physical address
AnnaBridge	167:e84263d55307	819	__STATIC_INLINE void L2C_CleanInvPa (void *pa)
AnnaBridge	167:e84263d55307	820	{
AnnaBridge	167:e84263d55307	821	L2C_310->CLEAN_INV_LINE_PA = (unsigned int)pa;
AnnaBridge	167:e84263d55307	822	L2C_Sync();
AnnaBridge	167:e84263d55307	823	}
AnnaBridge	167:e84263d55307	824	#endif
AnnaBridge	167:e84263d55307	825
AnnaBridge	167:e84263d55307	826	/* ########################## GIC functions ###################################### */
AnnaBridge	167:e84263d55307	827	#if (__GIC_PRESENT == 1U)
AnnaBridge	167:e84263d55307	828
AnnaBridge	167:e84263d55307	829	__STATIC_INLINE void GIC_EnableDistributor(void)
AnnaBridge	167:e84263d55307	830	{
AnnaBridge	167:e84263d55307	831	GICDistributor->ICDDCR \|= 1; //enable distributor
AnnaBridge	167:e84263d55307	832	}
AnnaBridge	167:e84263d55307	833
AnnaBridge	167:e84263d55307	834	__STATIC_INLINE void GIC_DisableDistributor(void)
AnnaBridge	167:e84263d55307	835	{
AnnaBridge	167:e84263d55307	836	GICDistributor->ICDDCR &=~1; //disable distributor
AnnaBridge	167:e84263d55307	837	}
AnnaBridge	167:e84263d55307	838
AnnaBridge	167:e84263d55307	839	__STATIC_INLINE uint32_t GIC_DistributorInfo(void)
AnnaBridge	167:e84263d55307	840	{
AnnaBridge	167:e84263d55307	841	return (uint32_t)(GICDistributor->ICDICTR);
AnnaBridge	167:e84263d55307	842	}
AnnaBridge	167:e84263d55307	843
AnnaBridge	167:e84263d55307	844	__STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
AnnaBridge	167:e84263d55307	845	{
AnnaBridge	167:e84263d55307	846	return (uint32_t)(GICDistributor->ICDIIDR);
AnnaBridge	167:e84263d55307	847	}
AnnaBridge	167:e84263d55307	848
AnnaBridge	167:e84263d55307	849	__STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
AnnaBridge	167:e84263d55307	850	{
AnnaBridge	167:e84263d55307	851	char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
AnnaBridge	167:e84263d55307	852	field += IRQn % 4;
AnnaBridge	167:e84263d55307	853	*field = (char)cpu_target & 0xf;
AnnaBridge	167:e84263d55307	854	}
AnnaBridge	167:e84263d55307	855
AnnaBridge	167:e84263d55307	856	__STATIC_INLINE void GIC_SetICDICFR (const uint32_t *ICDICFRn)
AnnaBridge	167:e84263d55307	857	{
AnnaBridge	167:e84263d55307	858	uint32_t i, num_irq;
AnnaBridge	167:e84263d55307	859
AnnaBridge	167:e84263d55307	860	//Get the maximum number of interrupts that the GIC supports
AnnaBridge	167:e84263d55307	861	num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
AnnaBridge	167:e84263d55307	862
AnnaBridge	167:e84263d55307	863	for (i = 0; i < (num_irq/16); i++)
AnnaBridge	167:e84263d55307	864	{
AnnaBridge	167:e84263d55307	865	GICDistributor->ICDISPR[i] = *ICDICFRn++;
AnnaBridge	167:e84263d55307	866	}
AnnaBridge	167:e84263d55307	867	}
AnnaBridge	167:e84263d55307	868
AnnaBridge	167:e84263d55307	869	__STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	870	{
AnnaBridge	167:e84263d55307	871	char* field = (char*)&(GICDistributor->ICDIPTR[IRQn / 4]);
AnnaBridge	167:e84263d55307	872	field += IRQn % 4;
AnnaBridge	167:e84263d55307	873	return ((uint32_t)*field & 0xf);
AnnaBridge	167:e84263d55307	874	}
AnnaBridge	167:e84263d55307	875
AnnaBridge	167:e84263d55307	876	__STATIC_INLINE void GIC_EnableInterface(void)
AnnaBridge	167:e84263d55307	877	{
AnnaBridge	167:e84263d55307	878	GICInterface->ICCICR \|= 1; //enable interface
AnnaBridge	167:e84263d55307	879	}
AnnaBridge	167:e84263d55307	880
AnnaBridge	167:e84263d55307	881	__STATIC_INLINE void GIC_DisableInterface(void)
AnnaBridge	167:e84263d55307	882	{
AnnaBridge	167:e84263d55307	883	GICInterface->ICCICR &=~1; //disable distributor
AnnaBridge	167:e84263d55307	884	}
AnnaBridge	167:e84263d55307	885
AnnaBridge	167:e84263d55307	886	__STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
AnnaBridge	167:e84263d55307	887	{
AnnaBridge	167:e84263d55307	888	return (IRQn_Type)(GICInterface->ICCIAR);
AnnaBridge	167:e84263d55307	889	}
AnnaBridge	167:e84263d55307	890
AnnaBridge	167:e84263d55307	891	__STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	892	{
AnnaBridge	167:e84263d55307	893	GICInterface->ICCEOIR = IRQn;
AnnaBridge	167:e84263d55307	894	}
AnnaBridge	167:e84263d55307	895
AnnaBridge	167:e84263d55307	896	__STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	897	{
AnnaBridge	167:e84263d55307	898	GICDistributor->ICDISER[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge	167:e84263d55307	899	}
AnnaBridge	167:e84263d55307	900
AnnaBridge	167:e84263d55307	901	__STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	902	{
AnnaBridge	167:e84263d55307	903	GICDistributor->ICDICER[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge	167:e84263d55307	904	}
AnnaBridge	167:e84263d55307	905
AnnaBridge	167:e84263d55307	906	__STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	907	{
AnnaBridge	167:e84263d55307	908	GICDistributor->ICDISPR[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge	167:e84263d55307	909	}
AnnaBridge	167:e84263d55307	910
AnnaBridge	167:e84263d55307	911	__STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	912	{
AnnaBridge	167:e84263d55307	913	GICDistributor->ICDICPR[IRQn / 32] = 1 << (IRQn % 32);
AnnaBridge	167:e84263d55307	914	}
AnnaBridge	167:e84263d55307	915
AnnaBridge	167:e84263d55307	916	__STATIC_INLINE void GIC_SetLevelModel(IRQn_Type IRQn, int8_t edge_level, int8_t model)
AnnaBridge	167:e84263d55307	917	{
AnnaBridge	167:e84263d55307	918	// Word-size read/writes must be used to access this register
AnnaBridge	167:e84263d55307	919	volatile uint32_t * field = &(GICDistributor->ICDICFR[IRQn / 16]);
AnnaBridge	167:e84263d55307	920	unsigned bit_shift = (IRQn % 16)<<1;
AnnaBridge	167:e84263d55307	921	unsigned int save_word;
AnnaBridge	167:e84263d55307	922
AnnaBridge	167:e84263d55307	923	save_word = *field;
AnnaBridge	167:e84263d55307	924	save_word &= (~(3 << bit_shift));
AnnaBridge	167:e84263d55307	925
AnnaBridge	167:e84263d55307	926	*field = (save_word \| (((edge_level<<1) \| model) << bit_shift));
AnnaBridge	167:e84263d55307	927	}
AnnaBridge	167:e84263d55307	928
AnnaBridge	167:e84263d55307	929	__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
AnnaBridge	167:e84263d55307	930	{
AnnaBridge	167:e84263d55307	931	char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
AnnaBridge	167:e84263d55307	932	field += IRQn % 4;
AnnaBridge	167:e84263d55307	933	*field = (char)priority;
AnnaBridge	167:e84263d55307	934	}
AnnaBridge	167:e84263d55307	935
AnnaBridge	167:e84263d55307	936	__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	937	{
AnnaBridge	167:e84263d55307	938	char* field = (char*)&(GICDistributor->ICDIPR[IRQn / 4]);
AnnaBridge	167:e84263d55307	939	field += IRQn % 4;
AnnaBridge	167:e84263d55307	940	return (uint32_t)*field;
AnnaBridge	167:e84263d55307	941	}
AnnaBridge	167:e84263d55307	942
AnnaBridge	167:e84263d55307	943	__STATIC_INLINE void GIC_InterfacePriorityMask(uint32_t priority)
AnnaBridge	167:e84263d55307	944	{
AnnaBridge	167:e84263d55307	945	GICInterface->ICCPMR = priority & 0xff; //set priority mask
AnnaBridge	167:e84263d55307	946	}
AnnaBridge	167:e84263d55307	947
AnnaBridge	167:e84263d55307	948	__STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
AnnaBridge	167:e84263d55307	949	{
AnnaBridge	167:e84263d55307	950	GICInterface->ICCBPR = binary_point & 0x07; //set binary point
AnnaBridge	167:e84263d55307	951	}
AnnaBridge	167:e84263d55307	952
AnnaBridge	167:e84263d55307	953	__STATIC_INLINE uint32_t GIC_GetBinaryPoint(uint32_t binary_point)
AnnaBridge	167:e84263d55307	954	{
AnnaBridge	167:e84263d55307	955	return (uint32_t)GICInterface->ICCBPR;
AnnaBridge	167:e84263d55307	956	}
AnnaBridge	167:e84263d55307	957
AnnaBridge	167:e84263d55307	958	__STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
AnnaBridge	167:e84263d55307	959	{
AnnaBridge	167:e84263d55307	960	uint32_t pending, active;
AnnaBridge	167:e84263d55307	961
AnnaBridge	167:e84263d55307	962	active = ((GICDistributor->ICDABR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
AnnaBridge	167:e84263d55307	963	pending =((GICDistributor->ICDISPR[IRQn / 32]) >> (IRQn % 32)) & 0x1;
AnnaBridge	167:e84263d55307	964
AnnaBridge	167:e84263d55307	965	return ((active<<1) \| pending);
AnnaBridge	167:e84263d55307	966	}
AnnaBridge	167:e84263d55307	967
AnnaBridge	167:e84263d55307	968	__STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
AnnaBridge	167:e84263d55307	969	{
AnnaBridge	167:e84263d55307	970	GICDistributor->ICDSGIR = ((filter_list & 0x3) << 24) \| ((target_list & 0xff) << 16) \| (IRQn & 0xf);
AnnaBridge	167:e84263d55307	971	}
AnnaBridge	167:e84263d55307	972
AnnaBridge	167:e84263d55307	973	__STATIC_INLINE void GIC_DistInit(void)
AnnaBridge	167:e84263d55307	974	{
AnnaBridge	167:e84263d55307	975	IRQn_Type i;
AnnaBridge	167:e84263d55307	976	uint32_t num_irq = 0;
AnnaBridge	167:e84263d55307	977	uint32_t priority_field;
AnnaBridge	167:e84263d55307	978
AnnaBridge	167:e84263d55307	979	//A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
AnnaBridge	167:e84263d55307	980	//configuring all of the interrupts as Secure.
AnnaBridge	167:e84263d55307	981
AnnaBridge	167:e84263d55307	982	//Disable interrupt forwarding
AnnaBridge	167:e84263d55307	983	GIC_DisableDistributor();
AnnaBridge	167:e84263d55307	984	//Get the maximum number of interrupts that the GIC supports
AnnaBridge	167:e84263d55307	985	num_irq = 32 * ((GIC_DistributorInfo() & 0x1f) + 1);
AnnaBridge	167:e84263d55307	986
AnnaBridge	167:e84263d55307	987	/* Priority level is implementation defined.
AnnaBridge	167:e84263d55307	988	To determine the number of priority bits implemented write 0xFF to an ICDIPR
AnnaBridge	167:e84263d55307	989	priority field and read back the value stored.*/
AnnaBridge	167:e84263d55307	990	GIC_SetPriority((IRQn_Type)0, 0xff);
AnnaBridge	167:e84263d55307	991	priority_field = GIC_GetPriority((IRQn_Type)0);
AnnaBridge	167:e84263d55307	992
AnnaBridge	167:e84263d55307	993	for (i = (IRQn_Type)32; i < num_irq; i++)
AnnaBridge	167:e84263d55307	994	{
AnnaBridge	167:e84263d55307	995	//Disable the SPI interrupt
AnnaBridge	167:e84263d55307	996	GIC_DisableIRQ(i);
AnnaBridge	167:e84263d55307	997	//Set level-sensitive and 1-N model
AnnaBridge	167:e84263d55307	998	GIC_SetLevelModel(i, 0, 1);
AnnaBridge	167:e84263d55307	999	//Set priority
AnnaBridge	167:e84263d55307	1000	GIC_SetPriority(i, priority_field/2);
AnnaBridge	167:e84263d55307	1001	//Set target list to CPU0
AnnaBridge	167:e84263d55307	1002	GIC_SetTarget(i, 1);
AnnaBridge	167:e84263d55307	1003	}
AnnaBridge	167:e84263d55307	1004	//Enable distributor
AnnaBridge	167:e84263d55307	1005	GIC_EnableDistributor();
AnnaBridge	167:e84263d55307	1006	}
AnnaBridge	167:e84263d55307	1007
AnnaBridge	167:e84263d55307	1008	__STATIC_INLINE void GIC_CPUInterfaceInit(void)
AnnaBridge	167:e84263d55307	1009	{
AnnaBridge	167:e84263d55307	1010	IRQn_Type i;
AnnaBridge	167:e84263d55307	1011	uint32_t priority_field;
AnnaBridge	167:e84263d55307	1012
AnnaBridge	167:e84263d55307	1013	//A reset sets all bits in the ICDISRs corresponding to the SPIs to 0,
AnnaBridge	167:e84263d55307	1014	//configuring all of the interrupts as Secure.
AnnaBridge	167:e84263d55307	1015
AnnaBridge	167:e84263d55307	1016	//Disable interrupt forwarding
AnnaBridge	167:e84263d55307	1017	GIC_DisableInterface();
AnnaBridge	167:e84263d55307	1018
AnnaBridge	167:e84263d55307	1019	/* Priority level is implementation defined.
AnnaBridge	167:e84263d55307	1020	To determine the number of priority bits implemented write 0xFF to an ICDIPR
AnnaBridge	167:e84263d55307	1021	priority field and read back the value stored.*/
AnnaBridge	167:e84263d55307	1022	GIC_SetPriority((IRQn_Type)0, 0xff);
AnnaBridge	167:e84263d55307	1023	priority_field = GIC_GetPriority((IRQn_Type)0);
AnnaBridge	167:e84263d55307	1024
AnnaBridge	167:e84263d55307	1025	//SGI and PPI
AnnaBridge	167:e84263d55307	1026	for (i = (IRQn_Type)0; i < 32; i++)
AnnaBridge	167:e84263d55307	1027	{
AnnaBridge	167:e84263d55307	1028	//Set level-sensitive and 1-N model for PPI
AnnaBridge	167:e84263d55307	1029	if(i > 15)
AnnaBridge	167:e84263d55307	1030	GIC_SetLevelModel(i, 0, 1);
AnnaBridge	167:e84263d55307	1031	//Disable SGI and PPI interrupts
AnnaBridge	167:e84263d55307	1032	GIC_DisableIRQ(i);
AnnaBridge	167:e84263d55307	1033	//Set priority
AnnaBridge	167:e84263d55307	1034	GIC_SetPriority(i, priority_field/2);
AnnaBridge	167:e84263d55307	1035	}
AnnaBridge	167:e84263d55307	1036	//Enable interface
AnnaBridge	167:e84263d55307	1037	GIC_EnableInterface();
AnnaBridge	167:e84263d55307	1038	//Set binary point to 0
AnnaBridge	167:e84263d55307	1039	GIC_SetBinaryPoint(0);
AnnaBridge	167:e84263d55307	1040	//Set priority mask
AnnaBridge	167:e84263d55307	1041	GIC_InterfacePriorityMask(0xff);
AnnaBridge	167:e84263d55307	1042	}
AnnaBridge	167:e84263d55307	1043
AnnaBridge	167:e84263d55307	1044	__STATIC_INLINE void GIC_Enable(void)
AnnaBridge	167:e84263d55307	1045	{
AnnaBridge	167:e84263d55307	1046	GIC_DistInit();
AnnaBridge	167:e84263d55307	1047	GIC_CPUInterfaceInit(); //per CPU
AnnaBridge	167:e84263d55307	1048	}
AnnaBridge	167:e84263d55307	1049	#endif
AnnaBridge	167:e84263d55307	1050
AnnaBridge	167:e84263d55307	1051	/* ########################## Generic Timer functions ############################ */
AnnaBridge	167:e84263d55307	1052	#if (__TIM_PRESENT == 1U)
AnnaBridge	167:e84263d55307	1053
AnnaBridge	167:e84263d55307	1054	/* PL1 Physical Timer */
AnnaBridge	167:e84263d55307	1055	#if (__CORTEX_A == 7U)
AnnaBridge	167:e84263d55307	1056	__STATIC_INLINE void PL1_SetLoadValue(uint32_t value) {
AnnaBridge	167:e84263d55307	1057	__set_CNTP_TVAL(value);
AnnaBridge	167:e84263d55307	1058	__ISB();
AnnaBridge	167:e84263d55307	1059	}
AnnaBridge	167:e84263d55307	1060
AnnaBridge	167:e84263d55307	1061	__STATIC_INLINE uint32_t PL1_GetCurrentValue() {
AnnaBridge	167:e84263d55307	1062	return(__get_CNTP_TVAL());
AnnaBridge	167:e84263d55307	1063	}
AnnaBridge	167:e84263d55307	1064
AnnaBridge	167:e84263d55307	1065	__STATIC_INLINE void PL1_SetControl(uint32_t value) {
AnnaBridge	167:e84263d55307	1066	__set_CNTP_CTL(value);
AnnaBridge	167:e84263d55307	1067	__ISB();
AnnaBridge	167:e84263d55307	1068	}
AnnaBridge	167:e84263d55307	1069
AnnaBridge	167:e84263d55307	1070	/* Private Timer */
AnnaBridge	167:e84263d55307	1071	#elif ((__CORTEX_A == 5U)\|\|(__CORTEX_A == 9U))
AnnaBridge	167:e84263d55307	1072	__STATIC_INLINE void PTIM_SetLoadValue(uint32_t value) {
AnnaBridge	167:e84263d55307	1073	PTIM->LOAD = value;
AnnaBridge	167:e84263d55307	1074	}
AnnaBridge	167:e84263d55307	1075
AnnaBridge	167:e84263d55307	1076	__STATIC_INLINE uint32_t PTIM_GetLoadValue() {
AnnaBridge	167:e84263d55307	1077	return(PTIM->LOAD);
AnnaBridge	167:e84263d55307	1078	}
AnnaBridge	167:e84263d55307	1079
AnnaBridge	167:e84263d55307	1080	__STATIC_INLINE uint32_t PTIM_GetCurrentValue() {
AnnaBridge	167:e84263d55307	1081	return(PTIM->COUNTER);
AnnaBridge	167:e84263d55307	1082	}
AnnaBridge	167:e84263d55307	1083
AnnaBridge	167:e84263d55307	1084	__STATIC_INLINE void PTIM_SetControl(uint32_t value) {
AnnaBridge	167:e84263d55307	1085	PTIM->CONTROL = value;
AnnaBridge	167:e84263d55307	1086	}
AnnaBridge	167:e84263d55307	1087
AnnaBridge	167:e84263d55307	1088	__STATIC_INLINE uint32_t PTIM_GetControl(void) {
AnnaBridge	167:e84263d55307	1089	return(PTIM->CONTROL);
AnnaBridge	167:e84263d55307	1090	}
AnnaBridge	167:e84263d55307	1091
AnnaBridge	167:e84263d55307	1092	__STATIC_INLINE void PTIM_ClearEventFlag(void) {
AnnaBridge	167:e84263d55307	1093	PTIM->ISR = 1;
AnnaBridge	167:e84263d55307	1094	}
AnnaBridge	167:e84263d55307	1095	#endif
AnnaBridge	167:e84263d55307	1096	#endif
AnnaBridge	167:e84263d55307	1097
AnnaBridge	167:e84263d55307	1098	/* ########################## MMU functions ###################################### */
AnnaBridge	167:e84263d55307	1099
AnnaBridge	167:e84263d55307	1100	#define SECTION_DESCRIPTOR (0x2)
AnnaBridge	167:e84263d55307	1101	#define SECTION_MASK (0xFFFFFFFC)
AnnaBridge	167:e84263d55307	1102
AnnaBridge	167:e84263d55307	1103	#define SECTION_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge	167:e84263d55307	1104	#define SECTION_B_SHIFT (2)
AnnaBridge	167:e84263d55307	1105	#define SECTION_C_SHIFT (3)
AnnaBridge	167:e84263d55307	1106	#define SECTION_TEX0_SHIFT (12)
AnnaBridge	167:e84263d55307	1107	#define SECTION_TEX1_SHIFT (13)
AnnaBridge	167:e84263d55307	1108	#define SECTION_TEX2_SHIFT (14)
AnnaBridge	167:e84263d55307	1109
AnnaBridge	167:e84263d55307	1110	#define SECTION_XN_MASK (0xFFFFFFEF)
AnnaBridge	167:e84263d55307	1111	#define SECTION_XN_SHIFT (4)
AnnaBridge	167:e84263d55307	1112
AnnaBridge	167:e84263d55307	1113	#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge	167:e84263d55307	1114	#define SECTION_DOMAIN_SHIFT (5)
AnnaBridge	167:e84263d55307	1115
AnnaBridge	167:e84263d55307	1116	#define SECTION_P_MASK (0xFFFFFDFF)
AnnaBridge	167:e84263d55307	1117	#define SECTION_P_SHIFT (9)
AnnaBridge	167:e84263d55307	1118
AnnaBridge	167:e84263d55307	1119	#define SECTION_AP_MASK (0xFFFF73FF)
AnnaBridge	167:e84263d55307	1120	#define SECTION_AP_SHIFT (10)
AnnaBridge	167:e84263d55307	1121	#define SECTION_AP2_SHIFT (15)
AnnaBridge	167:e84263d55307	1122
AnnaBridge	167:e84263d55307	1123	#define SECTION_S_MASK (0xFFFEFFFF)
AnnaBridge	167:e84263d55307	1124	#define SECTION_S_SHIFT (16)
AnnaBridge	167:e84263d55307	1125
AnnaBridge	167:e84263d55307	1126	#define SECTION_NG_MASK (0xFFFDFFFF)
AnnaBridge	167:e84263d55307	1127	#define SECTION_NG_SHIFT (17)
AnnaBridge	167:e84263d55307	1128
AnnaBridge	167:e84263d55307	1129	#define SECTION_NS_MASK (0xFFF7FFFF)
AnnaBridge	167:e84263d55307	1130	#define SECTION_NS_SHIFT (19)
AnnaBridge	167:e84263d55307	1131
AnnaBridge	167:e84263d55307	1132	#define PAGE_L1_DESCRIPTOR (0x1)
AnnaBridge	167:e84263d55307	1133	#define PAGE_L1_MASK (0xFFFFFFFC)
AnnaBridge	167:e84263d55307	1134
AnnaBridge	167:e84263d55307	1135	#define PAGE_L2_4K_DESC (0x2)
AnnaBridge	167:e84263d55307	1136	#define PAGE_L2_4K_MASK (0xFFFFFFFD)
AnnaBridge	167:e84263d55307	1137
AnnaBridge	167:e84263d55307	1138	#define PAGE_L2_64K_DESC (0x1)
AnnaBridge	167:e84263d55307	1139	#define PAGE_L2_64K_MASK (0xFFFFFFFC)
AnnaBridge	167:e84263d55307	1140
AnnaBridge	167:e84263d55307	1141	#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
AnnaBridge	167:e84263d55307	1142	#define PAGE_4K_B_SHIFT (2)
AnnaBridge	167:e84263d55307	1143	#define PAGE_4K_C_SHIFT (3)
AnnaBridge	167:e84263d55307	1144	#define PAGE_4K_TEX0_SHIFT (6)
AnnaBridge	167:e84263d55307	1145	#define PAGE_4K_TEX1_SHIFT (7)
AnnaBridge	167:e84263d55307	1146	#define PAGE_4K_TEX2_SHIFT (8)
AnnaBridge	167:e84263d55307	1147
AnnaBridge	167:e84263d55307	1148	#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge	167:e84263d55307	1149	#define PAGE_64K_B_SHIFT (2)
AnnaBridge	167:e84263d55307	1150	#define PAGE_64K_C_SHIFT (3)
AnnaBridge	167:e84263d55307	1151	#define PAGE_64K_TEX0_SHIFT (12)
AnnaBridge	167:e84263d55307	1152	#define PAGE_64K_TEX1_SHIFT (13)
AnnaBridge	167:e84263d55307	1153	#define PAGE_64K_TEX2_SHIFT (14)
AnnaBridge	167:e84263d55307	1154
AnnaBridge	167:e84263d55307	1155	#define PAGE_TEXCB_MASK (0xFFFF8FF3)
AnnaBridge	167:e84263d55307	1156	#define PAGE_B_SHIFT (2)
AnnaBridge	167:e84263d55307	1157	#define PAGE_C_SHIFT (3)
AnnaBridge	167:e84263d55307	1158	#define PAGE_TEX_SHIFT (12)
AnnaBridge	167:e84263d55307	1159
AnnaBridge	167:e84263d55307	1160	#define PAGE_XN_4K_MASK (0xFFFFFFFE)
AnnaBridge	167:e84263d55307	1161	#define PAGE_XN_4K_SHIFT (0)
AnnaBridge	167:e84263d55307	1162	#define PAGE_XN_64K_MASK (0xFFFF7FFF)
AnnaBridge	167:e84263d55307	1163	#define PAGE_XN_64K_SHIFT (15)
AnnaBridge	167:e84263d55307	1164
AnnaBridge	167:e84263d55307	1165	#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
AnnaBridge	167:e84263d55307	1166	#define PAGE_DOMAIN_SHIFT (5)
AnnaBridge	167:e84263d55307	1167
AnnaBridge	167:e84263d55307	1168	#define PAGE_P_MASK (0xFFFFFDFF)
AnnaBridge	167:e84263d55307	1169	#define PAGE_P_SHIFT (9)
AnnaBridge	167:e84263d55307	1170
AnnaBridge	167:e84263d55307	1171	#define PAGE_AP_MASK (0xFFFFFDCF)
AnnaBridge	167:e84263d55307	1172	#define PAGE_AP_SHIFT (4)
AnnaBridge	167:e84263d55307	1173	#define PAGE_AP2_SHIFT (9)
AnnaBridge	167:e84263d55307	1174
AnnaBridge	167:e84263d55307	1175	#define PAGE_S_MASK (0xFFFFFBFF)
AnnaBridge	167:e84263d55307	1176	#define PAGE_S_SHIFT (10)
AnnaBridge	167:e84263d55307	1177
AnnaBridge	167:e84263d55307	1178	#define PAGE_NG_MASK (0xFFFFF7FF)
AnnaBridge	167:e84263d55307	1179	#define PAGE_NG_SHIFT (11)
AnnaBridge	167:e84263d55307	1180
AnnaBridge	167:e84263d55307	1181	#define PAGE_NS_MASK (0xFFFFFFF7)
AnnaBridge	167:e84263d55307	1182	#define PAGE_NS_SHIFT (3)
AnnaBridge	167:e84263d55307	1183
AnnaBridge	167:e84263d55307	1184	#define OFFSET_1M (0x00100000)
AnnaBridge	167:e84263d55307	1185	#define OFFSET_64K (0x00010000)
AnnaBridge	167:e84263d55307	1186	#define OFFSET_4K (0x00001000)
AnnaBridge	167:e84263d55307	1187
AnnaBridge	167:e84263d55307	1188	#define DESCRIPTOR_FAULT (0x00000000)
AnnaBridge	167:e84263d55307	1189
AnnaBridge	167:e84263d55307	1190	/* Attributes enumerations */
AnnaBridge	167:e84263d55307	1191
AnnaBridge	167:e84263d55307	1192	/* Region size attributes */
AnnaBridge	167:e84263d55307	1193	typedef enum
AnnaBridge	167:e84263d55307	1194	{
AnnaBridge	167:e84263d55307	1195	SECTION,
AnnaBridge	167:e84263d55307	1196	PAGE_4k,
AnnaBridge	167:e84263d55307	1197	PAGE_64k,
AnnaBridge	167:e84263d55307	1198	} mmu_region_size_Type;
AnnaBridge	167:e84263d55307	1199
AnnaBridge	167:e84263d55307	1200	/* Region type attributes */
AnnaBridge	167:e84263d55307	1201	typedef enum
AnnaBridge	167:e84263d55307	1202	{
AnnaBridge	167:e84263d55307	1203	NORMAL,
AnnaBridge	167:e84263d55307	1204	DEVICE,
AnnaBridge	167:e84263d55307	1205	SHARED_DEVICE,
AnnaBridge	167:e84263d55307	1206	NON_SHARED_DEVICE,
AnnaBridge	167:e84263d55307	1207	STRONGLY_ORDERED
AnnaBridge	167:e84263d55307	1208	} mmu_memory_Type;
AnnaBridge	167:e84263d55307	1209
AnnaBridge	167:e84263d55307	1210	/* Region cacheability attributes */
AnnaBridge	167:e84263d55307	1211	typedef enum
AnnaBridge	167:e84263d55307	1212	{
AnnaBridge	167:e84263d55307	1213	NON_CACHEABLE,
AnnaBridge	167:e84263d55307	1214	WB_WA,
AnnaBridge	167:e84263d55307	1215	WT,
AnnaBridge	167:e84263d55307	1216	WB_NO_WA,
AnnaBridge	167:e84263d55307	1217	} mmu_cacheability_Type;
AnnaBridge	167:e84263d55307	1218
AnnaBridge	167:e84263d55307	1219	/* Region parity check attributes */
AnnaBridge	167:e84263d55307	1220	typedef enum
AnnaBridge	167:e84263d55307	1221	{
AnnaBridge	167:e84263d55307	1222	ECC_DISABLED,
AnnaBridge	167:e84263d55307	1223	ECC_ENABLED,
AnnaBridge	167:e84263d55307	1224	} mmu_ecc_check_Type;
AnnaBridge	167:e84263d55307	1225
AnnaBridge	167:e84263d55307	1226	/* Region execution attributes */
AnnaBridge	167:e84263d55307	1227	typedef enum
AnnaBridge	167:e84263d55307	1228	{
AnnaBridge	167:e84263d55307	1229	EXECUTE,
AnnaBridge	167:e84263d55307	1230	NON_EXECUTE,
AnnaBridge	167:e84263d55307	1231	} mmu_execute_Type;
AnnaBridge	167:e84263d55307	1232
AnnaBridge	167:e84263d55307	1233	/* Region global attributes */
AnnaBridge	167:e84263d55307	1234	typedef enum
AnnaBridge	167:e84263d55307	1235	{
AnnaBridge	167:e84263d55307	1236	GLOBAL,
AnnaBridge	167:e84263d55307	1237	NON_GLOBAL,
AnnaBridge	167:e84263d55307	1238	} mmu_global_Type;
AnnaBridge	167:e84263d55307	1239
AnnaBridge	167:e84263d55307	1240	/* Region shareability attributes */
AnnaBridge	167:e84263d55307	1241	typedef enum
AnnaBridge	167:e84263d55307	1242	{
AnnaBridge	167:e84263d55307	1243	NON_SHARED,
AnnaBridge	167:e84263d55307	1244	SHARED,
AnnaBridge	167:e84263d55307	1245	} mmu_shared_Type;
AnnaBridge	167:e84263d55307	1246
AnnaBridge	167:e84263d55307	1247	/* Region security attributes */
AnnaBridge	167:e84263d55307	1248	typedef enum
AnnaBridge	167:e84263d55307	1249	{
AnnaBridge	167:e84263d55307	1250	SECURE,
AnnaBridge	167:e84263d55307	1251	NON_SECURE,
AnnaBridge	167:e84263d55307	1252	} mmu_secure_Type;
AnnaBridge	167:e84263d55307	1253
AnnaBridge	167:e84263d55307	1254	/* Region access attributes */
AnnaBridge	167:e84263d55307	1255	typedef enum
AnnaBridge	167:e84263d55307	1256	{
AnnaBridge	167:e84263d55307	1257	NO_ACCESS,
AnnaBridge	167:e84263d55307	1258	RW,
AnnaBridge	167:e84263d55307	1259	READ,
AnnaBridge	167:e84263d55307	1260	} mmu_access_Type;
AnnaBridge	167:e84263d55307	1261
AnnaBridge	167:e84263d55307	1262	/* Memory Region definition */
AnnaBridge	167:e84263d55307	1263	typedef struct RegionStruct {
AnnaBridge	167:e84263d55307	1264	mmu_region_size_Type rg_t;
AnnaBridge	167:e84263d55307	1265	mmu_memory_Type mem_t;
AnnaBridge	167:e84263d55307	1266	uint8_t domain;
AnnaBridge	167:e84263d55307	1267	mmu_cacheability_Type inner_norm_t;
AnnaBridge	167:e84263d55307	1268	mmu_cacheability_Type outer_norm_t;
AnnaBridge	167:e84263d55307	1269	mmu_ecc_check_Type e_t;
AnnaBridge	167:e84263d55307	1270	mmu_execute_Type xn_t;
AnnaBridge	167:e84263d55307	1271	mmu_global_Type g_t;
AnnaBridge	167:e84263d55307	1272	mmu_secure_Type sec_t;
AnnaBridge	167:e84263d55307	1273	mmu_access_Type priv_t;
AnnaBridge	167:e84263d55307	1274	mmu_access_Type user_t;
AnnaBridge	167:e84263d55307	1275	mmu_shared_Type sh_t;
AnnaBridge	167:e84263d55307	1276
AnnaBridge	167:e84263d55307	1277	} mmu_region_attributes_Type;
AnnaBridge	167:e84263d55307	1278
AnnaBridge	167:e84263d55307	1279	//Following macros define the descriptors and attributes
AnnaBridge	167:e84263d55307	1280	//Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0
AnnaBridge	167:e84263d55307	1281	#define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	167:e84263d55307	1282	region.domain = 0x0; \
AnnaBridge	167:e84263d55307	1283	region.e_t = ECC_DISABLED; \
AnnaBridge	167:e84263d55307	1284	region.g_t = GLOBAL; \
AnnaBridge	167:e84263d55307	1285	region.inner_norm_t = WB_WA; \
AnnaBridge	167:e84263d55307	1286	region.outer_norm_t = WB_WA; \
AnnaBridge	167:e84263d55307	1287	region.mem_t = NORMAL; \
AnnaBridge	167:e84263d55307	1288	region.sec_t = SECURE; \
AnnaBridge	167:e84263d55307	1289	region.xn_t = EXECUTE; \
AnnaBridge	167:e84263d55307	1290	region.priv_t = RW; \
AnnaBridge	167:e84263d55307	1291	region.user_t = RW; \
AnnaBridge	167:e84263d55307	1292	region.sh_t = NON_SHARED; \
AnnaBridge	167:e84263d55307	1293	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	167:e84263d55307	1294
AnnaBridge	167:e84263d55307	1295	//Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0
AnnaBridge	167:e84263d55307	1296	#define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	167:e84263d55307	1297	region.domain = 0x0; \
AnnaBridge	167:e84263d55307	1298	region.e_t = ECC_DISABLED; \
AnnaBridge	167:e84263d55307	1299	region.g_t = GLOBAL; \
AnnaBridge	167:e84263d55307	1300	region.inner_norm_t = WB_WA; \
AnnaBridge	167:e84263d55307	1301	region.outer_norm_t = WB_WA; \
AnnaBridge	167:e84263d55307	1302	region.mem_t = NORMAL; \
AnnaBridge	167:e84263d55307	1303	region.sec_t = SECURE; \
AnnaBridge	167:e84263d55307	1304	region.xn_t = EXECUTE; \
AnnaBridge	167:e84263d55307	1305	region.priv_t = READ; \
AnnaBridge	167:e84263d55307	1306	region.user_t = READ; \
AnnaBridge	167:e84263d55307	1307	region.sh_t = NON_SHARED; \
AnnaBridge	167:e84263d55307	1308	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	167:e84263d55307	1309
AnnaBridge	167:e84263d55307	1310	//Sect_Normal_RO. Sect_Normal_Cod, but not executable
AnnaBridge	167:e84263d55307	1311	#define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	167:e84263d55307	1312	region.domain = 0x0; \
AnnaBridge	167:e84263d55307	1313	region.e_t = ECC_DISABLED; \
AnnaBridge	167:e84263d55307	1314	region.g_t = GLOBAL; \
AnnaBridge	167:e84263d55307	1315	region.inner_norm_t = WB_WA; \
AnnaBridge	167:e84263d55307	1316	region.outer_norm_t = WB_WA; \
AnnaBridge	167:e84263d55307	1317	region.mem_t = NORMAL; \
AnnaBridge	167:e84263d55307	1318	region.sec_t = SECURE; \
AnnaBridge	167:e84263d55307	1319	region.xn_t = NON_EXECUTE; \
AnnaBridge	167:e84263d55307	1320	region.priv_t = READ; \
AnnaBridge	167:e84263d55307	1321	region.user_t = READ; \
AnnaBridge	167:e84263d55307	1322	region.sh_t = NON_SHARED; \
AnnaBridge	167:e84263d55307	1323	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	167:e84263d55307	1324
AnnaBridge	167:e84263d55307	1325	//Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
AnnaBridge	167:e84263d55307	1326	#define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	167:e84263d55307	1327	region.domain = 0x0; \
AnnaBridge	167:e84263d55307	1328	region.e_t = ECC_DISABLED; \
AnnaBridge	167:e84263d55307	1329	region.g_t = GLOBAL; \
AnnaBridge	167:e84263d55307	1330	region.inner_norm_t = WB_WA; \
AnnaBridge	167:e84263d55307	1331	region.outer_norm_t = WB_WA; \
AnnaBridge	167:e84263d55307	1332	region.mem_t = NORMAL; \
AnnaBridge	167:e84263d55307	1333	region.sec_t = SECURE; \
AnnaBridge	167:e84263d55307	1334	region.xn_t = NON_EXECUTE; \
AnnaBridge	167:e84263d55307	1335	region.priv_t = RW; \
AnnaBridge	167:e84263d55307	1336	region.user_t = RW; \
AnnaBridge	167:e84263d55307	1337	region.sh_t = NON_SHARED; \
AnnaBridge	167:e84263d55307	1338	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	167:e84263d55307	1339	//Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
AnnaBridge	167:e84263d55307	1340	#define section_so(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	167:e84263d55307	1341	region.domain = 0x0; \
AnnaBridge	167:e84263d55307	1342	region.e_t = ECC_DISABLED; \
AnnaBridge	167:e84263d55307	1343	region.g_t = GLOBAL; \
AnnaBridge	167:e84263d55307	1344	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	167:e84263d55307	1345	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	167:e84263d55307	1346	region.mem_t = STRONGLY_ORDERED; \
AnnaBridge	167:e84263d55307	1347	region.sec_t = SECURE; \
AnnaBridge	167:e84263d55307	1348	region.xn_t = NON_EXECUTE; \
AnnaBridge	167:e84263d55307	1349	region.priv_t = RW; \
AnnaBridge	167:e84263d55307	1350	region.user_t = RW; \
AnnaBridge	167:e84263d55307	1351	region.sh_t = NON_SHARED; \
AnnaBridge	167:e84263d55307	1352	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	167:e84263d55307	1353
AnnaBridge	167:e84263d55307	1354	//Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
AnnaBridge	167:e84263d55307	1355	#define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	167:e84263d55307	1356	region.domain = 0x0; \
AnnaBridge	167:e84263d55307	1357	region.e_t = ECC_DISABLED; \
AnnaBridge	167:e84263d55307	1358	region.g_t = GLOBAL; \
AnnaBridge	167:e84263d55307	1359	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	167:e84263d55307	1360	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	167:e84263d55307	1361	region.mem_t = STRONGLY_ORDERED; \
AnnaBridge	167:e84263d55307	1362	region.sec_t = SECURE; \
AnnaBridge	167:e84263d55307	1363	region.xn_t = NON_EXECUTE; \
AnnaBridge	167:e84263d55307	1364	region.priv_t = READ; \
AnnaBridge	167:e84263d55307	1365	region.user_t = READ; \
AnnaBridge	167:e84263d55307	1366	region.sh_t = NON_SHARED; \
AnnaBridge	167:e84263d55307	1367	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	167:e84263d55307	1368
AnnaBridge	167:e84263d55307	1369	//Sect_Device_RW. Sect_Device_RO, but writeable
AnnaBridge	167:e84263d55307	1370	#define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
AnnaBridge	167:e84263d55307	1371	region.domain = 0x0; \
AnnaBridge	167:e84263d55307	1372	region.e_t = ECC_DISABLED; \
AnnaBridge	167:e84263d55307	1373	region.g_t = GLOBAL; \
AnnaBridge	167:e84263d55307	1374	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	167:e84263d55307	1375	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	167:e84263d55307	1376	region.mem_t = STRONGLY_ORDERED; \
AnnaBridge	167:e84263d55307	1377	region.sec_t = SECURE; \
AnnaBridge	167:e84263d55307	1378	region.xn_t = NON_EXECUTE; \
AnnaBridge	167:e84263d55307	1379	region.priv_t = RW; \
AnnaBridge	167:e84263d55307	1380	region.user_t = RW; \
AnnaBridge	167:e84263d55307	1381	region.sh_t = NON_SHARED; \
AnnaBridge	167:e84263d55307	1382	MMU_GetSectionDescriptor(&descriptor_l1, region);
AnnaBridge	167:e84263d55307	1383	//Page_4k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge	167:e84263d55307	1384	#define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
AnnaBridge	167:e84263d55307	1385	region.domain = 0x0; \
AnnaBridge	167:e84263d55307	1386	region.e_t = ECC_DISABLED; \
AnnaBridge	167:e84263d55307	1387	region.g_t = GLOBAL; \
AnnaBridge	167:e84263d55307	1388	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	167:e84263d55307	1389	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	167:e84263d55307	1390	region.mem_t = SHARED_DEVICE; \
AnnaBridge	167:e84263d55307	1391	region.sec_t = SECURE; \
AnnaBridge	167:e84263d55307	1392	region.xn_t = NON_EXECUTE; \
AnnaBridge	167:e84263d55307	1393	region.priv_t = RW; \
AnnaBridge	167:e84263d55307	1394	region.user_t = RW; \
AnnaBridge	167:e84263d55307	1395	region.sh_t = NON_SHARED; \
AnnaBridge	167:e84263d55307	1396	MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge	167:e84263d55307	1397
AnnaBridge	167:e84263d55307	1398	//Page_64k_Device_RW. Shared device, not executable, rw, domain 0
AnnaBridge	167:e84263d55307	1399	#define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
AnnaBridge	167:e84263d55307	1400	region.domain = 0x0; \
AnnaBridge	167:e84263d55307	1401	region.e_t = ECC_DISABLED; \
AnnaBridge	167:e84263d55307	1402	region.g_t = GLOBAL; \
AnnaBridge	167:e84263d55307	1403	region.inner_norm_t = NON_CACHEABLE; \
AnnaBridge	167:e84263d55307	1404	region.outer_norm_t = NON_CACHEABLE; \
AnnaBridge	167:e84263d55307	1405	region.mem_t = SHARED_DEVICE; \
AnnaBridge	167:e84263d55307	1406	region.sec_t = SECURE; \
AnnaBridge	167:e84263d55307	1407	region.xn_t = NON_EXECUTE; \
AnnaBridge	167:e84263d55307	1408	region.priv_t = RW; \
AnnaBridge	167:e84263d55307	1409	region.user_t = RW; \
AnnaBridge	167:e84263d55307	1410	region.sh_t = NON_SHARED; \
AnnaBridge	167:e84263d55307	1411	MMU_GetPageDescriptor(&descriptor_l1, &descriptor_l2, region);
AnnaBridge	167:e84263d55307	1412
AnnaBridge	167:e84263d55307	1413	/** \brief Set section execution-never attribute
AnnaBridge	167:e84263d55307	1414
AnnaBridge	167:e84263d55307	1415	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1416	\param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge	167:e84263d55307	1417
AnnaBridge	167:e84263d55307	1418	\return 0
AnnaBridge	167:e84263d55307	1419	*/
AnnaBridge	167:e84263d55307	1420	__STATIC_INLINE int MMU_XNSection(uint32_t *descriptor_l1, mmu_execute_Type xn)
AnnaBridge	167:e84263d55307	1421	{
AnnaBridge	167:e84263d55307	1422	*descriptor_l1 &= SECTION_XN_MASK;
AnnaBridge	167:e84263d55307	1423	*descriptor_l1 \|= ((xn & 0x1) << SECTION_XN_SHIFT);
AnnaBridge	167:e84263d55307	1424	return 0;
AnnaBridge	167:e84263d55307	1425	}
AnnaBridge	167:e84263d55307	1426
AnnaBridge	167:e84263d55307	1427	/** \brief Set section domain
AnnaBridge	167:e84263d55307	1428
AnnaBridge	167:e84263d55307	1429	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1430	\param [in] domain Section domain
AnnaBridge	167:e84263d55307	1431
AnnaBridge	167:e84263d55307	1432	\return 0
AnnaBridge	167:e84263d55307	1433	*/
AnnaBridge	167:e84263d55307	1434	__STATIC_INLINE int MMU_DomainSection(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge	167:e84263d55307	1435	{
AnnaBridge	167:e84263d55307	1436	*descriptor_l1 &= SECTION_DOMAIN_MASK;
AnnaBridge	167:e84263d55307	1437	*descriptor_l1 \|= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
AnnaBridge	167:e84263d55307	1438	return 0;
AnnaBridge	167:e84263d55307	1439	}
AnnaBridge	167:e84263d55307	1440
AnnaBridge	167:e84263d55307	1441	/** \brief Set section parity check
AnnaBridge	167:e84263d55307	1442
AnnaBridge	167:e84263d55307	1443	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1444	\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge	167:e84263d55307	1445
AnnaBridge	167:e84263d55307	1446	\return 0
AnnaBridge	167:e84263d55307	1447	*/
AnnaBridge	167:e84263d55307	1448	__STATIC_INLINE int MMU_PSection(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge	167:e84263d55307	1449	{
AnnaBridge	167:e84263d55307	1450	*descriptor_l1 &= SECTION_P_MASK;
AnnaBridge	167:e84263d55307	1451	*descriptor_l1 \|= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge	167:e84263d55307	1452	return 0;
AnnaBridge	167:e84263d55307	1453	}
AnnaBridge	167:e84263d55307	1454
AnnaBridge	167:e84263d55307	1455	/** \brief Set section access privileges
AnnaBridge	167:e84263d55307	1456
AnnaBridge	167:e84263d55307	1457	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1458	\param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge	167:e84263d55307	1459	\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge	167:e84263d55307	1460	\param [in] afe Access flag enable
AnnaBridge	167:e84263d55307	1461
AnnaBridge	167:e84263d55307	1462	\return 0
AnnaBridge	167:e84263d55307	1463	*/
AnnaBridge	167:e84263d55307	1464	__STATIC_INLINE int MMU_APSection(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge	167:e84263d55307	1465	{
AnnaBridge	167:e84263d55307	1466	uint32_t ap = 0;
AnnaBridge	167:e84263d55307	1467
AnnaBridge	167:e84263d55307	1468	if (afe == 0) { //full access
AnnaBridge	167:e84263d55307	1469	if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge	167:e84263d55307	1470	else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	167:e84263d55307	1471	else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge	167:e84263d55307	1472	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	167:e84263d55307	1473	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	167:e84263d55307	1474	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge	167:e84263d55307	1475	}
AnnaBridge	167:e84263d55307	1476
AnnaBridge	167:e84263d55307	1477	else { //Simplified access
AnnaBridge	167:e84263d55307	1478	if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	167:e84263d55307	1479	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	167:e84263d55307	1480	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	167:e84263d55307	1481	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge	167:e84263d55307	1482	}
AnnaBridge	167:e84263d55307	1483
AnnaBridge	167:e84263d55307	1484	*descriptor_l1 &= SECTION_AP_MASK;
AnnaBridge	167:e84263d55307	1485	*descriptor_l1 \|= (ap & 0x3) << SECTION_AP_SHIFT;
AnnaBridge	167:e84263d55307	1486	*descriptor_l1 \|= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
AnnaBridge	167:e84263d55307	1487
AnnaBridge	167:e84263d55307	1488	return 0;
AnnaBridge	167:e84263d55307	1489	}
AnnaBridge	167:e84263d55307	1490
AnnaBridge	167:e84263d55307	1491	/** \brief Set section shareability
AnnaBridge	167:e84263d55307	1492
AnnaBridge	167:e84263d55307	1493	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1494	\param [in] s_bit Section shareability: NON_SHARED, SHARED
AnnaBridge	167:e84263d55307	1495
AnnaBridge	167:e84263d55307	1496	\return 0
AnnaBridge	167:e84263d55307	1497	*/
AnnaBridge	167:e84263d55307	1498	__STATIC_INLINE int MMU_SharedSection(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
AnnaBridge	167:e84263d55307	1499	{
AnnaBridge	167:e84263d55307	1500	*descriptor_l1 &= SECTION_S_MASK;
AnnaBridge	167:e84263d55307	1501	*descriptor_l1 \|= ((s_bit & 0x1) << SECTION_S_SHIFT);
AnnaBridge	167:e84263d55307	1502	return 0;
AnnaBridge	167:e84263d55307	1503	}
AnnaBridge	167:e84263d55307	1504
AnnaBridge	167:e84263d55307	1505	/** \brief Set section Global attribute
AnnaBridge	167:e84263d55307	1506
AnnaBridge	167:e84263d55307	1507	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1508	\param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
AnnaBridge	167:e84263d55307	1509
AnnaBridge	167:e84263d55307	1510	\return 0
AnnaBridge	167:e84263d55307	1511	*/
AnnaBridge	167:e84263d55307	1512	__STATIC_INLINE int MMU_GlobalSection(uint32_t *descriptor_l1, mmu_global_Type g_bit)
AnnaBridge	167:e84263d55307	1513	{
AnnaBridge	167:e84263d55307	1514	*descriptor_l1 &= SECTION_NG_MASK;
AnnaBridge	167:e84263d55307	1515	*descriptor_l1 \|= ((g_bit & 0x1) << SECTION_NG_SHIFT);
AnnaBridge	167:e84263d55307	1516	return 0;
AnnaBridge	167:e84263d55307	1517	}
AnnaBridge	167:e84263d55307	1518
AnnaBridge	167:e84263d55307	1519	/** \brief Set section Security attribute
AnnaBridge	167:e84263d55307	1520
AnnaBridge	167:e84263d55307	1521	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1522	\param [in] s_bit Section Security attribute: SECURE, NON_SECURE
AnnaBridge	167:e84263d55307	1523
AnnaBridge	167:e84263d55307	1524	\return 0
AnnaBridge	167:e84263d55307	1525	*/
AnnaBridge	167:e84263d55307	1526	__STATIC_INLINE int MMU_SecureSection(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge	167:e84263d55307	1527	{
AnnaBridge	167:e84263d55307	1528	*descriptor_l1 &= SECTION_NS_MASK;
AnnaBridge	167:e84263d55307	1529	*descriptor_l1 \|= ((s_bit & 0x1) << SECTION_NS_SHIFT);
AnnaBridge	167:e84263d55307	1530	return 0;
AnnaBridge	167:e84263d55307	1531	}
AnnaBridge	167:e84263d55307	1532
AnnaBridge	167:e84263d55307	1533	/* Page 4k or 64k */
AnnaBridge	167:e84263d55307	1534	/** \brief Set 4k/64k page execution-never attribute
AnnaBridge	167:e84263d55307	1535
AnnaBridge	167:e84263d55307	1536	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	167:e84263d55307	1537	\param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
AnnaBridge	167:e84263d55307	1538	\param [in] page Page size: PAGE_4k, PAGE_64k,
AnnaBridge	167:e84263d55307	1539
AnnaBridge	167:e84263d55307	1540	\return 0
AnnaBridge	167:e84263d55307	1541	*/
AnnaBridge	167:e84263d55307	1542	__STATIC_INLINE int MMU_XNPage(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
AnnaBridge	167:e84263d55307	1543	{
AnnaBridge	167:e84263d55307	1544	if (page == PAGE_4k)
AnnaBridge	167:e84263d55307	1545	{
AnnaBridge	167:e84263d55307	1546	*descriptor_l2 &= PAGE_XN_4K_MASK;
AnnaBridge	167:e84263d55307	1547	*descriptor_l2 \|= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
AnnaBridge	167:e84263d55307	1548	}
AnnaBridge	167:e84263d55307	1549	else
AnnaBridge	167:e84263d55307	1550	{
AnnaBridge	167:e84263d55307	1551	*descriptor_l2 &= PAGE_XN_64K_MASK;
AnnaBridge	167:e84263d55307	1552	*descriptor_l2 \|= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
AnnaBridge	167:e84263d55307	1553	}
AnnaBridge	167:e84263d55307	1554	return 0;
AnnaBridge	167:e84263d55307	1555	}
AnnaBridge	167:e84263d55307	1556
AnnaBridge	167:e84263d55307	1557	/** \brief Set 4k/64k page domain
AnnaBridge	167:e84263d55307	1558
AnnaBridge	167:e84263d55307	1559	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1560	\param [in] domain Page domain
AnnaBridge	167:e84263d55307	1561
AnnaBridge	167:e84263d55307	1562	\return 0
AnnaBridge	167:e84263d55307	1563	*/
AnnaBridge	167:e84263d55307	1564	__STATIC_INLINE int MMU_DomainPage(uint32_t *descriptor_l1, uint8_t domain)
AnnaBridge	167:e84263d55307	1565	{
AnnaBridge	167:e84263d55307	1566	*descriptor_l1 &= PAGE_DOMAIN_MASK;
AnnaBridge	167:e84263d55307	1567	*descriptor_l1 \|= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
AnnaBridge	167:e84263d55307	1568	return 0;
AnnaBridge	167:e84263d55307	1569	}
AnnaBridge	167:e84263d55307	1570
AnnaBridge	167:e84263d55307	1571	/** \brief Set 4k/64k page parity check
AnnaBridge	167:e84263d55307	1572
AnnaBridge	167:e84263d55307	1573	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1574	\param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
AnnaBridge	167:e84263d55307	1575
AnnaBridge	167:e84263d55307	1576	\return 0
AnnaBridge	167:e84263d55307	1577	*/
AnnaBridge	167:e84263d55307	1578	__STATIC_INLINE int MMU_PPage(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
AnnaBridge	167:e84263d55307	1579	{
AnnaBridge	167:e84263d55307	1580	*descriptor_l1 &= SECTION_P_MASK;
AnnaBridge	167:e84263d55307	1581	*descriptor_l1 \|= ((p_bit & 0x1) << SECTION_P_SHIFT);
AnnaBridge	167:e84263d55307	1582	return 0;
AnnaBridge	167:e84263d55307	1583	}
AnnaBridge	167:e84263d55307	1584
AnnaBridge	167:e84263d55307	1585	/** \brief Set 4k/64k page access privileges
AnnaBridge	167:e84263d55307	1586
AnnaBridge	167:e84263d55307	1587	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	167:e84263d55307	1588	\param [in] user User Level Access: NO_ACCESS, RW, READ
AnnaBridge	167:e84263d55307	1589	\param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
AnnaBridge	167:e84263d55307	1590	\param [in] afe Access flag enable
AnnaBridge	167:e84263d55307	1591
AnnaBridge	167:e84263d55307	1592	\return 0
AnnaBridge	167:e84263d55307	1593	*/
AnnaBridge	167:e84263d55307	1594	__STATIC_INLINE int MMU_APPage(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
AnnaBridge	167:e84263d55307	1595	{
AnnaBridge	167:e84263d55307	1596	uint32_t ap = 0;
AnnaBridge	167:e84263d55307	1597
AnnaBridge	167:e84263d55307	1598	if (afe == 0) { //full access
AnnaBridge	167:e84263d55307	1599	if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
AnnaBridge	167:e84263d55307	1600	else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	167:e84263d55307	1601	else if ((priv == RW) && (user == READ)) { ap = 0x2; }
AnnaBridge	167:e84263d55307	1602	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	167:e84263d55307	1603	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	167:e84263d55307	1604	else if ((priv == READ) && (user == READ)) { ap = 0x6; }
AnnaBridge	167:e84263d55307	1605	}
AnnaBridge	167:e84263d55307	1606
AnnaBridge	167:e84263d55307	1607	else { //Simplified access
AnnaBridge	167:e84263d55307	1608	if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
AnnaBridge	167:e84263d55307	1609	else if ((priv == RW) && (user == RW)) { ap = 0x3; }
AnnaBridge	167:e84263d55307	1610	else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
AnnaBridge	167:e84263d55307	1611	else if ((priv == READ) && (user == READ)) { ap = 0x7; }
AnnaBridge	167:e84263d55307	1612	}
AnnaBridge	167:e84263d55307	1613
AnnaBridge	167:e84263d55307	1614	*descriptor_l2 &= PAGE_AP_MASK;
AnnaBridge	167:e84263d55307	1615	*descriptor_l2 \|= (ap & 0x3) << PAGE_AP_SHIFT;
AnnaBridge	167:e84263d55307	1616	*descriptor_l2 \|= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
AnnaBridge	167:e84263d55307	1617
AnnaBridge	167:e84263d55307	1618	return 0;
AnnaBridge	167:e84263d55307	1619	}
AnnaBridge	167:e84263d55307	1620
AnnaBridge	167:e84263d55307	1621	/** \brief Set 4k/64k page shareability
AnnaBridge	167:e84263d55307	1622
AnnaBridge	167:e84263d55307	1623	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	167:e84263d55307	1624	\param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
AnnaBridge	167:e84263d55307	1625
AnnaBridge	167:e84263d55307	1626	\return 0
AnnaBridge	167:e84263d55307	1627	*/
AnnaBridge	167:e84263d55307	1628	__STATIC_INLINE int MMU_SharedPage(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
AnnaBridge	167:e84263d55307	1629	{
AnnaBridge	167:e84263d55307	1630	*descriptor_l2 &= PAGE_S_MASK;
AnnaBridge	167:e84263d55307	1631	*descriptor_l2 \|= ((s_bit & 0x1) << PAGE_S_SHIFT);
AnnaBridge	167:e84263d55307	1632	return 0;
AnnaBridge	167:e84263d55307	1633	}
AnnaBridge	167:e84263d55307	1634
AnnaBridge	167:e84263d55307	1635	/** \brief Set 4k/64k page Global attribute
AnnaBridge	167:e84263d55307	1636
AnnaBridge	167:e84263d55307	1637	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	167:e84263d55307	1638	\param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
AnnaBridge	167:e84263d55307	1639
AnnaBridge	167:e84263d55307	1640	\return 0
AnnaBridge	167:e84263d55307	1641	*/
AnnaBridge	167:e84263d55307	1642	__STATIC_INLINE int MMU_GlobalPage(uint32_t *descriptor_l2, mmu_global_Type g_bit)
AnnaBridge	167:e84263d55307	1643	{
AnnaBridge	167:e84263d55307	1644	*descriptor_l2 &= PAGE_NG_MASK;
AnnaBridge	167:e84263d55307	1645	*descriptor_l2 \|= ((g_bit & 0x1) << PAGE_NG_SHIFT);
AnnaBridge	167:e84263d55307	1646	return 0;
AnnaBridge	167:e84263d55307	1647	}
AnnaBridge	167:e84263d55307	1648
AnnaBridge	167:e84263d55307	1649	/** \brief Set 4k/64k page Security attribute
AnnaBridge	167:e84263d55307	1650
AnnaBridge	167:e84263d55307	1651	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1652	\param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
AnnaBridge	167:e84263d55307	1653
AnnaBridge	167:e84263d55307	1654	\return 0
AnnaBridge	167:e84263d55307	1655	*/
AnnaBridge	167:e84263d55307	1656	__STATIC_INLINE int MMU_SecurePage(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
AnnaBridge	167:e84263d55307	1657	{
AnnaBridge	167:e84263d55307	1658	*descriptor_l1 &= PAGE_NS_MASK;
AnnaBridge	167:e84263d55307	1659	*descriptor_l1 \|= ((s_bit & 0x1) << PAGE_NS_SHIFT);
AnnaBridge	167:e84263d55307	1660	return 0;
AnnaBridge	167:e84263d55307	1661	}
AnnaBridge	167:e84263d55307	1662
AnnaBridge	167:e84263d55307	1663	/** \brief Set Section memory attributes
AnnaBridge	167:e84263d55307	1664
AnnaBridge	167:e84263d55307	1665	\param [out] descriptor_l1 L1 descriptor.
AnnaBridge	167:e84263d55307	1666	\param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge	167:e84263d55307	1667	\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	167:e84263d55307	1668	\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	167:e84263d55307	1669
AnnaBridge	167:e84263d55307	1670	\return 0
AnnaBridge	167:e84263d55307	1671	*/
AnnaBridge	167:e84263d55307	1672	__STATIC_INLINE int MMU_MemorySection(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
AnnaBridge	167:e84263d55307	1673	{
AnnaBridge	167:e84263d55307	1674	*descriptor_l1 &= SECTION_TEXCB_MASK;
AnnaBridge	167:e84263d55307	1675
AnnaBridge	167:e84263d55307	1676	if (STRONGLY_ORDERED == mem)
AnnaBridge	167:e84263d55307	1677	{
AnnaBridge	167:e84263d55307	1678	return 0;
AnnaBridge	167:e84263d55307	1679	}
AnnaBridge	167:e84263d55307	1680	else if (SHARED_DEVICE == mem)
AnnaBridge	167:e84263d55307	1681	{
AnnaBridge	167:e84263d55307	1682	*descriptor_l1 \|= (1 << SECTION_B_SHIFT);
AnnaBridge	167:e84263d55307	1683	}
AnnaBridge	167:e84263d55307	1684	else if (NON_SHARED_DEVICE == mem)
AnnaBridge	167:e84263d55307	1685	{
AnnaBridge	167:e84263d55307	1686	*descriptor_l1 \|= (1 << SECTION_TEX1_SHIFT);
AnnaBridge	167:e84263d55307	1687	}
AnnaBridge	167:e84263d55307	1688	else if (NORMAL == mem)
AnnaBridge	167:e84263d55307	1689	{
AnnaBridge	167:e84263d55307	1690	*descriptor_l1 \|= 1 << SECTION_TEX2_SHIFT;
AnnaBridge	167:e84263d55307	1691	switch(inner)
AnnaBridge	167:e84263d55307	1692	{
AnnaBridge	167:e84263d55307	1693	case NON_CACHEABLE:
AnnaBridge	167:e84263d55307	1694	break;
AnnaBridge	167:e84263d55307	1695	case WB_WA:
AnnaBridge	167:e84263d55307	1696	*descriptor_l1 \|= (1 << SECTION_B_SHIFT);
AnnaBridge	167:e84263d55307	1697	break;
AnnaBridge	167:e84263d55307	1698	case WT:
AnnaBridge	167:e84263d55307	1699	*descriptor_l1 \|= 1 << SECTION_C_SHIFT;
AnnaBridge	167:e84263d55307	1700	break;
AnnaBridge	167:e84263d55307	1701	case WB_NO_WA:
AnnaBridge	167:e84263d55307	1702	*descriptor_l1 \|= (1 << SECTION_B_SHIFT) \| (1 << SECTION_C_SHIFT);
AnnaBridge	167:e84263d55307	1703	break;
AnnaBridge	167:e84263d55307	1704	}
AnnaBridge	167:e84263d55307	1705	switch(outer)
AnnaBridge	167:e84263d55307	1706	{
AnnaBridge	167:e84263d55307	1707	case NON_CACHEABLE:
AnnaBridge	167:e84263d55307	1708	break;
AnnaBridge	167:e84263d55307	1709	case WB_WA:
AnnaBridge	167:e84263d55307	1710	*descriptor_l1 \|= (1 << SECTION_TEX0_SHIFT);
AnnaBridge	167:e84263d55307	1711	break;
AnnaBridge	167:e84263d55307	1712	case WT:
AnnaBridge	167:e84263d55307	1713	*descriptor_l1 \|= 1 << SECTION_TEX1_SHIFT;
AnnaBridge	167:e84263d55307	1714	break;
AnnaBridge	167:e84263d55307	1715	case WB_NO_WA:
AnnaBridge	167:e84263d55307	1716	*descriptor_l1 \|= (1 << SECTION_TEX0_SHIFT) \| (1 << SECTION_TEX0_SHIFT);
AnnaBridge	167:e84263d55307	1717	break;
AnnaBridge	167:e84263d55307	1718	}
AnnaBridge	167:e84263d55307	1719	}
AnnaBridge	167:e84263d55307	1720	return 0;
AnnaBridge	167:e84263d55307	1721	}
AnnaBridge	167:e84263d55307	1722
AnnaBridge	167:e84263d55307	1723	/** \brief Set 4k/64k page memory attributes
AnnaBridge	167:e84263d55307	1724
AnnaBridge	167:e84263d55307	1725	\param [out] descriptor_l2 L2 descriptor.
AnnaBridge	167:e84263d55307	1726	\param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
AnnaBridge	167:e84263d55307	1727	\param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	167:e84263d55307	1728	\param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
AnnaBridge	167:e84263d55307	1729	\param [in] page Page size
AnnaBridge	167:e84263d55307	1730
AnnaBridge	167:e84263d55307	1731	\return 0
AnnaBridge	167:e84263d55307	1732	*/
AnnaBridge	167:e84263d55307	1733	__STATIC_INLINE int MMU_MemoryPage(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
AnnaBridge	167:e84263d55307	1734	{
AnnaBridge	167:e84263d55307	1735	*descriptor_l2 &= PAGE_4K_TEXCB_MASK;
AnnaBridge	167:e84263d55307	1736
AnnaBridge	167:e84263d55307	1737	if (page == PAGE_64k)
AnnaBridge	167:e84263d55307	1738	{
AnnaBridge	167:e84263d55307	1739	//same as section
AnnaBridge	167:e84263d55307	1740	MMU_MemorySection(descriptor_l2, mem, outer, inner);
AnnaBridge	167:e84263d55307	1741	}
AnnaBridge	167:e84263d55307	1742	else
AnnaBridge	167:e84263d55307	1743	{
AnnaBridge	167:e84263d55307	1744	if (STRONGLY_ORDERED == mem)
AnnaBridge	167:e84263d55307	1745	{
AnnaBridge	167:e84263d55307	1746	return 0;
AnnaBridge	167:e84263d55307	1747	}
AnnaBridge	167:e84263d55307	1748	else if (SHARED_DEVICE == mem)
AnnaBridge	167:e84263d55307	1749	{
AnnaBridge	167:e84263d55307	1750	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT);
AnnaBridge	167:e84263d55307	1751	}
AnnaBridge	167:e84263d55307	1752	else if (NON_SHARED_DEVICE == mem)
AnnaBridge	167:e84263d55307	1753	{
AnnaBridge	167:e84263d55307	1754	*descriptor_l2 \|= (1 << PAGE_4K_TEX1_SHIFT);
AnnaBridge	167:e84263d55307	1755	}
AnnaBridge	167:e84263d55307	1756	else if (NORMAL == mem)
AnnaBridge	167:e84263d55307	1757	{
AnnaBridge	167:e84263d55307	1758	*descriptor_l2 \|= 1 << PAGE_4K_TEX2_SHIFT;
AnnaBridge	167:e84263d55307	1759	switch(inner)
AnnaBridge	167:e84263d55307	1760	{
AnnaBridge	167:e84263d55307	1761	case NON_CACHEABLE:
AnnaBridge	167:e84263d55307	1762	break;
AnnaBridge	167:e84263d55307	1763	case WB_WA:
AnnaBridge	167:e84263d55307	1764	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT);
AnnaBridge	167:e84263d55307	1765	break;
AnnaBridge	167:e84263d55307	1766	case WT:
AnnaBridge	167:e84263d55307	1767	*descriptor_l2 \|= 1 << PAGE_4K_C_SHIFT;
AnnaBridge	167:e84263d55307	1768	break;
AnnaBridge	167:e84263d55307	1769	case WB_NO_WA:
AnnaBridge	167:e84263d55307	1770	*descriptor_l2 \|= (1 << PAGE_4K_B_SHIFT) \| (1 << PAGE_4K_C_SHIFT);
AnnaBridge	167:e84263d55307	1771	break;
AnnaBridge	167:e84263d55307	1772	}
AnnaBridge	167:e84263d55307	1773	switch(outer)
AnnaBridge	167:e84263d55307	1774	{
AnnaBridge	167:e84263d55307	1775	case NON_CACHEABLE:
AnnaBridge	167:e84263d55307	1776	break;
AnnaBridge	167:e84263d55307	1777	case WB_WA:
AnnaBridge	167:e84263d55307	1778	*descriptor_l2 \|= (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge	167:e84263d55307	1779	break;
AnnaBridge	167:e84263d55307	1780	case WT:
AnnaBridge	167:e84263d55307	1781	*descriptor_l2 \|= 1 << PAGE_4K_TEX1_SHIFT;
AnnaBridge	167:e84263d55307	1782	break;
AnnaBridge	167:e84263d55307	1783	case WB_NO_WA:
AnnaBridge	167:e84263d55307	1784	*descriptor_l2 \|= (1 << PAGE_4K_TEX0_SHIFT) \| (1 << PAGE_4K_TEX0_SHIFT);
AnnaBridge	167:e84263d55307	1785	break;
AnnaBridge	167:e84263d55307	1786	}
AnnaBridge	167:e84263d55307	1787	}
AnnaBridge	167:e84263d55307	1788	}
AnnaBridge	167:e84263d55307	1789
AnnaBridge	167:e84263d55307	1790	return 0;
AnnaBridge	167:e84263d55307	1791	}
AnnaBridge	167:e84263d55307	1792
AnnaBridge	167:e84263d55307	1793	/** \brief Create a L1 section descriptor
AnnaBridge	167:e84263d55307	1794
AnnaBridge	167:e84263d55307	1795	\param [out] descriptor L1 descriptor
AnnaBridge	167:e84263d55307	1796	\param [in] reg Section attributes
AnnaBridge	167:e84263d55307	1797
AnnaBridge	167:e84263d55307	1798	\return 0
AnnaBridge	167:e84263d55307	1799	*/
AnnaBridge	167:e84263d55307	1800	__STATIC_INLINE int MMU_GetSectionDescriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
AnnaBridge	167:e84263d55307	1801	{
AnnaBridge	167:e84263d55307	1802	*descriptor = 0;
AnnaBridge	167:e84263d55307	1803
AnnaBridge	167:e84263d55307	1804	MMU_MemorySection(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
AnnaBridge	167:e84263d55307	1805	MMU_XNSection(descriptor,reg.xn_t);
AnnaBridge	167:e84263d55307	1806	MMU_DomainSection(descriptor, reg.domain);
AnnaBridge	167:e84263d55307	1807	MMU_PSection(descriptor, reg.e_t);
AnnaBridge	167:e84263d55307	1808	MMU_APSection(descriptor, reg.priv_t, reg.user_t, 1);
AnnaBridge	167:e84263d55307	1809	MMU_SharedSection(descriptor,reg.sh_t);
AnnaBridge	167:e84263d55307	1810	MMU_GlobalSection(descriptor,reg.g_t);
AnnaBridge	167:e84263d55307	1811	MMU_SecureSection(descriptor,reg.sec_t);
AnnaBridge	167:e84263d55307	1812	*descriptor &= SECTION_MASK;
AnnaBridge	167:e84263d55307	1813	*descriptor \|= SECTION_DESCRIPTOR;
AnnaBridge	167:e84263d55307	1814
AnnaBridge	167:e84263d55307	1815	return 0;
AnnaBridge	167:e84263d55307	1816	}
AnnaBridge	167:e84263d55307	1817
AnnaBridge	167:e84263d55307	1818
AnnaBridge	167:e84263d55307	1819	/** \brief Create a L1 and L2 4k/64k page descriptor
AnnaBridge	167:e84263d55307	1820
AnnaBridge	167:e84263d55307	1821	\param [out] descriptor L1 descriptor
AnnaBridge	167:e84263d55307	1822	\param [out] descriptor2 L2 descriptor
AnnaBridge	167:e84263d55307	1823	\param [in] reg 4k/64k page attributes
AnnaBridge	167:e84263d55307	1824
AnnaBridge	167:e84263d55307	1825	\return 0
AnnaBridge	167:e84263d55307	1826	*/
AnnaBridge	167:e84263d55307	1827	__STATIC_INLINE int MMU_GetPageDescriptor(uint32_t descriptor, uint32_t descriptor2, mmu_region_attributes_Type reg)
AnnaBridge	167:e84263d55307	1828	{
AnnaBridge	167:e84263d55307	1829	*descriptor = 0;
AnnaBridge	167:e84263d55307	1830	*descriptor2 = 0;
AnnaBridge	167:e84263d55307	1831
AnnaBridge	167:e84263d55307	1832	switch (reg.rg_t)
AnnaBridge	167:e84263d55307	1833	{
AnnaBridge	167:e84263d55307	1834	case PAGE_4k:
AnnaBridge	167:e84263d55307	1835	MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
AnnaBridge	167:e84263d55307	1836	MMU_XNPage(descriptor2, reg.xn_t, PAGE_4k);
AnnaBridge	167:e84263d55307	1837	MMU_DomainPage(descriptor, reg.domain);
AnnaBridge	167:e84263d55307	1838	MMU_PPage(descriptor, reg.e_t);
AnnaBridge	167:e84263d55307	1839	MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge	167:e84263d55307	1840	MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge	167:e84263d55307	1841	MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge	167:e84263d55307	1842	MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge	167:e84263d55307	1843	*descriptor &= PAGE_L1_MASK;
AnnaBridge	167:e84263d55307	1844	*descriptor \|= PAGE_L1_DESCRIPTOR;
AnnaBridge	167:e84263d55307	1845	*descriptor2 &= PAGE_L2_4K_MASK;
AnnaBridge	167:e84263d55307	1846	*descriptor2 \|= PAGE_L2_4K_DESC;
AnnaBridge	167:e84263d55307	1847	break;
AnnaBridge	167:e84263d55307	1848
AnnaBridge	167:e84263d55307	1849	case PAGE_64k:
AnnaBridge	167:e84263d55307	1850	MMU_MemoryPage(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
AnnaBridge	167:e84263d55307	1851	MMU_XNPage(descriptor2, reg.xn_t, PAGE_64k);
AnnaBridge	167:e84263d55307	1852	MMU_DomainPage(descriptor, reg.domain);
AnnaBridge	167:e84263d55307	1853	MMU_PPage(descriptor, reg.e_t);
AnnaBridge	167:e84263d55307	1854	MMU_APPage(descriptor2, reg.priv_t, reg.user_t, 1);
AnnaBridge	167:e84263d55307	1855	MMU_SharedPage(descriptor2,reg.sh_t);
AnnaBridge	167:e84263d55307	1856	MMU_GlobalPage(descriptor2,reg.g_t);
AnnaBridge	167:e84263d55307	1857	MMU_SecurePage(descriptor,reg.sec_t);
AnnaBridge	167:e84263d55307	1858	*descriptor &= PAGE_L1_MASK;
AnnaBridge	167:e84263d55307	1859	*descriptor \|= PAGE_L1_DESCRIPTOR;
AnnaBridge	167:e84263d55307	1860	*descriptor2 &= PAGE_L2_64K_MASK;
AnnaBridge	167:e84263d55307	1861	*descriptor2 \|= PAGE_L2_64K_DESC;
AnnaBridge	167:e84263d55307	1862	break;
AnnaBridge	167:e84263d55307	1863
AnnaBridge	167:e84263d55307	1864	case SECTION:
AnnaBridge	167:e84263d55307	1865	//error
AnnaBridge	167:e84263d55307	1866	break;
AnnaBridge	167:e84263d55307	1867	}
AnnaBridge	167:e84263d55307	1868
AnnaBridge	167:e84263d55307	1869	return 0;
AnnaBridge	167:e84263d55307	1870	}
AnnaBridge	167:e84263d55307	1871
AnnaBridge	167:e84263d55307	1872	/** \brief Create a 1MB Section
AnnaBridge	167:e84263d55307	1873
AnnaBridge	167:e84263d55307	1874	\param [in] ttb Translation table base address
AnnaBridge	167:e84263d55307	1875	\param [in] base_address Section base address
AnnaBridge	167:e84263d55307	1876	\param [in] count Number of sections to create
AnnaBridge	167:e84263d55307	1877	\param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge	167:e84263d55307	1878
AnnaBridge	167:e84263d55307	1879	*/
AnnaBridge	167:e84263d55307	1880	__STATIC_INLINE void MMU_TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
AnnaBridge	167:e84263d55307	1881	{
AnnaBridge	167:e84263d55307	1882	uint32_t offset;
AnnaBridge	167:e84263d55307	1883	uint32_t entry;
AnnaBridge	167:e84263d55307	1884	uint32_t i;
AnnaBridge	167:e84263d55307	1885
AnnaBridge	167:e84263d55307	1886	offset = base_address >> 20;
AnnaBridge	167:e84263d55307	1887	entry = (base_address & 0xFFF00000) \| descriptor_l1;
AnnaBridge	167:e84263d55307	1888
AnnaBridge	167:e84263d55307	1889	//4 bytes aligned
AnnaBridge	167:e84263d55307	1890	ttb = ttb + offset;
AnnaBridge	167:e84263d55307	1891
AnnaBridge	167:e84263d55307	1892	for (i = 0; i < count; i++ )
AnnaBridge	167:e84263d55307	1893	{
AnnaBridge	167:e84263d55307	1894	//4 bytes aligned
AnnaBridge	167:e84263d55307	1895	*ttb++ = entry;
AnnaBridge	167:e84263d55307	1896	entry += OFFSET_1M;
AnnaBridge	167:e84263d55307	1897	}
AnnaBridge	167:e84263d55307	1898	}
AnnaBridge	167:e84263d55307	1899
AnnaBridge	167:e84263d55307	1900	/** \brief Create a 4k page entry
AnnaBridge	167:e84263d55307	1901
AnnaBridge	167:e84263d55307	1902	\param [in] ttb L1 table base address
AnnaBridge	167:e84263d55307	1903	\param [in] base_address 4k base address
AnnaBridge	167:e84263d55307	1904	\param [in] count Number of 4k pages to create
AnnaBridge	167:e84263d55307	1905	\param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge	167:e84263d55307	1906	\param [in] ttb_l2 L2 table base address
AnnaBridge	167:e84263d55307	1907	\param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge	167:e84263d55307	1908
AnnaBridge	167:e84263d55307	1909	*/
AnnaBridge	167:e84263d55307	1910	__STATIC_INLINE void MMU_TTPage4k(uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2 )
AnnaBridge	167:e84263d55307	1911	{
AnnaBridge	167:e84263d55307	1912
AnnaBridge	167:e84263d55307	1913	uint32_t offset, offset2;
AnnaBridge	167:e84263d55307	1914	uint32_t entry, entry2;
AnnaBridge	167:e84263d55307	1915	uint32_t i;
AnnaBridge	167:e84263d55307	1916
AnnaBridge	167:e84263d55307	1917	offset = base_address >> 20;
AnnaBridge	167:e84263d55307	1918	entry = ((int)ttb_l2 & 0xFFFFFC00) \| descriptor_l1;
AnnaBridge	167:e84263d55307	1919
AnnaBridge	167:e84263d55307	1920	//4 bytes aligned
AnnaBridge	167:e84263d55307	1921	ttb += offset;
AnnaBridge	167:e84263d55307	1922	//create l1_entry
AnnaBridge	167:e84263d55307	1923	*ttb = entry;
AnnaBridge	167:e84263d55307	1924
AnnaBridge	167:e84263d55307	1925	offset2 = (base_address & 0xff000) >> 12;
AnnaBridge	167:e84263d55307	1926	ttb_l2 += offset2;
AnnaBridge	167:e84263d55307	1927	entry2 = (base_address & 0xFFFFF000) \| descriptor_l2;
AnnaBridge	167:e84263d55307	1928	for (i = 0; i < count; i++ )
AnnaBridge	167:e84263d55307	1929	{
AnnaBridge	167:e84263d55307	1930	//4 bytes aligned
AnnaBridge	167:e84263d55307	1931	*ttb_l2++ = entry2;
AnnaBridge	167:e84263d55307	1932	entry2 += OFFSET_4K;
AnnaBridge	167:e84263d55307	1933	}
AnnaBridge	167:e84263d55307	1934	}
AnnaBridge	167:e84263d55307	1935
AnnaBridge	167:e84263d55307	1936	/** \brief Create a 64k page entry
AnnaBridge	167:e84263d55307	1937
AnnaBridge	167:e84263d55307	1938	\param [in] ttb L1 table base address
AnnaBridge	167:e84263d55307	1939	\param [in] base_address 64k base address
AnnaBridge	167:e84263d55307	1940	\param [in] count Number of 64k pages to create
AnnaBridge	167:e84263d55307	1941	\param [in] descriptor_l1 L1 descriptor (region attributes)
AnnaBridge	167:e84263d55307	1942	\param [in] ttb_l2 L2 table base address
AnnaBridge	167:e84263d55307	1943	\param [in] descriptor_l2 L2 descriptor (region attributes)
AnnaBridge	167:e84263d55307	1944
AnnaBridge	167:e84263d55307	1945	*/
AnnaBridge	167:e84263d55307	1946	__STATIC_INLINE void MMU_TTPage64k(uint32_t ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t ttb_l2, uint32_t descriptor_l2 )
AnnaBridge	167:e84263d55307	1947	{
AnnaBridge	167:e84263d55307	1948	uint32_t offset, offset2;
AnnaBridge	167:e84263d55307	1949	uint32_t entry, entry2;
AnnaBridge	167:e84263d55307	1950	uint32_t i,j;
AnnaBridge	167:e84263d55307	1951
AnnaBridge	167:e84263d55307	1952
AnnaBridge	167:e84263d55307	1953	offset = base_address >> 20;
AnnaBridge	167:e84263d55307	1954	entry = ((int)ttb_l2 & 0xFFFFFC00) \| descriptor_l1;
AnnaBridge	167:e84263d55307	1955
AnnaBridge	167:e84263d55307	1956	//4 bytes aligned
AnnaBridge	167:e84263d55307	1957	ttb += offset;
AnnaBridge	167:e84263d55307	1958	//create l1_entry
AnnaBridge	167:e84263d55307	1959	*ttb = entry;
AnnaBridge	167:e84263d55307	1960
AnnaBridge	167:e84263d55307	1961	offset2 = (base_address & 0xff000) >> 12;
AnnaBridge	167:e84263d55307	1962	ttb_l2 += offset2;
AnnaBridge	167:e84263d55307	1963	entry2 = (base_address & 0xFFFF0000) \| descriptor_l2;
AnnaBridge	167:e84263d55307	1964	for (i = 0; i < count; i++ )
AnnaBridge	167:e84263d55307	1965	{
AnnaBridge	167:e84263d55307	1966	//create 16 entries
AnnaBridge	167:e84263d55307	1967	for (j = 0; j < 16; j++)
AnnaBridge	167:e84263d55307	1968	{
AnnaBridge	167:e84263d55307	1969	//4 bytes aligned
AnnaBridge	167:e84263d55307	1970	*ttb_l2++ = entry2;
AnnaBridge	167:e84263d55307	1971	}
AnnaBridge	167:e84263d55307	1972	entry2 += OFFSET_64K;
AnnaBridge	167:e84263d55307	1973	}
AnnaBridge	167:e84263d55307	1974	}
AnnaBridge	167:e84263d55307	1975
AnnaBridge	167:e84263d55307	1976	/** \brief Enable MMU
AnnaBridge	167:e84263d55307	1977
AnnaBridge	167:e84263d55307	1978	Enable MMU
AnnaBridge	167:e84263d55307	1979	*/
AnnaBridge	167:e84263d55307	1980	__STATIC_INLINE void MMU_Enable(void) {
AnnaBridge	167:e84263d55307	1981	// Set M bit 0 to enable the MMU
AnnaBridge	167:e84263d55307	1982	// Set AFE bit to enable simplified access permissions model
AnnaBridge	167:e84263d55307	1983	// Clear TRE bit to disable TEX remap and A bit to disable strict alignment fault checking
AnnaBridge	167:e84263d55307	1984	__set_SCTLR( (__get_SCTLR() & ~(1 << 28) & ~(1 << 1)) \| 1 \| (1 << 29));
AnnaBridge	167:e84263d55307	1985	__ISB();
AnnaBridge	167:e84263d55307	1986	}
AnnaBridge	167:e84263d55307	1987
AnnaBridge	167:e84263d55307	1988	/** \brief Disable MMU
AnnaBridge	167:e84263d55307	1989
AnnaBridge	167:e84263d55307	1990	Disable MMU
AnnaBridge	167:e84263d55307	1991	*/
AnnaBridge	167:e84263d55307	1992	__STATIC_INLINE void MMU_Disable(void) {
AnnaBridge	167:e84263d55307	1993	// Clear M bit 0 to disable the MMU
AnnaBridge	167:e84263d55307	1994	__set_SCTLR( __get_SCTLR() & ~1);
AnnaBridge	167:e84263d55307	1995	__ISB();
AnnaBridge	167:e84263d55307	1996	}
AnnaBridge	167:e84263d55307	1997
AnnaBridge	167:e84263d55307	1998	/** \brief Invalidate entire unified TLB
AnnaBridge	167:e84263d55307	1999
AnnaBridge	167:e84263d55307	2000	TLBIALL. Invalidate entire unified TLB
AnnaBridge	167:e84263d55307	2001	*/
AnnaBridge	167:e84263d55307	2002
AnnaBridge	167:e84263d55307	2003	__STATIC_INLINE void MMU_InvalidateTLB(void) {
AnnaBridge	167:e84263d55307	2004	__set_TLBIALL(0);
AnnaBridge	167:e84263d55307	2005	__DSB(); //ensure completion of the invalidation
AnnaBridge	167:e84263d55307	2006	__ISB(); //ensure instruction fetch path sees new state
AnnaBridge	167:e84263d55307	2007	}
AnnaBridge	167:e84263d55307	2008
AnnaBridge	167:e84263d55307	2009
AnnaBridge	167:e84263d55307	2010	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	2011	}
AnnaBridge	167:e84263d55307	2012	#endif
AnnaBridge	167:e84263d55307	2013
AnnaBridge	167:e84263d55307	2014	#endif /* __CORE_CA_H_DEPENDANT */
AnnaBridge	167:e84263d55307	2015
AnnaBridge	167:e84263d55307	2016	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	27 Oct 2017
Imports:	56
Forks:	0
Commits:	182
Dependents:	41
Dependencies:	0
Followers:	12

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cmsis/core_ca.h@181:36facd806e4a, 2018-07-30 (annotated)

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