Diff: main.cpp

Revision:

38:ec3b16c130d7

Parent:

37:8bdc71f3e874

Child:

39:82dc3daecf32

diff -r 8bdc71f3e874 -r ec3b16c130d7 main.cpp
--- a/main.cpp	Tue Jan 27 17:12:37 2015 +0000
+++ b/main.cpp	Wed Jan 28 04:56:07 2015 +0000
@@ -63,34 +63,190 @@
     pc.baud(230400);
     pc.printf("Starting\r\n");
     
+    
+// Turn on the ADC0 and ADC1 clocks as well as the PDB clocks to test ADC triggered by PDB
+SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK;
+SIM_SCGC3 |= SIM_SCGC3_ADC1_MASK;
+SIM_SCGC6 |= SIM_SCGC6_PDB_MASK;
+
+    
+    
+    analog_initialization(A0);
+    //analog_initialization(A2);
+    
+    ADC0->CFG1 |= ADC_CFG1_ADLPC_MASK; // high power mode for faster frequencies                   
+    //ADC0->SC2 |= ADC_SC2_ADTRG_MASK; // enable hardware trigger
+    SIM_SOPT7 |= 0;
+    
+    // put in continuous conversion mode
+    //pc.printf("ADC0_SC3: %08x\r\n", ADC0->SC3);
+    
+    // enable the DMA
+    ADC0->SC2 |= ADC_SC2_DMAEN_MASK;
+    //ADC1->SC2 |= ADC_SC2_DMAEN_MASK;
+    ADC0->SC3 = 0; // Reset SC3
+    //ADC1->SC3 = 0; // Reset SC3
+    
+    dma_init(sample_array1, sample_array2, angle_array, TOTAL_SAMPLES);
+    
     // initialize the Programmable Delay Block
-    PDB0->MOD = ;// the period of the PDB
-    PDB0->SC |= PDB_SC_CONT_MASK; // run PDB in continuous mode
-    PDB0->SC |= PDB_SC_PDBEN_MASK; // enables the PDB
+    SIM->SCGC6 |= SIM_SCGC6_PDB_MASK; // turn on the clock to the PDB
+    
+    
+// Configure System Integration Module for defaults as far as ADC
+SIM_SOPT7 &= ~(SIM_SOPT7_ADC1ALTTRGEN_MASK  | // selects PDB not ALT trigger
+            SIM_SOPT7_ADC1PRETRGSEL_MASK |
+            SIM_SOPT7_ADC0ALTTRGEN_MASK  | // selects PDB not ALT trigger
+            SIM_SOPT7_ADC0ALTTRGEN_MASK) ;
+SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0);       // applies only in case of ALT trigger, in which case PDB external pin input trigger for ADC
+SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0);       // same for both ADCs
+    
+    
+
+// Configure the Peripheral Delay Block (PDB):
+// enable PDB, pdb counter clock = busclock / 20 , continous triggers, sw trigger , and use prescaler too
+PDB0_SC =  PDB_SC_CONT_MASK       // Contintuous, rather than one-shot, mode
+     | PDB_SC_PDBEN_MASK      // PDB enabled
+     //| PDB_SC_PDBIE_MASK      // PDB Interrupt Enable
+     | PDB_SC_PRESCALER(0x5)  // Slow down the period of the PDB for testing
+     | PDB_SC_TRGSEL(0xf)     // Trigger source is Software Trigger to be invoked in this file
+     | PDB_SC_MULT(2);        // Multiplication factor 20 for the prescale divider for the counter clock
+                              // the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time.
+
+PDB0_IDLY = 0x0000;   // need to trigger interrupt every counter reset which happens when modulus reached
+
+PDB0_MOD = 0xffff;    // largest period possible with the slections above, so slow you can see each conversion.
+
+// channel 0 pretrigger 0 and 1 enabled and delayed
+PDB0_CH0C1 = PDB_C1_EN(0x01)
+       | PDB_C1_TOS(0x01)
+       | PDB_C1_EN(0x02)
+       | PDB_C1_TOS(0x02) ;
+
+PDB0_CH0DLY0 = 100 ;
+PDB0_CH0DLY1 = 300 ;
+
+// channel 1 pretrigger 0 and 1 enabled and delayed
+PDB0_CH1C1 = PDB_C1_EN(0x01)
+       | PDB_C1_TOS(0x01)
+       | PDB_C1_EN(0x02)
+       | PDB_C1_TOS(0x02) ;
+
+PDB0_CH1DLY0 = 200 ;
+PDB0_CH1DLY1 = 400 ;
+
+PDB0_SC =  PDB_SC_CONT_MASK        // Contintuous, rather than one-shot, mode
+     | PDB_SC_PDBEN_MASK       // PDB enabled
+     | PDB_SC_PDBIE_MASK       // PDB Interrupt Enable
+     | PDB_SC_PRESCALER(0x5)   // Slow down the period of the PDB for testing
+     | PDB_SC_TRGSEL(0xf)      // Trigger source is Software Trigger to be invoked in this file
+     | PDB_SC_MULT(2)          // Multiplication factor 20 for the prescale divider for the counter clock
+     | PDB_SC_LDOK_MASK;       // Need to ok the loading or it will not load certain regsiters!
+                               // the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time.
+
+
+
+//PDB configured above
+/////////////////////////////////////////////////////////////////////////////////////////
+//ADC configured below
+/*
+// setup the initial ADC default configuration
+Master_Adc_Config.CONFIG1  = ADLPC_NORMAL
+                        | ADC_CFG1_ADIV(ADIV_4)
+                        | ADLSMP_LONG
+                        | ADC_CFG1_MODE(MODE_16)
+                        | ADC_CFG1_ADICLK(ADICLK_BUS);
+Master_Adc_Config.CONFIG2  = MUXSEL_ADCA
+                        | ADACKEN_DISABLED
+                        | ADHSC_HISPEED
+                        | ADC_CFG2_ADLSTS(ADLSTS_20) ;
+Master_Adc_Config.COMPARE1 = 0x1234u ;                 // can be anything
+Master_Adc_Config.COMPARE2 = 0x5678u ;                 // can be anything
+                                                    // since not using
+                                                    // compare feature
+Master_Adc_Config.STATUS2  = ADTRG_HW
+                        | ACFE_DISABLED
+                        | ACFGT_GREATER
+                        | ACREN_ENABLED
+                        | DMAEN_DISABLED
+                        | ADC_SC2_REFSEL(REFSEL_EXT);
+
+Master_Adc_Config.STATUS3  = CAL_OFF
+                        | ADCO_SINGLE
+                        | AVGE_ENABLED
+                        | ADC_SC3_AVGS(AVGS_32);
+
+Master_Adc_Config.PGA      = PGAEN_DISABLED
+                        | PGACHP_NOCHOP
+                        | PGALP_NORMAL
+                        | ADC_PGA_PGAG(PGAG_64);
+Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
+Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31);
+
+
+// Configure ADC as it will be used, but becuase ADC_SC1_ADCH is 31,
+// the ADC will be inactive.  Channel 31 is just disable function.
+// There really is no channel 31.
+
+ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);  // config ADC
+
+// Calibrate the ADC in the configuration in which it will be used:
+ADC_Cal(ADC0_BASE_PTR);                    // do the calibration
+
+// The structure still has the desired configuration.  So restore it.
+// Why restore it?  The calibration makes some adjustments to the
+// configuration of the ADC.  The are now undone:
+
+// config the ADC again to desired conditions
+ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);
+
+// REPEAT for BOTH ADC's.  However we will only 'use' the results from
+// the ADC wired to the Potentiometer on the Kinetis Tower Card.
+
+// Repeating for ADC1:
+ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config);  // config ADC
+ADC_Cal(ADC1_BASE_PTR);                    // do the calibration
+//  ADC_Read_Cal(ADC1_BASE_PTR,&CalibrationStore[0]);   // store the cal
+
+
+// config the ADC again to default conditions
+ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config);
+
+// *****************************************************************************
+//      ADC0 and ADC1 using the PDB trigger in ping pong
+// *****************************************************************************
+
+// use interrupts, single ended mode, and real channel numbers now:
+
+Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC0_CHANA);
+Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC0_CHANB);
+ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config);  // config ADC0
+
+Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC1_CHANA);
+Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC1_CHANB);
+ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config);  // config ADC1
+*/
     
     
     
     
-    analog_initialization(A0);
-    analog_initialization(A2);
-    
-    // put in high power mode for faster frequencies
-    ADC0->CFG1 |= ADC_CFG1_ADLPC_MASK;                    
-    
-    // put in continuous conversion mode
-    pc.printf("ADC0_SC3: %08x\r\n", ADC0->SC3);
     
-    // enable the DMA
-    ADC0->SC2 |= ADC_SC2_DMAEN_MASK;
-    ADC1->SC2 |= ADC_SC2_DMAEN_MASK;
-    ADC0->SC3 = 0; // Reset SC3
-    ADC1->SC3 = 0; // Reset SC3
+    /*
+    PDB0->SC = 0x0100; // DMA enable and Load OK
+    PDB0->MOD = 1000;// the period of the PDB
+    // AOS
+    PDB0->SC |= PDB_SC_CONT_MASK; // run PDB in continuous mode
+    PDB0->SC |= PDB_SC_TRGSEL(7); // set trigger selection to 7
+    PDB0->SC |= PDB_SC_LDOK_MASK; // load values into the register
+    PDB0->SC |= PDB_SC_PDBEN_MASK; // enables the PDB
+    PDB0->SC |= PDB_SC_SWTRIG_MASK; // enable software trigger (start the PDB)
+    */
+    PDB0->SC |= PDB_SC_SWTRIG_MASK; // enable software trigger (start the PDB)
     
-    dma_init(sample_array1, sample_array2, angle_array, TOTAL_SAMPLES);
-    pc.printf("SampleArr: %08x\r\n", &sample_array1);
-    uint16_t* dma_csr = (uint16_t*) 0x4000901C;
-    uint32_t* dma_daddr = (uint32_t*) 0x40009010;
-    *dma_csr |= 1;
+    //pc.printf("SampleArr: %08x\r\n", &sample_array1);
+    //uint16_t* dma_csr = (uint16_t*) 0x4000901C;
+    //uint32_t* dma_daddr = (uint32_t*) 0x40009010;
+    //*dma_csr |= 1;
     
     // Start the sampling loop
     current_sample_index = WAITING_TO_BEGIN;
@@ -213,7 +369,7 @@
     adc_hal_set_reference_voltage_mode(instance, kAdcVoltageVref);
     adc_hal_set_resolution_mode(instance, kAdcSingleDiff16);
     adc_hal_configure_continuous_conversion(instance, false); // true=continuous conversion mode, false = single conversion mode
-    adc_hal_configure_hw_trigger(instance, true); // true=hw trigger, false=sw trigger
+    adc_hal_configure_hw_trigger(instance, false); // true=hw trigger, false=sw trigger
     adc_hal_configure_hw_average(instance, false);
     adc_hal_set_hw_average_mode(instance, kAdcHwAverageCount4);
     adc_hal_set_group_mux(instance, kAdcChannelMuxB); // only B channels are avail