Diff: adc.cpp

Revision:

46:a015ebf4663b

Parent:

45:d591d138cdeb

Child:

47:54fafe151669

--- a/adc.cpp	Sat Jan 31 07:25:52 2015 +0000
+++ b/adc.cpp	Sat Jan 31 08:13:33 2015 +0000
@@ -31,6 +31,7 @@
     
     // Set ADC hardware trigger to PDB0
     SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0);
+    SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0);
     
     // Setup Configuration Register 1 
     ADC0_CFG1 = 0; // clear register
@@ -39,6 +40,12 @@
     ADC0_CFG1 |= ADC_CFG1_ADIV(0);      // select short sample time
     ADC0_CFG1 &= ~ADC_CFG1_ADLSMP_MASK; // select short sample time
     ADC0_CFG1 &= ~ADC_CFG1_ADLPC_MASK;  // select normal power configuration
+    ADC1_CFG1 = 0; // clear register
+    ADC1_CFG1 |= ADC_CFG1_ADICLK(0);    // select bus clock
+    ADC1_CFG1 |= ADC_CFG1_MODE(3);      // select 16-bit 2's complement output
+    ADC1_CFG1 |= ADC_CFG1_ADIV(0);      // select short sample time
+    ADC1_CFG1 &= ~ADC_CFG1_ADLSMP_MASK; // select short sample time
+    ADC1_CFG1 &= ~ADC_CFG1_ADLPC_MASK;  // select normal power configuration
     
     // Setup Configuration Register 2 
     ADC0_CFG2 = 0; // clear register
@@ -50,15 +57,25 @@
     ADC0_SC2 |= ADC_SC2_REFSEL(0);  // select external voltage reference
     ADC0_SC2 |= ADC_SC2_DMAEN_MASK; // enable DMA
     ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // select software trigger until calibration is complete
+    ADC1_SC2 = 0;                   // clear register
+    ADC1_SC2 |= ADC_SC2_REFSEL(0);  // select external voltage reference
+    ADC1_SC2 |= ADC_SC2_DMAEN_MASK; // enable DMA
+    ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // select software trigger until calibration is complete
     
     // Setup Status and Control Register 3 
     ADC0_SC3 = 0;  // Hardware Average set to 4 samples averaged
                    // Hardware Average Disabled
                    // select single conversion mode
+    ADC1_SC3 = 0;  // Hardware Average set to 4 samples averaged
+                   // Hardware Average Disabled
+                   // select single conversion mode
     
     // calibrate the ADC
     ADC0_SC3 |= ADC_SC3_CAL_MASK; // start calibration
     while(ADC0_SC3&ADC_SC3_CALF_MASK) {} // wait for calibration to complete
+    ADC1_SC3 |= ADC_SC3_CAL_MASK; // start calibration
+    while(ADC1_SC3&ADC_SC3_CALF_MASK) {} // wait for calibration to complete
+    
     
     // calculate the gains (see user manual page 864)
     int16_t gain = (ADC0_CLP0+ADC0_CLP1+ADC0_CLP2+ADC0_CLP3+ADC0_CLP4+ADC0_CLPS);
@@ -66,13 +83,23 @@
     gain |= 0x8000;  // set the MSB
     ADC0_PG = gain;
     
+    gain = (ADC1_CLP0+ADC1_CLP1+ADC1_CLP2+ADC1_CLP3+ADC1_CLP4+ADC1_CLPS);
+    gain = (gain>>1); // divide by 2
+    gain |= 0x8000;  // set the MSB
+    ADC1_PG = gain;
+    
     gain = (ADC0_CLM0+ADC0_CLM1+ADC0_CLM2+ADC0_CLM3+ADC0_CLM4+ADC0_CLMS);
     gain = (gain>>1); // divide by 2
     gain |= 0x8000;  // set the MSB
     ADC0_MG = gain;
     
+    gain = (ADC1_CLM0+ADC1_CLM1+ADC1_CLM2+ADC1_CLM3+ADC1_CLM4+ADC1_CLMS);
+    gain = (gain>>1); // divide by 2
+    gain |= 0x8000;  // set the MSB
+    ADC1_MG = gain;
+    
     ADC0_SC3 &= ~ADC_SC3_CAL_MASK; // stop calibration
-    
+    ADC1_SC3 &= ~ADC_SC3_CAL_MASK; // stop calibration
     
     
     
@@ -84,16 +111,23 @@
     green = 0;
     
     ADC0_SC2 |= ADC_SC2_ADTRG_MASK; // select hardware trigger now that calibration is complete
+    ADC1_SC2 |= ADC_SC2_ADTRG_MASK; // select hardware trigger now that calibration is complete
     
     // Setup Status and Control Register 1A 
     ADC0_SC1A = 0; // clear register
     ADC0_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
     ADC0_SC1A |= ADC_SC1_AIEN_MASK;  // enable interrupt (for debugging)
     ADC0_SC1A |= ADC_SC1_ADCH(13);   // select channel 13
+    ADC1_SC1A = 0; // clear register
+    ADC1_SC1A &= ~ADC_SC1_DIFF_MASK; // select single-ended mode
+    ADC1_SC1A |= ADC_SC1_AIEN_MASK;  // enable interrupt (for debugging)
+    ADC1_SC1A |= ADC_SC1_ADCH(13);   // select channel 13
     
     // Check if ADC is finished initializing  TODO:  This part doesn't seem right, but I did it according to 871
     while( (ADC0_SC1A&ADC_SC1_COCO_MASK)) {}
     gain = ADC0_RA; // read the register to clear SC1A[COCO]
+    while( (ADC1_SC1A&ADC_SC1_COCO_MASK)) {}
+    gain = ADC1_RA; // read the register to clear SC1A[COCO]
     
     
     
@@ -125,27 +159,34 @@
     
     // set ADC to continuous mode
     ADC0_SC3 |= ADC_SC3_ADCO_MASK;
+    ADC1_SC3 |= ADC_SC3_ADCO_MASK;
     
     // set ADC to software trigger
-    ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK;
+    ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK;
     
     // start ADC conversion (SW trigger)
-    //ADC0_SC1A |= ADC_SC1_ADCH(13);   // write to SC1A causing a trigger
+    ADC0_SC1A |= ADC_SC1_ADCH(13);   // write to SC1A causing a trigger
+    ADC1_SC1A |= ADC_SC1_ADCH(14);   // write to SC1A causing a trigger
     //BW_ADC_SC1n_ADCH(0, 0, kAdcChannel13); // trigger the ADC
 }
 
 void adc_stop() {
     // set ADC to hardware trigger
     ADC0_SC2 |= ADC_SC2_ADTRG_MASK;
+    ADC1_SC2 |= ADC_SC2_ADTRG_MASK;
     
     // set to single conversion mode effectively stopping the ADC unless a timer triggers the ADC
     ADC0_SC3 &= ~ADC_SC3_ADCO_MASK; 
+    ADC1_SC3 &= ~ADC_SC3_ADCO_MASK; 
 }
 
 void adc_single_sample() {
     ADC0_SC3 &= ~ADC_SC3_ADCO_MASK;  // single conversion mode
+    ADC1_SC3 &= ~ADC_SC3_ADCO_MASK;  // single conversion mode
     ADC0_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
+    ADC1_SC2 &= ~ADC_SC2_ADTRG_MASK; // set ADC to software trigger
     ADC0_SC1A |= ADC_SC1_ADCH(13);   // write to SC1A causing a trigger
+    ADC1_SC1A |= ADC_SC1_ADCH(14);   // write to SC1A causing a trigger
 }
 
 void ADC0_IRQHandler() {